/openbmc/linux/Documentation/gpu/amdgpu/display/ |
H A D | dc-glossary.rst | 41 * PPLL: Pixel PLL
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/openbmc/linux/drivers/clk/qcom/ |
H A D | Kconfig | 24 tristate "MSM8916 A53 PLL" 26 Support for the A53 PLL on MSM8916 devices. It provides 32 tristate "A7 PLL driver for SDX55 and SDX65" 34 Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with 123 tristate "IPQ APSS PLL" 125 Support for APSS PLL on ipq devices. The APSS PLL is the main 1065 tristate "High-Frequency PLL (HFPLL) Clock Controller"
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | layerscape-pci.txt | 7 which is used to describe the PLL settings at the time of chip-reset.
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/openbmc/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm-cygnus-clock.dtsi | 44 /* Cygnus ARM PLL */
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/openbmc/u-boot/doc/device-tree-bindings/video/ |
H A D | exynos_mipi_dsi.txt | 29 samsung,dsim-config-pll-stable-time: the PLL Timer for stability
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | samsung,exynos7-clock.yaml | 18 - "fin_pll" - PLL input clock from XXTI
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/openbmc/linux/drivers/clk/samsung/ |
H A D | clk-exynos5433.c | 805 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 807 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 870 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 1063 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1065 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1067 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", 1069 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", 2615 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 3301 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3589 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", [all …]
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H A D | clk.h | 271 #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \ macro
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra124-xusb-padctl.yaml | 69 description: UTMI PLL power supply. Must supply 1.8 V. 72 description: PLLE reference PLL power supply. Must supply 1.05 V. 75 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
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H A D | ti,phy-j721e-wiz.yaml | 123 description: Phandle to clock nodes representing the two inputs to PLL.
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/openbmc/linux/Documentation/power/ |
H A D | s2ram.rst | 64 PLL's, and it just _hangs_. Using the regular VGA console and letting X
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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/ |
H A D | cpufreq-mediatek.txt | 9 source (usually MAINPLL) when the original CPU PLL is under
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | ti,sn65dsi86.yaml | 41 description: A 1.8V supply that powers the DisplayPort PLL.
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H A D | samsung,mipi-dsim.yaml | 68 description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | motorcomm,yt8xxx.yaml | 45 If set, keep the PLL enabled even if there is no link. Useful if you
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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra124-sor.yaml | 64 description: PLL supply for HDMI/DP
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/openbmc/linux/drivers/media/dvb-frontends/ |
H A D | Kconfig | 281 tristate "Infineon TUA6100 PLL" 285 A DVB-S PLL chip. 755 comment "Digital terrestrial only tuners/PLL" 759 tristate "Generic I2C PLL based tuners" 763 This module drives a number of tuners based on PLL chips with a
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/openbmc/u-boot/board/Barix/ipam390/ |
H A D | ipam390-ais-uart.cfg | 119 ; the system PLL and the peripheral's clocks are changed together.
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/openbmc/u-boot/arch/arm/mach-mvebu/ |
H A D | Kconfig | 46 # Armada PLL frequency (used for NAND clock generation)
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/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/ |
H A D | adi,adf4350.yaml | 43 If set the PLL tunes to this frequency (in Hz) on driver probe.
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/openbmc/linux/Documentation/devicetree/bindings/display/samsung/ |
H A D | samsung,exynos-hdmi.yaml | 89 VDD 1.0V HDMI PLL.
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/openbmc/linux/drivers/mfd/ |
H A D | cs42l43.c | 438 CS42L43_IRQ_REG(PLL_LOST_LOCK, PLL), 439 CS42L43_IRQ_REG(PLL_READY, PLL),
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/openbmc/linux/drivers/clk/ |
H A D | clk-stm32f4.c | 492 PLL, enumerator 587 { PLL, 192, { "pll", "pll48", NULL } }, 593 { PLL, 50, { "pll", "pll-q", "pll-r" } },
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H A D | clk-stm32mp1.c | 1230 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ macro 1773 PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR), 1774 PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR), 1775 PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR), 1776 PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
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/openbmc/linux/arch/arm/boot/dts/marvell/ |
H A D | armada-370-xp.dtsi | 306 /* 2 GHz fixed main PLL */
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