| /openbmc/openbmc/poky/meta/recipes-devtools/gcc/gcc/ |
| H A D | CVE-2023-4039.patch | 820 /* FP and LR are placed in the linkage record. */
1503 /* FP and LR are placed in the linkage record. */
1860 * a probe using LR at SP + 80 bytes (or some other value >= 16)
1870 Putting LR before other registers prevents push/pop allocation
1871 when shadow call stacks are enabled, since LR is restored
1875 to be LR, since a later patch removes that restriction.
1882 when LR was not in the first 16 bytes.
1919 /* FP and LR are placed in the linkage record. */
2747 - | LR' | |
2758 + | LR' |
[all …]
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | omap3-evm-common.dtsi | 105 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap3-evm-common.dtsi | 105 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
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| /openbmc/u-boot/arch/arm/lib/ |
| H A D | vectors.S | 209 stmdb r8, {sp, lr}^ @ Calling SP, LR
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| /openbmc/linux/net/ethtool/ |
| H A D | common.c | 156 __DEFINE_LINK_MODE_NAME(10000, LR, Full),
319 __DEFINE_LINK_MODE_PARAMS(10000, LR, Full),
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| /openbmc/linux/Documentation/bpf/ |
| H A D | map_lru_hash_update.dot | 67 rankdir=LR;
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| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | macros.inc | 97 #define fWRITE_LR(A) (LR = A)
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| /openbmc/linux/arch/powerpc/platforms/8xx/ |
| H A D | Kconfig | 121 (by not placing conditional branches or branches to LR or CTR
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| /openbmc/linux/Documentation/powerpc/ |
| H A D | syscall64-abi.rst | 45 stack frame LR and CR save fields are not used.
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| H A D | papr_hcalls.rst | 82 | LR | Y | Link Register |
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| H A D | transactional_memory.rst | 63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | entry-header.S | 173 @ Store/load the USER SP and LR registers by switching to the SYS
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| /openbmc/qemu/target/hexagon/ |
| H A D | attribs_def.h.inc | 103 DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR")
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| /openbmc/libpldm/ |
| H A D | README.md | 94 direction LR
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| /openbmc/openbmc/meta-raspberrypi/recipes-graphics/userland/files/ |
| H A D | 0003-wayland-Add-Wayland-example.patch | 74 …QZ&9@5EL:JQ?OVBRYEU\<LS@PWCTZ3<FEOY1;EDNW07@18A39?27>1:C=FOHU]BSZFV\CSYESY@LR>GOBKS3?ELW_ERZ>ITM]f…
75 …*���u��ASeAUY?PXBU[@PZDV]=PU@SVCVX=QVAUZ?OU=KQ>MS@LR=JPBJR=LN8HJ8CG4AD0;>+7:6?B=FJ6<ABGL/9<ENR=HL3…
76 …LR<HMBQT>MT9KS=OV<OTASU>OS|��k��D]m3L\4M]7OaBZlOgyn��x��s��\u�Ict-H\,Gb4S4GX,CS��ċ��z�����}������…
77 …�u��v����������ˍ�ą�������w��l��<Xi4N]4M^1GV/EP.EQ9IV7HU<LW8GT5FO>NU9IN=MS<LR<LR9JP@NT=KQ>MS>JP:FL…
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 651 #define LR SPRN_LR macro
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | t32.decode | 410 # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
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| /openbmc/qemu/tcg/ppc/ |
| H A D | tcg-target.c.inc | 513 #define LR SPR(8, 0)
2364 tcg_out32(s, MFSPR | RT(arg) | LR);
2841 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
2868 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
2883 tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR);
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| /openbmc/linux/Documentation/livepatch/ |
| H A D | livepatch.rst | 431 Each function has to handle TOC and save LR before it could call
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| /openbmc/linux/Documentation/admin-guide/media/ |
| H A D | ipu3.rst | 455 rankdir="LR"
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/fbida/files/ |
| H A D | support-jpeg-turbo.patch | 1693 - JXFORM_TRANSPOSE, /* transpose across UL-to-LR axis */
1755 + JXFORM_TRANSPOSE, /* transpose across UL-to-LR axis */
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| /openbmc/linux/arch/arm64/tools/ |
| H A D | sysreg | 2537 Field 7:0 LR
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| /openbmc/qemu/hw/intc/ |
| H A D | trace-events | 170 … idx, int hppvlpi, int grp, int prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d …
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| /openbmc/qemu/tcg/aarch64/ |
| H A D | tcg-target.c.inc | 3214 /* Push (FP, LR) and allocate space for all saved registers. */
3271 /* Pop (FP, LR), restore SP to previous frame. */
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| /openbmc/qemu/tcg/arm/ |
| H A D | tcg-target.c.inc | 1648 * opcode into LR for the slow path. We will not be using
|