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/openbmc/linux/drivers/clk/sunxi-ng/ |
H A D | ccu-sun50i-h6.c | db754893 Wed Oct 31 13:36:28 CDT 2018 Jagan Teki <jagan@amarulasolutions.com> clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
MUX bits for MMC clock register range are 25:24 where 24 is shift and 2 is width So fix the width number from 3 to 2.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> db754893 Wed Oct 31 13:36:28 CDT 2018 Jagan Teki <jagan@amarulasolutions.com> clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width MUX bits for MMC clock register range are 25:24 where 24 is shift and 2 is width So fix the width number from 3 to 2. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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