Searched hist:b4983e16 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/board/freescale/mpc8610hpcd/ |
| H A D | ddr.c | b4983e16 Fri Nov 21 02:31:43 CST 2008 Dave Liu <daveliu@freescale.com> fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
|
| /openbmc/u-boot/board/freescale/mpc8544ds/ |
| H A D | ddr.c | b4983e16 Fri Nov 21 02:31:43 CST 2008 Dave Liu <daveliu@freescale.com> fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
|
| /openbmc/u-boot/board/freescale/mpc8641hpcn/ |
| H A D | ddr.c | b4983e16 Fri Nov 21 02:31:43 CST 2008 Dave Liu <daveliu@freescale.com> fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
|