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H A D | amd64_edac.c | 73ba8593 Mon Sep 19 10:34:45 CDT 2011 Borislav Petkov <borislav.petkov@amd.com> amd64_edac: Add a fix for Erratum 505
When accessing the scrub rate control register (F3x58) on F15h, the DRAM controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the scrub rate configuration can take effect. See Erratum 505 in the AMD F15h revision guide for more details.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> 73ba8593 Mon Sep 19 10:34:45 CDT 2011 Borislav Petkov <borislav.petkov@amd.com> amd64_edac: Add a fix for Erratum 505 When accessing the scrub rate control register (F3x58) on F15h, the DRAM controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the scrub rate configuration can take effect. See Erratum 505 in the AMD F15h revision guide for more details. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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