Searched hist:"6 d4811c4" (Results 1 – 2 of 2) sorted by relevance
/openbmc/qemu/docs/system/arm/ |
H A D | mps2.rst | 6d4811c4 Thu Sep 03 15:20:47 CDT 2020 Peter Maydell <peter.maydell@linaro.org> hw/arm/mps2: New board model mps2-an500 Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
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/openbmc/qemu/hw/arm/ |
H A D | mps2.c | 6d4811c4 Thu Sep 03 15:20:47 CDT 2020 Peter Maydell <peter.maydell@linaro.org> hw/arm/mps2: New board model mps2-an500 Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
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