/openbmc/linux/arch/powerpc/platforms/cell/ |
H A D | spu_callbacks.c | 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness
We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry.
That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all.
Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it.
As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality.
The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers.
This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry. That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all. Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it. As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality. The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers. This version clobbers r9-r12, XER, CTR, and CR0-1,5-7. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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/openbmc/linux/arch/powerpc/include/uapi/asm/ |
H A D | unistd.h | 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness
We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry.
That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all.
Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it.
As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality.
The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers.
This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry. That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all. Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it. As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality. The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers. This version clobbers r9-r12, XER, CTR, and CR0-1,5-7. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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/openbmc/linux/arch/powerpc/kernel/ |
H A D | syscalls.c | 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness
We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry.
That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all.
Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it.
As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality.
The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers.
This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry. That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all. Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it. As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality. The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers. This version clobbers r9-r12, XER, CTR, and CR0-1,5-7. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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/openbmc/linux/arch/powerpc/include/asm/ |
H A D | unistd.h | 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness
We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry.
That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all.
Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it.
As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality.
The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers.
This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> 529d235a Sat Mar 28 05:35:16 CDT 2015 Michael Ellerman <mpe@ellerman.id.au> powerpc: Add a proper syscall for switching endianness We currently have a "special" syscall for switching endianness. This is syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall exception entry. That has a few problems, firstly the syscall number is outside of the usual range, which confuses various tools. For example strace doesn't recognise the syscall at all. Secondly it's handled explicitly as a special case in the syscall exception entry, which is complicated enough without it. As a first step toward removing the special syscall, we need to add a regular syscall that implements the same functionality. The logic is simple, it simply toggles the MSR_LE bit in the userspace MSR. This is the same as the special syscall, with the caveat that the special syscall clobbers fewer registers. This version clobbers r9-r12, XER, CTR, and CR0-1,5-7. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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