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H A D | mt8192.dtsi | 29288bab Tue Dec 06 05:23:27 CST 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> arm64: dts: mt8192: Add complete CPU caches information
This SoC features two clusters composed of: - 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 4x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 2MB, 16-way set associative.
With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221206112330.78431-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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