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H A D | tegra194-p3509-0000.dtsi | 2838cfdd Thu Nov 17 02:38:34 CST 2022 Thierry Reding <treding@nvidia.com> arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space.
Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children.
While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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H A D | tegra234-p3737-0000+p3701-0000.dts | 2838cfdd Thu Nov 17 02:38:34 CST 2022 Thierry Reding <treding@nvidia.com> arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space.
Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children.
While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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H A D | tegra234.dtsi | 2838cfdd Thu Nov 17 02:38:34 CST 2022 Thierry Reding <treding@nvidia.com> arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space.
Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children.
While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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H A D | tegra194-p2972-0000.dts | 2838cfdd Thu Nov 17 02:38:34 CST 2022 Thierry Reding <treding@nvidia.com> arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space.
Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children.
While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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H A D | tegra194.dtsi | 2838cfdd Thu Nov 17 02:38:34 CST 2022 Thierry Reding <treding@nvidia.com> arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space.
Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children.
While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|