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/openbmc/linux/drivers/clk/mmp/
H A Dclk-frac.c35 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_round_rate()
54 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_recalc_rate() local
61 num = (val >> masks->num_shift) & masks->num_mask; in clk_factor_recalc_rate()
64 den = (val >> masks->den_shift) & masks->den_mask; in clk_factor_recalc_rate()
71 do_div(rate, num * factor->masks->factor); in clk_factor_recalc_rate()
81 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_set_rate() local
90 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_set_rate()
103 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_set_rate()
104 val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; in clk_factor_set_rate()
106 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_set_rate()
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/openbmc/linux/drivers/clk/spear/
H A Dclk-aux-synth.c77 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; in clk_aux_recalc_rate()
78 if (eqn == aux->masks->eq1_mask) in clk_aux_recalc_rate()
82 num = (val >> aux->masks->xscale_sel_shift) & in clk_aux_recalc_rate()
83 aux->masks->xscale_sel_mask; in clk_aux_recalc_rate()
86 den *= (val >> aux->masks->yscale_sel_shift) & in clk_aux_recalc_rate()
87 aux->masks->yscale_sel_mask; in clk_aux_recalc_rate()
111 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); in clk_aux_set_rate()
112 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << in clk_aux_set_rate()
113 aux->masks->eq_sel_shift; in clk_aux_set_rate()
114 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); in clk_aux_set_rate()
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/openbmc/linux/sound/soc/codecs/
H A Dtscs42xx.h124 /* Field Masks */
132 /* Register Masks */
147 /* Field Masks */
155 /* Register Masks */
170 /* Field Masks */
178 /* Register Masks */
195 /* Field Masks */
203 /* Register Masks */
220 /* Field Masks */
228 /* Register Masks */
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/openbmc/linux/lib/
H A Dgroup_cpus.c47 cpumask_var_t *masks; in alloc_node_to_cpumask() local
50 masks = kcalloc(nr_node_ids, sizeof(cpumask_var_t), GFP_KERNEL); in alloc_node_to_cpumask()
51 if (!masks) in alloc_node_to_cpumask()
55 if (!zalloc_cpumask_var(&masks[node], GFP_KERNEL)) in alloc_node_to_cpumask()
59 return masks; in alloc_node_to_cpumask()
63 free_cpumask_var(masks[node]); in alloc_node_to_cpumask()
64 kfree(masks); in alloc_node_to_cpumask()
68 static void free_node_to_cpumask(cpumask_var_t *masks) in free_node_to_cpumask() argument
73 free_cpumask_var(masks[node]); in free_node_to_cpumask()
74 kfree(masks); in free_node_to_cpumask()
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/openbmc/phosphor-power/phosphor-regulators/src/actions/
H A Di2c_write_bytes_action.hpp61 reg{reg}, values{values}, masks{} in I2CWriteBytesAction()
80 * @param masks One or more bit masks. The number of bit masks must match
87 const std::vector<uint8_t>& masks) : in I2CWriteBytesAction() argument
88 reg{reg}, values{values}, masks{masks} in I2CWriteBytesAction()
96 // Masks vector must have same size as values vector
97 if (masks.size() != values.size())
99 throw std::invalid_argument{"Masks vector has invalid size"};
110 * The device register, byte values, and bit masks (if any) were specified
143 * Returns the bit masks.
148 * @return bit masks
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H A Di2c_compare_bytes_action.hpp75 * @param masks One or more bit masks. The number of bit masks must match
83 const std::vector<uint8_t>& masks) : in I2CCompareBytesAction() argument
84 reg{reg}, values{values}, masks{masks} in I2CCompareBytesAction()
92 // Masks vector must have same size as values vector
93 if (masks.size() != values.size())
95 throw std::invalid_argument{"Masks vector has invalid size"};
107 * The device register, byte values, and bit masks (if any) were specified
141 * Returns the bit masks.
147 * @return bit masks
151 return masks; in getMasks()
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H A Di2c_write_bytes_action.cpp35 if (masks.size() == 0) in execute()
54 valuesToWrite[i] = (values[i] & masks[i]) | in execute()
55 (currentValues[i] & (~masks[i])); in execute()
81 ss << " ], masks: [ "; in toString()
82 for (unsigned int i = 0; i < masks.size(); ++i) in toString()
84 ss << ((i > 0) ? ", " : "") << "0x" << static_cast<uint16_t>(masks[i]); in toString()
/openbmc/phosphor-power/phosphor-regulators/test/actions/
H A Di2c_write_bytes_action_tests.cpp89 // const std::vector<uint8_t>& masks)
96 std::vector<uint8_t> masks{0x7E, 0x3C}; in TEST() local
97 I2CWriteBytesAction action{0xA0, values, masks}; in TEST()
118 std::vector<uint8_t> masks{}; in TEST() local
119 I2CWriteBytesAction action{0xA0, values, masks}; in TEST()
131 // Test where fails: Masks vector different size than values vector in TEST()
135 std::vector<uint8_t> masks{0x7E, 0x3C}; in TEST() local
136 I2CWriteBytesAction action{0x7C, values, masks}; in TEST()
141 EXPECT_STREQ(e.what(), "Masks vector has invalid size"); in TEST()
151 // Test where works: Masks not specified in TEST()
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H A Di2c_compare_bytes_action_tests.cpp89 // const std::vector<uint8_t>& masks)
96 std::vector<uint8_t> masks{0x7E, 0x3C}; in TEST() local
97 I2CCompareBytesAction action{0xA0, values, masks}; in TEST()
118 std::vector<uint8_t> masks{}; in TEST() local
119 I2CCompareBytesAction action{0xA0, values, masks}; in TEST()
131 // Test where fails: Masks vector different size than values vector in TEST()
135 std::vector<uint8_t> masks{0x7E, 0x3C}; in TEST() local
136 I2CCompareBytesAction action{0x7C, values, masks}; in TEST()
141 EXPECT_STREQ(e.what(), "Masks vector has invalid size"); in TEST()
175 // Masks : 0x7E = 0111 1110 0x3C = 0011 1100 in TEST()
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/openbmc/linux/kernel/irq/
H A Daffinity.c19 * irq_create_affinity_masks - Create affinity masks for multiqueue spreading
29 struct irq_affinity_desc *masks = NULL; in irq_create_affinity_masks() local
59 masks = kcalloc(nvecs, sizeof(*masks), GFP_KERNEL); in irq_create_affinity_masks()
60 if (!masks) in irq_create_affinity_masks()
65 cpumask_copy(&masks[curvec].mask, irq_default_affinity); in irq_create_affinity_masks()
77 kfree(masks); in irq_create_affinity_masks()
82 cpumask_copy(&masks[curvec + j].mask, &result[j]); in irq_create_affinity_masks()
95 cpumask_copy(&masks[curvec].mask, irq_default_affinity); in irq_create_affinity_masks()
99 masks[i].is_managed = 1; in irq_create_affinity_masks()
101 return masks; in irq_create_affinity_masks()
/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz8795.c165 const u32 *masks; in ksz8_r_mib_cnt() local
172 masks = dev->info->masks; in ksz8_r_mib_cnt()
187 if (check & masks[MIB_COUNTER_VALID]) { in ksz8_r_mib_cnt()
189 if (check & masks[MIB_COUNTER_OVERFLOW]) in ksz8_r_mib_cnt()
201 const u32 *masks; in ksz8795_r_mib_pkt() local
208 masks = dev->info->masks; in ksz8795_r_mib_pkt()
225 if (check & masks[MIB_COUNTER_VALID]) { in ksz8795_r_mib_pkt()
234 if (check & masks[MIB_COUNTER_OVERFLOW]) { in ksz8795_r_mib_pkt()
240 if (check & masks[MIB_COUNTER_OVERFLOW]) in ksz8795_r_mib_pkt()
386 const u32 *masks; in ksz8_valid_dyn_entry() local
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/openbmc/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h35 /* Tx control register masks and shifts */
43 /* Rx control register masks and shifts */
53 /* Interrupt enable for data buffer events register masks and shifts */
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
141 /* GE MAC, PCS reset control register masks and shifts */
147 /* Tx phase sync FIFO control register masks and shifts */
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
261 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
263 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
265 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
267 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
272 reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; in dpp1_cm_get_reg_field()
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/openbmc/linux/arch/arm/mach-s3c/
H A Dwakeup-mask.h27 * @masks: The list of masks to use.
28 * @nr_masks: The number of entries pointed to buy @masks.
31 * of interrupts and control bits in @masks. We do this at suspend time
36 const struct samsung_wakeup_mask *masks,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb_cm.c53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
73 reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in dwb3_get_reg_field_ogam()
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H A Ddcn30_dpp_cm.c177 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
179 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
182 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
184 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
186 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
188 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
191 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
193 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
195 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
197 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; in dpp3_gamcor_reg_field()
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/openbmc/linux/block/
H A Dblk-mq-cpumap.c20 const struct cpumask *masks; in blk_mq_map_queues() local
23 masks = group_cpus_evenly(qmap->nr_queues); in blk_mq_map_queues()
24 if (!masks) { in blk_mq_map_queues()
31 for_each_cpu(cpu, &masks[queue]) in blk_mq_map_queues()
34 kfree(masks); in blk_mq_map_queues()
/openbmc/linux/drivers/media/pci/dt3155/
H A Ddt3155.h69 /* CSR1 bit masks */
88 /* INT_CSR bit masks */
96 /* IIC_CSR1 bit masks */
99 /* IIC_CSR2 bit masks */
105 /* CSR2 bit masks */
115 /* CSR_EVEN/ODD bit masks */
120 /* CONFIG bit masks */
131 /* AD_CMD bit masks */
/openbmc/linux/drivers/media/i2c/
H A Dadv7393_regs.h92 /* Bit masks for Mode Select Register */
98 /* Bit masks for Mode Register 0 */
103 /* Bit masks for SD brightness/WSS */
107 /* Bit masks for soft reset register */
110 /* Bit masks for HD Mode Register 1 */
132 /* Bit masks for SD Mode Register 1 */
143 /* Bit masks for SD Mode Register 2 */
156 /* Bit masks for HD Mode Register 6 */
H A Dadv7343_regs.h84 /* Bit masks for Mode Select Register */
90 /* Bit masks for Mode Register 0 */
95 /* Bit masks for DAC output levels */
98 /* Bit masks for soft reset register */
101 /* Bit masks for HD Mode Register 1 */
123 /* Bit masks for SD Mode Register 1 */
134 /* Bit masks for SD Mode Register 2 */
147 /* Bit masks for HD Mode Register 6 */
/openbmc/phosphor-power/phosphor-regulators/tools/
H A Dvalidate-regulators-config.py70 Check if the number of bit masks in the 'masks' property matches the number
79 if "masks" in object:
80 if len(object.get("masks", [])) != len(object.get("values", [])):
83 + "The masks array must have the same size as the values"
84 + " array. masks: "
85 + str(object.get("masks", []))
93 if "masks" in object:
94 if len(object.get("masks", [])) != len(object.get("values", [])):
97 + "The masks array must have the same size as the values "
98 + "array. masks: "
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/openbmc/linux/drivers/usb/misc/
H A Dbrcmstb-usb-pinmap.c154 res = of_property_read_u32_index(dn, "brcm,in-masks", index++, in parse_pins()
157 dev_err(dev, "Error getting 1st brcm,in-masks for %s\n", in parse_pins()
161 res = of_property_read_u32_index(dn, "brcm,in-masks", index++, in parse_pins()
164 dev_err(dev, "Error getting 2nd brcm,in-masks for %s\n", in parse_pins()
186 res = of_property_read_u32_index(dn, "brcm,out-masks", index++, in parse_pins()
189 dev_err(dev, "Error getting 1st brcm,out-masks for %s\n", in parse_pins()
193 res = of_property_read_u32_index(dn, "brcm,out-masks", index++, in parse_pins()
196 dev_err(dev, "Error getting 2nd brcm,out-masks for %s\n", in parse_pins()
200 res = of_property_read_u32_index(dn, "brcm,out-masks", index++, in parse_pins()
203 dev_err(dev, "Error getting 3rd brcm,out-masks for %s\n", in parse_pins()
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/openbmc/qemu/include/hw/s390x/
H A Devent-facility.h31 /* SCLP event masks */
57 uint8_t masks[]; member
59 * Layout of the masks is
68 #define WEM_CP_RECEIVE_MASK(wem, mask_len) ((wem)->masks)
69 #define WEM_CP_SEND_MASK(wem, mask_len) ((wem)->masks + (mask_len))
70 #define WEM_RECEIVE_MASK(wem, mask_len) ((wem)->masks + 2 * (mask_len))
71 #define WEM_SEND_MASK(wem, mask_len) ((wem)->masks + 3 * (mask_len))
/openbmc/linux/drivers/virtio/
H A Dvirtio_vdpa.c306 struct cpumask *masks = NULL; in create_affinity_masks() local
319 masks = kcalloc(nvecs, sizeof(*masks), GFP_KERNEL); in create_affinity_masks()
320 if (!masks) in create_affinity_masks()
325 cpumask_setall(&masks[curvec]); in create_affinity_masks()
333 kfree(masks); in create_affinity_masks()
338 cpumask_copy(&masks[curvec + j], &result[j]); in create_affinity_masks()
351 cpumask_setall(&masks[curvec]); in create_affinity_masks()
353 return masks; in create_affinity_masks()
367 struct cpumask *masks; in virtio_vdpa_find_vqs() local
373 masks = create_affinity_masks(nvqs, desc ? desc : &default_affd); in virtio_vdpa_find_vqs()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_hw.c41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
80 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) in get_channel_status()
82 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) in get_channel_status()
84 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) in get_channel_status()
86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status()
287 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) in set_speed()
622 const struct dce_i2c_mask *masks) in dce_i2c_hw_construct() argument
629 dce_i2c_hw->masks = masks; in dce_i2c_hw_construct()
645 const struct dce_i2c_mask *masks) in dce100_i2c_hw_construct() argument
652 masks); in dce100_i2c_hw_construct()
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