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/openbmc/linux/drivers/dma/
H A Dfsl-edma-common.c14 #include "fsl-edma-common.h"
93 if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr)) in fsl_edma3_enable_request()
94 edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr); in fsl_edma3_enable_request()
104 struct edma_regs *regs = &fsl_chan->edma->regs; in fsl_edma_enable_request()
110 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { in fsl_edma_enable_request()
111 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); in fsl_edma_enable_request()
112 edma_writeb(fsl_chan->edma, ch, regs->serq); in fsl_edma_enable_request()
130 edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr); in fsl_edma3_disable_request()
138 struct edma_regs *regs = &fsl_chan->edma->regs; in fsl_edma_disable_request()
144 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { in fsl_edma_disable_request()
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H A Dmcf-edma-main.c10 #include <linux/platform_data/dma-mcf-edma.h>
12 #include "fsl-edma-common.h"
81 IORESOURCE_IRQ, "edma-tx-00-15"); in mcf_edma_irq_init()
86 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma); in mcf_edma_irq_init()
91 IORESOURCE_IRQ, "edma-tx-16-55"); in mcf_edma_irq_init()
96 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma); in mcf_edma_irq_init()
100 ret = platform_get_irq_byname(pdev, "edma-tx-56-63"); in mcf_edma_irq_init()
103 0, "eDMA", mcf_edma); in mcf_edma_irq_init()
108 ret = platform_get_irq_byname(pdev, "edma-err"); in mcf_edma_irq_init()
111 0, "eDMA", mcf_edma); in mcf_edma_irq_init()
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H A Dfsl-edma-common.h138 struct fsl_edma_engine *edma; member
237 edma_readl(chan->edma, &chan->tcd->__name) : \
238 edma_readw(chan->edma, &chan->tcd->__name))
242 edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \
243 edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
246 edma_readl(chan->edma, \
250 edma_writel(chan->edma, val, \
255 * The eDMA controller's endian is independent of the CPU core's endian.
259 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) in edma_readl() argument
261 if (edma->big_endian) in edma_readl()
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H A Dfsl-edma-main.c3 * drivers/dma/fsl-edma.c
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
12 #include <dt-bindings/dma/fsl-edma.h>
26 #include "fsl-edma-common.h"
191 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
195 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
201 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); in fsl_edma_irq_init()
203 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); in fsl_edma_irq_init()
208 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); in fsl_edma_irq_init()
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H A DMakefile32 obj-$(CONFIG_DW_EDMA) += dw-edma/
35 fsl-edma-objs := fsl-edma-main.o fsl-edma-common.o
36 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
37 mcf-edma-objs := mcf-edma-main.o fsl-edma-common.o
38 obj-$(CONFIG_MCF_EDMA) += mcf-edma.o
H A Dep93xx_dma.c135 * @edma: pointer to the engine device
166 const struct ep93xx_dma_engine *edma; member
744 edmac->edma->hw_submit(edmac); in ep93xx_dma_advance_work()
802 switch (edmac->edma->hw_interrupt(edmac)) { in ep93xx_dma_interrupt()
850 edmac->edma->hw_submit(edmac); in ep93xx_dma_tx_submit()
875 if (!edmac->edma->m2m) { in ep93xx_dma_alloc_chan_resources()
910 ret = edmac->edma->hw_setup(edmac); in ep93xx_dma_alloc_chan_resources()
962 edmac->edma->hw_shutdown(edmac); in ep93xx_dma_free_chan_resources()
1044 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { in ep93xx_dma_prep_slave_sg()
1125 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { in ep93xx_dma_prep_dma_cyclic()
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dti-edma.txt1 Texas Instruments eDMA
20 - reg: Memory map of eDMA CC
24 - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
30 - ti,hwmods: Name of the hwmods associated to the eDMA CC.
40 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
42 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
46 Single uint32 for EDMA with 32 channels, array of two uint32 for
47 EDMA with 64 channels. See example and
61 - reg: Memory map of eDMA TC
67 - ti,hwmods: Name of the hwmods associated to the eDMA TC.
[all …]
H A Dfsl,edma.yaml4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
25 - fsl,imx8qm-edma
29 - const: fsl,ls1028a-edma
30 - const: fsl,vf610-edma
64 eDMA are implemented in big endian mode, otherwise in little mode.
83 - fsl,imx8qm-edma
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H A Dti-dma-crossbar.txt5 "ti,am335x-edma-crossbar" for AM335x and AM437x
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
20 memcpy channels in eDMA.
26 For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
29 When mux 0 is used the DMA channel can be requested directly from edma node.
/openbmc/linux/drivers/dma/dw-edma/
H A DMakefile3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o \
6 dw-edma-objs := dw-edma-core.o \
7 dw-edma-v0-core.o \
8 dw-hdma-v0-core.o $(dw-edma-y)
9 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
H A DKconfig4 tristate "Synopsys DesignWare eDMA controller driver"
9 Support the Synopsys DesignWare eDMA controller, normally
15 tristate "Synopsys DesignWare eDMA PCIe driver"
19 eDMA controller and an endpoint PCIe device. This also serves
H A Ddw-edma-pcie.c4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
18 #include "dw-edma-core.h"
40 /* eDMA registers location */
42 /* eDMA memory linked list location */
45 /* eDMA memory data location */
56 /* eDMA registers location */
60 /* eDMA memory linked list location */
73 /* eDMA memory data location */
196 pci_err(pdev, "eDMA BAR I/O remapping failed\n"); in dw_edma_pcie_probe()
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H A Ddw-edma-v0-debugfs.c4 * Synopsys DesignWare eDMA v0 core
12 #include "dw-edma-v0-debugfs.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-core.h"
143 /* eDMA global registers */ in dw_edma_debugfs_regs_wr()
148 /* eDMA interrupts registers */ in dw_edma_debugfs_regs_wr()
164 /* eDMA channel context grouping */ in dw_edma_debugfs_regs_wr()
205 /* eDMA global registers */ in dw_edma_debugfs_regs_rd()
210 /* eDMA interrupts registers */ in dw_edma_debugfs_regs_rd()
227 /* eDMA channel context grouping */ in dw_edma_debugfs_regs_rd()
H A Ddw-edma-v0-core.h4 * Synopsys DesignWare eDMA v0 core
12 #include <linux/dma/edma.h>
14 /* eDMA core register */
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-designware.c15 #include <linux/dma/edma.h>
129 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ in dw_pcie_get_resources()
146 /* eDMA region can be mapped to a custom base address */ in dw_pcie_get_resources()
147 if (!pci->edma.reg_base) { in dw_pcie_get_resources()
150 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
151 if (IS_ERR(pci->edma.reg_base)) in dw_pcie_get_resources()
152 return PTR_ERR(pci->edma.reg_base); in dw_pcie_get_resources()
154 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; in dw_pcie_get_resources()
851 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); in dw_pcie_readl_dma()
853 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); in dw_pcie_readl_dma()
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/openbmc/linux/include/linux/dma/
H A Dedma.h4 * Synopsys DesignWare eDMA core driver
30 * struct dw_edma_core_ops - platform-specific eDMA methods
31 * @irq_vector: Get IRQ number of the passed eDMA channel. Note the
33 * numbering with the eDMA write channels being placed
38 * the DW PCIe RP/EP controller with the DW eDMA device in
56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
57 * @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint
64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
65 * @dev: struct device of the eDMA controller
/openbmc/u-boot/arch/arm/dts/
H A Ddm816x.dtsi134 edma: edma@49000000 { label
181 dmas = <&edma 52>;
198 dmas = <&edma 58 &edma 59>;
209 dmas = <&edma 60 &edma 61>;
300 dmas = <&edma 16 &edma 17
301 &edma 18 &edma 19
302 &edma 20 &edma 21
303 &edma 22 &edma 23>;
313 dmas = <&edma 24 &edma 25>;
377 dmas = <&edma 26 &edma 27>;
[all …]
H A Dam33xx.dtsi240 compatible = "ti,am335x-edma-crossbar";
244 dma-masters = <&edma>;
259 edma: edma@49000000 { label
273 ti,edma-memcpy-channels = <20 21>;
351 dmas = <&edma 26 0>, <&edma 27 0>;
362 dmas = <&edma 28 0>, <&edma 29 0>;
373 dmas = <&edma 30 0>, <&edma 31 0>;
452 dmas = <&edma 2 0
453 &edma 3 0>;
596 dmas = <&edma 16 0
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddm814x.dtsi267 dmas = <&edma 16 0 &edma 17 0
268 &edma 18 0 &edma 19 0
269 &edma 20 0 &edma 21 0
270 &edma 22 0 &edma 23 0>;
284 dmas = <&edma 42 0 &edma 43 0
285 &edma 44 0 &edma 45 0>;
289 /* Board must configure dmas with edma_xbar for EDMA */
342 dmas = <&edma 26 0 &edma 27 0>;
352 dmas = <&edma 28 0 &edma 29 0>;
362 dmas = <&edma 30 0 &edma 31 0>;
[all …]
H A Ddm816x.dtsi149 edma: dma@0 { label
162 ti,edma-memcpy-channels = <20 21>;
296 dmas = <&edma 52 0>;
418 dmas = <&edma 16 0 &edma 17 0
419 &edma 18 0 &edma 19 0
420 &edma 20 0 &edma 21 0
421 &edma 22 0 &edma 23 0>;
431 dmas = <&edma 24 0 &edma 25 0>;
531 dmas = <&edma 26 0 &edma 27 0>;
541 dmas = <&edma 28 0 &edma 29 0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
74 normally mapped to the 0x0 address of this region, while eDMA
78 Platform-specific eDMA registers. Some platforms may have eDMA
135 Indicates that the eDMA Tx/Rx transfer is complete or that an
136 error has occurred on the corresponding channel. eDMA can have
137 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
138 to 16 IRQ signals all together. Write eDMA channels shall go
H A Dsnps,dw-pcie.yaml56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
83 normally mapped to the 0x0 address of this region, while eDMA
87 Platform-specific eDMA registers. Some platforms may have eDMA
144 Indicates that the eDMA Tx/Rx transfer is complete or that an
145 error has occurred on the corresponding channel. eDMA can have
146 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
147 to 16 IRQ signals all together. Write eDMA channels shall go
/openbmc/linux/sound/soc/ti/
H A Dedma-pcm.c3 * edma-pcm.c - eDMA PCM driver using dmaengine for AM3xxx, AM4xxx
19 #include "edma-pcm.h"
31 .periods_max = 19, /* Limit by edma dmaengine driver */
62 MODULE_DESCRIPTION("eDMA PCM ASoC platform driver");
/openbmc/linux/include/linux/platform_data/
H A Ddma-mcf-edma.h3 * Freescale eDMA platform data, ColdFire SoC's family.
27 * struct mcf_edma_platform_data - platform specific data for eDMA engine
29 * @ver The eDMA module version.
30 * @dma_channels The number of eDMA channels.
H A Dedma.h3 * TI EDMA definitions
22 * buffer or for several discontiguous smaller buffers. An EDMA transfer
28 * The EDMA Channel Controller (CC) maps requests from channels into physical
62 /* platform_data for EDMA driver */

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