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/openbmc/qemu/target/xtensa/
H A Dtranslate.c853 uint32_t coprocessor = 0; in disas_xtensa_insn() local
957 coprocessor |= ops->coprocessor; in disas_xtensa_insn()
1053 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) { in disas_xtensa_insn()
1499 /* TODO: GPIO32 may be a part of coprocessor */ in translate_clrb_expstate()
1981 /* TODO: GPIO32 may be a part of coprocessor */ in translate_read_impwire()
2158 /* TODO: GPIO32 may be a part of coprocessor */ in translate_setb_expstate()
2436 /* TODO: GPIO32 may be a part of coprocessor */ in translate_wrmsk_expstate()
6629 .coprocessor = 0x1,
6633 .coprocessor = 0x1,
6638 .coprocessor = 0x1,
[all …]
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dpcie_function.hpp32 Coprocessor, enumerator
71 {DeviceClass::Coprocessor, "Coprocessor"},
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie-asm.h16 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
17 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
30 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
71 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
H A Dtie.h19 /* Basic parameters of each coprocessor: */
24 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
42 /* Save area for non-coprocessor optional and custom (TIE) state: */
62 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
/openbmc/qemu/docs/system/arm/
H A Dmax78000.rst6 The max78000 is a Cortex-M4 based SOC with a RISC-V coprocessor. The RISC-V coprocessor is not supp…
H A Dnuvoton.rst82 * Coprocessor
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie.h19 /* Basic parameters of each coprocessor: */
24 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
42 /* Save area for non-coprocessor optional and custom (TIE) state: */
62 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
H A Dtie-asm.h16 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
17 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
37 * Macro to save all non-coprocessor (extra) custom TIE and optional state
101 * Macro to restore all non-coprocessor (extra) custom TIE and optional state
/openbmc/qemu/target/arm/tcg/
H A Dm-nocp.decode23 # range of coprocessor-space encodings, with the exception of
28 # decoding FP instructions which are in the coprocessor space).
29 # If the coprocessor is not present or disabled then we will generate
/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h155 msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
157 msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
256 /* Disable coprocessor traps */
258 msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
259 msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dtie-asm.h16 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
17 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
36 * Macro to store all non-coprocessor (extra) custom TIE and optional state
90 * Macro to load all non-coprocessor (extra) custom TIE and optional state
H A Dtie.h19 /* Save area for non-coprocessor optional and custom (TIE) state: */
39 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DPCIeFunction.interface.yaml75 - name: Coprocessor
77 A coprocessor
/openbmc/u-boot/arch/mips/include/asm/
H A Disadep.h5 * of Coprocessor 0 registers.
H A Dmipsregs.h34 * Coprocessor 0 register names
92 * Coprocessor 0 Set 1 register names
99 * Coprocessor 0 Set 2 register names
104 * Coprocessor 0 Set 3 register names
317 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
327 * Bitfields and bit numbers in the coprocessor 0 cause register.
365 * Bits in the coprocessor 0 EBase register.
370 * Bits in the coprocessor 0 config register.
463 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
699 * Coprocessor 1 (FPU) register names
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/openbmc/qemu/target/mips/tcg/
H A Dexception.c108 [EXCP_CpU] = "coprocessor unusable",
122 [EXCP_C2E] = "precise coprocessor 2",
H A Dtranslate.h66 /* Coprocessor 1 (rs field) */
148 * and emit a 'coprocessor unusable' exception.
/openbmc/qemu/target/arm/
H A Dcpu-sysregs.h10 * Following is similar to the coprocessor regs encodings, but with an argument
H A Dcpregs.h141 * Interface for defining coprocessor registers.
147 * When looking up a coprocessor register we look for it
149 * coprocessor number
173 * To enable banking of coprocessor registers depending on ns-bit we
195 * version used as a key for the coprocessor register hashtable
841 * Access functions for coprocessor registers. These cannot fail and
847 /* Access permission check functions for coprocessor registers. */
861 /* Definition of an ARM coprocessor register */
866 * Location of register: coprocessor number and (crn,crm,opc1,opc2)
963 * coprocessor state to the kernel for KVM or out for
[all …]
/openbmc/qemu/bsd-user/arm/
H A Dtarget_arch_cpu.h60 * o Both modes implement coprocessor instructions, which we don't in target_cpu_loop()
61 * do here. FreeBSD just implements them for the VFP coprocessor in target_cpu_loop()
/openbmc/u-boot/arch/nds32/cpu/n1213/ae3xx/
H A Dlowlevel_init.S128 * Some of Andes CPU version support FPU coprocessor, if so,
/openbmc/u-boot/arch/x86/include/asm/
H A Dprocessor-flags.h30 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DPCIeFunction.v1_6_0.json57 "Coprocessor",
64 "Coprocessor": "A coprocessor.", string
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DPCIeFunction.v1_6_0.json57 "Coprocessor",
64 "Coprocessor": "A coprocessor.", string
/openbmc/qemu/bsd-user/freebsd/
H A Dtarget_os_siginfo.h133 #define TARGET_ILL_COPROC (7) /* Coprocessor error. */

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