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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dbrcm,bcm6345-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM6345 reset controller
9 description: This document describes the BCM6345 reset controller.
12 - Álvaro Fernández Rojas <noltari@gmail.com>
16 const: brcm,bcm6345-reset
21 "#reset-cells":
25 - compatible
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm3380.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm3380-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/bcm3380-reset.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
22 u-boot,dm-pre-reloc;
25 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
28 u-boot,dm-pre-reloc;
32 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm6318.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6318-clock.h>
7 #include <dt-bindings/dma/bcm6318-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm6318-power-domain.h>
10 #include <dt-bindings/reset/bcm6318-reset.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 u-boot,dm-pre-reloc;
27 compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm6368.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6368-clock.h>
7 #include <dt-bindings/dma/bcm6368-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6368-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm63268.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm63268-clock.h>
7 #include <dt-bindings/dma/bcm63268-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm63268-power-domain.h>
10 #include <dt-bindings/reset/bcm63268-reset.h>
23 #address-cells = <1>;
24 #size-cells = <0>;
25 u-boot,dm-pre-reloc;
28 compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm6348.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6348-clock.h>
7 #include <dt-bindings/dma/bcm6348-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6348-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6362.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6362-clock.h>
7 #include <dt-bindings/dma/bcm6362-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm6362-power-domain.h>
10 #include <dt-bindings/reset/bcm6362-reset.h>
23 #address-cells = <1>;
24 #size-cells = <0>;
25 u-boot,dm-pre-reloc;
28 compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm6358.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6358-clock.h>
7 #include <dt-bindings/dma/bcm6358-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6358-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6338.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6338-clock.h>
7 #include <dt-bindings/dma/bcm6338-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6338-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6328.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6328-clock.h>
7 #include <dt-bindings/dma/bcm6328-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm6328-power-domain.h>
10 #include <dt-bindings/reset/bcm6328-reset.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 u-boot,dm-pre-reloc;
27 compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm63268.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm63268-clock.h"
4 #include "dt-bindings/reset/bcm63268-reset.h"
5 #include "dt-bindings/soc/bcm63268-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
[all …]
H A Dbcm6358.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6358-clock.h"
4 #include "dt-bindings/reset/bcm6358-reset.h"
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 mips-hpt-frequency = <150000000>;
31 periph_osc: periph-osc {
32 compatible = "fixed-clock";
[all …]
H A Dbcm6362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6362-clock.h"
4 #include "dt-bindings/reset/bcm6362-reset.h"
5 #include "dt-bindings/soc/bcm6362-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
[all …]
H A Dbcm6368.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6368-clock.h"
4 #include "dt-bindings/reset/bcm6368-reset.h"
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 mips-hpt-frequency = <200000000>;
31 periph_osc: periph-osc {
32 compatible = "fixed-clock";
[all …]
H A Dbcm6328.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6328-clock.h"
4 #include "dt-bindings/reset/bcm6328-reset.h"
5 #include "dt-bindings/soc/bcm6328-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <160000000>;
32 periph_osc: periph-osc {
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-bcm6345.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BCM6345 Reset Controller Driver
13 #include <linux/reset-controller.h>
38 spin_lock_irqsave(&bcm6345_reset->lock, flags); in bcm6345_reset_update()
39 val = __raw_readl(bcm6345_reset->base); in bcm6345_reset_update()
44 __raw_writel(val, bcm6345_reset->base); in bcm6345_reset_update()
45 spin_unlock_irqrestore(&bcm6345_reset->lock, flags); in bcm6345_reset_update()
71 * Ensure component is taken out reset state by sleeping also after in bcm6345_reset_reset()
72 * deasserting the reset. Otherwise, the component may not be ready in bcm6345_reset_reset()
86 return !(__raw_readl(bcm6345_reset->base) & BIT(id)); in bcm6345_reset_status()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += hisilicon/
4 obj-y += starfive/
5 obj-$(CONFIG_ARCH_STI) += sti/
6 obj-$(CONFIG_ARCH_TEGRA) += tegra/
7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
[all …]
/openbmc/u-boot/drivers/reset/
H A DKconfig1 menu "Reset Controller Support"
4 bool "Enable reset controllers using Driver Model"
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
12 although driving such reset isgnals using GPIOs may be more
16 bool "Enable the sandbox reset test driver"
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
[all …]
H A Dreset-bcm6345.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Derived from linux/arch/mips/bcm63xx/reset.c:
12 #include <reset-uclass.h>
23 struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev); in bcm6345_reset_assert()
25 clrbits_be32(priv->regs, BIT(rst->id)); in bcm6345_reset_assert()
33 struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev); in bcm6345_reset_deassert()
35 setbits_be32(priv->regs, BIT(rst->id)); in bcm6345_reset_deassert()
48 if (rst->id >= MAX_RESETS) in bcm6345_reset_request()
49 return -EINVAL; in bcm6345_reset_request()
62 { .compatible = "brcm,bcm6345-reset" },
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_DM_RESET) += reset-uclass.o
7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
8 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
9 obj-$(CONFIG_STI_RESET) += sti-reset.o
10 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
11 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
12 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
13 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
14 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
[all …]
/openbmc/u-boot/drivers/watchdog/
H A DKconfig4 bool "Enable U-Boot watchdog reset"
6 This option enables U-Boot watchdog support where U-Boot is using
7 watchdog_reset function to service watchdog device in U-Boot. Enable
8 this option if you want to service enabled watchdog by U-Boot. Disable
9 this option if you want U-Boot to start watchdog but never service it.
15 bool "Disable reset watchdog"
17 Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
18 that the watchdog will not be fed in u-boot.
57 start, restart, stop and reset (expire immediately).
84 The watchdog timer is stopped when initialized. It performs reset, either
[all …]
H A Dbcm6345_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
35 writel(WDT_CTL_START1_MASK, priv->regs + WDT_CTL_REG); in bcm6345_wdt_reset()
36 writel(WDT_CTL_START2_MASK, priv->regs + WDT_CTL_REG); in bcm6345_wdt_reset()
53 writel(timeout, priv->regs + WDT_VAL_REG); in bcm6345_wdt_start()
67 writel(WDT_CTL_STOP1_MASK, priv->regs + WDT_CTL_REG); in bcm6345_wdt_stop()
68 writel(WDT_CTL_STOP2_MASK, priv->regs + WDT_CTL_REG); in bcm6345_wdt_stop()
75 .reset = bcm6345_wdt_reset,
81 { .compatible = "brcm,bcm6345-wdt" },
89 priv->regs = dev_remap_addr(dev); in bcm6345_wdt_probe()
90 if (!priv->regs) in bcm6345_wdt_probe()
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4908.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
[all …]

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