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Searched full:clk_top_armpll_div_pll1 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183.dtsi286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,cci.yaml69 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8183-clk.h165 #define CLK_TOP_ARMPLL_DIV_PLL1 129 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8183.c645 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),