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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,spmi-clkdiv.yaml54 #size-cells = <0>;
58 reg = <0x5b00>;
/openbmc/linux/drivers/media/i2c/
H A Dov8856.c26 #define OV8856_REG_CHIP_ID 0x300a
27 #define OV8856_CHIP_ID 0x00885a
29 #define OV8856_REG_MODE_SELECT 0x0100
30 #define OV8856_MODE_STANDBY 0x00
31 #define OV8856_MODE_STREAMING 0x01
34 #define OV8856_2A_MODULE 0x01
35 #define OV8856_1B_MODULE 0x02
37 /* the OTP read-out buffer is at 0x7000 and 0xf is the offset
40 #define OV8856_MODULE_REVISION 0x700f
41 #define OV8856_OTP_MODE_CTRL 0x3d84
[all …]
H A Dov5670.c22 #define OV5670_REG_CHIP_ID 0x300a
23 #define OV5670_CHIP_ID 0x005670
25 #define OV5670_REG_MODE_SELECT 0x0100
26 #define OV5670_MODE_STANDBY 0x00
27 #define OV5670_MODE_STREAMING 0x01
29 #define OV5670_REG_SOFTWARE_RST 0x0103
30 #define OV5670_SOFTWARE_RST 0x01
32 #define OV5670_MIPI_SC_CTRL0_REG 0x3018
39 #define OV5670_REG_VTS 0x380e
40 #define OV5670_VTS_30FPS 0x0808 /* default for 30 fps */
[all …]
H A Dov5695.c30 #define CHIP_ID 0x005695
31 #define OV5695_REG_CHIP_ID 0x300a
33 #define OV5695_REG_CTRL_MODE 0x0100
34 #define OV5695_MODE_SW_STANDBY 0x0
35 #define OV5695_MODE_STREAMING BIT(0)
37 #define OV5695_REG_EXPOSURE 0x3500
40 #define OV5695_VTS_MAX 0x7fff
42 #define OV5695_REG_ANALOG_GAIN 0x3509
43 #define ANALOG_GAIN_MIN 0x10
44 #define ANALOG_GAIN_MAX 0xf8
[all …]
H A Dov5675.c28 #define OV5675_REG_CHIP_ID 0x300a
29 #define OV5675_CHIP_ID 0x5675
31 #define OV5675_REG_MODE_SELECT 0x0100
32 #define OV5675_MODE_STANDBY 0x00
33 #define OV5675_MODE_STREAMING 0x01
36 #define OV5675_REG_VTS 0x380e
37 #define OV5675_VTS_30FPS 0x07e4
38 #define OV5675_VTS_30FPS_MIN 0x07e4
39 #define OV5675_VTS_MAX 0x7fff
42 #define OV5675_REG_HTS 0x380c
[all …]
H A Dov8858.c36 #define OV8858_REG_ADDR_MASK 0xffff
41 #define OV8858_REG_SC_CTRL0100 OV8858_REG_8BIT(0x0100)
42 #define OV8858_MODE_SW_STANDBY 0x0
43 #define OV8858_MODE_STREAMING 0x1
45 #define OV8858_REG_CHIP_ID OV8858_REG_24BIT(0x300a)
46 #define OV8858_CHIP_ID 0x008858
48 #define OV8858_REG_SUB_ID OV8858_REG_8BIT(0x302a)
49 #define OV8858_R1A 0xb0
50 #define OV8858_R2A 0xb2
52 #define OV8858_REG_LONG_EXPO OV8858_REG_24BIT(0x3500)
[all …]
H A Dov08x40.c17 #define OV08X40_REG_MODE_SELECT 0x0100
18 #define OV08X40_MODE_STANDBY 0x00
19 #define OV08X40_MODE_STREAMING 0x01
21 #define OV08X40_REG_AO_STANDBY 0x1000
22 #define OV08X40_AO_STREAMING 0x04
24 #define OV08X40_REG_MS_SELECT 0x1001
25 #define OV08X40_MS_STANDBY 0x00
26 #define OV08X40_MS_STREAMING 0x04
28 #define OV08X40_REG_SOFTWARE_RST 0x0103
29 #define OV08X40_SOFTWARE_RST 0x01
[all …]
/openbmc/linux/drivers/acpi/acpica/
H A Damlcode.h17 #define AML_ZERO_OP (u16) 0x00
18 #define AML_ONE_OP (u16) 0x01
19 #define AML_ALIAS_OP (u16) 0x06
20 #define AML_NAME_OP (u16) 0x08
21 #define AML_BYTE_OP (u16) 0x0a
22 #define AML_WORD_OP (u16) 0x0b
23 #define AML_DWORD_OP (u16) 0x0c
24 #define AML_STRING_OP (u16) 0x0d
25 #define AML_QWORD_OP (u16) 0x0e /* ACPI 2.0 */
26 #define AML_SCOPE_OP (u16) 0x10
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dstv6111.c37 { 2572, 0 },
73 { 1548, 0 },
109 { 4870, 0x3000 },
110 { 4850, 0x3C00 },
111 { 4800, 0x4500 },
112 { 4750, 0x4800 },
113 { 4700, 0x4B00 },
114 { 4650, 0x4D00 },
115 { 4600, 0x4F00 },
116 { 4550, 0x5100 },
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
H A Dstm32h7-pinfunc.h4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
13 #define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/openbmc/linux/sound/pci/hda/
H A Dpatch_cirrus.c67 #define CS420X_VENDOR_NID 0x11
68 #define CS_DIG_OUT1_PIN_NID 0x10
69 #define CS_DIG_OUT2_PIN_NID 0x15
70 #define CS_DMIC1_PIN_NID 0x0e
71 #define CS_DMIC2_PIN_NID 0x12
74 #define IDX_SPDIF_STAT 0x0000
75 #define IDX_SPDIF_CTL 0x0001
76 #define IDX_ADC_CFG 0x0002
78 * 0 = immediate,
83 #define CS_COEF_ADC_SZC_MASK (3 << 0)
[all …]
/openbmc/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/openbmc/linux/arch/ia64/kernel/
H A Divt.S37 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
62 #if 0
65 # define PSR_DEFAULT_BITS 0
68 #if 0
92 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
94 DBG_FAULT(0)
149 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
150 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
157 ld8 r17=[r17] // get *pgd (may be 0)
164 (p7) ld8 r29=[r28] // get *pud (may be 0)
[all …]
/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz_common.c35 #define MIB_COUNTER_NUM 0x20
114 { 0x00, "rx" },
115 { 0x01, "rx_hi" },
116 { 0x02, "rx_undersize" },
117 { 0x03, "rx_fragments" },
118 { 0x04, "rx_oversize" },
119 { 0x05, "rx_jabbers" },
120 { 0x06, "rx_symbol_err" },
121 { 0x07, "rx_crc_err" },
122 { 0x08, "rx_align_err" },
[all …]
/openbmc/linux/drivers/input/joystick/
H A Dxpad.c80 #define MAP_DPAD_TO_BUTTONS (1 << 0)
90 #define XTYPE_XBOX 0
101 #define PKT_XB 0
131 { 0x0079, 0x18d4, "GPD Win 2 X-Box Controller", 0, XTYPE_XBOX360 },
132 { 0x03eb, 0xff01, "Wooting One (Legacy)", 0, XTYPE_XBOX360 },
133 { 0x03eb, 0xff02, "Wooting Two (Legacy)", 0, XTYPE_XBOX360 },
134 { 0x03f0, 0x038D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wired */
135 { 0x03f0, 0x048D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wireless */
136 { 0x03f0, 0x0495, "HyperX Clutch Gladiate", 0, XTYPE_XBOXONE },
137 { 0x03f0, 0x07A0, "HyperX Clutch Gladiate RGB", 0, XTYPE_XBOXONE },
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc26 C(0x1a00, AR, RR_a, Z, r1, r2, new, r1_32, add, adds32)
27 C(0xb9f8, ARK, RRF_a, DO, r2, r3, new, r1_32, add, adds32)
28 C(0x5a00, A, RX_a, Z, r1, m2_32s, new, r1_32, add, adds32)
29 C(0xe35a, AY, RXY_a, LD, r1, m2_32s, new, r1_32, add, adds32)
30 C(0xb908, AGR, RRE, Z, r1, r2, r1, 0, add, adds64)
31 C(0xb918, AGFR, RRE, Z, r1, r2_32s, r1, 0, add, adds64)
32 C(0xb9e8, AGRK, RRF_a, DO, r2, r3, r1, 0, add, adds64)
33 C(0xe308, AG, RXY_a, Z, r1, m2_64, r1, 0, add, adds64)
34 C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64)
35 F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_4_3_offset.h29 // base address: 0x8000
30 …GRBM_CNTL 0x0000
31 …e regGRBM_CNTL_BASE_IDX 0
32 …GRBM_SKEW_CNTL 0x0001
33 …e regGRBM_SKEW_CNTL_BASE_IDX 0
34 …GRBM_STATUS2 0x0002
35 …e regGRBM_STATUS2_BASE_IDX 0
36 …GRBM_PWR_CNTL 0x0003
37 …e regGRBM_PWR_CNTL_BASE_IDX 0
38 …GRBM_STATUS 0x0004
[all …]
H A Dgc_9_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]

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