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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dbrcm,b53.yaml144 #size-cells = <0>;
152 #size-cells = <0>;
154 port@0 {
155 reg = <0>;
196 reg = <0x36000 0x1000>,
197 <0x3f308 0x8>,
198 <0x3f410 0xc>;
229 #size-cells = <0>;
231 port@0 {
233 reg = <0>;
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_2_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_1_3_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_1_0_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_0_1_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]