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/openbmc/u-boot/include/configs/
H A Darndale.h12 "fdtfile=exynos5250-arndale.dtb\0"
27 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
31 #define CONFIG_IRAM_STACK 0x02050000
41 #define CONFIG_S5P_PA_SYSRAM 0x02020000
45 #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7100-audclk.yaml51 reg = <0x10480000 0x10000>;
/openbmc/linux/Documentation/devicetree/bindings/devfreq/event/
H A Dsamsung,exynos-ppmu.yaml43 '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
80 reg = <0x106a0000 0x2000>;
103 reg = <0x112a0000 0x2000>;
118 reg = <0x10480000 0x2000>;
123 reg = <0x10490000 0x2000>;
134 reg = <0x104a0000 0x2000>;
139 reg = <0x104b0000 0x2000>;
144 reg = <0x104c0000 0x2000>;
149 reg = <0x104d0000 0x2000>;
158 reg = <0x106a0000 0x2000>;
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4.dtsi27 reg = <0x10440000 0x1000>;
34 cpu-offset = <0x4000>;
35 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
40 reg = <0x13800000 0x3c>;
41 id = <0>;
46 reg = <0x13810000 0x3c>;
52 reg = <0x13820000 0x3c>;
58 reg = <0x13830000 0x3c>;
64 reg = <0x13840000 0x3c>;
70 #size-cells = <0>;
[all …]
/openbmc/u-boot/board/terasic/de0-nano-soc/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
11 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
12 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
18 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
35 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
44 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
45 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
[all …]
/openbmc/u-boot/board/ebv/socrates/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/devboards/dbm-soc1/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/samtec/vining_fpga/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/sr1500/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/terasic/de1-soc/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/terasic/sockit/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/is1/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/altera/cyclone5-socdk/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/openbmc/u-boot/board/terasic/de10-nano/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/altera/arria5-socdk/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/openbmc/qemu/hw/arm/
H A Dexynos4210.c41 #define EXYNOS4210_CHIPID_ADDR 0x10000000
44 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
47 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000
50 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000
53 #define EXYNOS4210_I2C_SHIFT 0x00010000
54 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000
60 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000
61 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000
62 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000
63 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4.dtsi68 reg = <0x03810000 0x0c>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
110 reg = <0x10023c40 0x20>;
111 #power-domain-cells = <0>;
117 reg = <0x10023c60 0x20>;
118 #power-domain-cells = <0>;
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]