1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/errno.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/random.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/eq.h>
42 #include <linux/debugfs.h>
43
44 #include "mlx5_core.h"
45 #include "lib/eq.h"
46 #include "lib/tout.h"
47 #define CREATE_TRACE_POINTS
48 #include "diag/cmd_tracepoint.h"
49
50 struct mlx5_ifc_mbox_out_bits {
51 u8 status[0x8];
52 u8 reserved_at_8[0x18];
53
54 u8 syndrome[0x20];
55
56 u8 reserved_at_40[0x40];
57 };
58
59 struct mlx5_ifc_mbox_in_bits {
60 u8 opcode[0x10];
61 u8 uid[0x10];
62
63 u8 reserved_at_20[0x10];
64 u8 op_mod[0x10];
65
66 u8 reserved_at_40[0x40];
67 };
68
69 enum {
70 CMD_IF_REV = 5,
71 };
72
73 enum {
74 CMD_MODE_POLLING,
75 CMD_MODE_EVENTS
76 };
77
78 enum {
79 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
80 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
81 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
82 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
83 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
84 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
85 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
86 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
87 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
88 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
89 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
90 };
91
in_to_opcode(void * in)92 static u16 in_to_opcode(void *in)
93 {
94 return MLX5_GET(mbox_in, in, opcode);
95 }
96
97 /* Returns true for opcodes that might be triggered very frequently and throttle
98 * the command interface. Limit their command slots usage.
99 */
mlx5_cmd_is_throttle_opcode(u16 op)100 static bool mlx5_cmd_is_throttle_opcode(u16 op)
101 {
102 switch (op) {
103 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
104 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
105 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
106 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
107 case MLX5_CMD_OP_SYNC_CRYPTO:
108 return true;
109 }
110 return false;
111 }
112
113 static struct mlx5_cmd_work_ent *
cmd_alloc_ent(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)114 cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,
115 struct mlx5_cmd_msg *out, void *uout, int uout_size,
116 mlx5_cmd_cbk_t cbk, void *context, int page_queue)
117 {
118 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
119 struct mlx5_cmd_work_ent *ent;
120
121 ent = kzalloc(sizeof(*ent), alloc_flags);
122 if (!ent)
123 return ERR_PTR(-ENOMEM);
124
125 ent->idx = -EINVAL;
126 ent->in = in;
127 ent->out = out;
128 ent->uout = uout;
129 ent->uout_size = uout_size;
130 ent->callback = cbk;
131 ent->context = context;
132 ent->cmd = cmd;
133 ent->page_queue = page_queue;
134 ent->op = in_to_opcode(in->first.data);
135 refcount_set(&ent->refcnt, 1);
136
137 return ent;
138 }
139
cmd_free_ent(struct mlx5_cmd_work_ent * ent)140 static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)
141 {
142 kfree(ent);
143 }
144
alloc_token(struct mlx5_cmd * cmd)145 static u8 alloc_token(struct mlx5_cmd *cmd)
146 {
147 u8 token;
148
149 spin_lock(&cmd->token_lock);
150 cmd->token++;
151 if (cmd->token == 0)
152 cmd->token++;
153 token = cmd->token;
154 spin_unlock(&cmd->token_lock);
155
156 return token;
157 }
158
cmd_alloc_index(struct mlx5_cmd * cmd,struct mlx5_cmd_work_ent * ent)159 static int cmd_alloc_index(struct mlx5_cmd *cmd, struct mlx5_cmd_work_ent *ent)
160 {
161 unsigned long flags;
162 int ret;
163
164 spin_lock_irqsave(&cmd->alloc_lock, flags);
165 ret = find_first_bit(&cmd->vars.bitmask, cmd->vars.max_reg_cmds);
166 if (ret < cmd->vars.max_reg_cmds) {
167 clear_bit(ret, &cmd->vars.bitmask);
168 ent->idx = ret;
169 cmd->ent_arr[ent->idx] = ent;
170 }
171 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
172
173 return ret < cmd->vars.max_reg_cmds ? ret : -ENOMEM;
174 }
175
cmd_free_index(struct mlx5_cmd * cmd,int idx)176 static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
177 {
178 lockdep_assert_held(&cmd->alloc_lock);
179 set_bit(idx, &cmd->vars.bitmask);
180 }
181
cmd_ent_get(struct mlx5_cmd_work_ent * ent)182 static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
183 {
184 refcount_inc(&ent->refcnt);
185 }
186
cmd_ent_put(struct mlx5_cmd_work_ent * ent)187 static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
188 {
189 struct mlx5_cmd *cmd = ent->cmd;
190 unsigned long flags;
191
192 spin_lock_irqsave(&cmd->alloc_lock, flags);
193 if (!refcount_dec_and_test(&ent->refcnt))
194 goto out;
195
196 if (ent->idx >= 0) {
197 cmd_free_index(cmd, ent->idx);
198 up(ent->page_queue ? &cmd->vars.pages_sem : &cmd->vars.sem);
199 }
200
201 cmd_free_ent(ent);
202 out:
203 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
204 }
205
get_inst(struct mlx5_cmd * cmd,int idx)206 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
207 {
208 return cmd->cmd_buf + (idx << cmd->vars.log_stride);
209 }
210
mlx5_calc_cmd_blocks(struct mlx5_cmd_msg * msg)211 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
212 {
213 int size = msg->len;
214 int blen = size - min_t(int, sizeof(msg->first.data), size);
215
216 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
217 }
218
xor8_buf(void * buf,size_t offset,int len)219 static u8 xor8_buf(void *buf, size_t offset, int len)
220 {
221 u8 *ptr = buf;
222 u8 sum = 0;
223 int i;
224 int end = len + offset;
225
226 for (i = offset; i < end; i++)
227 sum ^= ptr[i];
228
229 return sum;
230 }
231
verify_block_sig(struct mlx5_cmd_prot_block * block)232 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
233 {
234 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
235 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
236
237 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
238 return -EHWPOISON;
239
240 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
241 return -EHWPOISON;
242
243 return 0;
244 }
245
calc_block_sig(struct mlx5_cmd_prot_block * block)246 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
247 {
248 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
249 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
250
251 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
252 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
253 }
254
calc_chain_sig(struct mlx5_cmd_msg * msg)255 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
256 {
257 struct mlx5_cmd_mailbox *next = msg->next;
258 int n = mlx5_calc_cmd_blocks(msg);
259 int i = 0;
260
261 for (i = 0; i < n && next; i++) {
262 calc_block_sig(next->buf);
263 next = next->next;
264 }
265 }
266
set_signature(struct mlx5_cmd_work_ent * ent,int csum)267 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
268 {
269 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
270 if (csum) {
271 calc_chain_sig(ent->in);
272 calc_chain_sig(ent->out);
273 }
274 }
275
poll_timeout(struct mlx5_cmd_work_ent * ent)276 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
277 {
278 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, cmd);
279 u64 cmd_to_ms = mlx5_tout_ms(dev, CMD);
280 unsigned long poll_end;
281 u8 own;
282
283 poll_end = jiffies + msecs_to_jiffies(cmd_to_ms + 1000);
284
285 do {
286 own = READ_ONCE(ent->lay->status_own);
287 if (!(own & CMD_OWNER_HW)) {
288 ent->ret = 0;
289 return;
290 }
291 cond_resched();
292 } while (time_before(jiffies, poll_end));
293
294 ent->ret = -ETIMEDOUT;
295 }
296
verify_signature(struct mlx5_cmd_work_ent * ent)297 static int verify_signature(struct mlx5_cmd_work_ent *ent)
298 {
299 struct mlx5_cmd_mailbox *next = ent->out->next;
300 int n = mlx5_calc_cmd_blocks(ent->out);
301 int err;
302 u8 sig;
303 int i = 0;
304
305 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
306 if (sig != 0xff)
307 return -EHWPOISON;
308
309 for (i = 0; i < n && next; i++) {
310 err = verify_block_sig(next->buf);
311 if (err)
312 return -EHWPOISON;
313
314 next = next->next;
315 }
316
317 return 0;
318 }
319
dump_buf(void * buf,int size,int data_only,int offset,int idx)320 static void dump_buf(void *buf, int size, int data_only, int offset, int idx)
321 {
322 __be32 *p = buf;
323 int i;
324
325 for (i = 0; i < size; i += 16) {
326 pr_debug("cmd[%d]: %03x: %08x %08x %08x %08x\n", idx, offset,
327 be32_to_cpu(p[0]), be32_to_cpu(p[1]),
328 be32_to_cpu(p[2]), be32_to_cpu(p[3]));
329 p += 4;
330 offset += 16;
331 }
332 if (!data_only)
333 pr_debug("\n");
334 }
335
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)336 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
337 u32 *synd, u8 *status)
338 {
339 *synd = 0;
340 *status = 0;
341
342 switch (op) {
343 case MLX5_CMD_OP_TEARDOWN_HCA:
344 case MLX5_CMD_OP_DISABLE_HCA:
345 case MLX5_CMD_OP_MANAGE_PAGES:
346 case MLX5_CMD_OP_DESTROY_MKEY:
347 case MLX5_CMD_OP_DESTROY_EQ:
348 case MLX5_CMD_OP_DESTROY_CQ:
349 case MLX5_CMD_OP_DESTROY_QP:
350 case MLX5_CMD_OP_DESTROY_PSV:
351 case MLX5_CMD_OP_DESTROY_SRQ:
352 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
353 case MLX5_CMD_OP_DESTROY_XRQ:
354 case MLX5_CMD_OP_DESTROY_DCT:
355 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
356 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
357 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
358 case MLX5_CMD_OP_DEALLOC_PD:
359 case MLX5_CMD_OP_DEALLOC_UAR:
360 case MLX5_CMD_OP_DETACH_FROM_MCG:
361 case MLX5_CMD_OP_DEALLOC_XRCD:
362 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
363 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
364 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
365 case MLX5_CMD_OP_DESTROY_LAG:
366 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
367 case MLX5_CMD_OP_DESTROY_TIR:
368 case MLX5_CMD_OP_DESTROY_SQ:
369 case MLX5_CMD_OP_DESTROY_RQ:
370 case MLX5_CMD_OP_DESTROY_RMP:
371 case MLX5_CMD_OP_DESTROY_TIS:
372 case MLX5_CMD_OP_DESTROY_RQT:
373 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
374 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
375 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
376 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
377 case MLX5_CMD_OP_2ERR_QP:
378 case MLX5_CMD_OP_2RST_QP:
379 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
380 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
381 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
382 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
383 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
384 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
385 case MLX5_CMD_OP_FPGA_DESTROY_QP:
386 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
387 case MLX5_CMD_OP_DEALLOC_MEMIC:
388 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
389 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
390 case MLX5_CMD_OP_DEALLOC_SF:
391 case MLX5_CMD_OP_DESTROY_UCTX:
392 case MLX5_CMD_OP_DESTROY_UMEM:
393 case MLX5_CMD_OP_MODIFY_RQT:
394 return MLX5_CMD_STAT_OK;
395
396 case MLX5_CMD_OP_QUERY_HCA_CAP:
397 case MLX5_CMD_OP_QUERY_ADAPTER:
398 case MLX5_CMD_OP_INIT_HCA:
399 case MLX5_CMD_OP_ENABLE_HCA:
400 case MLX5_CMD_OP_QUERY_PAGES:
401 case MLX5_CMD_OP_SET_HCA_CAP:
402 case MLX5_CMD_OP_QUERY_ISSI:
403 case MLX5_CMD_OP_SET_ISSI:
404 case MLX5_CMD_OP_CREATE_MKEY:
405 case MLX5_CMD_OP_QUERY_MKEY:
406 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
407 case MLX5_CMD_OP_CREATE_EQ:
408 case MLX5_CMD_OP_QUERY_EQ:
409 case MLX5_CMD_OP_GEN_EQE:
410 case MLX5_CMD_OP_CREATE_CQ:
411 case MLX5_CMD_OP_QUERY_CQ:
412 case MLX5_CMD_OP_MODIFY_CQ:
413 case MLX5_CMD_OP_CREATE_QP:
414 case MLX5_CMD_OP_RST2INIT_QP:
415 case MLX5_CMD_OP_INIT2RTR_QP:
416 case MLX5_CMD_OP_RTR2RTS_QP:
417 case MLX5_CMD_OP_RTS2RTS_QP:
418 case MLX5_CMD_OP_SQERR2RTS_QP:
419 case MLX5_CMD_OP_QUERY_QP:
420 case MLX5_CMD_OP_SQD_RTS_QP:
421 case MLX5_CMD_OP_INIT2INIT_QP:
422 case MLX5_CMD_OP_CREATE_PSV:
423 case MLX5_CMD_OP_CREATE_SRQ:
424 case MLX5_CMD_OP_QUERY_SRQ:
425 case MLX5_CMD_OP_ARM_RQ:
426 case MLX5_CMD_OP_CREATE_XRC_SRQ:
427 case MLX5_CMD_OP_QUERY_XRC_SRQ:
428 case MLX5_CMD_OP_ARM_XRC_SRQ:
429 case MLX5_CMD_OP_CREATE_XRQ:
430 case MLX5_CMD_OP_QUERY_XRQ:
431 case MLX5_CMD_OP_ARM_XRQ:
432 case MLX5_CMD_OP_CREATE_DCT:
433 case MLX5_CMD_OP_DRAIN_DCT:
434 case MLX5_CMD_OP_QUERY_DCT:
435 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
436 case MLX5_CMD_OP_QUERY_VPORT_STATE:
437 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
438 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
439 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
440 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
441 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
442 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
443 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
444 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
445 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
446 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
447 case MLX5_CMD_OP_QUERY_VNIC_ENV:
448 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
449 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
450 case MLX5_CMD_OP_QUERY_Q_COUNTER:
451 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
452 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
453 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
454 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
455 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
456 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
457 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
458 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
459 case MLX5_CMD_OP_ALLOC_PD:
460 case MLX5_CMD_OP_ALLOC_UAR:
461 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
462 case MLX5_CMD_OP_ACCESS_REG:
463 case MLX5_CMD_OP_ATTACH_TO_MCG:
464 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
465 case MLX5_CMD_OP_MAD_IFC:
466 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
467 case MLX5_CMD_OP_SET_MAD_DEMUX:
468 case MLX5_CMD_OP_NOP:
469 case MLX5_CMD_OP_ALLOC_XRCD:
470 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
471 case MLX5_CMD_OP_QUERY_CONG_STATUS:
472 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
473 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
474 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
475 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
476 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
477 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
478 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
479 case MLX5_CMD_OP_CREATE_LAG:
480 case MLX5_CMD_OP_MODIFY_LAG:
481 case MLX5_CMD_OP_QUERY_LAG:
482 case MLX5_CMD_OP_CREATE_VPORT_LAG:
483 case MLX5_CMD_OP_CREATE_TIR:
484 case MLX5_CMD_OP_MODIFY_TIR:
485 case MLX5_CMD_OP_QUERY_TIR:
486 case MLX5_CMD_OP_CREATE_SQ:
487 case MLX5_CMD_OP_MODIFY_SQ:
488 case MLX5_CMD_OP_QUERY_SQ:
489 case MLX5_CMD_OP_CREATE_RQ:
490 case MLX5_CMD_OP_MODIFY_RQ:
491 case MLX5_CMD_OP_QUERY_RQ:
492 case MLX5_CMD_OP_CREATE_RMP:
493 case MLX5_CMD_OP_MODIFY_RMP:
494 case MLX5_CMD_OP_QUERY_RMP:
495 case MLX5_CMD_OP_CREATE_TIS:
496 case MLX5_CMD_OP_MODIFY_TIS:
497 case MLX5_CMD_OP_QUERY_TIS:
498 case MLX5_CMD_OP_CREATE_RQT:
499 case MLX5_CMD_OP_QUERY_RQT:
500
501 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
502 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
503 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
504 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
505 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
506 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
507 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
508 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
509 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
510 case MLX5_CMD_OP_FPGA_CREATE_QP:
511 case MLX5_CMD_OP_FPGA_MODIFY_QP:
512 case MLX5_CMD_OP_FPGA_QUERY_QP:
513 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
514 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
515 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
516 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
517 case MLX5_CMD_OP_CREATE_UCTX:
518 case MLX5_CMD_OP_CREATE_UMEM:
519 case MLX5_CMD_OP_ALLOC_MEMIC:
520 case MLX5_CMD_OP_MODIFY_XRQ:
521 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
522 case MLX5_CMD_OP_QUERY_VHCA_STATE:
523 case MLX5_CMD_OP_MODIFY_VHCA_STATE:
524 case MLX5_CMD_OP_ALLOC_SF:
525 case MLX5_CMD_OP_SUSPEND_VHCA:
526 case MLX5_CMD_OP_RESUME_VHCA:
527 case MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE:
528 case MLX5_CMD_OP_SAVE_VHCA_STATE:
529 case MLX5_CMD_OP_LOAD_VHCA_STATE:
530 case MLX5_CMD_OP_SYNC_CRYPTO:
531 *status = MLX5_DRIVER_STATUS_ABORTED;
532 *synd = MLX5_DRIVER_SYND;
533 return -ENOLINK;
534 default:
535 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
536 return -EINVAL;
537 }
538 }
539
mlx5_command_str(int command)540 const char *mlx5_command_str(int command)
541 {
542 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
543
544 switch (command) {
545 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
546 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
547 MLX5_COMMAND_STR_CASE(INIT_HCA);
548 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
549 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
550 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
551 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
552 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
553 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
554 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
555 MLX5_COMMAND_STR_CASE(SET_ISSI);
556 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
557 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
558 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
559 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
560 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
561 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
562 MLX5_COMMAND_STR_CASE(CREATE_EQ);
563 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
564 MLX5_COMMAND_STR_CASE(QUERY_EQ);
565 MLX5_COMMAND_STR_CASE(GEN_EQE);
566 MLX5_COMMAND_STR_CASE(CREATE_CQ);
567 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
568 MLX5_COMMAND_STR_CASE(QUERY_CQ);
569 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
570 MLX5_COMMAND_STR_CASE(CREATE_QP);
571 MLX5_COMMAND_STR_CASE(DESTROY_QP);
572 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
573 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
574 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
575 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
576 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
577 MLX5_COMMAND_STR_CASE(2ERR_QP);
578 MLX5_COMMAND_STR_CASE(2RST_QP);
579 MLX5_COMMAND_STR_CASE(QUERY_QP);
580 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
581 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
582 MLX5_COMMAND_STR_CASE(CREATE_PSV);
583 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
584 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
585 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
586 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
587 MLX5_COMMAND_STR_CASE(ARM_RQ);
588 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
589 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
590 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
591 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
592 MLX5_COMMAND_STR_CASE(CREATE_DCT);
593 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
594 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
595 MLX5_COMMAND_STR_CASE(QUERY_DCT);
596 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
597 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
598 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
599 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
600 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
601 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
602 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
603 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
604 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
605 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
606 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
607 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
608 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
609 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
610 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
611 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
612 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
613 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
614 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
615 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
616 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
617 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
618 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
619 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
620 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
621 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
622 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
623 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
624 MLX5_COMMAND_STR_CASE(ALLOC_PD);
625 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
626 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
627 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
628 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
629 MLX5_COMMAND_STR_CASE(ACCESS_REG);
630 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
631 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
632 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
633 MLX5_COMMAND_STR_CASE(MAD_IFC);
634 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
635 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
636 MLX5_COMMAND_STR_CASE(NOP);
637 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
638 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
639 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
640 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
641 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
642 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
643 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
644 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
645 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
646 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
647 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
648 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
649 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
650 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
651 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
652 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
653 MLX5_COMMAND_STR_CASE(CREATE_LAG);
654 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
655 MLX5_COMMAND_STR_CASE(QUERY_LAG);
656 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
657 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
658 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
659 MLX5_COMMAND_STR_CASE(CREATE_TIR);
660 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
661 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
662 MLX5_COMMAND_STR_CASE(QUERY_TIR);
663 MLX5_COMMAND_STR_CASE(CREATE_SQ);
664 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
665 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
666 MLX5_COMMAND_STR_CASE(QUERY_SQ);
667 MLX5_COMMAND_STR_CASE(CREATE_RQ);
668 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
669 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
670 MLX5_COMMAND_STR_CASE(QUERY_RQ);
671 MLX5_COMMAND_STR_CASE(CREATE_RMP);
672 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
673 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
674 MLX5_COMMAND_STR_CASE(QUERY_RMP);
675 MLX5_COMMAND_STR_CASE(CREATE_TIS);
676 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
677 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
678 MLX5_COMMAND_STR_CASE(QUERY_TIS);
679 MLX5_COMMAND_STR_CASE(CREATE_RQT);
680 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
681 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
682 MLX5_COMMAND_STR_CASE(QUERY_RQT);
683 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
684 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
685 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
686 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
687 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
688 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
689 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
690 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
691 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
692 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
693 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
694 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
695 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
696 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
697 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
698 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
699 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
700 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
701 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
702 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
703 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
704 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
705 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
706 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
707 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
708 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
709 MLX5_COMMAND_STR_CASE(ARM_XRQ);
710 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
711 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
712 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
713 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
714 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
715 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
716 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
717 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
718 MLX5_COMMAND_STR_CASE(CREATE_UCTX);
719 MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
720 MLX5_COMMAND_STR_CASE(CREATE_UMEM);
721 MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
722 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
723 MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
724 MLX5_COMMAND_STR_CASE(QUERY_VHCA_STATE);
725 MLX5_COMMAND_STR_CASE(MODIFY_VHCA_STATE);
726 MLX5_COMMAND_STR_CASE(ALLOC_SF);
727 MLX5_COMMAND_STR_CASE(DEALLOC_SF);
728 MLX5_COMMAND_STR_CASE(SUSPEND_VHCA);
729 MLX5_COMMAND_STR_CASE(RESUME_VHCA);
730 MLX5_COMMAND_STR_CASE(QUERY_VHCA_MIGRATION_STATE);
731 MLX5_COMMAND_STR_CASE(SAVE_VHCA_STATE);
732 MLX5_COMMAND_STR_CASE(LOAD_VHCA_STATE);
733 MLX5_COMMAND_STR_CASE(SYNC_CRYPTO);
734 default: return "unknown command opcode";
735 }
736 }
737
cmd_status_str(u8 status)738 static const char *cmd_status_str(u8 status)
739 {
740 switch (status) {
741 case MLX5_CMD_STAT_OK:
742 return "OK";
743 case MLX5_CMD_STAT_INT_ERR:
744 return "internal error";
745 case MLX5_CMD_STAT_BAD_OP_ERR:
746 return "bad operation";
747 case MLX5_CMD_STAT_BAD_PARAM_ERR:
748 return "bad parameter";
749 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
750 return "bad system state";
751 case MLX5_CMD_STAT_BAD_RES_ERR:
752 return "bad resource";
753 case MLX5_CMD_STAT_RES_BUSY:
754 return "resource busy";
755 case MLX5_CMD_STAT_LIM_ERR:
756 return "limits exceeded";
757 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
758 return "bad resource state";
759 case MLX5_CMD_STAT_IX_ERR:
760 return "bad index";
761 case MLX5_CMD_STAT_NO_RES_ERR:
762 return "no resources";
763 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
764 return "bad input length";
765 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
766 return "bad output length";
767 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
768 return "bad QP state";
769 case MLX5_CMD_STAT_BAD_PKT_ERR:
770 return "bad packet (discarded)";
771 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
772 return "bad size too many outstanding CQEs";
773 default:
774 return "unknown status";
775 }
776 }
777
cmd_status_to_err(u8 status)778 static int cmd_status_to_err(u8 status)
779 {
780 switch (status) {
781 case MLX5_CMD_STAT_OK: return 0;
782 case MLX5_CMD_STAT_INT_ERR: return -EIO;
783 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
784 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
785 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
786 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
787 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
788 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
789 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
790 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
791 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
792 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
793 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
794 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
795 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
796 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
797 default: return -EIO;
798 }
799 }
800
mlx5_cmd_out_err(struct mlx5_core_dev * dev,u16 opcode,u16 op_mod,void * out)801 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)
802 {
803 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
804 u8 status = MLX5_GET(mbox_out, out, status);
805
806 mlx5_core_err_rl(dev,
807 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x), err(%d)\n",
808 mlx5_command_str(opcode), opcode, op_mod,
809 cmd_status_str(status), status, syndrome, cmd_status_to_err(status));
810 }
811 EXPORT_SYMBOL(mlx5_cmd_out_err);
812
cmd_status_print(struct mlx5_core_dev * dev,void * in,void * out)813 static void cmd_status_print(struct mlx5_core_dev *dev, void *in, void *out)
814 {
815 u16 opcode, op_mod;
816 u16 uid;
817
818 opcode = in_to_opcode(in);
819 op_mod = MLX5_GET(mbox_in, in, op_mod);
820 uid = MLX5_GET(mbox_in, in, uid);
821
822 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY &&
823 opcode != MLX5_CMD_OP_CREATE_UCTX)
824 mlx5_cmd_out_err(dev, opcode, op_mod, out);
825 }
826
mlx5_cmd_check(struct mlx5_core_dev * dev,int err,void * in,void * out)827 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out)
828 {
829 /* aborted due to PCI error or via reset flow mlx5_cmd_trigger_completions() */
830 if (err == -ENXIO) {
831 u16 opcode = in_to_opcode(in);
832 u32 syndrome;
833 u8 status;
834
835 /* PCI Error, emulate command return status, for smooth reset */
836 err = mlx5_internal_err_ret_value(dev, opcode, &syndrome, &status);
837 MLX5_SET(mbox_out, out, status, status);
838 MLX5_SET(mbox_out, out, syndrome, syndrome);
839 if (!err)
840 return 0;
841 }
842
843 /* driver or FW delivery error */
844 if (err != -EREMOTEIO && err)
845 return err;
846
847 /* check outbox status */
848 err = cmd_status_to_err(MLX5_GET(mbox_out, out, status));
849 if (err)
850 cmd_status_print(dev, in, out);
851
852 return err;
853 }
854 EXPORT_SYMBOL(mlx5_cmd_check);
855
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)856 static void dump_command(struct mlx5_core_dev *dev,
857 struct mlx5_cmd_work_ent *ent, int input)
858 {
859 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
860 struct mlx5_cmd_mailbox *next = msg->next;
861 int n = mlx5_calc_cmd_blocks(msg);
862 u16 op = ent->op;
863 int data_only;
864 u32 offset = 0;
865 int dump_len;
866 int i;
867
868 mlx5_core_dbg(dev, "cmd[%d]: start dump\n", ent->idx);
869 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
870
871 if (data_only)
872 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
873 "cmd[%d]: dump command data %s(0x%x) %s\n",
874 ent->idx, mlx5_command_str(op), op,
875 input ? "INPUT" : "OUTPUT");
876 else
877 mlx5_core_dbg(dev, "cmd[%d]: dump command %s(0x%x) %s\n",
878 ent->idx, mlx5_command_str(op), op,
879 input ? "INPUT" : "OUTPUT");
880
881 if (data_only) {
882 if (input) {
883 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset, ent->idx);
884 offset += sizeof(ent->lay->in);
885 } else {
886 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset, ent->idx);
887 offset += sizeof(ent->lay->out);
888 }
889 } else {
890 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset, ent->idx);
891 offset += sizeof(*ent->lay);
892 }
893
894 for (i = 0; i < n && next; i++) {
895 if (data_only) {
896 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
897 dump_buf(next->buf, dump_len, 1, offset, ent->idx);
898 offset += MLX5_CMD_DATA_BLOCK_SIZE;
899 } else {
900 mlx5_core_dbg(dev, "cmd[%d]: command block:\n", ent->idx);
901 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset,
902 ent->idx);
903 offset += sizeof(struct mlx5_cmd_prot_block);
904 }
905 next = next->next;
906 }
907
908 if (data_only)
909 pr_debug("\n");
910
911 mlx5_core_dbg(dev, "cmd[%d]: end dump\n", ent->idx);
912 }
913
914 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
915
cb_timeout_handler(struct work_struct * work)916 static void cb_timeout_handler(struct work_struct *work)
917 {
918 struct delayed_work *dwork = container_of(work, struct delayed_work,
919 work);
920 struct mlx5_cmd_work_ent *ent = container_of(dwork,
921 struct mlx5_cmd_work_ent,
922 cb_timeout_work);
923 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
924 cmd);
925
926 mlx5_cmd_eq_recover(dev);
927
928 /* Maybe got handled by eq recover ? */
929 if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) {
930 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx,
931 mlx5_command_str(ent->op), ent->op);
932 goto out; /* phew, already handled */
933 }
934
935 ent->ret = -ETIMEDOUT;
936 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n",
937 ent->idx, mlx5_command_str(ent->op), ent->op);
938 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
939
940 out:
941 cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */
942 }
943
944 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
945 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
946 struct mlx5_cmd_msg *msg);
947
opcode_allowed(struct mlx5_cmd * cmd,u16 opcode)948 static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)
949 {
950 if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL)
951 return true;
952
953 return cmd->allowed_opcode == opcode;
954 }
955
mlx5_cmd_is_down(struct mlx5_core_dev * dev)956 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)
957 {
958 return pci_channel_offline(dev->pdev) ||
959 dev->cmd.state != MLX5_CMDIF_STATE_UP ||
960 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR;
961 }
962
cmd_work_handler(struct work_struct * work)963 static void cmd_work_handler(struct work_struct *work)
964 {
965 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
966 struct mlx5_cmd *cmd = ent->cmd;
967 bool poll_cmd = ent->polling;
968 struct mlx5_cmd_layout *lay;
969 struct mlx5_core_dev *dev;
970 unsigned long timeout;
971 unsigned long flags;
972 int alloc_ret;
973 int cmd_mode;
974
975 complete(&ent->handling);
976
977 dev = container_of(cmd, struct mlx5_core_dev, cmd);
978 timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
979
980 if (!ent->page_queue) {
981 if (down_timeout(&cmd->vars.sem, timeout)) {
982 mlx5_core_warn(dev, "%s(0x%x) timed out while waiting for a slot.\n",
983 mlx5_command_str(ent->op), ent->op);
984 if (ent->callback) {
985 ent->callback(-EBUSY, ent->context);
986 mlx5_free_cmd_msg(dev, ent->out);
987 free_msg(dev, ent->in);
988 cmd_ent_put(ent);
989 } else {
990 ent->ret = -EBUSY;
991 complete(&ent->done);
992 }
993 complete(&ent->slotted);
994 return;
995 }
996 alloc_ret = cmd_alloc_index(cmd, ent);
997 if (alloc_ret < 0) {
998 mlx5_core_err_rl(dev, "failed to allocate command entry\n");
999 if (ent->callback) {
1000 ent->callback(-EAGAIN, ent->context);
1001 mlx5_free_cmd_msg(dev, ent->out);
1002 free_msg(dev, ent->in);
1003 cmd_ent_put(ent);
1004 } else {
1005 ent->ret = -EAGAIN;
1006 complete(&ent->done);
1007 }
1008 up(&cmd->vars.sem);
1009 complete(&ent->slotted);
1010 return;
1011 }
1012 } else {
1013 down(&cmd->vars.pages_sem);
1014 ent->idx = cmd->vars.max_reg_cmds;
1015 spin_lock_irqsave(&cmd->alloc_lock, flags);
1016 clear_bit(ent->idx, &cmd->vars.bitmask);
1017 cmd->ent_arr[ent->idx] = ent;
1018 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
1019 }
1020
1021 complete(&ent->slotted);
1022
1023 lay = get_inst(cmd, ent->idx);
1024 ent->lay = lay;
1025 memset(lay, 0, sizeof(*lay));
1026 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
1027 if (ent->in->next)
1028 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
1029 lay->inlen = cpu_to_be32(ent->in->len);
1030 if (ent->out->next)
1031 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
1032 lay->outlen = cpu_to_be32(ent->out->len);
1033 lay->type = MLX5_PCI_CMD_XPORT;
1034 lay->token = ent->token;
1035 lay->status_own = CMD_OWNER_HW;
1036 set_signature(ent, !cmd->checksum_disabled);
1037 dump_command(dev, ent, 1);
1038 ent->ts1 = ktime_get_ns();
1039 cmd_mode = cmd->mode;
1040
1041 if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, timeout))
1042 cmd_ent_get(ent);
1043 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
1044
1045 cmd_ent_get(ent); /* for the _real_ FW event on completion */
1046 /* Skip sending command to fw if internal error */
1047 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) {
1048 ent->ret = -ENXIO;
1049 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1050 return;
1051 }
1052
1053 /* ring doorbell after the descriptor is valid */
1054 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
1055 wmb();
1056 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
1057 /* if not in polling don't use ent after this point */
1058 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
1059 poll_timeout(ent);
1060 /* make sure we read the descriptor after ownership is SW */
1061 rmb();
1062 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, (ent->ret == -ETIMEDOUT));
1063 }
1064 }
1065
deliv_status_to_err(u8 status)1066 static int deliv_status_to_err(u8 status)
1067 {
1068 switch (status) {
1069 case MLX5_CMD_DELIVERY_STAT_OK:
1070 case MLX5_DRIVER_STATUS_ABORTED:
1071 return 0;
1072 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1073 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1074 return -EBADR;
1075 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1076 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1077 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1078 return -EFAULT; /* Bad address */
1079 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1080 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1081 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1082 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1083 return -ENOMSG;
1084 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1085 return -EIO;
1086 default:
1087 return -EINVAL;
1088 }
1089 }
1090
deliv_status_to_str(u8 status)1091 static const char *deliv_status_to_str(u8 status)
1092 {
1093 switch (status) {
1094 case MLX5_CMD_DELIVERY_STAT_OK:
1095 return "no errors";
1096 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1097 return "signature error";
1098 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1099 return "token error";
1100 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1101 return "bad block number";
1102 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1103 return "output pointer not aligned to block size";
1104 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1105 return "input pointer not aligned to block size";
1106 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1107 return "firmware internal error";
1108 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1109 return "command input length error";
1110 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1111 return "command output length error";
1112 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1113 return "reserved fields not cleared";
1114 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1115 return "bad command descriptor type";
1116 default:
1117 return "unknown status code";
1118 }
1119 }
1120
1121 enum {
1122 MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5 * 1000,
1123 };
1124
wait_func_handle_exec_timeout(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1125 static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,
1126 struct mlx5_cmd_work_ent *ent)
1127 {
1128 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_RECOVER_MSEC);
1129
1130 mlx5_cmd_eq_recover(dev);
1131
1132 /* Re-wait on the ent->done after executing the recovery flow. If the
1133 * recovery flow (or any other recovery flow running simultaneously)
1134 * has recovered an EQE, it should cause the entry to be completed by
1135 * the command interface.
1136 */
1137 if (wait_for_completion_timeout(&ent->done, timeout)) {
1138 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) recovered after timeout\n", ent->idx,
1139 mlx5_command_str(ent->op), ent->op);
1140 return;
1141 }
1142
1143 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) No done completion\n", ent->idx,
1144 mlx5_command_str(ent->op), ent->op);
1145
1146 ent->ret = -ETIMEDOUT;
1147 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1148 }
1149
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1150 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
1151 {
1152 unsigned long timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
1153 struct mlx5_cmd *cmd = &dev->cmd;
1154 int err;
1155
1156 if (!wait_for_completion_timeout(&ent->handling, timeout) &&
1157 cancel_work_sync(&ent->work)) {
1158 ent->ret = -ECANCELED;
1159 goto out_err;
1160 }
1161
1162 wait_for_completion(&ent->slotted);
1163
1164 if (cmd->mode == CMD_MODE_POLLING || ent->polling)
1165 wait_for_completion(&ent->done);
1166 else if (!wait_for_completion_timeout(&ent->done, timeout))
1167 wait_func_handle_exec_timeout(dev, ent);
1168
1169 out_err:
1170 err = ent->ret;
1171
1172 if (err == -ETIMEDOUT) {
1173 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
1174 mlx5_command_str(ent->op), ent->op);
1175 } else if (err == -ECANCELED) {
1176 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
1177 mlx5_command_str(ent->op), ent->op);
1178 } else if (err == -EBUSY) {
1179 mlx5_core_warn(dev, "%s(0x%x) timeout while waiting for command semaphore.\n",
1180 mlx5_command_str(ent->op), ent->op);
1181 }
1182 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1183 err, deliv_status_to_str(ent->status), ent->status);
1184
1185 return err;
1186 }
1187
1188 /* Notes:
1189 * 1. Callback functions may not sleep
1190 * 2. page queue commands do not support asynchrous completion
1191 *
1192 * return value in case (!callback):
1193 * ret < 0 : Command execution couldn't be submitted by driver
1194 * ret > 0 : Command execution couldn't be performed by firmware
1195 * ret == 0: Command was executed by FW, Caller must check FW outbox status.
1196 *
1197 * return value in case (callback):
1198 * ret < 0 : Command execution couldn't be submitted by driver
1199 * ret == 0: Command will be submitted to FW for execution
1200 * and the callback will be called for further status updates
1201 */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 token,bool force_polling)1202 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1203 struct mlx5_cmd_msg *out, void *uout, int uout_size,
1204 mlx5_cmd_cbk_t callback,
1205 void *context, int page_queue,
1206 u8 token, bool force_polling)
1207 {
1208 struct mlx5_cmd *cmd = &dev->cmd;
1209 struct mlx5_cmd_work_ent *ent;
1210 struct mlx5_cmd_stats *stats;
1211 u8 status = 0;
1212 int err = 0;
1213 s64 ds;
1214
1215 if (callback && page_queue)
1216 return -EINVAL;
1217
1218 ent = cmd_alloc_ent(cmd, in, out, uout, uout_size,
1219 callback, context, page_queue);
1220 if (IS_ERR(ent))
1221 return PTR_ERR(ent);
1222
1223 /* put for this ent is when consumed, depending on the use case
1224 * 1) (!callback) blocking flow: by caller after wait_func completes
1225 * 2) (callback) flow: by mlx5_cmd_comp_handler() when ent is handled
1226 */
1227
1228 ent->token = token;
1229 ent->polling = force_polling;
1230
1231 init_completion(&ent->handling);
1232 init_completion(&ent->slotted);
1233 if (!callback)
1234 init_completion(&ent->done);
1235
1236 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1237 INIT_WORK(&ent->work, cmd_work_handler);
1238 if (page_queue) {
1239 cmd_work_handler(&ent->work);
1240 } else if (!queue_work(cmd->wq, &ent->work)) {
1241 mlx5_core_warn(dev, "failed to queue work\n");
1242 err = -EALREADY;
1243 goto out_free;
1244 }
1245
1246 if (callback)
1247 return 0; /* mlx5_cmd_comp_handler() will put(ent) */
1248
1249 err = wait_func(dev, ent);
1250 if (err == -ETIMEDOUT || err == -ECANCELED || err == -EBUSY)
1251 goto out_free;
1252
1253 ds = ent->ts2 - ent->ts1;
1254 stats = xa_load(&cmd->stats, ent->op);
1255 if (stats) {
1256 spin_lock_irq(&stats->lock);
1257 stats->sum += ds;
1258 ++stats->n;
1259 spin_unlock_irq(&stats->lock);
1260 }
1261 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1262 "fw exec time for %s is %lld nsec\n",
1263 mlx5_command_str(ent->op), ds);
1264
1265 out_free:
1266 status = ent->status;
1267 cmd_ent_put(ent);
1268 return err ? : status;
1269 }
1270
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1271 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1272 size_t count, loff_t *pos)
1273 {
1274 struct mlx5_core_dev *dev = filp->private_data;
1275 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1276 char lbuf[3];
1277 int err;
1278
1279 if (!dbg->in_msg || !dbg->out_msg)
1280 return -ENOMEM;
1281
1282 if (count < sizeof(lbuf) - 1)
1283 return -EINVAL;
1284
1285 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1286 return -EFAULT;
1287
1288 lbuf[sizeof(lbuf) - 1] = 0;
1289
1290 if (strcmp(lbuf, "go"))
1291 return -EINVAL;
1292
1293 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1294
1295 return err ? err : count;
1296 }
1297
1298 static const struct file_operations fops = {
1299 .owner = THIS_MODULE,
1300 .open = simple_open,
1301 .write = dbg_write,
1302 };
1303
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)1304 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1305 u8 token)
1306 {
1307 struct mlx5_cmd_prot_block *block;
1308 struct mlx5_cmd_mailbox *next;
1309 int copy;
1310
1311 if (!to || !from)
1312 return -ENOMEM;
1313
1314 copy = min_t(int, size, sizeof(to->first.data));
1315 memcpy(to->first.data, from, copy);
1316 size -= copy;
1317 from += copy;
1318
1319 next = to->next;
1320 while (size) {
1321 if (!next) {
1322 /* this is a BUG */
1323 return -ENOMEM;
1324 }
1325
1326 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1327 block = next->buf;
1328 memcpy(block->data, from, copy);
1329 from += copy;
1330 size -= copy;
1331 block->token = token;
1332 next = next->next;
1333 }
1334
1335 return 0;
1336 }
1337
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)1338 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1339 {
1340 struct mlx5_cmd_prot_block *block;
1341 struct mlx5_cmd_mailbox *next;
1342 int copy;
1343
1344 if (!to || !from)
1345 return -ENOMEM;
1346
1347 copy = min_t(int, size, sizeof(from->first.data));
1348 memcpy(to, from->first.data, copy);
1349 size -= copy;
1350 to += copy;
1351
1352 next = from->next;
1353 while (size) {
1354 if (!next) {
1355 /* this is a BUG */
1356 return -ENOMEM;
1357 }
1358
1359 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1360 block = next->buf;
1361
1362 memcpy(to, block->data, copy);
1363 to += copy;
1364 size -= copy;
1365 next = next->next;
1366 }
1367
1368 return 0;
1369 }
1370
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)1371 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1372 gfp_t flags)
1373 {
1374 struct mlx5_cmd_mailbox *mailbox;
1375
1376 mailbox = kmalloc(sizeof(*mailbox), flags);
1377 if (!mailbox)
1378 return ERR_PTR(-ENOMEM);
1379
1380 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1381 &mailbox->dma);
1382 if (!mailbox->buf) {
1383 mlx5_core_dbg(dev, "failed allocation\n");
1384 kfree(mailbox);
1385 return ERR_PTR(-ENOMEM);
1386 }
1387 mailbox->next = NULL;
1388
1389 return mailbox;
1390 }
1391
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1392 static void free_cmd_box(struct mlx5_core_dev *dev,
1393 struct mlx5_cmd_mailbox *mailbox)
1394 {
1395 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1396 kfree(mailbox);
1397 }
1398
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1399 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1400 gfp_t flags, int size,
1401 u8 token)
1402 {
1403 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1404 struct mlx5_cmd_prot_block *block;
1405 struct mlx5_cmd_msg *msg;
1406 int err;
1407 int n;
1408 int i;
1409
1410 msg = kzalloc(sizeof(*msg), flags);
1411 if (!msg)
1412 return ERR_PTR(-ENOMEM);
1413
1414 msg->len = size;
1415 n = mlx5_calc_cmd_blocks(msg);
1416
1417 for (i = 0; i < n; i++) {
1418 tmp = alloc_cmd_box(dev, flags);
1419 if (IS_ERR(tmp)) {
1420 mlx5_core_warn(dev, "failed allocating block\n");
1421 err = PTR_ERR(tmp);
1422 goto err_alloc;
1423 }
1424
1425 block = tmp->buf;
1426 tmp->next = head;
1427 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1428 block->block_num = cpu_to_be32(n - i - 1);
1429 block->token = token;
1430 head = tmp;
1431 }
1432 msg->next = head;
1433 return msg;
1434
1435 err_alloc:
1436 while (head) {
1437 tmp = head->next;
1438 free_cmd_box(dev, head);
1439 head = tmp;
1440 }
1441 kfree(msg);
1442
1443 return ERR_PTR(err);
1444 }
1445
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1446 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1447 struct mlx5_cmd_msg *msg)
1448 {
1449 struct mlx5_cmd_mailbox *head = msg->next;
1450 struct mlx5_cmd_mailbox *next;
1451
1452 while (head) {
1453 next = head->next;
1454 free_cmd_box(dev, head);
1455 head = next;
1456 }
1457 kfree(msg);
1458 }
1459
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1460 static ssize_t data_write(struct file *filp, const char __user *buf,
1461 size_t count, loff_t *pos)
1462 {
1463 struct mlx5_core_dev *dev = filp->private_data;
1464 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1465 void *ptr;
1466
1467 if (*pos != 0)
1468 return -EINVAL;
1469
1470 kfree(dbg->in_msg);
1471 dbg->in_msg = NULL;
1472 dbg->inlen = 0;
1473 ptr = memdup_user(buf, count);
1474 if (IS_ERR(ptr))
1475 return PTR_ERR(ptr);
1476 dbg->in_msg = ptr;
1477 dbg->inlen = count;
1478
1479 *pos = count;
1480
1481 return count;
1482 }
1483
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1484 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1485 loff_t *pos)
1486 {
1487 struct mlx5_core_dev *dev = filp->private_data;
1488 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1489
1490 if (!dbg->out_msg)
1491 return -ENOMEM;
1492
1493 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1494 dbg->outlen);
1495 }
1496
1497 static const struct file_operations dfops = {
1498 .owner = THIS_MODULE,
1499 .open = simple_open,
1500 .write = data_write,
1501 .read = data_read,
1502 };
1503
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1504 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1505 loff_t *pos)
1506 {
1507 struct mlx5_core_dev *dev = filp->private_data;
1508 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1509 char outlen[8];
1510 int err;
1511
1512 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1513 if (err < 0)
1514 return err;
1515
1516 return simple_read_from_buffer(buf, count, pos, outlen, err);
1517 }
1518
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1519 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1520 size_t count, loff_t *pos)
1521 {
1522 struct mlx5_core_dev *dev = filp->private_data;
1523 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1524 char outlen_str[8] = {0};
1525 int outlen;
1526 void *ptr;
1527 int err;
1528
1529 if (*pos != 0 || count > 6)
1530 return -EINVAL;
1531
1532 kfree(dbg->out_msg);
1533 dbg->out_msg = NULL;
1534 dbg->outlen = 0;
1535
1536 if (copy_from_user(outlen_str, buf, count))
1537 return -EFAULT;
1538
1539 err = sscanf(outlen_str, "%d", &outlen);
1540 if (err != 1)
1541 return -EINVAL;
1542
1543 ptr = kzalloc(outlen, GFP_KERNEL);
1544 if (!ptr)
1545 return -ENOMEM;
1546
1547 dbg->out_msg = ptr;
1548 dbg->outlen = outlen;
1549
1550 *pos = count;
1551
1552 return count;
1553 }
1554
1555 static const struct file_operations olfops = {
1556 .owner = THIS_MODULE,
1557 .open = simple_open,
1558 .write = outlen_write,
1559 .read = outlen_read,
1560 };
1561
set_wqname(struct mlx5_core_dev * dev)1562 static void set_wqname(struct mlx5_core_dev *dev)
1563 {
1564 struct mlx5_cmd *cmd = &dev->cmd;
1565
1566 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1567 dev_name(dev->device));
1568 }
1569
clean_debug_files(struct mlx5_core_dev * dev)1570 static void clean_debug_files(struct mlx5_core_dev *dev)
1571 {
1572 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1573
1574 if (!mlx5_debugfs_root)
1575 return;
1576
1577 debugfs_remove_recursive(dbg->dbg_root);
1578 }
1579
create_debugfs_files(struct mlx5_core_dev * dev)1580 static void create_debugfs_files(struct mlx5_core_dev *dev)
1581 {
1582 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1583
1584 dbg->dbg_root = debugfs_create_dir("cmd", mlx5_debugfs_get_dev_root(dev));
1585
1586 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1587 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1588 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1589 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1590 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1591 }
1592
mlx5_cmd_allowed_opcode(struct mlx5_core_dev * dev,u16 opcode)1593 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode)
1594 {
1595 struct mlx5_cmd *cmd = &dev->cmd;
1596 int i;
1597
1598 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1599 down(&cmd->vars.sem);
1600 down(&cmd->vars.pages_sem);
1601
1602 cmd->allowed_opcode = opcode;
1603
1604 up(&cmd->vars.pages_sem);
1605 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1606 up(&cmd->vars.sem);
1607 }
1608
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1609 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1610 {
1611 struct mlx5_cmd *cmd = &dev->cmd;
1612 int i;
1613
1614 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1615 down(&cmd->vars.sem);
1616 down(&cmd->vars.pages_sem);
1617
1618 cmd->mode = mode;
1619
1620 up(&cmd->vars.pages_sem);
1621 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1622 up(&cmd->vars.sem);
1623 }
1624
cmd_comp_notifier(struct notifier_block * nb,unsigned long type,void * data)1625 static int cmd_comp_notifier(struct notifier_block *nb,
1626 unsigned long type, void *data)
1627 {
1628 struct mlx5_core_dev *dev;
1629 struct mlx5_cmd *cmd;
1630 struct mlx5_eqe *eqe;
1631
1632 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1633 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1634 eqe = data;
1635
1636 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1637 return NOTIFY_DONE;
1638
1639 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1640
1641 return NOTIFY_OK;
1642 }
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1643 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1644 {
1645 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1646 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1647 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1648 }
1649
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1650 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1651 {
1652 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1653 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1654 }
1655
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1656 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1657 {
1658 unsigned long flags;
1659
1660 if (msg->parent) {
1661 spin_lock_irqsave(&msg->parent->lock, flags);
1662 list_add_tail(&msg->list, &msg->parent->head);
1663 spin_unlock_irqrestore(&msg->parent->lock, flags);
1664 } else {
1665 mlx5_free_cmd_msg(dev, msg);
1666 }
1667 }
1668
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec,bool forced)1669 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1670 {
1671 struct mlx5_cmd *cmd = &dev->cmd;
1672 struct mlx5_cmd_work_ent *ent;
1673 mlx5_cmd_cbk_t callback;
1674 void *context;
1675 int err;
1676 int i;
1677 s64 ds;
1678 struct mlx5_cmd_stats *stats;
1679 unsigned long flags;
1680 unsigned long vector;
1681
1682 /* there can be at most 32 command queues */
1683 vector = vec & 0xffffffff;
1684 for (i = 0; i < (1 << cmd->vars.log_sz); i++) {
1685 if (test_bit(i, &vector)) {
1686 ent = cmd->ent_arr[i];
1687
1688 /* if we already completed the command, ignore it */
1689 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1690 &ent->state)) {
1691 /* only real completion can free the cmd slot */
1692 if (!forced) {
1693 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1694 ent->idx);
1695 cmd_ent_put(ent);
1696 }
1697 continue;
1698 }
1699
1700 if (ent->callback && cancel_delayed_work(&ent->cb_timeout_work))
1701 cmd_ent_put(ent); /* timeout work was canceled */
1702
1703 if (!forced || /* Real FW completion */
1704 mlx5_cmd_is_down(dev) || /* No real FW completion is expected */
1705 !opcode_allowed(cmd, ent->op))
1706 cmd_ent_put(ent);
1707
1708 ent->ts2 = ktime_get_ns();
1709 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1710 dump_command(dev, ent, 0);
1711
1712 if (vec & MLX5_TRIGGERED_CMD_COMP)
1713 ent->ret = -ENXIO;
1714
1715 if (!ent->ret) { /* Command completed by FW */
1716 if (!cmd->checksum_disabled)
1717 ent->ret = verify_signature(ent);
1718
1719 ent->status = ent->lay->status_own >> 1;
1720
1721 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1722 ent->ret, deliv_status_to_str(ent->status), ent->status);
1723 }
1724
1725 if (ent->callback) {
1726 ds = ent->ts2 - ent->ts1;
1727 stats = xa_load(&cmd->stats, ent->op);
1728 if (stats) {
1729 spin_lock_irqsave(&stats->lock, flags);
1730 stats->sum += ds;
1731 ++stats->n;
1732 spin_unlock_irqrestore(&stats->lock, flags);
1733 }
1734
1735 callback = ent->callback;
1736 context = ent->context;
1737 err = ent->ret ? : ent->status;
1738 if (err > 0) /* Failed in FW, command didn't execute */
1739 err = deliv_status_to_err(err);
1740
1741 if (!err)
1742 err = mlx5_copy_from_msg(ent->uout,
1743 ent->out,
1744 ent->uout_size);
1745
1746 mlx5_free_cmd_msg(dev, ent->out);
1747 free_msg(dev, ent->in);
1748
1749 /* final consumer is done, release ent */
1750 cmd_ent_put(ent);
1751 callback(err, context);
1752 } else {
1753 /* release wait_func() so mlx5_cmd_invoke()
1754 * can make the final ent_put()
1755 */
1756 complete(&ent->done);
1757 }
1758 }
1759 }
1760 }
1761
1762 #define MLX5_MAX_MANAGE_PAGES_CMD_ENT 1
1763 #define MLX5_CMD_MASK ((1UL << (cmd->vars.max_reg_cmds + \
1764 MLX5_MAX_MANAGE_PAGES_CMD_ENT)) - 1)
1765
mlx5_cmd_trigger_completions(struct mlx5_core_dev * dev)1766 static void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1767 {
1768 struct mlx5_cmd *cmd = &dev->cmd;
1769 unsigned long bitmask;
1770 unsigned long flags;
1771 u64 vector;
1772 int i;
1773
1774 /* wait for pending handlers to complete */
1775 mlx5_eq_synchronize_cmd_irq(dev);
1776 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1777 vector = ~dev->cmd.vars.bitmask & MLX5_CMD_MASK;
1778 if (!vector)
1779 goto no_trig;
1780
1781 bitmask = vector;
1782 /* we must increment the allocated entries refcount before triggering the completions
1783 * to guarantee pending commands will not get freed in the meanwhile.
1784 * For that reason, it also has to be done inside the alloc_lock.
1785 */
1786 for_each_set_bit(i, &bitmask, (1 << cmd->vars.log_sz))
1787 cmd_ent_get(cmd->ent_arr[i]);
1788 vector |= MLX5_TRIGGERED_CMD_COMP;
1789 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1790
1791 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1792 mlx5_cmd_comp_handler(dev, vector, true);
1793 for_each_set_bit(i, &bitmask, (1 << cmd->vars.log_sz))
1794 cmd_ent_put(cmd->ent_arr[i]);
1795 return;
1796
1797 no_trig:
1798 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1799 }
1800
mlx5_cmd_flush(struct mlx5_core_dev * dev)1801 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1802 {
1803 struct mlx5_cmd *cmd = &dev->cmd;
1804 int i;
1805
1806 for (i = 0; i < cmd->vars.max_reg_cmds; i++) {
1807 while (down_trylock(&cmd->vars.sem)) {
1808 mlx5_cmd_trigger_completions(dev);
1809 cond_resched();
1810 }
1811 }
1812
1813 while (down_trylock(&cmd->vars.pages_sem)) {
1814 mlx5_cmd_trigger_completions(dev);
1815 cond_resched();
1816 }
1817
1818 /* Unlock cmdif */
1819 up(&cmd->vars.pages_sem);
1820 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1821 up(&cmd->vars.sem);
1822 }
1823
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1824 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1825 gfp_t gfp)
1826 {
1827 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1828 struct cmd_msg_cache *ch = NULL;
1829 struct mlx5_cmd *cmd = &dev->cmd;
1830 int i;
1831
1832 if (in_size <= 16)
1833 goto cache_miss;
1834
1835 for (i = 0; i < dev->profile.num_cmd_caches; i++) {
1836 ch = &cmd->cache[i];
1837 if (in_size > ch->max_inbox_size)
1838 continue;
1839 spin_lock_irq(&ch->lock);
1840 if (list_empty(&ch->head)) {
1841 spin_unlock_irq(&ch->lock);
1842 continue;
1843 }
1844 msg = list_entry(ch->head.next, typeof(*msg), list);
1845 /* For cached lists, we must explicitly state what is
1846 * the real size
1847 */
1848 msg->len = in_size;
1849 list_del(&msg->list);
1850 spin_unlock_irq(&ch->lock);
1851 break;
1852 }
1853
1854 if (!IS_ERR(msg))
1855 return msg;
1856
1857 cache_miss:
1858 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1859 return msg;
1860 }
1861
is_manage_pages(void * in)1862 static int is_manage_pages(void *in)
1863 {
1864 return in_to_opcode(in) == MLX5_CMD_OP_MANAGE_PAGES;
1865 }
1866
1867 /* Notes:
1868 * 1. Callback functions may not sleep
1869 * 2. Page queue commands do not support asynchrous completion
1870 */
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context,bool force_polling)1871 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1872 int out_size, mlx5_cmd_cbk_t callback, void *context,
1873 bool force_polling)
1874 {
1875 struct mlx5_cmd_msg *inb, *outb;
1876 u16 opcode = in_to_opcode(in);
1877 bool throttle_op;
1878 int pages_queue;
1879 gfp_t gfp;
1880 u8 token;
1881 int err;
1882
1883 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode))
1884 return -ENXIO;
1885
1886 throttle_op = mlx5_cmd_is_throttle_opcode(opcode);
1887 if (throttle_op) {
1888 /* atomic context may not sleep */
1889 if (callback)
1890 return -EINVAL;
1891 down(&dev->cmd.vars.throttle_sem);
1892 }
1893
1894 pages_queue = is_manage_pages(in);
1895 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1896
1897 inb = alloc_msg(dev, in_size, gfp);
1898 if (IS_ERR(inb)) {
1899 err = PTR_ERR(inb);
1900 goto out_up;
1901 }
1902
1903 token = alloc_token(&dev->cmd);
1904
1905 err = mlx5_copy_to_msg(inb, in, in_size, token);
1906 if (err) {
1907 mlx5_core_warn(dev, "err %d\n", err);
1908 goto out_in;
1909 }
1910
1911 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1912 if (IS_ERR(outb)) {
1913 err = PTR_ERR(outb);
1914 goto out_in;
1915 }
1916
1917 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1918 pages_queue, token, force_polling);
1919 if (callback)
1920 return err;
1921
1922 if (err > 0) /* Failed in FW, command didn't execute */
1923 err = deliv_status_to_err(err);
1924
1925 if (err)
1926 goto out_out;
1927
1928 /* command completed by FW */
1929 err = mlx5_copy_from_msg(out, outb, out_size);
1930 out_out:
1931 mlx5_free_cmd_msg(dev, outb);
1932 out_in:
1933 free_msg(dev, inb);
1934 out_up:
1935 if (throttle_op)
1936 up(&dev->cmd.vars.throttle_sem);
1937 return err;
1938 }
1939
mlx5_cmd_err_trace(struct mlx5_core_dev * dev,u16 opcode,u16 op_mod,void * out)1940 static void mlx5_cmd_err_trace(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)
1941 {
1942 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
1943 u8 status = MLX5_GET(mbox_out, out, status);
1944
1945 trace_mlx5_cmd(mlx5_command_str(opcode), opcode, op_mod,
1946 cmd_status_str(status), status, syndrome,
1947 cmd_status_to_err(status));
1948 }
1949
cmd_status_log(struct mlx5_core_dev * dev,u16 opcode,u8 status,u32 syndrome,int err)1950 static void cmd_status_log(struct mlx5_core_dev *dev, u16 opcode, u8 status,
1951 u32 syndrome, int err)
1952 {
1953 const char *namep = mlx5_command_str(opcode);
1954 struct mlx5_cmd_stats *stats;
1955 unsigned long flags;
1956
1957 if (!err || !(strcmp(namep, "unknown command opcode")))
1958 return;
1959
1960 stats = xa_load(&dev->cmd.stats, opcode);
1961 if (!stats)
1962 return;
1963 spin_lock_irqsave(&stats->lock, flags);
1964 stats->failed++;
1965 if (err < 0)
1966 stats->last_failed_errno = -err;
1967 if (err == -EREMOTEIO) {
1968 stats->failed_mbox_status++;
1969 stats->last_failed_mbox_status = status;
1970 stats->last_failed_syndrome = syndrome;
1971 }
1972 spin_unlock_irqrestore(&stats->lock, flags);
1973 }
1974
1975 /* preserve -EREMOTEIO for outbox.status != OK, otherwise return err as is */
cmd_status_err(struct mlx5_core_dev * dev,int err,u16 opcode,u16 op_mod,void * out)1976 static int cmd_status_err(struct mlx5_core_dev *dev, int err, u16 opcode, u16 op_mod, void *out)
1977 {
1978 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
1979 u8 status = MLX5_GET(mbox_out, out, status);
1980
1981 if (err == -EREMOTEIO) /* -EREMOTEIO is preserved */
1982 err = -EIO;
1983
1984 if (!err && status != MLX5_CMD_STAT_OK) {
1985 err = -EREMOTEIO;
1986 mlx5_cmd_err_trace(dev, opcode, op_mod, out);
1987 }
1988
1989 cmd_status_log(dev, opcode, status, syndrome, err);
1990 return err;
1991 }
1992
1993 /**
1994 * mlx5_cmd_do - Executes a fw command, wait for completion.
1995 * Unlike mlx5_cmd_exec, this function will not translate or intercept
1996 * outbox.status and will return -EREMOTEIO when
1997 * outbox.status != MLX5_CMD_STAT_OK
1998 *
1999 * @dev: mlx5 core device
2000 * @in: inbox mlx5_ifc command buffer
2001 * @in_size: inbox buffer size
2002 * @out: outbox mlx5_ifc buffer
2003 * @out_size: outbox size
2004 *
2005 * @return:
2006 * -EREMOTEIO : Command executed by FW, outbox.status != MLX5_CMD_STAT_OK.
2007 * Caller must check FW outbox status.
2008 * 0 : Command execution successful, outbox.status == MLX5_CMD_STAT_OK.
2009 * < 0 : Command execution couldn't be performed by firmware or driver
2010 */
mlx5_cmd_do(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2011 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size)
2012 {
2013 int err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
2014 u16 op_mod = MLX5_GET(mbox_in, in, op_mod);
2015 u16 opcode = in_to_opcode(in);
2016
2017 return cmd_status_err(dev, err, opcode, op_mod, out);
2018 }
2019 EXPORT_SYMBOL(mlx5_cmd_do);
2020
2021 /**
2022 * mlx5_cmd_exec - Executes a fw command, wait for completion
2023 *
2024 * @dev: mlx5 core device
2025 * @in: inbox mlx5_ifc command buffer
2026 * @in_size: inbox buffer size
2027 * @out: outbox mlx5_ifc buffer
2028 * @out_size: outbox size
2029 *
2030 * @return: 0 if no error, FW command execution was successful
2031 * and outbox status is ok.
2032 */
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2033 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
2034 int out_size)
2035 {
2036 int err = mlx5_cmd_do(dev, in, in_size, out, out_size);
2037
2038 return mlx5_cmd_check(dev, err, in, out);
2039 }
2040 EXPORT_SYMBOL(mlx5_cmd_exec);
2041
2042 /**
2043 * mlx5_cmd_exec_polling - Executes a fw command, poll for completion
2044 * Needed for driver force teardown, when command completion EQ
2045 * will not be available to complete the command
2046 *
2047 * @dev: mlx5 core device
2048 * @in: inbox mlx5_ifc command buffer
2049 * @in_size: inbox buffer size
2050 * @out: outbox mlx5_ifc buffer
2051 * @out_size: outbox size
2052 *
2053 * @return: 0 if no error, FW command execution was successful
2054 * and outbox status is ok.
2055 */
mlx5_cmd_exec_polling(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2056 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
2057 void *out, int out_size)
2058 {
2059 int err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
2060 u16 op_mod = MLX5_GET(mbox_in, in, op_mod);
2061 u16 opcode = in_to_opcode(in);
2062
2063 err = cmd_status_err(dev, err, opcode, op_mod, out);
2064 return mlx5_cmd_check(dev, err, in, out);
2065 }
2066 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
2067
mlx5_cmd_init_async_ctx(struct mlx5_core_dev * dev,struct mlx5_async_ctx * ctx)2068 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
2069 struct mlx5_async_ctx *ctx)
2070 {
2071 ctx->dev = dev;
2072 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
2073 atomic_set(&ctx->num_inflight, 1);
2074 init_completion(&ctx->inflight_done);
2075 }
2076 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
2077
2078 /**
2079 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
2080 * @ctx: The ctx to clean
2081 *
2082 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
2083 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
2084 * the call mlx5_cleanup_async_ctx().
2085 */
mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx * ctx)2086 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
2087 {
2088 if (!atomic_dec_and_test(&ctx->num_inflight))
2089 wait_for_completion(&ctx->inflight_done);
2090 }
2091 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
2092
mlx5_cmd_exec_cb_handler(int status,void * _work)2093 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
2094 {
2095 struct mlx5_async_work *work = _work;
2096 struct mlx5_async_ctx *ctx;
2097
2098 ctx = work->ctx;
2099 status = cmd_status_err(ctx->dev, status, work->opcode, work->op_mod, work->out);
2100 work->user_callback(status, work);
2101 if (atomic_dec_and_test(&ctx->num_inflight))
2102 complete(&ctx->inflight_done);
2103 }
2104
mlx5_cmd_exec_cb(struct mlx5_async_ctx * ctx,void * in,int in_size,void * out,int out_size,mlx5_async_cbk_t callback,struct mlx5_async_work * work)2105 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
2106 void *out, int out_size, mlx5_async_cbk_t callback,
2107 struct mlx5_async_work *work)
2108 {
2109 int ret;
2110
2111 work->ctx = ctx;
2112 work->user_callback = callback;
2113 work->opcode = in_to_opcode(in);
2114 work->op_mod = MLX5_GET(mbox_in, in, op_mod);
2115 work->out = out;
2116 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
2117 return -EIO;
2118 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
2119 mlx5_cmd_exec_cb_handler, work, false);
2120 if (ret && atomic_dec_and_test(&ctx->num_inflight))
2121 complete(&ctx->inflight_done);
2122
2123 return ret;
2124 }
2125 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
2126
destroy_msg_cache(struct mlx5_core_dev * dev)2127 static void destroy_msg_cache(struct mlx5_core_dev *dev)
2128 {
2129 struct cmd_msg_cache *ch;
2130 struct mlx5_cmd_msg *msg;
2131 struct mlx5_cmd_msg *n;
2132 int i;
2133
2134 for (i = 0; i < dev->profile.num_cmd_caches; i++) {
2135 ch = &dev->cmd.cache[i];
2136 list_for_each_entry_safe(msg, n, &ch->head, list) {
2137 list_del(&msg->list);
2138 mlx5_free_cmd_msg(dev, msg);
2139 }
2140 }
2141 }
2142
2143 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
2144 512, 32, 16, 8, 2
2145 };
2146
2147 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
2148 16 + MLX5_CMD_DATA_BLOCK_SIZE,
2149 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
2150 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
2151 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
2152 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
2153 };
2154
create_msg_cache(struct mlx5_core_dev * dev)2155 static void create_msg_cache(struct mlx5_core_dev *dev)
2156 {
2157 struct mlx5_cmd *cmd = &dev->cmd;
2158 struct cmd_msg_cache *ch;
2159 struct mlx5_cmd_msg *msg;
2160 int i;
2161 int k;
2162
2163 /* Initialize and fill the caches with initial entries */
2164 for (k = 0; k < dev->profile.num_cmd_caches; k++) {
2165 ch = &cmd->cache[k];
2166 spin_lock_init(&ch->lock);
2167 INIT_LIST_HEAD(&ch->head);
2168 ch->num_ent = cmd_cache_num_ent[k];
2169 ch->max_inbox_size = cmd_cache_ent_size[k];
2170 for (i = 0; i < ch->num_ent; i++) {
2171 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
2172 ch->max_inbox_size, 0);
2173 if (IS_ERR(msg))
2174 break;
2175 msg->parent = ch;
2176 list_add_tail(&msg->list, &ch->head);
2177 }
2178 }
2179 }
2180
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2181 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2182 {
2183 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE,
2184 &cmd->alloc_dma, GFP_KERNEL);
2185 if (!cmd->cmd_alloc_buf)
2186 return -ENOMEM;
2187
2188 /* make sure it is aligned to 4K */
2189 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
2190 cmd->cmd_buf = cmd->cmd_alloc_buf;
2191 cmd->dma = cmd->alloc_dma;
2192 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
2193 return 0;
2194 }
2195
2196 dma_free_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
2197 cmd->alloc_dma);
2198 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev),
2199 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
2200 &cmd->alloc_dma, GFP_KERNEL);
2201 if (!cmd->cmd_alloc_buf)
2202 return -ENOMEM;
2203
2204 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
2205 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
2206 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
2207 return 0;
2208 }
2209
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2210 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2211 {
2212 dma_free_coherent(mlx5_core_dma_dev(dev), cmd->alloc_size, cmd->cmd_alloc_buf,
2213 cmd->alloc_dma);
2214 }
2215
cmdif_rev(struct mlx5_core_dev * dev)2216 static u16 cmdif_rev(struct mlx5_core_dev *dev)
2217 {
2218 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2219 }
2220
mlx5_cmd_init(struct mlx5_core_dev * dev)2221 int mlx5_cmd_init(struct mlx5_core_dev *dev)
2222 {
2223 struct mlx5_cmd *cmd = &dev->cmd;
2224
2225 cmd->checksum_disabled = 1;
2226
2227 spin_lock_init(&cmd->alloc_lock);
2228 spin_lock_init(&cmd->token_lock);
2229
2230 set_wqname(dev);
2231 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
2232 if (!cmd->wq) {
2233 mlx5_core_err(dev, "failed to create command workqueue\n");
2234 return -ENOMEM;
2235 }
2236
2237 mlx5_cmdif_debugfs_init(dev);
2238
2239 return 0;
2240 }
2241
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)2242 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2243 {
2244 struct mlx5_cmd *cmd = &dev->cmd;
2245
2246 mlx5_cmdif_debugfs_cleanup(dev);
2247 destroy_workqueue(cmd->wq);
2248 }
2249
mlx5_cmd_enable(struct mlx5_core_dev * dev)2250 int mlx5_cmd_enable(struct mlx5_core_dev *dev)
2251 {
2252 int size = sizeof(struct mlx5_cmd_prot_block);
2253 int align = roundup_pow_of_two(size);
2254 struct mlx5_cmd *cmd = &dev->cmd;
2255 u32 cmd_h, cmd_l;
2256 int err;
2257
2258 memset(&cmd->vars, 0, sizeof(cmd->vars));
2259 cmd->vars.cmdif_rev = cmdif_rev(dev);
2260 if (cmd->vars.cmdif_rev != CMD_IF_REV) {
2261 mlx5_core_err(dev,
2262 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
2263 CMD_IF_REV, cmd->vars.cmdif_rev);
2264 return -EINVAL;
2265 }
2266
2267 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
2268 cmd->vars.log_sz = cmd_l >> 4 & 0xf;
2269 cmd->vars.log_stride = cmd_l & 0xf;
2270 if (1 << cmd->vars.log_sz > MLX5_MAX_COMMANDS) {
2271 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
2272 1 << cmd->vars.log_sz);
2273 return -EINVAL;
2274 }
2275
2276 if (cmd->vars.log_sz + cmd->vars.log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
2277 mlx5_core_err(dev, "command queue size overflow\n");
2278 return -EINVAL;
2279 }
2280
2281 cmd->state = MLX5_CMDIF_STATE_DOWN;
2282 cmd->vars.max_reg_cmds = (1 << cmd->vars.log_sz) - 1;
2283 cmd->vars.bitmask = MLX5_CMD_MASK;
2284
2285 sema_init(&cmd->vars.sem, cmd->vars.max_reg_cmds);
2286 sema_init(&cmd->vars.pages_sem, 1);
2287 sema_init(&cmd->vars.throttle_sem, DIV_ROUND_UP(cmd->vars.max_reg_cmds, 2));
2288
2289 cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0);
2290 if (!cmd->pool)
2291 return -ENOMEM;
2292
2293 err = alloc_cmd_page(dev, cmd);
2294 if (err)
2295 goto err_free_pool;
2296
2297 cmd_h = (u32)((u64)(cmd->dma) >> 32);
2298 cmd_l = (u32)(cmd->dma);
2299 if (cmd_l & 0xfff) {
2300 mlx5_core_err(dev, "invalid command queue address\n");
2301 err = -ENOMEM;
2302 goto err_cmd_page;
2303 }
2304
2305 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
2306 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
2307
2308 /* Make sure firmware sees the complete address before we proceed */
2309 wmb();
2310
2311 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
2312
2313 cmd->mode = CMD_MODE_POLLING;
2314 cmd->allowed_opcode = CMD_ALLOWED_OPCODE_ALL;
2315
2316 create_msg_cache(dev);
2317 create_debugfs_files(dev);
2318
2319 return 0;
2320
2321 err_cmd_page:
2322 free_cmd_page(dev, cmd);
2323 err_free_pool:
2324 dma_pool_destroy(cmd->pool);
2325 return err;
2326 }
2327
mlx5_cmd_disable(struct mlx5_core_dev * dev)2328 void mlx5_cmd_disable(struct mlx5_core_dev *dev)
2329 {
2330 struct mlx5_cmd *cmd = &dev->cmd;
2331
2332 flush_workqueue(cmd->wq);
2333 clean_debug_files(dev);
2334 destroy_msg_cache(dev);
2335 free_cmd_page(dev, cmd);
2336 dma_pool_destroy(cmd->pool);
2337 }
2338
mlx5_cmd_set_state(struct mlx5_core_dev * dev,enum mlx5_cmdif_state cmdif_state)2339 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
2340 enum mlx5_cmdif_state cmdif_state)
2341 {
2342 dev->cmd.state = cmdif_state;
2343 }
2344