1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 status = "fail"; 317 }; 318 319 dmic_codec: dmic-codec { 320 compatible = "dmic-codec"; 321 num-channels = <2>; 322 wakeup-delay-ms = <50>; 323 }; 324 325 sound: mt8195-sound { 326 mediatek,platform = <&afe>; 327 status = "disabled"; 328 }; 329 330 clk13m: fixed-factor-clock-13m { 331 compatible = "fixed-factor-clock"; 332 #clock-cells = <0>; 333 clocks = <&clk26m>; 334 clock-div = <2>; 335 clock-mult = <1>; 336 clock-output-names = "clk13m"; 337 }; 338 339 clk26m: oscillator-26m { 340 compatible = "fixed-clock"; 341 #clock-cells = <0>; 342 clock-frequency = <26000000>; 343 clock-output-names = "clk26m"; 344 }; 345 346 clk32k: oscillator-32k { 347 compatible = "fixed-clock"; 348 #clock-cells = <0>; 349 clock-frequency = <32768>; 350 clock-output-names = "clk32k"; 351 }; 352 353 performance: performance-controller@11bc10 { 354 compatible = "mediatek,cpufreq-hw"; 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 356 #performance-domain-cells = <1>; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-390000000 { 364 opp-hz = /bits/ 64 <390000000>; 365 opp-microvolt = <625000>; 366 }; 367 opp-410000000 { 368 opp-hz = /bits/ 64 <410000000>; 369 opp-microvolt = <631250>; 370 }; 371 opp-431000000 { 372 opp-hz = /bits/ 64 <431000000>; 373 opp-microvolt = <631250>; 374 }; 375 opp-473000000 { 376 opp-hz = /bits/ 64 <473000000>; 377 opp-microvolt = <637500>; 378 }; 379 opp-515000000 { 380 opp-hz = /bits/ 64 <515000000>; 381 opp-microvolt = <637500>; 382 }; 383 opp-556000000 { 384 opp-hz = /bits/ 64 <556000000>; 385 opp-microvolt = <643750>; 386 }; 387 opp-598000000 { 388 opp-hz = /bits/ 64 <598000000>; 389 opp-microvolt = <650000>; 390 }; 391 opp-640000000 { 392 opp-hz = /bits/ 64 <640000000>; 393 opp-microvolt = <650000>; 394 }; 395 opp-670000000 { 396 opp-hz = /bits/ 64 <670000000>; 397 opp-microvolt = <662500>; 398 }; 399 opp-700000000 { 400 opp-hz = /bits/ 64 <700000000>; 401 opp-microvolt = <675000>; 402 }; 403 opp-730000000 { 404 opp-hz = /bits/ 64 <730000000>; 405 opp-microvolt = <687500>; 406 }; 407 opp-760000000 { 408 opp-hz = /bits/ 64 <760000000>; 409 opp-microvolt = <700000>; 410 }; 411 opp-790000000 { 412 opp-hz = /bits/ 64 <790000000>; 413 opp-microvolt = <712500>; 414 }; 415 opp-820000000 { 416 opp-hz = /bits/ 64 <820000000>; 417 opp-microvolt = <725000>; 418 }; 419 opp-850000000 { 420 opp-hz = /bits/ 64 <850000000>; 421 opp-microvolt = <737500>; 422 }; 423 opp-880000000 { 424 opp-hz = /bits/ 64 <880000000>; 425 opp-microvolt = <750000>; 426 }; 427 }; 428 429 pmu-a55 { 430 compatible = "arm,cortex-a55-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 433 }; 434 435 pmu-a78 { 436 compatible = "arm,cortex-a78-pmu"; 437 interrupt-parent = <&gic>; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 }; 445 446 timer: timer { 447 compatible = "arm,armv8-timer"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 453 }; 454 455 soc { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 compatible = "simple-bus"; 459 ranges; 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 461 462 gic: interrupt-controller@c000000 { 463 compatible = "arm,gic-v3"; 464 #interrupt-cells = <4>; 465 #redistributor-regions = <1>; 466 interrupt-parent = <&gic>; 467 interrupt-controller; 468 reg = <0 0x0c000000 0 0x40000>, 469 <0 0x0c040000 0 0x200000>; 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 479 }; 480 }; 481 }; 482 483 topckgen: syscon@10000000 { 484 compatible = "mediatek,mt8195-topckgen", "syscon"; 485 reg = <0 0x10000000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 infracfg_ao: syscon@10001000 { 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 491 reg = <0 0x10001000 0 0x1000>; 492 #clock-cells = <1>; 493 #reset-cells = <1>; 494 }; 495 496 pericfg: syscon@10003000 { 497 compatible = "mediatek,mt8195-pericfg", "syscon"; 498 reg = <0 0x10003000 0 0x1000>; 499 #clock-cells = <1>; 500 }; 501 502 pio: pinctrl@10005000 { 503 compatible = "mediatek,mt8195-pinctrl"; 504 reg = <0 0x10005000 0 0x1000>, 505 <0 0x11d10000 0 0x1000>, 506 <0 0x11d30000 0 0x1000>, 507 <0 0x11d40000 0 0x1000>, 508 <0 0x11e20000 0 0x1000>, 509 <0 0x11eb0000 0 0x1000>, 510 <0 0x11f40000 0 0x1000>, 511 <0 0x1000b000 0 0x1000>; 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 513 "iocfg_br", "iocfg_lm", "iocfg_rb", 514 "iocfg_tl", "eint"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pio 0 0 144>; 518 interrupt-controller; 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 520 #interrupt-cells = <2>; 521 }; 522 523 scpsys: syscon@10006000 { 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 525 reg = <0 0x10006000 0 0x1000>; 526 527 /* System Power Manager */ 528 spm: power-controller { 529 compatible = "mediatek,mt8195-power-controller"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 /* power domain of the SoC */ 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 536 reg = <MT8195_POWER_DOMAIN_MFG0>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 #power-domain-cells = <1>; 540 541 power-domain@MT8195_POWER_DOMAIN_MFG1 { 542 reg = <MT8195_POWER_DOMAIN_MFG1>; 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 544 <&topckgen CLK_TOP_MFG_CORE_TMP>; 545 clock-names = "mfg", "alt"; 546 mediatek,infracfg = <&infracfg_ao>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 #power-domain-cells = <1>; 550 551 power-domain@MT8195_POWER_DOMAIN_MFG2 { 552 reg = <MT8195_POWER_DOMAIN_MFG2>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@MT8195_POWER_DOMAIN_MFG3 { 557 reg = <MT8195_POWER_DOMAIN_MFG3>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_MFG4 { 562 reg = <MT8195_POWER_DOMAIN_MFG4>; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8195_POWER_DOMAIN_MFG5 { 567 reg = <MT8195_POWER_DOMAIN_MFG5>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_MFG6 { 572 reg = <MT8195_POWER_DOMAIN_MFG6>; 573 #power-domain-cells = <0>; 574 }; 575 }; 576 }; 577 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 580 clocks = <&topckgen CLK_TOP_VPP>, 581 <&topckgen CLK_TOP_CAM>, 582 <&topckgen CLK_TOP_CCU>, 583 <&topckgen CLK_TOP_IMG>, 584 <&topckgen CLK_TOP_VENC>, 585 <&topckgen CLK_TOP_VDEC>, 586 <&topckgen CLK_TOP_WPE_VPP>, 587 <&topckgen CLK_TOP_CFG_VPP0>, 588 <&vppsys0 CLK_VPP0_SMI_COMMON>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 593 <&vppsys0 CLK_VPP0_GALS_INFRA>, 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 597 <&vppsys0 CLK_VPP0_SMI_REORDER>, 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 602 <&vppsys0 CLK_VPP0_SMI_RSI>, 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 612 "vppsys0-12", "vppsys0-13", "vppsys0-14", 613 "vppsys0-15", "vppsys0-16", "vppsys0-17", 614 "vppsys0-18"; 615 mediatek,infracfg = <&infracfg_ao>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 621 reg = <MT8195_POWER_DOMAIN_VDEC1>; 622 clocks = <&vdecsys CLK_VDEC_LARB1>; 623 clock-names = "vdec1-0"; 624 mediatek,infracfg = <&infracfg_ao>; 625 #power-domain-cells = <0>; 626 }; 627 628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 630 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>; 631 clock-names = "venc1-larb"; 632 mediatek,infracfg = <&infracfg_ao>; 633 #power-domain-cells = <0>; 634 }; 635 636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 637 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 638 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 639 <&vdosys0 CLK_VDO0_SMI_GALS>, 640 <&vdosys0 CLK_VDO0_SMI_COMMON>, 641 <&vdosys0 CLK_VDO0_SMI_EMI>, 642 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 643 <&vdosys0 CLK_VDO0_SMI_LARB>, 644 <&vdosys0 CLK_VDO0_SMI_RSI>; 645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 646 "vdosys0-2", "vdosys0-3", 647 "vdosys0-4", "vdosys0-5"; 648 mediatek,infracfg = <&infracfg_ao>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 #power-domain-cells = <1>; 652 653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 654 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 655 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 656 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 657 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 658 clock-names = "vppsys1", "vppsys1-0", 659 "vppsys1-1"; 660 mediatek,infracfg = <&infracfg_ao>; 661 #power-domain-cells = <0>; 662 }; 663 664 power-domain@MT8195_POWER_DOMAIN_WPESYS { 665 reg = <MT8195_POWER_DOMAIN_WPESYS>; 666 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 667 <&wpesys CLK_WPE_SMI_LARB8>, 668 <&wpesys CLK_WPE_SMI_LARB7_P>, 669 <&wpesys CLK_WPE_SMI_LARB8_P>; 670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 671 "wepsys-3"; 672 mediatek,infracfg = <&infracfg_ao>; 673 #power-domain-cells = <0>; 674 }; 675 676 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 677 reg = <MT8195_POWER_DOMAIN_VDEC0>; 678 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 679 clock-names = "vdec0-0"; 680 mediatek,infracfg = <&infracfg_ao>; 681 #power-domain-cells = <0>; 682 }; 683 684 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 685 reg = <MT8195_POWER_DOMAIN_VDEC2>; 686 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 687 clock-names = "vdec2-0"; 688 mediatek,infracfg = <&infracfg_ao>; 689 #power-domain-cells = <0>; 690 }; 691 692 power-domain@MT8195_POWER_DOMAIN_VENC { 693 reg = <MT8195_POWER_DOMAIN_VENC>; 694 clocks = <&vencsys CLK_VENC_LARB>; 695 clock-names = "venc0-larb"; 696 mediatek,infracfg = <&infracfg_ao>; 697 #power-domain-cells = <0>; 698 }; 699 700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 701 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 702 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 703 <&vdosys1 CLK_VDO1_SMI_LARB2>, 704 <&vdosys1 CLK_VDO1_SMI_LARB3>, 705 <&vdosys1 CLK_VDO1_GALS>; 706 clock-names = "vdosys1", "vdosys1-0", 707 "vdosys1-1", "vdosys1-2"; 708 mediatek,infracfg = <&infracfg_ao>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 #power-domain-cells = <1>; 712 713 power-domain@MT8195_POWER_DOMAIN_DP_TX { 714 reg = <MT8195_POWER_DOMAIN_DP_TX>; 715 mediatek,infracfg = <&infracfg_ao>; 716 #power-domain-cells = <0>; 717 }; 718 719 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 720 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 721 mediatek,infracfg = <&infracfg_ao>; 722 #power-domain-cells = <0>; 723 }; 724 725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 726 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 727 clocks = <&topckgen CLK_TOP_HDMI_APB>; 728 clock-names = "hdmi_tx"; 729 #power-domain-cells = <0>; 730 }; 731 }; 732 733 power-domain@MT8195_POWER_DOMAIN_IMG { 734 reg = <MT8195_POWER_DOMAIN_IMG>; 735 clocks = <&imgsys CLK_IMG_LARB9>, 736 <&imgsys CLK_IMG_GALS>; 737 clock-names = "img-0", "img-1"; 738 mediatek,infracfg = <&infracfg_ao>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 #power-domain-cells = <1>; 742 743 power-domain@MT8195_POWER_DOMAIN_DIP { 744 reg = <MT8195_POWER_DOMAIN_DIP>; 745 #power-domain-cells = <0>; 746 }; 747 748 power-domain@MT8195_POWER_DOMAIN_IPE { 749 reg = <MT8195_POWER_DOMAIN_IPE>; 750 clocks = <&topckgen CLK_TOP_IPE>, 751 <&imgsys CLK_IMG_IPE>, 752 <&ipesys CLK_IPE_SMI_LARB12>; 753 clock-names = "ipe", "ipe-0", "ipe-1"; 754 mediatek,infracfg = <&infracfg_ao>; 755 #power-domain-cells = <0>; 756 }; 757 }; 758 759 power-domain@MT8195_POWER_DOMAIN_CAM { 760 reg = <MT8195_POWER_DOMAIN_CAM>; 761 clocks = <&camsys CLK_CAM_LARB13>, 762 <&camsys CLK_CAM_LARB14>, 763 <&camsys CLK_CAM_CAM2MM0_GALS>, 764 <&camsys CLK_CAM_CAM2MM1_GALS>, 765 <&camsys CLK_CAM_CAM2SYS_GALS>; 766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 767 "cam-4"; 768 mediatek,infracfg = <&infracfg_ao>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 #power-domain-cells = <1>; 772 773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 774 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 775 #power-domain-cells = <0>; 776 }; 777 778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 779 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 780 #power-domain-cells = <0>; 781 }; 782 783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 784 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 785 #power-domain-cells = <0>; 786 }; 787 }; 788 }; 789 }; 790 791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 792 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 793 mediatek,infracfg = <&infracfg_ao>; 794 #power-domain-cells = <0>; 795 }; 796 797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 798 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 799 mediatek,infracfg = <&infracfg_ao>; 800 #power-domain-cells = <0>; 801 }; 802 803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 804 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 805 #power-domain-cells = <0>; 806 }; 807 808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 809 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 810 #power-domain-cells = <0>; 811 }; 812 813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 814 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 815 clocks = <&topckgen CLK_TOP_SENINF>, 816 <&topckgen CLK_TOP_SENINF2>; 817 clock-names = "csi_rx_top", "csi_rx_top1"; 818 #power-domain-cells = <0>; 819 }; 820 821 power-domain@MT8195_POWER_DOMAIN_ETHER { 822 reg = <MT8195_POWER_DOMAIN_ETHER>; 823 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 824 clock-names = "ether"; 825 #power-domain-cells = <0>; 826 }; 827 828 power-domain@MT8195_POWER_DOMAIN_ADSP { 829 reg = <MT8195_POWER_DOMAIN_ADSP>; 830 clocks = <&topckgen CLK_TOP_ADSP>, 831 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 832 clock-names = "adsp", "adsp1"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 mediatek,infracfg = <&infracfg_ao>; 836 #power-domain-cells = <1>; 837 838 power-domain@MT8195_POWER_DOMAIN_AUDIO { 839 reg = <MT8195_POWER_DOMAIN_AUDIO>; 840 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 841 <&topckgen CLK_TOP_AUD_INTBUS>, 842 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 843 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 844 clock-names = "audio", "audio1", "audio2", 845 "audio3"; 846 mediatek,infracfg = <&infracfg_ao>; 847 #power-domain-cells = <0>; 848 }; 849 }; 850 }; 851 }; 852 853 watchdog: watchdog@10007000 { 854 compatible = "mediatek,mt8195-wdt"; 855 mediatek,disable-extrst; 856 reg = <0 0x10007000 0 0x100>; 857 #reset-cells = <1>; 858 }; 859 860 apmixedsys: syscon@1000c000 { 861 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 862 reg = <0 0x1000c000 0 0x1000>; 863 #clock-cells = <1>; 864 }; 865 866 systimer: timer@10017000 { 867 compatible = "mediatek,mt8195-timer", 868 "mediatek,mt6765-timer"; 869 reg = <0 0x10017000 0 0x1000>; 870 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 871 clocks = <&clk13m>; 872 }; 873 874 pwrap: pwrap@10024000 { 875 compatible = "mediatek,mt8195-pwrap", "syscon"; 876 reg = <0 0x10024000 0 0x1000>; 877 reg-names = "pwrap"; 878 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 879 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 880 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 881 clock-names = "spi", "wrap"; 882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 884 }; 885 886 spmi: spmi@10027000 { 887 compatible = "mediatek,mt8195-spmi"; 888 reg = <0 0x10027000 0 0x000e00>, 889 <0 0x10029000 0 0x000100>; 890 reg-names = "pmif", "spmimst"; 891 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 892 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 893 <&topckgen CLK_TOP_SPMI_M_MST>; 894 clock-names = "pmif_sys_ck", 895 "pmif_tmr_ck", 896 "spmimst_clk_mux"; 897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 899 }; 900 901 iommu_infra: infra-iommu@10315000 { 902 compatible = "mediatek,mt8195-iommu-infra"; 903 reg = <0 0x10315000 0 0x5000>; 904 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 905 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 906 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 907 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 908 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 909 #iommu-cells = <1>; 910 }; 911 912 gce0: mailbox@10320000 { 913 compatible = "mediatek,mt8195-gce"; 914 reg = <0 0x10320000 0 0x4000>; 915 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 916 #mbox-cells = <2>; 917 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 918 }; 919 920 gce1: mailbox@10330000 { 921 compatible = "mediatek,mt8195-gce"; 922 reg = <0 0x10330000 0 0x4000>; 923 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 924 #mbox-cells = <2>; 925 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 926 }; 927 928 scp: scp@10500000 { 929 compatible = "mediatek,mt8195-scp"; 930 reg = <0 0x10500000 0 0x100000>, 931 <0 0x10720000 0 0xe0000>, 932 <0 0x10700000 0 0x8000>; 933 reg-names = "sram", "cfg", "l1tcm"; 934 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 935 status = "disabled"; 936 }; 937 938 scp_adsp: clock-controller@10720000 { 939 compatible = "mediatek,mt8195-scp_adsp"; 940 reg = <0 0x10720000 0 0x1000>; 941 #clock-cells = <1>; 942 }; 943 944 adsp: dsp@10803000 { 945 compatible = "mediatek,mt8195-dsp"; 946 reg = <0 0x10803000 0 0x1000>, 947 <0 0x10840000 0 0x40000>; 948 reg-names = "cfg", "sram"; 949 clocks = <&topckgen CLK_TOP_ADSP>, 950 <&clk26m>, 951 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 952 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 953 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 954 <&topckgen CLK_TOP_AUDIO_H>; 955 clock-names = "adsp_sel", 956 "clk26m_ck", 957 "audio_local_bus", 958 "mainpll_d7_d2", 959 "scp_adsp_audiodsp", 960 "audio_h"; 961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 962 mbox-names = "rx", "tx"; 963 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 964 status = "disabled"; 965 }; 966 967 adsp_mailbox0: mailbox@10816000 { 968 compatible = "mediatek,mt8195-adsp-mbox"; 969 #mbox-cells = <0>; 970 reg = <0 0x10816000 0 0x1000>; 971 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 972 }; 973 974 adsp_mailbox1: mailbox@10817000 { 975 compatible = "mediatek,mt8195-adsp-mbox"; 976 #mbox-cells = <0>; 977 reg = <0 0x10817000 0 0x1000>; 978 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 979 }; 980 981 afe: mt8195-afe-pcm@10890000 { 982 compatible = "mediatek,mt8195-audio"; 983 reg = <0 0x10890000 0 0x10000>; 984 mediatek,topckgen = <&topckgen>; 985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 986 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 987 resets = <&watchdog 14>; 988 reset-names = "audiosys"; 989 clocks = <&clk26m>, 990 <&apmixedsys CLK_APMIXED_APLL1>, 991 <&apmixedsys CLK_APMIXED_APLL2>, 992 <&topckgen CLK_TOP_APLL12_DIV0>, 993 <&topckgen CLK_TOP_APLL12_DIV1>, 994 <&topckgen CLK_TOP_APLL12_DIV2>, 995 <&topckgen CLK_TOP_APLL12_DIV3>, 996 <&topckgen CLK_TOP_APLL12_DIV9>, 997 <&topckgen CLK_TOP_A1SYS_HP>, 998 <&topckgen CLK_TOP_AUD_INTBUS>, 999 <&topckgen CLK_TOP_AUDIO_H>, 1000 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1001 <&topckgen CLK_TOP_DPTX_MCK>, 1002 <&topckgen CLK_TOP_I2SO1_MCK>, 1003 <&topckgen CLK_TOP_I2SO2_MCK>, 1004 <&topckgen CLK_TOP_I2SI1_MCK>, 1005 <&topckgen CLK_TOP_I2SI2_MCK>, 1006 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1007 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1008 clock-names = "clk26m", 1009 "apll1_ck", 1010 "apll2_ck", 1011 "apll12_div0", 1012 "apll12_div1", 1013 "apll12_div2", 1014 "apll12_div3", 1015 "apll12_div9", 1016 "a1sys_hp_sel", 1017 "aud_intbus_sel", 1018 "audio_h_sel", 1019 "audio_local_bus_sel", 1020 "dptx_m_sel", 1021 "i2so1_m_sel", 1022 "i2so2_m_sel", 1023 "i2si1_m_sel", 1024 "i2si2_m_sel", 1025 "infra_ao_audio_26m_b", 1026 "scp_adsp_audiodsp"; 1027 status = "disabled"; 1028 }; 1029 1030 uart0: serial@11001100 { 1031 compatible = "mediatek,mt8195-uart", 1032 "mediatek,mt6577-uart"; 1033 reg = <0 0x11001100 0 0x100>; 1034 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1035 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1036 clock-names = "baud", "bus"; 1037 status = "disabled"; 1038 }; 1039 1040 uart1: serial@11001200 { 1041 compatible = "mediatek,mt8195-uart", 1042 "mediatek,mt6577-uart"; 1043 reg = <0 0x11001200 0 0x100>; 1044 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1045 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1046 clock-names = "baud", "bus"; 1047 status = "disabled"; 1048 }; 1049 1050 uart2: serial@11001300 { 1051 compatible = "mediatek,mt8195-uart", 1052 "mediatek,mt6577-uart"; 1053 reg = <0 0x11001300 0 0x100>; 1054 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1055 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1056 clock-names = "baud", "bus"; 1057 status = "disabled"; 1058 }; 1059 1060 uart3: serial@11001400 { 1061 compatible = "mediatek,mt8195-uart", 1062 "mediatek,mt6577-uart"; 1063 reg = <0 0x11001400 0 0x100>; 1064 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1065 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1066 clock-names = "baud", "bus"; 1067 status = "disabled"; 1068 }; 1069 1070 uart4: serial@11001500 { 1071 compatible = "mediatek,mt8195-uart", 1072 "mediatek,mt6577-uart"; 1073 reg = <0 0x11001500 0 0x100>; 1074 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1075 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1076 clock-names = "baud", "bus"; 1077 status = "disabled"; 1078 }; 1079 1080 uart5: serial@11001600 { 1081 compatible = "mediatek,mt8195-uart", 1082 "mediatek,mt6577-uart"; 1083 reg = <0 0x11001600 0 0x100>; 1084 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1085 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1086 clock-names = "baud", "bus"; 1087 status = "disabled"; 1088 }; 1089 1090 auxadc: auxadc@11002000 { 1091 compatible = "mediatek,mt8195-auxadc", 1092 "mediatek,mt8173-auxadc"; 1093 reg = <0 0x11002000 0 0x1000>; 1094 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1095 clock-names = "main"; 1096 #io-channel-cells = <1>; 1097 status = "disabled"; 1098 }; 1099 1100 pericfg_ao: syscon@11003000 { 1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1102 reg = <0 0x11003000 0 0x1000>; 1103 #clock-cells = <1>; 1104 }; 1105 1106 spi0: spi@1100a000 { 1107 compatible = "mediatek,mt8195-spi", 1108 "mediatek,mt6765-spi"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 reg = <0 0x1100a000 0 0x1000>; 1112 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1113 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1114 <&topckgen CLK_TOP_SPI>, 1115 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1116 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1117 status = "disabled"; 1118 }; 1119 1120 lvts_ap: thermal-sensor@1100b000 { 1121 compatible = "mediatek,mt8195-lvts-ap"; 1122 reg = <0 0x1100b000 0 0x1000>; 1123 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1124 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1125 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1128 #thermal-sensor-cells = <1>; 1129 }; 1130 1131 disp_pwm0: pwm@1100e000 { 1132 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1133 reg = <0 0x1100e000 0 0x1000>; 1134 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1135 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1136 #pwm-cells = <2>; 1137 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1138 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1139 clock-names = "main", "mm"; 1140 status = "disabled"; 1141 }; 1142 1143 disp_pwm1: pwm@1100f000 { 1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1145 reg = <0 0x1100f000 0 0x1000>; 1146 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1147 #pwm-cells = <2>; 1148 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1149 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1150 clock-names = "main", "mm"; 1151 status = "disabled"; 1152 }; 1153 1154 spi1: spi@11010000 { 1155 compatible = "mediatek,mt8195-spi", 1156 "mediatek,mt6765-spi"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 reg = <0 0x11010000 0 0x1000>; 1160 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1161 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1162 <&topckgen CLK_TOP_SPI>, 1163 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1164 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1165 status = "disabled"; 1166 }; 1167 1168 spi2: spi@11012000 { 1169 compatible = "mediatek,mt8195-spi", 1170 "mediatek,mt6765-spi"; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 reg = <0 0x11012000 0 0x1000>; 1174 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1175 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1176 <&topckgen CLK_TOP_SPI>, 1177 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1178 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1179 status = "disabled"; 1180 }; 1181 1182 spi3: spi@11013000 { 1183 compatible = "mediatek,mt8195-spi", 1184 "mediatek,mt6765-spi"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 reg = <0 0x11013000 0 0x1000>; 1188 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1189 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1190 <&topckgen CLK_TOP_SPI>, 1191 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1192 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1193 status = "disabled"; 1194 }; 1195 1196 spi4: spi@11018000 { 1197 compatible = "mediatek,mt8195-spi", 1198 "mediatek,mt6765-spi"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 reg = <0 0x11018000 0 0x1000>; 1202 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1203 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1204 <&topckgen CLK_TOP_SPI>, 1205 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1206 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1207 status = "disabled"; 1208 }; 1209 1210 spi5: spi@11019000 { 1211 compatible = "mediatek,mt8195-spi", 1212 "mediatek,mt6765-spi"; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 reg = <0 0x11019000 0 0x1000>; 1216 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1217 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1218 <&topckgen CLK_TOP_SPI>, 1219 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1220 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1221 status = "disabled"; 1222 }; 1223 1224 spis0: spi@1101d000 { 1225 compatible = "mediatek,mt8195-spi-slave"; 1226 reg = <0 0x1101d000 0 0x1000>; 1227 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1228 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1229 clock-names = "spi"; 1230 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1231 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1232 status = "disabled"; 1233 }; 1234 1235 spis1: spi@1101e000 { 1236 compatible = "mediatek,mt8195-spi-slave"; 1237 reg = <0 0x1101e000 0 0x1000>; 1238 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1239 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1240 clock-names = "spi"; 1241 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1242 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1243 status = "disabled"; 1244 }; 1245 1246 eth: ethernet@11021000 { 1247 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1248 reg = <0 0x11021000 0 0x4000>; 1249 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1250 interrupt-names = "macirq"; 1251 clock-names = "axi", 1252 "apb", 1253 "mac_main", 1254 "ptp_ref", 1255 "rmii_internal", 1256 "mac_cg"; 1257 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1258 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1259 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1260 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1261 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1262 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1263 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1264 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1265 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1266 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1267 <&topckgen CLK_TOP_ETHPLL_D8>, 1268 <&topckgen CLK_TOP_ETHPLL_D10>; 1269 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1270 mediatek,pericfg = <&infracfg_ao>; 1271 snps,axi-config = <&stmmac_axi_setup>; 1272 snps,mtl-rx-config = <&mtl_rx_setup>; 1273 snps,mtl-tx-config = <&mtl_tx_setup>; 1274 snps,txpbl = <16>; 1275 snps,rxpbl = <16>; 1276 snps,clk-csr = <0>; 1277 status = "disabled"; 1278 1279 mdio { 1280 compatible = "snps,dwmac-mdio"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 }; 1284 1285 stmmac_axi_setup: stmmac-axi-config { 1286 snps,wr_osr_lmt = <0x7>; 1287 snps,rd_osr_lmt = <0x7>; 1288 snps,blen = <0 0 0 0 16 8 4>; 1289 }; 1290 1291 mtl_rx_setup: rx-queues-config { 1292 snps,rx-queues-to-use = <4>; 1293 snps,rx-sched-sp; 1294 queue0 { 1295 snps,dcb-algorithm; 1296 snps,map-to-dma-channel = <0x0>; 1297 }; 1298 queue1 { 1299 snps,dcb-algorithm; 1300 snps,map-to-dma-channel = <0x0>; 1301 }; 1302 queue2 { 1303 snps,dcb-algorithm; 1304 snps,map-to-dma-channel = <0x0>; 1305 }; 1306 queue3 { 1307 snps,dcb-algorithm; 1308 snps,map-to-dma-channel = <0x0>; 1309 }; 1310 }; 1311 1312 mtl_tx_setup: tx-queues-config { 1313 snps,tx-queues-to-use = <4>; 1314 snps,tx-sched-wrr; 1315 queue0 { 1316 snps,weight = <0x10>; 1317 snps,dcb-algorithm; 1318 snps,priority = <0x0>; 1319 }; 1320 queue1 { 1321 snps,weight = <0x11>; 1322 snps,dcb-algorithm; 1323 snps,priority = <0x1>; 1324 }; 1325 queue2 { 1326 snps,weight = <0x12>; 1327 snps,dcb-algorithm; 1328 snps,priority = <0x2>; 1329 }; 1330 queue3 { 1331 snps,weight = <0x13>; 1332 snps,dcb-algorithm; 1333 snps,priority = <0x3>; 1334 }; 1335 }; 1336 }; 1337 1338 xhci0: usb@11200000 { 1339 compatible = "mediatek,mt8195-xhci", 1340 "mediatek,mtk-xhci"; 1341 reg = <0 0x11200000 0 0x1000>, 1342 <0 0x11203e00 0 0x0100>; 1343 reg-names = "mac", "ippc"; 1344 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1345 phys = <&u2port0 PHY_TYPE_USB2>, 1346 <&u3port0 PHY_TYPE_USB3>; 1347 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1348 <&topckgen CLK_TOP_SSUSB_XHCI>; 1349 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1350 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1351 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1352 <&topckgen CLK_TOP_SSUSB_REF>, 1353 <&apmixedsys CLK_APMIXED_USB1PLL>, 1354 <&clk26m>, 1355 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1356 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1357 "xhci_ck"; 1358 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1359 wakeup-source; 1360 status = "disabled"; 1361 }; 1362 1363 mmc0: mmc@11230000 { 1364 compatible = "mediatek,mt8195-mmc", 1365 "mediatek,mt8183-mmc"; 1366 reg = <0 0x11230000 0 0x10000>, 1367 <0 0x11f50000 0 0x1000>; 1368 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1369 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1370 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1371 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1372 clock-names = "source", "hclk", "source_cg"; 1373 status = "disabled"; 1374 }; 1375 1376 mmc1: mmc@11240000 { 1377 compatible = "mediatek,mt8195-mmc", 1378 "mediatek,mt8183-mmc"; 1379 reg = <0 0x11240000 0 0x1000>, 1380 <0 0x11c70000 0 0x1000>; 1381 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1382 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1383 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1384 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1385 clock-names = "source", "hclk", "source_cg"; 1386 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1387 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1388 status = "disabled"; 1389 }; 1390 1391 mmc2: mmc@11250000 { 1392 compatible = "mediatek,mt8195-mmc", 1393 "mediatek,mt8183-mmc"; 1394 reg = <0 0x11250000 0 0x1000>, 1395 <0 0x11e60000 0 0x1000>; 1396 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1397 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1398 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1399 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1400 clock-names = "source", "hclk", "source_cg"; 1401 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1402 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1403 status = "disabled"; 1404 }; 1405 1406 lvts_mcu: thermal-sensor@11278000 { 1407 compatible = "mediatek,mt8195-lvts-mcu"; 1408 reg = <0 0x11278000 0 0x1000>; 1409 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1410 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1411 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1412 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1413 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1414 #thermal-sensor-cells = <1>; 1415 }; 1416 1417 xhci1: usb@11290000 { 1418 compatible = "mediatek,mt8195-xhci", 1419 "mediatek,mtk-xhci"; 1420 reg = <0 0x11290000 0 0x1000>, 1421 <0 0x11293e00 0 0x0100>; 1422 reg-names = "mac", "ippc"; 1423 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1424 phys = <&u2port1 PHY_TYPE_USB2>; 1425 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1426 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1427 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1428 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1429 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1430 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1431 <&apmixedsys CLK_APMIXED_USB1PLL>, 1432 <&clk26m>, 1433 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1434 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1435 "xhci_ck"; 1436 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1437 wakeup-source; 1438 status = "disabled"; 1439 }; 1440 1441 xhci2: usb@112a0000 { 1442 compatible = "mediatek,mt8195-xhci", 1443 "mediatek,mtk-xhci"; 1444 reg = <0 0x112a0000 0 0x1000>, 1445 <0 0x112a3e00 0 0x0100>; 1446 reg-names = "mac", "ippc"; 1447 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1448 phys = <&u2port2 PHY_TYPE_USB2>; 1449 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1450 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1451 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1452 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1453 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1454 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1455 <&clk26m>, 1456 <&clk26m>, 1457 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1458 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1459 "xhci_ck"; 1460 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1461 wakeup-source; 1462 status = "disabled"; 1463 }; 1464 1465 xhci3: usb@112b0000 { 1466 compatible = "mediatek,mt8195-xhci", 1467 "mediatek,mtk-xhci"; 1468 reg = <0 0x112b0000 0 0x1000>, 1469 <0 0x112b3e00 0 0x0100>; 1470 reg-names = "mac", "ippc"; 1471 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1472 phys = <&u2port3 PHY_TYPE_USB2>; 1473 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1474 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1475 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1476 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1477 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1478 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1479 <&clk26m>, 1480 <&clk26m>, 1481 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1482 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1483 "xhci_ck"; 1484 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1485 wakeup-source; 1486 status = "disabled"; 1487 }; 1488 1489 pcie0: pcie@112f0000 { 1490 compatible = "mediatek,mt8195-pcie", 1491 "mediatek,mt8192-pcie"; 1492 device_type = "pci"; 1493 #address-cells = <3>; 1494 #size-cells = <2>; 1495 reg = <0 0x112f0000 0 0x4000>; 1496 reg-names = "pcie-mac"; 1497 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1498 bus-range = <0x00 0xff>; 1499 ranges = <0x81000000 0 0x20000000 1500 0x0 0x20000000 0 0x200000>, 1501 <0x82000000 0 0x20200000 1502 0x0 0x20200000 0 0x3e00000>; 1503 1504 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1505 iommu-map-mask = <0x0>; 1506 1507 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1508 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1509 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1510 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1511 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1512 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1513 clock-names = "pl_250m", "tl_26m", "tl_96m", 1514 "tl_32k", "peri_26m", "peri_mem"; 1515 assigned-clocks = <&topckgen CLK_TOP_TL>; 1516 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1517 1518 phys = <&pciephy>; 1519 phy-names = "pcie-phy"; 1520 1521 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1522 1523 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1524 reset-names = "mac"; 1525 1526 #interrupt-cells = <1>; 1527 interrupt-map-mask = <0 0 0 7>; 1528 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1529 <0 0 0 2 &pcie_intc0 1>, 1530 <0 0 0 3 &pcie_intc0 2>, 1531 <0 0 0 4 &pcie_intc0 3>; 1532 status = "disabled"; 1533 1534 pcie_intc0: interrupt-controller { 1535 interrupt-controller; 1536 #address-cells = <0>; 1537 #interrupt-cells = <1>; 1538 }; 1539 }; 1540 1541 pcie1: pcie@112f8000 { 1542 compatible = "mediatek,mt8195-pcie", 1543 "mediatek,mt8192-pcie"; 1544 device_type = "pci"; 1545 #address-cells = <3>; 1546 #size-cells = <2>; 1547 reg = <0 0x112f8000 0 0x4000>; 1548 reg-names = "pcie-mac"; 1549 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1550 bus-range = <0x00 0xff>; 1551 ranges = <0x81000000 0 0x24000000 1552 0x0 0x24000000 0 0x200000>, 1553 <0x82000000 0 0x24200000 1554 0x0 0x24200000 0 0x3e00000>; 1555 1556 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1557 iommu-map-mask = <0x0>; 1558 1559 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1560 <&clk26m>, 1561 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1562 <&clk26m>, 1563 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1564 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1565 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1566 clock-names = "pl_250m", "tl_26m", "tl_96m", 1567 "tl_32k", "peri_26m", "peri_mem"; 1568 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1569 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1570 1571 phys = <&u3port1 PHY_TYPE_PCIE>; 1572 phy-names = "pcie-phy"; 1573 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1574 1575 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1576 reset-names = "mac"; 1577 1578 #interrupt-cells = <1>; 1579 interrupt-map-mask = <0 0 0 7>; 1580 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1581 <0 0 0 2 &pcie_intc1 1>, 1582 <0 0 0 3 &pcie_intc1 2>, 1583 <0 0 0 4 &pcie_intc1 3>; 1584 status = "disabled"; 1585 1586 pcie_intc1: interrupt-controller { 1587 interrupt-controller; 1588 #address-cells = <0>; 1589 #interrupt-cells = <1>; 1590 }; 1591 }; 1592 1593 nor_flash: spi@1132c000 { 1594 compatible = "mediatek,mt8195-nor", 1595 "mediatek,mt8173-nor"; 1596 reg = <0 0x1132c000 0 0x1000>; 1597 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1598 clocks = <&topckgen CLK_TOP_SPINOR>, 1599 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1600 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1601 clock-names = "spi", "sf", "axi"; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 efuse: efuse@11c10000 { 1608 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1609 reg = <0 0x11c10000 0 0x1000>; 1610 #address-cells = <1>; 1611 #size-cells = <1>; 1612 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1613 reg = <0x184 0x1>; 1614 bits = <0 5>; 1615 }; 1616 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1617 reg = <0x184 0x2>; 1618 bits = <5 5>; 1619 }; 1620 u3_intr_p0: usb3-intr@185 { 1621 reg = <0x185 0x1>; 1622 bits = <2 6>; 1623 }; 1624 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1625 reg = <0x186 0x1>; 1626 bits = <0 5>; 1627 }; 1628 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1629 reg = <0x186 0x2>; 1630 bits = <5 5>; 1631 }; 1632 comb_intr_p1: usb3-intr@187 { 1633 reg = <0x187 0x1>; 1634 bits = <2 6>; 1635 }; 1636 u2_intr_p0: usb2-intr-p0@188,1 { 1637 reg = <0x188 0x1>; 1638 bits = <0 5>; 1639 }; 1640 u2_intr_p1: usb2-intr-p1@188,2 { 1641 reg = <0x188 0x2>; 1642 bits = <5 5>; 1643 }; 1644 u2_intr_p2: usb2-intr-p2@189,1 { 1645 reg = <0x189 0x1>; 1646 bits = <2 5>; 1647 }; 1648 u2_intr_p3: usb2-intr-p3@189,2 { 1649 reg = <0x189 0x2>; 1650 bits = <7 5>; 1651 }; 1652 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1653 reg = <0x190 0x1>; 1654 bits = <0 4>; 1655 }; 1656 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1657 reg = <0x190 0x1>; 1658 bits = <4 4>; 1659 }; 1660 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1661 reg = <0x191 0x1>; 1662 bits = <0 4>; 1663 }; 1664 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1665 reg = <0x191 0x1>; 1666 bits = <4 4>; 1667 }; 1668 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1669 reg = <0x192 0x1>; 1670 bits = <0 4>; 1671 }; 1672 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1673 reg = <0x192 0x1>; 1674 bits = <4 4>; 1675 }; 1676 pciephy_glb_intr: pciephy-glb-intr@193 { 1677 reg = <0x193 0x1>; 1678 bits = <0 4>; 1679 }; 1680 dp_calibration: dp-data@1ac { 1681 reg = <0x1ac 0x10>; 1682 }; 1683 lvts_efuse_data1: lvts1-calib@1bc { 1684 reg = <0x1bc 0x14>; 1685 }; 1686 lvts_efuse_data2: lvts2-calib@1d0 { 1687 reg = <0x1d0 0x38>; 1688 }; 1689 }; 1690 1691 u3phy2: t-phy@11c40000 { 1692 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1693 #address-cells = <1>; 1694 #size-cells = <1>; 1695 ranges = <0 0 0x11c40000 0x700>; 1696 status = "disabled"; 1697 1698 u2port2: usb-phy@0 { 1699 reg = <0x0 0x700>; 1700 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1701 clock-names = "ref"; 1702 #phy-cells = <1>; 1703 }; 1704 }; 1705 1706 u3phy3: t-phy@11c50000 { 1707 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1708 #address-cells = <1>; 1709 #size-cells = <1>; 1710 ranges = <0 0 0x11c50000 0x700>; 1711 status = "disabled"; 1712 1713 u2port3: usb-phy@0 { 1714 reg = <0x0 0x700>; 1715 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1716 clock-names = "ref"; 1717 #phy-cells = <1>; 1718 }; 1719 }; 1720 1721 i2c5: i2c@11d00000 { 1722 compatible = "mediatek,mt8195-i2c", 1723 "mediatek,mt8192-i2c"; 1724 reg = <0 0x11d00000 0 0x1000>, 1725 <0 0x10220580 0 0x80>; 1726 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1727 clock-div = <1>; 1728 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1729 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1730 clock-names = "main", "dma"; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 status = "disabled"; 1734 }; 1735 1736 i2c6: i2c@11d01000 { 1737 compatible = "mediatek,mt8195-i2c", 1738 "mediatek,mt8192-i2c"; 1739 reg = <0 0x11d01000 0 0x1000>, 1740 <0 0x10220600 0 0x80>; 1741 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1742 clock-div = <1>; 1743 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1744 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1745 clock-names = "main", "dma"; 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 status = "disabled"; 1749 }; 1750 1751 i2c7: i2c@11d02000 { 1752 compatible = "mediatek,mt8195-i2c", 1753 "mediatek,mt8192-i2c"; 1754 reg = <0 0x11d02000 0 0x1000>, 1755 <0 0x10220680 0 0x80>; 1756 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1757 clock-div = <1>; 1758 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1759 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1760 clock-names = "main", "dma"; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 status = "disabled"; 1764 }; 1765 1766 imp_iic_wrap_s: clock-controller@11d03000 { 1767 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1768 reg = <0 0x11d03000 0 0x1000>; 1769 #clock-cells = <1>; 1770 }; 1771 1772 i2c0: i2c@11e00000 { 1773 compatible = "mediatek,mt8195-i2c", 1774 "mediatek,mt8192-i2c"; 1775 reg = <0 0x11e00000 0 0x1000>, 1776 <0 0x10220080 0 0x80>; 1777 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1778 clock-div = <1>; 1779 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1780 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1781 clock-names = "main", "dma"; 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 status = "disabled"; 1785 }; 1786 1787 i2c1: i2c@11e01000 { 1788 compatible = "mediatek,mt8195-i2c", 1789 "mediatek,mt8192-i2c"; 1790 reg = <0 0x11e01000 0 0x1000>, 1791 <0 0x10220200 0 0x80>; 1792 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1793 clock-div = <1>; 1794 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1795 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1796 clock-names = "main", "dma"; 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 status = "disabled"; 1800 }; 1801 1802 i2c2: i2c@11e02000 { 1803 compatible = "mediatek,mt8195-i2c", 1804 "mediatek,mt8192-i2c"; 1805 reg = <0 0x11e02000 0 0x1000>, 1806 <0 0x10220380 0 0x80>; 1807 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1808 clock-div = <1>; 1809 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1810 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1811 clock-names = "main", "dma"; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 status = "disabled"; 1815 }; 1816 1817 i2c3: i2c@11e03000 { 1818 compatible = "mediatek,mt8195-i2c", 1819 "mediatek,mt8192-i2c"; 1820 reg = <0 0x11e03000 0 0x1000>, 1821 <0 0x10220480 0 0x80>; 1822 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1823 clock-div = <1>; 1824 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1825 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1826 clock-names = "main", "dma"; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 status = "disabled"; 1830 }; 1831 1832 i2c4: i2c@11e04000 { 1833 compatible = "mediatek,mt8195-i2c", 1834 "mediatek,mt8192-i2c"; 1835 reg = <0 0x11e04000 0 0x1000>, 1836 <0 0x10220500 0 0x80>; 1837 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1838 clock-div = <1>; 1839 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1840 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1841 clock-names = "main", "dma"; 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 status = "disabled"; 1845 }; 1846 1847 imp_iic_wrap_w: clock-controller@11e05000 { 1848 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1849 reg = <0 0x11e05000 0 0x1000>; 1850 #clock-cells = <1>; 1851 }; 1852 1853 u3phy1: t-phy@11e30000 { 1854 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1855 #address-cells = <1>; 1856 #size-cells = <1>; 1857 ranges = <0 0 0x11e30000 0xe00>; 1858 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1859 status = "disabled"; 1860 1861 u2port1: usb-phy@0 { 1862 reg = <0x0 0x700>; 1863 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1864 <&clk26m>; 1865 clock-names = "ref", "da_ref"; 1866 #phy-cells = <1>; 1867 }; 1868 1869 u3port1: usb-phy@700 { 1870 reg = <0x700 0x700>; 1871 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1872 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1873 clock-names = "ref", "da_ref"; 1874 nvmem-cells = <&comb_intr_p1>, 1875 <&comb_rx_imp_p1>, 1876 <&comb_tx_imp_p1>; 1877 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1878 #phy-cells = <1>; 1879 }; 1880 }; 1881 1882 u3phy0: t-phy@11e40000 { 1883 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1884 #address-cells = <1>; 1885 #size-cells = <1>; 1886 ranges = <0 0 0x11e40000 0xe00>; 1887 status = "disabled"; 1888 1889 u2port0: usb-phy@0 { 1890 reg = <0x0 0x700>; 1891 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1892 <&clk26m>; 1893 clock-names = "ref", "da_ref"; 1894 #phy-cells = <1>; 1895 }; 1896 1897 u3port0: usb-phy@700 { 1898 reg = <0x700 0x700>; 1899 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1900 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1901 clock-names = "ref", "da_ref"; 1902 nvmem-cells = <&u3_intr_p0>, 1903 <&u3_rx_imp_p0>, 1904 <&u3_tx_imp_p0>; 1905 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1906 #phy-cells = <1>; 1907 }; 1908 }; 1909 1910 pciephy: phy@11e80000 { 1911 compatible = "mediatek,mt8195-pcie-phy"; 1912 reg = <0 0x11e80000 0 0x10000>; 1913 reg-names = "sif"; 1914 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1915 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1916 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1917 <&pciephy_rx_ln1>; 1918 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1919 "tx_ln0_nmos", "rx_ln0", 1920 "tx_ln1_pmos", "tx_ln1_nmos", 1921 "rx_ln1"; 1922 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1923 #phy-cells = <0>; 1924 status = "disabled"; 1925 }; 1926 1927 ufsphy: ufs-phy@11fa0000 { 1928 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1929 reg = <0 0x11fa0000 0 0xc000>; 1930 clocks = <&clk26m>, <&clk26m>; 1931 clock-names = "unipro", "mp"; 1932 #phy-cells = <0>; 1933 status = "disabled"; 1934 }; 1935 1936 gpu: gpu@13000000 { 1937 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 1938 "arm,mali-valhall-jm"; 1939 reg = <0 0x13000000 0 0x4000>; 1940 1941 clocks = <&mfgcfg CLK_MFG_BG3D>; 1942 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 1943 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 1944 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 1945 interrupt-names = "job", "mmu", "gpu"; 1946 operating-points-v2 = <&gpu_opp_table>; 1947 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 1948 <&spm MT8195_POWER_DOMAIN_MFG3>, 1949 <&spm MT8195_POWER_DOMAIN_MFG4>, 1950 <&spm MT8195_POWER_DOMAIN_MFG5>, 1951 <&spm MT8195_POWER_DOMAIN_MFG6>; 1952 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1953 status = "disabled"; 1954 }; 1955 1956 mfgcfg: clock-controller@13fbf000 { 1957 compatible = "mediatek,mt8195-mfgcfg"; 1958 reg = <0 0x13fbf000 0 0x1000>; 1959 #clock-cells = <1>; 1960 }; 1961 1962 vppsys0: syscon@14000000 { 1963 compatible = "mediatek,mt8195-vppsys0", "syscon"; 1964 reg = <0 0x14000000 0 0x1000>; 1965 #clock-cells = <1>; 1966 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; 1967 }; 1968 1969 mutex@1400f000 { 1970 compatible = "mediatek,mt8195-vpp-mutex"; 1971 reg = <0 0x1400f000 0 0x1000>; 1972 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 1973 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 1974 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 1975 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1976 }; 1977 1978 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1979 compatible = "mediatek,mt8195-smi-sub-common"; 1980 reg = <0 0x14010000 0 0x1000>; 1981 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1982 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1983 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1984 clock-names = "apb", "smi", "gals0"; 1985 mediatek,smi = <&smi_common_vpp>; 1986 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1987 }; 1988 1989 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1990 compatible = "mediatek,mt8195-smi-sub-common"; 1991 reg = <0 0x14011000 0 0x1000>; 1992 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1993 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1994 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1995 clock-names = "apb", "smi", "gals0"; 1996 mediatek,smi = <&smi_common_vpp>; 1997 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1998 }; 1999 2000 smi_common_vpp: smi@14012000 { 2001 compatible = "mediatek,mt8195-smi-common-vpp"; 2002 reg = <0 0x14012000 0 0x1000>; 2003 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2004 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2005 <&vppsys0 CLK_VPP0_SMI_RSI>, 2006 <&vppsys0 CLK_VPP0_SMI_RSI>; 2007 clock-names = "apb", "smi", "gals0", "gals1"; 2008 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2009 }; 2010 2011 larb4: larb@14013000 { 2012 compatible = "mediatek,mt8195-smi-larb"; 2013 reg = <0 0x14013000 0 0x1000>; 2014 mediatek,larb-id = <4>; 2015 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2016 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2017 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2018 clock-names = "apb", "smi"; 2019 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2020 }; 2021 2022 iommu_vpp: iommu@14018000 { 2023 compatible = "mediatek,mt8195-iommu-vpp"; 2024 reg = <0 0x14018000 0 0x1000>; 2025 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2026 &larb12 &larb14 &larb16 &larb18 2027 &larb20 &larb22 &larb23 &larb26 2028 &larb27>; 2029 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2030 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2031 clock-names = "bclk"; 2032 #iommu-cells = <1>; 2033 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2034 }; 2035 2036 wpesys: clock-controller@14e00000 { 2037 compatible = "mediatek,mt8195-wpesys"; 2038 reg = <0 0x14e00000 0 0x1000>; 2039 #clock-cells = <1>; 2040 }; 2041 2042 wpesys_vpp0: clock-controller@14e02000 { 2043 compatible = "mediatek,mt8195-wpesys_vpp0"; 2044 reg = <0 0x14e02000 0 0x1000>; 2045 #clock-cells = <1>; 2046 }; 2047 2048 wpesys_vpp1: clock-controller@14e03000 { 2049 compatible = "mediatek,mt8195-wpesys_vpp1"; 2050 reg = <0 0x14e03000 0 0x1000>; 2051 #clock-cells = <1>; 2052 }; 2053 2054 larb7: larb@14e04000 { 2055 compatible = "mediatek,mt8195-smi-larb"; 2056 reg = <0 0x14e04000 0 0x1000>; 2057 mediatek,larb-id = <7>; 2058 mediatek,smi = <&smi_common_vdo>; 2059 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2060 <&wpesys CLK_WPE_SMI_LARB7>; 2061 clock-names = "apb", "smi"; 2062 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2063 }; 2064 2065 larb8: larb@14e05000 { 2066 compatible = "mediatek,mt8195-smi-larb"; 2067 reg = <0 0x14e05000 0 0x1000>; 2068 mediatek,larb-id = <8>; 2069 mediatek,smi = <&smi_common_vpp>; 2070 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2071 <&wpesys CLK_WPE_SMI_LARB8>, 2072 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2073 clock-names = "apb", "smi", "gals"; 2074 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2075 }; 2076 2077 vppsys1: syscon@14f00000 { 2078 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2079 reg = <0 0x14f00000 0 0x1000>; 2080 #clock-cells = <1>; 2081 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; 2082 }; 2083 2084 mutex@14f01000 { 2085 compatible = "mediatek,mt8195-vpp-mutex"; 2086 reg = <0 0x14f01000 0 0x1000>; 2087 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2088 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2089 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2090 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2091 }; 2092 2093 larb5: larb@14f02000 { 2094 compatible = "mediatek,mt8195-smi-larb"; 2095 reg = <0 0x14f02000 0 0x1000>; 2096 mediatek,larb-id = <5>; 2097 mediatek,smi = <&smi_common_vdo>; 2098 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2099 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2100 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2101 clock-names = "apb", "smi", "gals"; 2102 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2103 }; 2104 2105 larb6: larb@14f03000 { 2106 compatible = "mediatek,mt8195-smi-larb"; 2107 reg = <0 0x14f03000 0 0x1000>; 2108 mediatek,larb-id = <6>; 2109 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2110 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2111 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2112 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2113 clock-names = "apb", "smi", "gals"; 2114 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2115 }; 2116 2117 imgsys: clock-controller@15000000 { 2118 compatible = "mediatek,mt8195-imgsys"; 2119 reg = <0 0x15000000 0 0x1000>; 2120 #clock-cells = <1>; 2121 }; 2122 2123 larb9: larb@15001000 { 2124 compatible = "mediatek,mt8195-smi-larb"; 2125 reg = <0 0x15001000 0 0x1000>; 2126 mediatek,larb-id = <9>; 2127 mediatek,smi = <&smi_sub_common_img1_3x1>; 2128 clocks = <&imgsys CLK_IMG_LARB9>, 2129 <&imgsys CLK_IMG_LARB9>, 2130 <&imgsys CLK_IMG_GALS>; 2131 clock-names = "apb", "smi", "gals"; 2132 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2133 }; 2134 2135 smi_sub_common_img0_3x1: smi@15002000 { 2136 compatible = "mediatek,mt8195-smi-sub-common"; 2137 reg = <0 0x15002000 0 0x1000>; 2138 clocks = <&imgsys CLK_IMG_IPE>, 2139 <&imgsys CLK_IMG_IPE>, 2140 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2141 clock-names = "apb", "smi", "gals0"; 2142 mediatek,smi = <&smi_common_vpp>; 2143 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2144 }; 2145 2146 smi_sub_common_img1_3x1: smi@15003000 { 2147 compatible = "mediatek,mt8195-smi-sub-common"; 2148 reg = <0 0x15003000 0 0x1000>; 2149 clocks = <&imgsys CLK_IMG_LARB9>, 2150 <&imgsys CLK_IMG_LARB9>, 2151 <&imgsys CLK_IMG_GALS>; 2152 clock-names = "apb", "smi", "gals0"; 2153 mediatek,smi = <&smi_common_vdo>; 2154 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2155 }; 2156 2157 imgsys1_dip_top: clock-controller@15110000 { 2158 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2159 reg = <0 0x15110000 0 0x1000>; 2160 #clock-cells = <1>; 2161 }; 2162 2163 larb10: larb@15120000 { 2164 compatible = "mediatek,mt8195-smi-larb"; 2165 reg = <0 0x15120000 0 0x1000>; 2166 mediatek,larb-id = <10>; 2167 mediatek,smi = <&smi_sub_common_img1_3x1>; 2168 clocks = <&imgsys CLK_IMG_DIP0>, 2169 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2170 clock-names = "apb", "smi"; 2171 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2172 }; 2173 2174 imgsys1_dip_nr: clock-controller@15130000 { 2175 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2176 reg = <0 0x15130000 0 0x1000>; 2177 #clock-cells = <1>; 2178 }; 2179 2180 imgsys1_wpe: clock-controller@15220000 { 2181 compatible = "mediatek,mt8195-imgsys1_wpe"; 2182 reg = <0 0x15220000 0 0x1000>; 2183 #clock-cells = <1>; 2184 }; 2185 2186 larb11: larb@15230000 { 2187 compatible = "mediatek,mt8195-smi-larb"; 2188 reg = <0 0x15230000 0 0x1000>; 2189 mediatek,larb-id = <11>; 2190 mediatek,smi = <&smi_sub_common_img1_3x1>; 2191 clocks = <&imgsys CLK_IMG_WPE0>, 2192 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2193 clock-names = "apb", "smi"; 2194 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2195 }; 2196 2197 ipesys: clock-controller@15330000 { 2198 compatible = "mediatek,mt8195-ipesys"; 2199 reg = <0 0x15330000 0 0x1000>; 2200 #clock-cells = <1>; 2201 }; 2202 2203 larb12: larb@15340000 { 2204 compatible = "mediatek,mt8195-smi-larb"; 2205 reg = <0 0x15340000 0 0x1000>; 2206 mediatek,larb-id = <12>; 2207 mediatek,smi = <&smi_sub_common_img0_3x1>; 2208 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2209 <&ipesys CLK_IPE_SMI_LARB12>; 2210 clock-names = "apb", "smi"; 2211 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2212 }; 2213 2214 camsys: clock-controller@16000000 { 2215 compatible = "mediatek,mt8195-camsys"; 2216 reg = <0 0x16000000 0 0x1000>; 2217 #clock-cells = <1>; 2218 }; 2219 2220 larb13: larb@16001000 { 2221 compatible = "mediatek,mt8195-smi-larb"; 2222 reg = <0 0x16001000 0 0x1000>; 2223 mediatek,larb-id = <13>; 2224 mediatek,smi = <&smi_sub_common_cam_4x1>; 2225 clocks = <&camsys CLK_CAM_LARB13>, 2226 <&camsys CLK_CAM_LARB13>, 2227 <&camsys CLK_CAM_CAM2MM0_GALS>; 2228 clock-names = "apb", "smi", "gals"; 2229 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2230 }; 2231 2232 larb14: larb@16002000 { 2233 compatible = "mediatek,mt8195-smi-larb"; 2234 reg = <0 0x16002000 0 0x1000>; 2235 mediatek,larb-id = <14>; 2236 mediatek,smi = <&smi_sub_common_cam_7x1>; 2237 clocks = <&camsys CLK_CAM_LARB14>, 2238 <&camsys CLK_CAM_LARB14>; 2239 clock-names = "apb", "smi"; 2240 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2241 }; 2242 2243 smi_sub_common_cam_4x1: smi@16004000 { 2244 compatible = "mediatek,mt8195-smi-sub-common"; 2245 reg = <0 0x16004000 0 0x1000>; 2246 clocks = <&camsys CLK_CAM_LARB13>, 2247 <&camsys CLK_CAM_LARB13>, 2248 <&camsys CLK_CAM_CAM2MM0_GALS>; 2249 clock-names = "apb", "smi", "gals0"; 2250 mediatek,smi = <&smi_common_vdo>; 2251 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2252 }; 2253 2254 smi_sub_common_cam_7x1: smi@16005000 { 2255 compatible = "mediatek,mt8195-smi-sub-common"; 2256 reg = <0 0x16005000 0 0x1000>; 2257 clocks = <&camsys CLK_CAM_LARB14>, 2258 <&camsys CLK_CAM_CAM2MM1_GALS>, 2259 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2260 clock-names = "apb", "smi", "gals0"; 2261 mediatek,smi = <&smi_common_vpp>; 2262 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2263 }; 2264 2265 larb16: larb@16012000 { 2266 compatible = "mediatek,mt8195-smi-larb"; 2267 reg = <0 0x16012000 0 0x1000>; 2268 mediatek,larb-id = <16>; 2269 mediatek,smi = <&smi_sub_common_cam_7x1>; 2270 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2271 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2272 clock-names = "apb", "smi"; 2273 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2274 }; 2275 2276 larb17: larb@16013000 { 2277 compatible = "mediatek,mt8195-smi-larb"; 2278 reg = <0 0x16013000 0 0x1000>; 2279 mediatek,larb-id = <17>; 2280 mediatek,smi = <&smi_sub_common_cam_4x1>; 2281 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2282 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2283 clock-names = "apb", "smi"; 2284 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2285 }; 2286 2287 larb27: larb@16014000 { 2288 compatible = "mediatek,mt8195-smi-larb"; 2289 reg = <0 0x16014000 0 0x1000>; 2290 mediatek,larb-id = <27>; 2291 mediatek,smi = <&smi_sub_common_cam_7x1>; 2292 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2293 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2294 clock-names = "apb", "smi"; 2295 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2296 }; 2297 2298 larb28: larb@16015000 { 2299 compatible = "mediatek,mt8195-smi-larb"; 2300 reg = <0 0x16015000 0 0x1000>; 2301 mediatek,larb-id = <28>; 2302 mediatek,smi = <&smi_sub_common_cam_4x1>; 2303 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2304 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2305 clock-names = "apb", "smi"; 2306 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2307 }; 2308 2309 camsys_rawa: clock-controller@1604f000 { 2310 compatible = "mediatek,mt8195-camsys_rawa"; 2311 reg = <0 0x1604f000 0 0x1000>; 2312 #clock-cells = <1>; 2313 }; 2314 2315 camsys_yuva: clock-controller@1606f000 { 2316 compatible = "mediatek,mt8195-camsys_yuva"; 2317 reg = <0 0x1606f000 0 0x1000>; 2318 #clock-cells = <1>; 2319 }; 2320 2321 camsys_rawb: clock-controller@1608f000 { 2322 compatible = "mediatek,mt8195-camsys_rawb"; 2323 reg = <0 0x1608f000 0 0x1000>; 2324 #clock-cells = <1>; 2325 }; 2326 2327 camsys_yuvb: clock-controller@160af000 { 2328 compatible = "mediatek,mt8195-camsys_yuvb"; 2329 reg = <0 0x160af000 0 0x1000>; 2330 #clock-cells = <1>; 2331 }; 2332 2333 camsys_mraw: clock-controller@16140000 { 2334 compatible = "mediatek,mt8195-camsys_mraw"; 2335 reg = <0 0x16140000 0 0x1000>; 2336 #clock-cells = <1>; 2337 }; 2338 2339 larb25: larb@16141000 { 2340 compatible = "mediatek,mt8195-smi-larb"; 2341 reg = <0 0x16141000 0 0x1000>; 2342 mediatek,larb-id = <25>; 2343 mediatek,smi = <&smi_sub_common_cam_4x1>; 2344 clocks = <&camsys CLK_CAM_LARB13>, 2345 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2346 <&camsys CLK_CAM_CAM2MM0_GALS>; 2347 clock-names = "apb", "smi", "gals"; 2348 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2349 }; 2350 2351 larb26: larb@16142000 { 2352 compatible = "mediatek,mt8195-smi-larb"; 2353 reg = <0 0x16142000 0 0x1000>; 2354 mediatek,larb-id = <26>; 2355 mediatek,smi = <&smi_sub_common_cam_7x1>; 2356 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2357 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2358 clock-names = "apb", "smi"; 2359 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2360 2361 }; 2362 2363 ccusys: clock-controller@17200000 { 2364 compatible = "mediatek,mt8195-ccusys"; 2365 reg = <0 0x17200000 0 0x1000>; 2366 #clock-cells = <1>; 2367 }; 2368 2369 larb18: larb@17201000 { 2370 compatible = "mediatek,mt8195-smi-larb"; 2371 reg = <0 0x17201000 0 0x1000>; 2372 mediatek,larb-id = <18>; 2373 mediatek,smi = <&smi_sub_common_cam_7x1>; 2374 clocks = <&ccusys CLK_CCU_LARB18>, 2375 <&ccusys CLK_CCU_LARB18>; 2376 clock-names = "apb", "smi"; 2377 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2378 }; 2379 2380 video-codec@18000000 { 2381 compatible = "mediatek,mt8195-vcodec-dec"; 2382 mediatek,scp = <&scp>; 2383 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2384 #address-cells = <2>; 2385 #size-cells = <2>; 2386 reg = <0 0x18000000 0 0x1000>, 2387 <0 0x18004000 0 0x1000>; 2388 ranges = <0 0 0 0x18000000 0 0x26000>; 2389 2390 video-codec@2000 { 2391 compatible = "mediatek,mtk-vcodec-lat-soc"; 2392 reg = <0 0x2000 0 0x800>; 2393 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2394 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2395 clocks = <&topckgen CLK_TOP_VDEC>, 2396 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2397 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2398 <&topckgen CLK_TOP_UNIVPLL_D4>; 2399 clock-names = "sel", "vdec", "lat", "top"; 2400 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2401 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2402 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2403 }; 2404 2405 video-codec@10000 { 2406 compatible = "mediatek,mtk-vcodec-lat"; 2407 reg = <0 0x10000 0 0x800>; 2408 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2409 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2410 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2411 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2412 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2413 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2414 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2415 clocks = <&topckgen CLK_TOP_VDEC>, 2416 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2417 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2418 <&topckgen CLK_TOP_UNIVPLL_D4>; 2419 clock-names = "sel", "vdec", "lat", "top"; 2420 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2421 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2422 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2423 }; 2424 2425 video-codec@25000 { 2426 compatible = "mediatek,mtk-vcodec-core"; 2427 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2428 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2429 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2430 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2431 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2432 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2433 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2434 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2435 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2436 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2437 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2438 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2439 clocks = <&topckgen CLK_TOP_VDEC>, 2440 <&vdecsys CLK_VDEC_VDEC>, 2441 <&vdecsys CLK_VDEC_LAT>, 2442 <&topckgen CLK_TOP_UNIVPLL_D4>; 2443 clock-names = "sel", "vdec", "lat", "top"; 2444 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2445 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2446 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2447 }; 2448 }; 2449 2450 larb24: larb@1800d000 { 2451 compatible = "mediatek,mt8195-smi-larb"; 2452 reg = <0 0x1800d000 0 0x1000>; 2453 mediatek,larb-id = <24>; 2454 mediatek,smi = <&smi_common_vdo>; 2455 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2456 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2457 clock-names = "apb", "smi"; 2458 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2459 }; 2460 2461 larb23: larb@1800e000 { 2462 compatible = "mediatek,mt8195-smi-larb"; 2463 reg = <0 0x1800e000 0 0x1000>; 2464 mediatek,larb-id = <23>; 2465 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2466 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2467 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2468 clock-names = "apb", "smi"; 2469 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2470 }; 2471 2472 vdecsys_soc: clock-controller@1800f000 { 2473 compatible = "mediatek,mt8195-vdecsys_soc"; 2474 reg = <0 0x1800f000 0 0x1000>; 2475 #clock-cells = <1>; 2476 }; 2477 2478 larb21: larb@1802e000 { 2479 compatible = "mediatek,mt8195-smi-larb"; 2480 reg = <0 0x1802e000 0 0x1000>; 2481 mediatek,larb-id = <21>; 2482 mediatek,smi = <&smi_common_vdo>; 2483 clocks = <&vdecsys CLK_VDEC_LARB1>, 2484 <&vdecsys CLK_VDEC_LARB1>; 2485 clock-names = "apb", "smi"; 2486 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2487 }; 2488 2489 vdecsys: clock-controller@1802f000 { 2490 compatible = "mediatek,mt8195-vdecsys"; 2491 reg = <0 0x1802f000 0 0x1000>; 2492 #clock-cells = <1>; 2493 }; 2494 2495 larb22: larb@1803e000 { 2496 compatible = "mediatek,mt8195-smi-larb"; 2497 reg = <0 0x1803e000 0 0x1000>; 2498 mediatek,larb-id = <22>; 2499 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2500 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2501 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2502 clock-names = "apb", "smi"; 2503 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2504 }; 2505 2506 vdecsys_core1: clock-controller@1803f000 { 2507 compatible = "mediatek,mt8195-vdecsys_core1"; 2508 reg = <0 0x1803f000 0 0x1000>; 2509 #clock-cells = <1>; 2510 }; 2511 2512 apusys_pll: clock-controller@190f3000 { 2513 compatible = "mediatek,mt8195-apusys_pll"; 2514 reg = <0 0x190f3000 0 0x1000>; 2515 #clock-cells = <1>; 2516 }; 2517 2518 vencsys: clock-controller@1a000000 { 2519 compatible = "mediatek,mt8195-vencsys"; 2520 reg = <0 0x1a000000 0 0x1000>; 2521 #clock-cells = <1>; 2522 }; 2523 2524 larb19: larb@1a010000 { 2525 compatible = "mediatek,mt8195-smi-larb"; 2526 reg = <0 0x1a010000 0 0x1000>; 2527 mediatek,larb-id = <19>; 2528 mediatek,smi = <&smi_common_vdo>; 2529 clocks = <&vencsys CLK_VENC_VENC>, 2530 <&vencsys CLK_VENC_GALS>; 2531 clock-names = "apb", "smi"; 2532 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2533 }; 2534 2535 venc: video-codec@1a020000 { 2536 compatible = "mediatek,mt8195-vcodec-enc"; 2537 reg = <0 0x1a020000 0 0x10000>; 2538 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2539 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2540 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2541 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2542 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2543 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2544 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2545 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2546 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2547 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2548 mediatek,scp = <&scp>; 2549 clocks = <&vencsys CLK_VENC_VENC>; 2550 clock-names = "venc_sel"; 2551 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2552 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2553 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2554 #address-cells = <2>; 2555 #size-cells = <2>; 2556 }; 2557 2558 jpgdec-master { 2559 compatible = "mediatek,mt8195-jpgdec"; 2560 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2561 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2562 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2563 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2564 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2565 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2566 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2567 #address-cells = <2>; 2568 #size-cells = <2>; 2569 ranges; 2570 2571 jpgdec@1a040000 { 2572 compatible = "mediatek,mt8195-jpgdec-hw"; 2573 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2574 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2575 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2576 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2577 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2578 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2579 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2580 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2581 clocks = <&vencsys CLK_VENC_JPGDEC>; 2582 clock-names = "jpgdec"; 2583 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2584 }; 2585 2586 jpgdec@1a050000 { 2587 compatible = "mediatek,mt8195-jpgdec-hw"; 2588 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2589 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2590 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2591 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2592 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2593 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2594 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2595 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 2596 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 2597 clock-names = "jpgdec"; 2598 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2599 }; 2600 2601 jpgdec@1b040000 { 2602 compatible = "mediatek,mt8195-jpgdec-hw"; 2603 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 2604 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 2605 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 2606 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 2607 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 2608 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 2609 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 2610 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 2611 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 2612 clock-names = "jpgdec"; 2613 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2614 }; 2615 }; 2616 2617 vencsys_core1: clock-controller@1b000000 { 2618 compatible = "mediatek,mt8195-vencsys_core1"; 2619 reg = <0 0x1b000000 0 0x1000>; 2620 #clock-cells = <1>; 2621 }; 2622 2623 vdosys0: syscon@1c01a000 { 2624 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 2625 reg = <0 0x1c01a000 0 0x1000>; 2626 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2627 #clock-cells = <1>; 2628 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 2629 }; 2630 2631 2632 jpgenc-master { 2633 compatible = "mediatek,mt8195-jpgenc"; 2634 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2635 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2636 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2637 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2638 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2639 #address-cells = <2>; 2640 #size-cells = <2>; 2641 ranges; 2642 2643 jpgenc@1a030000 { 2644 compatible = "mediatek,mt8195-jpgenc-hw"; 2645 reg = <0 0x1a030000 0 0x10000>; 2646 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 2647 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 2648 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 2649 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 2650 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 2651 clocks = <&vencsys CLK_VENC_JPGENC>; 2652 clock-names = "jpgenc"; 2653 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2654 }; 2655 2656 jpgenc@1b030000 { 2657 compatible = "mediatek,mt8195-jpgenc-hw"; 2658 reg = <0 0x1b030000 0 0x10000>; 2659 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2660 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2661 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2662 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2663 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 2664 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 2665 clock-names = "jpgenc"; 2666 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2667 }; 2668 }; 2669 2670 larb20: larb@1b010000 { 2671 compatible = "mediatek,mt8195-smi-larb"; 2672 reg = <0 0x1b010000 0 0x1000>; 2673 mediatek,larb-id = <20>; 2674 mediatek,smi = <&smi_common_vpp>; 2675 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, 2676 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2677 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2678 clock-names = "apb", "smi", "gals"; 2679 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2680 }; 2681 2682 ovl0: ovl@1c000000 { 2683 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2684 reg = <0 0x1c000000 0 0x1000>; 2685 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2686 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2687 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2688 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2689 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2690 }; 2691 2692 rdma0: rdma@1c002000 { 2693 compatible = "mediatek,mt8195-disp-rdma"; 2694 reg = <0 0x1c002000 0 0x1000>; 2695 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2696 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2697 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2698 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2699 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2700 }; 2701 2702 color0: color@1c003000 { 2703 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2704 reg = <0 0x1c003000 0 0x1000>; 2705 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2706 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2707 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2708 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2709 }; 2710 2711 ccorr0: ccorr@1c004000 { 2712 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2713 reg = <0 0x1c004000 0 0x1000>; 2714 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2715 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2716 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2717 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2718 }; 2719 2720 aal0: aal@1c005000 { 2721 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2722 reg = <0 0x1c005000 0 0x1000>; 2723 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2724 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2725 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2726 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2727 }; 2728 2729 gamma0: gamma@1c006000 { 2730 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2731 reg = <0 0x1c006000 0 0x1000>; 2732 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2733 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2734 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2735 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2736 }; 2737 2738 dither0: dither@1c007000 { 2739 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2740 reg = <0 0x1c007000 0 0x1000>; 2741 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2742 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2743 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2744 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2745 }; 2746 2747 dsc0: dsc@1c009000 { 2748 compatible = "mediatek,mt8195-disp-dsc"; 2749 reg = <0 0x1c009000 0 0x1000>; 2750 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2751 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2752 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2753 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2754 }; 2755 2756 merge0: merge@1c014000 { 2757 compatible = "mediatek,mt8195-disp-merge"; 2758 reg = <0 0x1c014000 0 0x1000>; 2759 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2760 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2761 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2762 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2763 }; 2764 2765 dp_intf0: dp-intf@1c015000 { 2766 compatible = "mediatek,mt8195-dp-intf"; 2767 reg = <0 0x1c015000 0 0x1000>; 2768 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2769 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2770 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2771 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2772 clock-names = "engine", "pixel", "pll"; 2773 status = "disabled"; 2774 }; 2775 2776 mutex: mutex@1c016000 { 2777 compatible = "mediatek,mt8195-disp-mutex"; 2778 reg = <0 0x1c016000 0 0x1000>; 2779 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2780 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2781 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2782 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 2783 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2784 }; 2785 2786 larb0: larb@1c018000 { 2787 compatible = "mediatek,mt8195-smi-larb"; 2788 reg = <0 0x1c018000 0 0x1000>; 2789 mediatek,larb-id = <0>; 2790 mediatek,smi = <&smi_common_vdo>; 2791 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2792 <&vdosys0 CLK_VDO0_SMI_LARB>, 2793 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2794 clock-names = "apb", "smi", "gals"; 2795 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2796 }; 2797 2798 larb1: larb@1c019000 { 2799 compatible = "mediatek,mt8195-smi-larb"; 2800 reg = <0 0x1c019000 0 0x1000>; 2801 mediatek,larb-id = <1>; 2802 mediatek,smi = <&smi_common_vpp>; 2803 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2804 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2805 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2806 clock-names = "apb", "smi", "gals"; 2807 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2808 }; 2809 2810 vdosys1: syscon@1c100000 { 2811 compatible = "mediatek,mt8195-vdosys1", "syscon"; 2812 reg = <0 0x1c100000 0 0x1000>; 2813 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 2814 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 2815 #clock-cells = <1>; 2816 #reset-cells = <1>; 2817 }; 2818 2819 smi_common_vdo: smi@1c01b000 { 2820 compatible = "mediatek,mt8195-smi-common-vdo"; 2821 reg = <0 0x1c01b000 0 0x1000>; 2822 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2823 <&vdosys0 CLK_VDO0_SMI_EMI>, 2824 <&vdosys0 CLK_VDO0_SMI_RSI>, 2825 <&vdosys0 CLK_VDO0_SMI_GALS>; 2826 clock-names = "apb", "smi", "gals0", "gals1"; 2827 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2828 2829 }; 2830 2831 iommu_vdo: iommu@1c01f000 { 2832 compatible = "mediatek,mt8195-iommu-vdo"; 2833 reg = <0 0x1c01f000 0 0x1000>; 2834 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2835 &larb10 &larb11 &larb13 &larb17 2836 &larb19 &larb21 &larb24 &larb25 2837 &larb28>; 2838 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2839 #iommu-cells = <1>; 2840 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2841 clock-names = "bclk"; 2842 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2843 }; 2844 2845 mutex1: mutex@1c101000 { 2846 compatible = "mediatek,mt8195-disp-mutex"; 2847 reg = <0 0x1c101000 0 0x1000>; 2848 reg-names = "vdo1_mutex"; 2849 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 2850 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2851 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 2852 clock-names = "vdo1_mutex"; 2853 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 2854 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 2855 }; 2856 2857 larb2: larb@1c102000 { 2858 compatible = "mediatek,mt8195-smi-larb"; 2859 reg = <0 0x1c102000 0 0x1000>; 2860 mediatek,larb-id = <2>; 2861 mediatek,smi = <&smi_common_vdo>; 2862 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2863 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2864 <&vdosys1 CLK_VDO1_GALS>; 2865 clock-names = "apb", "smi", "gals"; 2866 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2867 }; 2868 2869 larb3: larb@1c103000 { 2870 compatible = "mediatek,mt8195-smi-larb"; 2871 reg = <0 0x1c103000 0 0x1000>; 2872 mediatek,larb-id = <3>; 2873 mediatek,smi = <&smi_common_vpp>; 2874 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2875 <&vdosys1 CLK_VDO1_GALS>, 2876 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2877 clock-names = "apb", "smi", "gals"; 2878 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2879 }; 2880 2881 vdo1_rdma0: dma-controller@1c104000 { 2882 compatible = "mediatek,mt8195-vdo1-rdma"; 2883 reg = <0 0x1c104000 0 0x1000>; 2884 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 2885 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 2886 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2887 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 2888 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 2889 #dma-cells = <1>; 2890 }; 2891 2892 vdo1_rdma1: dma-controller@1c105000 { 2893 compatible = "mediatek,mt8195-vdo1-rdma"; 2894 reg = <0 0x1c105000 0 0x1000>; 2895 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 2896 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 2897 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2898 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 2899 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 2900 #dma-cells = <1>; 2901 }; 2902 2903 vdo1_rdma2: dma-controller@1c106000 { 2904 compatible = "mediatek,mt8195-vdo1-rdma"; 2905 reg = <0 0x1c106000 0 0x1000>; 2906 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 2907 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 2908 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2909 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 2910 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 2911 #dma-cells = <1>; 2912 }; 2913 2914 vdo1_rdma3: dma-controller@1c107000 { 2915 compatible = "mediatek,mt8195-vdo1-rdma"; 2916 reg = <0 0x1c107000 0 0x1000>; 2917 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 2918 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 2919 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2920 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 2921 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 2922 #dma-cells = <1>; 2923 }; 2924 2925 vdo1_rdma4: dma-controller@1c108000 { 2926 compatible = "mediatek,mt8195-vdo1-rdma"; 2927 reg = <0 0x1c108000 0 0x1000>; 2928 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 2929 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 2930 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2931 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 2932 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 2933 #dma-cells = <1>; 2934 }; 2935 2936 vdo1_rdma5: dma-controller@1c109000 { 2937 compatible = "mediatek,mt8195-vdo1-rdma"; 2938 reg = <0 0x1c109000 0 0x1000>; 2939 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 2940 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 2941 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2942 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 2943 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 2944 #dma-cells = <1>; 2945 }; 2946 2947 vdo1_rdma6: dma-controller@1c10a000 { 2948 compatible = "mediatek,mt8195-vdo1-rdma"; 2949 reg = <0 0x1c10a000 0 0x1000>; 2950 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 2951 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 2952 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2953 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 2954 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 2955 #dma-cells = <1>; 2956 }; 2957 2958 vdo1_rdma7: dma-controller@1c10b000 { 2959 compatible = "mediatek,mt8195-vdo1-rdma"; 2960 reg = <0 0x1c10b000 0 0x1000>; 2961 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 2962 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 2963 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2964 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 2965 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 2966 #dma-cells = <1>; 2967 }; 2968 2969 merge1: vpp-merge@1c10c000 { 2970 compatible = "mediatek,mt8195-disp-merge"; 2971 reg = <0 0x1c10c000 0 0x1000>; 2972 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 2973 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 2974 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 2975 clock-names = "merge","merge_async"; 2976 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2977 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 2978 mediatek,merge-mute; 2979 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 2980 }; 2981 2982 merge2: vpp-merge@1c10d000 { 2983 compatible = "mediatek,mt8195-disp-merge"; 2984 reg = <0 0x1c10d000 0 0x1000>; 2985 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 2986 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 2987 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 2988 clock-names = "merge","merge_async"; 2989 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2990 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 2991 mediatek,merge-mute; 2992 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 2993 }; 2994 2995 merge3: vpp-merge@1c10e000 { 2996 compatible = "mediatek,mt8195-disp-merge"; 2997 reg = <0 0x1c10e000 0 0x1000>; 2998 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 2999 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3000 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3001 clock-names = "merge","merge_async"; 3002 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3003 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3004 mediatek,merge-mute; 3005 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3006 }; 3007 3008 merge4: vpp-merge@1c10f000 { 3009 compatible = "mediatek,mt8195-disp-merge"; 3010 reg = <0 0x1c10f000 0 0x1000>; 3011 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3012 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3013 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3014 clock-names = "merge","merge_async"; 3015 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3016 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3017 mediatek,merge-mute; 3018 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3019 }; 3020 3021 merge5: vpp-merge@1c110000 { 3022 compatible = "mediatek,mt8195-disp-merge"; 3023 reg = <0 0x1c110000 0 0x1000>; 3024 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3025 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3026 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3027 clock-names = "merge","merge_async"; 3028 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3029 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3030 mediatek,merge-fifo-en; 3031 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3032 }; 3033 3034 dp_intf1: dp-intf@1c113000 { 3035 compatible = "mediatek,mt8195-dp-intf"; 3036 reg = <0 0x1c113000 0 0x1000>; 3037 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3038 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3039 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3040 <&vdosys1 CLK_VDO1_DPINTF>, 3041 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3042 clock-names = "engine", "pixel", "pll"; 3043 status = "disabled"; 3044 }; 3045 3046 ethdr0: hdr-engine@1c114000 { 3047 compatible = "mediatek,mt8195-disp-ethdr"; 3048 reg = <0 0x1c114000 0 0x1000>, 3049 <0 0x1c115000 0 0x1000>, 3050 <0 0x1c117000 0 0x1000>, 3051 <0 0x1c119000 0 0x1000>, 3052 <0 0x1c11a000 0 0x1000>, 3053 <0 0x1c11b000 0 0x1000>, 3054 <0 0x1c11c000 0 0x1000>; 3055 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3056 "vdo_be", "adl_ds"; 3057 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3058 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3059 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3060 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3061 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3062 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3063 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3064 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3065 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3066 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3067 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3068 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3069 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3070 <&vdosys1 CLK_VDO1_26M_SLOW>, 3071 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3072 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3073 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3074 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3075 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3076 <&topckgen CLK_TOP_ETHDR>; 3077 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3078 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3079 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3080 "ethdr_top"; 3081 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3082 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3083 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3084 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3085 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3086 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3087 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3088 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3089 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3090 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3091 "gfx_fe1_async", "vdo_be_async"; 3092 }; 3093 3094 edp_tx: edp-tx@1c500000 { 3095 compatible = "mediatek,mt8195-edp-tx"; 3096 reg = <0 0x1c500000 0 0x8000>; 3097 nvmem-cells = <&dp_calibration>; 3098 nvmem-cell-names = "dp_calibration_data"; 3099 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3100 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3101 max-linkrate-mhz = <8100>; 3102 status = "disabled"; 3103 }; 3104 3105 dp_tx: dp-tx@1c600000 { 3106 compatible = "mediatek,mt8195-dp-tx"; 3107 reg = <0 0x1c600000 0 0x8000>; 3108 nvmem-cells = <&dp_calibration>; 3109 nvmem-cell-names = "dp_calibration_data"; 3110 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3111 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3112 max-linkrate-mhz = <8100>; 3113 status = "disabled"; 3114 }; 3115 }; 3116 3117 thermal_zones: thermal-zones { 3118 cpu0-thermal { 3119 polling-delay = <1000>; 3120 polling-delay-passive = <250>; 3121 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3122 3123 trips { 3124 cpu0_alert: trip-alert { 3125 temperature = <85000>; 3126 hysteresis = <2000>; 3127 type = "passive"; 3128 }; 3129 3130 cpu0_crit: trip-crit { 3131 temperature = <100000>; 3132 hysteresis = <2000>; 3133 type = "critical"; 3134 }; 3135 }; 3136 3137 cooling-maps { 3138 map0 { 3139 trip = <&cpu0_alert>; 3140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3141 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3142 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3143 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3144 }; 3145 }; 3146 }; 3147 3148 cpu1-thermal { 3149 polling-delay = <1000>; 3150 polling-delay-passive = <250>; 3151 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3152 3153 trips { 3154 cpu1_alert: trip-alert { 3155 temperature = <85000>; 3156 hysteresis = <2000>; 3157 type = "passive"; 3158 }; 3159 3160 cpu1_crit: trip-crit { 3161 temperature = <100000>; 3162 hysteresis = <2000>; 3163 type = "critical"; 3164 }; 3165 }; 3166 3167 cooling-maps { 3168 map0 { 3169 trip = <&cpu1_alert>; 3170 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3171 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3172 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3173 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3174 }; 3175 }; 3176 }; 3177 3178 cpu2-thermal { 3179 polling-delay = <1000>; 3180 polling-delay-passive = <250>; 3181 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3182 3183 trips { 3184 cpu2_alert: trip-alert { 3185 temperature = <85000>; 3186 hysteresis = <2000>; 3187 type = "passive"; 3188 }; 3189 3190 cpu2_crit: trip-crit { 3191 temperature = <100000>; 3192 hysteresis = <2000>; 3193 type = "critical"; 3194 }; 3195 }; 3196 3197 cooling-maps { 3198 map0 { 3199 trip = <&cpu2_alert>; 3200 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3201 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3202 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3203 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3204 }; 3205 }; 3206 }; 3207 3208 cpu3-thermal { 3209 polling-delay = <1000>; 3210 polling-delay-passive = <250>; 3211 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3212 3213 trips { 3214 cpu3_alert: trip-alert { 3215 temperature = <85000>; 3216 hysteresis = <2000>; 3217 type = "passive"; 3218 }; 3219 3220 cpu3_crit: trip-crit { 3221 temperature = <100000>; 3222 hysteresis = <2000>; 3223 type = "critical"; 3224 }; 3225 }; 3226 3227 cooling-maps { 3228 map0 { 3229 trip = <&cpu3_alert>; 3230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3234 }; 3235 }; 3236 }; 3237 3238 cpu4-thermal { 3239 polling-delay = <1000>; 3240 polling-delay-passive = <250>; 3241 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3242 3243 trips { 3244 cpu4_alert: trip-alert { 3245 temperature = <85000>; 3246 hysteresis = <2000>; 3247 type = "passive"; 3248 }; 3249 3250 cpu4_crit: trip-crit { 3251 temperature = <100000>; 3252 hysteresis = <2000>; 3253 type = "critical"; 3254 }; 3255 }; 3256 3257 cooling-maps { 3258 map0 { 3259 trip = <&cpu4_alert>; 3260 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3261 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3262 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3263 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3264 }; 3265 }; 3266 }; 3267 3268 cpu5-thermal { 3269 polling-delay = <1000>; 3270 polling-delay-passive = <250>; 3271 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3272 3273 trips { 3274 cpu5_alert: trip-alert { 3275 temperature = <85000>; 3276 hysteresis = <2000>; 3277 type = "passive"; 3278 }; 3279 3280 cpu5_crit: trip-crit { 3281 temperature = <100000>; 3282 hysteresis = <2000>; 3283 type = "critical"; 3284 }; 3285 }; 3286 3287 cooling-maps { 3288 map0 { 3289 trip = <&cpu5_alert>; 3290 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3291 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3292 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3293 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3294 }; 3295 }; 3296 }; 3297 3298 cpu6-thermal { 3299 polling-delay = <1000>; 3300 polling-delay-passive = <250>; 3301 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3302 3303 trips { 3304 cpu6_alert: trip-alert { 3305 temperature = <85000>; 3306 hysteresis = <2000>; 3307 type = "passive"; 3308 }; 3309 3310 cpu6_crit: trip-crit { 3311 temperature = <100000>; 3312 hysteresis = <2000>; 3313 type = "critical"; 3314 }; 3315 }; 3316 3317 cooling-maps { 3318 map0 { 3319 trip = <&cpu6_alert>; 3320 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3321 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3322 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3323 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3324 }; 3325 }; 3326 }; 3327 3328 cpu7-thermal { 3329 polling-delay = <1000>; 3330 polling-delay-passive = <250>; 3331 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3332 3333 trips { 3334 cpu7_alert: trip-alert { 3335 temperature = <85000>; 3336 hysteresis = <2000>; 3337 type = "passive"; 3338 }; 3339 3340 cpu7_crit: trip-crit { 3341 temperature = <100000>; 3342 hysteresis = <2000>; 3343 type = "critical"; 3344 }; 3345 }; 3346 3347 cooling-maps { 3348 map0 { 3349 trip = <&cpu7_alert>; 3350 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3351 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3352 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3353 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3354 }; 3355 }; 3356 }; 3357 3358 vpu0-thermal { 3359 polling-delay = <1000>; 3360 polling-delay-passive = <250>; 3361 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 3362 3363 trips { 3364 vpu0_alert: trip-alert { 3365 temperature = <85000>; 3366 hysteresis = <2000>; 3367 type = "passive"; 3368 }; 3369 3370 vpu0_crit: trip-crit { 3371 temperature = <100000>; 3372 hysteresis = <2000>; 3373 type = "critical"; 3374 }; 3375 }; 3376 }; 3377 3378 vpu1-thermal { 3379 polling-delay = <1000>; 3380 polling-delay-passive = <250>; 3381 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 3382 3383 trips { 3384 vpu1_alert: trip-alert { 3385 temperature = <85000>; 3386 hysteresis = <2000>; 3387 type = "passive"; 3388 }; 3389 3390 vpu1_crit: trip-crit { 3391 temperature = <100000>; 3392 hysteresis = <2000>; 3393 type = "critical"; 3394 }; 3395 }; 3396 }; 3397 3398 gpu0-thermal { 3399 polling-delay = <1000>; 3400 polling-delay-passive = <250>; 3401 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 3402 3403 trips { 3404 gpu0_alert: trip-alert { 3405 temperature = <85000>; 3406 hysteresis = <2000>; 3407 type = "passive"; 3408 }; 3409 3410 gpu0_crit: trip-crit { 3411 temperature = <100000>; 3412 hysteresis = <2000>; 3413 type = "critical"; 3414 }; 3415 }; 3416 }; 3417 3418 gpu1-thermal { 3419 polling-delay = <1000>; 3420 polling-delay-passive = <250>; 3421 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 3422 3423 trips { 3424 gpu1_alert: trip-alert { 3425 temperature = <85000>; 3426 hysteresis = <2000>; 3427 type = "passive"; 3428 }; 3429 3430 gpu1_crit: trip-crit { 3431 temperature = <100000>; 3432 hysteresis = <2000>; 3433 type = "critical"; 3434 }; 3435 }; 3436 }; 3437 3438 vdec-thermal { 3439 polling-delay = <1000>; 3440 polling-delay-passive = <250>; 3441 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 3442 3443 trips { 3444 vdec_alert: trip-alert { 3445 temperature = <85000>; 3446 hysteresis = <2000>; 3447 type = "passive"; 3448 }; 3449 3450 vdec_crit: trip-crit { 3451 temperature = <100000>; 3452 hysteresis = <2000>; 3453 type = "critical"; 3454 }; 3455 }; 3456 }; 3457 3458 img-thermal { 3459 polling-delay = <1000>; 3460 polling-delay-passive = <250>; 3461 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 3462 3463 trips { 3464 img_alert: trip-alert { 3465 temperature = <85000>; 3466 hysteresis = <2000>; 3467 type = "passive"; 3468 }; 3469 3470 img_crit: trip-crit { 3471 temperature = <100000>; 3472 hysteresis = <2000>; 3473 type = "critical"; 3474 }; 3475 }; 3476 }; 3477 3478 infra-thermal { 3479 polling-delay = <1000>; 3480 polling-delay-passive = <250>; 3481 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 3482 3483 trips { 3484 infra_alert: trip-alert { 3485 temperature = <85000>; 3486 hysteresis = <2000>; 3487 type = "passive"; 3488 }; 3489 3490 infra_crit: trip-crit { 3491 temperature = <100000>; 3492 hysteresis = <2000>; 3493 type = "critical"; 3494 }; 3495 }; 3496 }; 3497 3498 cam0-thermal { 3499 polling-delay = <1000>; 3500 polling-delay-passive = <250>; 3501 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 3502 3503 trips { 3504 cam0_alert: trip-alert { 3505 temperature = <85000>; 3506 hysteresis = <2000>; 3507 type = "passive"; 3508 }; 3509 3510 cam0_crit: trip-crit { 3511 temperature = <100000>; 3512 hysteresis = <2000>; 3513 type = "critical"; 3514 }; 3515 }; 3516 }; 3517 3518 cam1-thermal { 3519 polling-delay = <1000>; 3520 polling-delay-passive = <250>; 3521 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 3522 3523 trips { 3524 cam1_alert: trip-alert { 3525 temperature = <85000>; 3526 hysteresis = <2000>; 3527 type = "passive"; 3528 }; 3529 3530 cam1_crit: trip-crit { 3531 temperature = <100000>; 3532 hysteresis = <2000>; 3533 type = "critical"; 3534 }; 3535 }; 3536 }; 3537 }; 3538}; 3539