xref: /openbmc/linux/drivers/i2c/busses/i2c-npcm7xx.c (revision 92e73d80)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Nuvoton NPCM7xx I2C Controller driver
4  *
5  * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
6  */
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/debugfs.h>
10 #include <linux/errno.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 
23 enum i2c_mode {
24 	I2C_MASTER,
25 	I2C_SLAVE,
26 };
27 
28 /*
29  * External I2C Interface driver xfer indication values, which indicate status
30  * of the bus.
31  */
32 enum i2c_state_ind {
33 	I2C_NO_STATUS_IND = 0,
34 	I2C_SLAVE_RCV_IND,
35 	I2C_SLAVE_XMIT_IND,
36 	I2C_SLAVE_XMIT_MISSING_DATA_IND,
37 	I2C_SLAVE_RESTART_IND,
38 	I2C_SLAVE_DONE_IND,
39 	I2C_MASTER_DONE_IND,
40 	I2C_NACK_IND,
41 	I2C_BUS_ERR_IND,
42 	I2C_WAKE_UP_IND,
43 	I2C_BLOCK_BYTES_ERR_IND,
44 	I2C_SLAVE_RCV_MISSING_DATA_IND,
45 };
46 
47 /*
48  * Operation type values (used to define the operation currently running)
49  * module is interrupt driven, on each interrupt the current operation is
50  * checked to see if the module is currently reading or writing.
51  */
52 enum i2c_oper {
53 	I2C_NO_OPER = 0,
54 	I2C_WRITE_OPER,
55 	I2C_READ_OPER,
56 };
57 
58 /* I2C Bank (module had 2 banks of registers) */
59 enum i2c_bank {
60 	I2C_BANK_0 = 0,
61 	I2C_BANK_1,
62 };
63 
64 /* Internal I2C states values (for the I2C module state machine). */
65 enum i2c_state {
66 	I2C_DISABLE = 0,
67 	I2C_IDLE,
68 	I2C_MASTER_START,
69 	I2C_SLAVE_MATCH,
70 	I2C_OPER_STARTED,
71 	I2C_STOP_PENDING,
72 };
73 
74 #if IS_ENABLED(CONFIG_I2C_SLAVE)
75 /* Module supports setting multiple own slave addresses */
76 enum i2c_addr {
77 	I2C_SLAVE_ADDR1 = 0,
78 	I2C_SLAVE_ADDR2,
79 	I2C_SLAVE_ADDR3,
80 	I2C_SLAVE_ADDR4,
81 	I2C_SLAVE_ADDR5,
82 	I2C_SLAVE_ADDR6,
83 	I2C_SLAVE_ADDR7,
84 	I2C_SLAVE_ADDR8,
85 	I2C_SLAVE_ADDR9,
86 	I2C_SLAVE_ADDR10,
87 	I2C_GC_ADDR,
88 	I2C_ARP_ADDR,
89 };
90 #endif
91 
92 /* init register and default value required to enable module */
93 #define NPCM_I2CSEGCTL			0xE4
94 
95 /* Common regs */
96 #define NPCM_I2CSDA			0x00
97 #define NPCM_I2CST			0x02
98 #define NPCM_I2CCST			0x04
99 #define NPCM_I2CCTL1			0x06
100 #define NPCM_I2CADDR1			0x08
101 #define NPCM_I2CCTL2			0x0A
102 #define NPCM_I2CADDR2			0x0C
103 #define NPCM_I2CCTL3			0x0E
104 #define NPCM_I2CCST2			0x18
105 #define NPCM_I2CCST3			0x19
106 #define I2C_VER				0x1F
107 
108 /* BANK 0 regs */
109 #define NPCM_I2CADDR3			0x10
110 #define NPCM_I2CADDR7			0x11
111 #define NPCM_I2CADDR4			0x12
112 #define NPCM_I2CADDR8			0x13
113 #define NPCM_I2CADDR5			0x14
114 #define NPCM_I2CADDR9			0x15
115 #define NPCM_I2CADDR6			0x16
116 #define NPCM_I2CADDR10			0x17
117 #define NPCM_I2CCTL4			0x1A
118 #define NPCM_I2CCTL5			0x1B
119 #define NPCM_I2CSCLLT			0x1C /* SCL Low Time */
120 #define NPCM_I2CFIF_CTL			0x1D /* FIFO Control */
121 #define NPCM_I2CSCLHT			0x1E /* SCL High Time */
122 
123 /* BANK 1 regs */
124 #define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */
125 #define NPCM_I2CTXF_CTL			0x12 /* Tx-FIFO Control */
126 #define NPCM_I2CT_OUT			0x14 /* Bus T.O. */
127 #define NPCM_I2CPEC			0x16 /* PEC Data */
128 #define NPCM_I2CTXF_STS			0x1A /* Tx-FIFO Status */
129 #define NPCM_I2CRXF_STS			0x1C /* Rx-FIFO Status */
130 #define NPCM_I2CRXF_CTL			0x1E /* Rx-FIFO Control */
131 
132 #if IS_ENABLED(CONFIG_I2C_SLAVE)
133 /*
134  * npcm_i2caddr array:
135  * The module supports having multiple own slave addresses.
136  * Since the addr regs are sprinkled all over the address space,
137  * use this array to get the address or each register.
138  */
139 #define I2C_NUM_OWN_ADDR 2
140 #define I2C_NUM_OWN_ADDR_SUPPORTED 2
141 
142 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
143 	NPCM_I2CADDR1, NPCM_I2CADDR2,
144 };
145 #endif
146 
147 /* NPCM_I2CST reg fields */
148 #define NPCM_I2CST_XMIT			BIT(0)	/* Transmit mode */
149 #define NPCM_I2CST_MASTER		BIT(1)	/* Master mode */
150 #define NPCM_I2CST_NMATCH		BIT(2)	/* New match */
151 #define NPCM_I2CST_STASTR		BIT(3)	/* Stall after start */
152 #define NPCM_I2CST_NEGACK		BIT(4)	/* Negative ACK */
153 #define NPCM_I2CST_BER			BIT(5)	/* Bus error */
154 #define NPCM_I2CST_SDAST		BIT(6)	/* SDA status */
155 #define NPCM_I2CST_SLVSTP		BIT(7)	/* Slave stop */
156 
157 /* NPCM_I2CCST reg fields */
158 #define NPCM_I2CCST_BUSY		BIT(0)	/* Busy */
159 #define NPCM_I2CCST_BB			BIT(1)	/* Bus busy */
160 #define NPCM_I2CCST_MATCH		BIT(2)	/* Address match */
161 #define NPCM_I2CCST_GCMATCH		BIT(3)	/* Global call match */
162 #define NPCM_I2CCST_TSDA		BIT(4)	/* Test SDA line */
163 #define NPCM_I2CCST_TGSCL		BIT(5)	/* Toggle SCL line */
164 #define NPCM_I2CCST_MATCHAF		BIT(6)	/* Match address field */
165 #define NPCM_I2CCST_ARPMATCH		BIT(7)	/* ARP address match */
166 
167 /* NPCM_I2CCTL1 reg fields */
168 #define NPCM_I2CCTL1_START		BIT(0)	/* Generate start condition */
169 #define NPCM_I2CCTL1_STOP		BIT(1)	/* Generate stop condition */
170 #define NPCM_I2CCTL1_INTEN		BIT(2)	/* Interrupt enable */
171 #define NPCM_I2CCTL1_EOBINTE		BIT(3)
172 #define NPCM_I2CCTL1_ACK		BIT(4)
173 #define NPCM_I2CCTL1_GCMEN		BIT(5)	/* Global call match enable */
174 #define NPCM_I2CCTL1_NMINTE		BIT(6)	/* New match interrupt enable */
175 #define NPCM_I2CCTL1_STASTRE		BIT(7)	/* Stall after start enable */
176 
177 /* RW1S fields (inside a RW reg): */
178 #define NPCM_I2CCTL1_RWS   \
179 	(NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
180 
181 /* npcm_i2caddr reg fields */
182 #define NPCM_I2CADDR_A			GENMASK(6, 0)	/* Address */
183 #define NPCM_I2CADDR_SAEN		BIT(7)		/* Slave address enable */
184 
185 /* NPCM_I2CCTL2 reg fields */
186 #define I2CCTL2_ENABLE			BIT(0)		/* Module enable */
187 #define I2CCTL2_SCLFRQ6_0		GENMASK(7, 1)	/* Bits 0:6 of frequency divisor */
188 
189 /* NPCM_I2CCTL3 reg fields */
190 #define I2CCTL3_SCLFRQ8_7		GENMASK(1, 0)	/* Bits 7:8 of frequency divisor */
191 #define I2CCTL3_ARPMEN			BIT(2)	/* ARP match enable */
192 #define I2CCTL3_IDL_START		BIT(3)
193 #define I2CCTL3_400K_MODE		BIT(4)
194 #define I2CCTL3_BNK_SEL			BIT(5)
195 #define I2CCTL3_SDA_LVL			BIT(6)
196 #define I2CCTL3_SCL_LVL			BIT(7)
197 
198 /* NPCM_I2CCST2 reg fields */
199 #define NPCM_I2CCST2_MATCHA1F		BIT(0)
200 #define NPCM_I2CCST2_MATCHA2F		BIT(1)
201 #define NPCM_I2CCST2_MATCHA3F		BIT(2)
202 #define NPCM_I2CCST2_MATCHA4F		BIT(3)
203 #define NPCM_I2CCST2_MATCHA5F		BIT(4)
204 #define NPCM_I2CCST2_MATCHA6F		BIT(5)
205 #define NPCM_I2CCST2_MATCHA7F		BIT(5)
206 #define NPCM_I2CCST2_INTSTS		BIT(7)
207 
208 /* NPCM_I2CCST3 reg fields */
209 #define NPCM_I2CCST3_MATCHA8F		BIT(0)
210 #define NPCM_I2CCST3_MATCHA9F		BIT(1)
211 #define NPCM_I2CCST3_MATCHA10F		BIT(2)
212 #define NPCM_I2CCST3_EO_BUSY		BIT(7)
213 
214 /* NPCM_I2CCTL4 reg fields */
215 #define I2CCTL4_HLDT			GENMASK(5, 0)
216 #define I2CCTL4_LVL_WE			BIT(7)
217 
218 /* NPCM_I2CCTL5 reg fields */
219 #define I2CCTL5_DBNCT			GENMASK(3, 0)
220 
221 /* NPCM_I2CFIF_CTS reg fields */
222 #define NPCM_I2CFIF_CTS_RXF_TXE		BIT(1)
223 #define NPCM_I2CFIF_CTS_RFTE_IE		BIT(3)
224 #define NPCM_I2CFIF_CTS_CLR_FIFO	BIT(6)
225 #define NPCM_I2CFIF_CTS_SLVRSTR		BIT(7)
226 
227 /* NPCM_I2CTXF_CTL reg field */
228 #define NPCM_I2CTXF_CTL_THR_TXIE	BIT(6)
229 
230 /* NPCM_I2CT_OUT reg fields */
231 #define NPCM_I2CT_OUT_TO_CKDIV		GENMASK(5, 0)
232 #define NPCM_I2CT_OUT_T_OUTIE		BIT(6)
233 #define NPCM_I2CT_OUT_T_OUTST		BIT(7)
234 
235 /* NPCM_I2CTXF_STS reg fields */
236 #define NPCM_I2CTXF_STS_TX_THST		BIT(6)
237 
238 /* NPCM_I2CRXF_STS reg fields */
239 #define NPCM_I2CRXF_STS_RX_THST		BIT(6)
240 
241 /* NPCM_I2CFIF_CTL reg fields */
242 #define NPCM_I2CFIF_CTL_FIFO_EN		BIT(4)
243 
244 /* NPCM_I2CRXF_CTL reg fields */
245 #define NPCM_I2CRXF_CTL_THR_RXIE	BIT(6)
246 
247 #define MAX_I2C_HW_FIFO_SIZE		32
248 
249 /* I2C_VER reg fields */
250 #define I2C_VER_VERSION			GENMASK(6, 0)
251 #define I2C_VER_FIFO_EN			BIT(7)
252 
253 /* stall/stuck timeout in us */
254 #define DEFAULT_STALL_COUNT		25
255 
256 /* SCLFRQ field position */
257 #define SCLFRQ_0_TO_6			GENMASK(6, 0)
258 #define SCLFRQ_7_TO_8			GENMASK(8, 7)
259 
260 /* supported clk settings. values in Hz. */
261 #define I2C_FREQ_MIN_HZ			10000
262 #define I2C_FREQ_MAX_HZ			I2C_MAX_FAST_MODE_PLUS_FREQ
263 
264 struct npcm_i2c_data {
265 	u8 fifo_size;
266 	u32 segctl_init_val;
267 	u8 txf_sts_tx_bytes;
268 	u8 rxf_sts_rx_bytes;
269 	u8 rxf_ctl_last_pec;
270 };
271 
272 static const struct npcm_i2c_data npxm7xx_i2c_data = {
273 	.fifo_size = 16,
274 	.segctl_init_val = 0x0333F000,
275 	.txf_sts_tx_bytes = GENMASK(4, 0),
276 	.rxf_sts_rx_bytes = GENMASK(4, 0),
277 	.rxf_ctl_last_pec = BIT(5),
278 };
279 
280 static const struct npcm_i2c_data npxm8xx_i2c_data = {
281 	.fifo_size = 32,
282 	.segctl_init_val = 0x9333F000,
283 	.txf_sts_tx_bytes = GENMASK(5, 0),
284 	.rxf_sts_rx_bytes = GENMASK(5, 0),
285 	.rxf_ctl_last_pec = BIT(7),
286 };
287 
288 /* Status of one I2C module */
289 struct npcm_i2c {
290 	struct i2c_adapter adap;
291 	struct device *dev;
292 	unsigned char __iomem *reg;
293 	const struct npcm_i2c_data *data;
294 	spinlock_t lock;   /* IRQ synchronization */
295 	struct completion cmd_complete;
296 	int cmd_err;
297 	struct i2c_msg *msgs;
298 	int msgs_num;
299 	int num;
300 	u32 apb_clk;
301 	struct i2c_bus_recovery_info rinfo;
302 	enum i2c_state state;
303 	enum i2c_oper operation;
304 	enum i2c_mode master_or_slave;
305 	enum i2c_state_ind stop_ind;
306 	u8 dest_addr;
307 	u8 *rd_buf;
308 	u16 rd_size;
309 	u16 rd_ind;
310 	u8 *wr_buf;
311 	u16 wr_size;
312 	u16 wr_ind;
313 	bool fifo_use;
314 	u16 PEC_mask; /* PEC bit mask per slave address */
315 	bool PEC_use;
316 	bool read_block_use;
317 	unsigned long int_time_stamp;
318 	unsigned long bus_freq; /* in Hz */
319 #if IS_ENABLED(CONFIG_I2C_SLAVE)
320 	u8 own_slave_addr;
321 	struct i2c_client *slave;
322 	int slv_rd_size;
323 	int slv_rd_ind;
324 	int slv_wr_size;
325 	int slv_wr_ind;
326 	u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];
327 	u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];
328 #endif
329 	struct dentry *debugfs; /* debugfs device directory */
330 	u64 ber_cnt;
331 	u64 rec_succ_cnt;
332 	u64 rec_fail_cnt;
333 	u64 nack_cnt;
334 	u64 timeout_cnt;
335 	u64 tx_complete_cnt;
336 };
337 
npcm_i2c_select_bank(struct npcm_i2c * bus,enum i2c_bank bank)338 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
339 					enum i2c_bank bank)
340 {
341 	u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
342 
343 	if (bank == I2C_BANK_0)
344 		i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
345 	else
346 		i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
347 	iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
348 }
349 
npcm_i2c_init_params(struct npcm_i2c * bus)350 static void npcm_i2c_init_params(struct npcm_i2c *bus)
351 {
352 	bus->stop_ind = I2C_NO_STATUS_IND;
353 	bus->rd_size = 0;
354 	bus->wr_size = 0;
355 	bus->rd_ind = 0;
356 	bus->wr_ind = 0;
357 	bus->read_block_use = false;
358 	bus->int_time_stamp = 0;
359 	bus->PEC_use = false;
360 	bus->PEC_mask = 0;
361 #if IS_ENABLED(CONFIG_I2C_SLAVE)
362 	if (bus->slave)
363 		bus->master_or_slave = I2C_SLAVE;
364 #endif
365 }
366 
npcm_i2c_wr_byte(struct npcm_i2c * bus,u8 data)367 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
368 {
369 	iowrite8(data, bus->reg + NPCM_I2CSDA);
370 }
371 
npcm_i2c_rd_byte(struct npcm_i2c * bus)372 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
373 {
374 	return ioread8(bus->reg + NPCM_I2CSDA);
375 }
376 
npcm_i2c_get_SCL(struct i2c_adapter * _adap)377 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
378 {
379 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
380 
381 	return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
382 }
383 
npcm_i2c_get_SDA(struct i2c_adapter * _adap)384 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
385 {
386 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
387 
388 	return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
389 }
390 
npcm_i2c_get_index(struct npcm_i2c * bus)391 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
392 {
393 	if (bus->operation == I2C_READ_OPER)
394 		return bus->rd_ind;
395 	if (bus->operation == I2C_WRITE_OPER)
396 		return bus->wr_ind;
397 	return 0;
398 }
399 
400 /* quick protocol (just address) */
npcm_i2c_is_quick(struct npcm_i2c * bus)401 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
402 {
403 	return bus->wr_size == 0 && bus->rd_size == 0;
404 }
405 
npcm_i2c_disable(struct npcm_i2c * bus)406 static void npcm_i2c_disable(struct npcm_i2c *bus)
407 {
408 	u8 i2cctl2;
409 
410 #if IS_ENABLED(CONFIG_I2C_SLAVE)
411 	int i;
412 
413 	/* Slave addresses removal */
414 	for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
415 		iowrite8(0, bus->reg + npcm_i2caddr[i]);
416 
417 #endif
418 	/* Disable module */
419 	i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
420 	i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
421 	iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
422 
423 	bus->state = I2C_DISABLE;
424 }
425 
npcm_i2c_enable(struct npcm_i2c * bus)426 static void npcm_i2c_enable(struct npcm_i2c *bus)
427 {
428 	u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
429 
430 	i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
431 	iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
432 	bus->state = I2C_IDLE;
433 }
434 
435 /* enable\disable end of busy (EOB) interrupts */
npcm_i2c_eob_int(struct npcm_i2c * bus,bool enable)436 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
437 {
438 	u8 val;
439 
440 	/* Clear EO_BUSY pending bit: */
441 	val = ioread8(bus->reg + NPCM_I2CCST3);
442 	val = val | NPCM_I2CCST3_EO_BUSY;
443 	iowrite8(val, bus->reg + NPCM_I2CCST3);
444 
445 	val = ioread8(bus->reg + NPCM_I2CCTL1);
446 	val &= ~NPCM_I2CCTL1_RWS;
447 	if (enable)
448 		val |= NPCM_I2CCTL1_EOBINTE;
449 	else
450 		val &= ~NPCM_I2CCTL1_EOBINTE;
451 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
452 }
453 
npcm_i2c_tx_fifo_empty(struct npcm_i2c * bus)454 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
455 {
456 	u8 tx_fifo_sts;
457 
458 	tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
459 	/* check if TX FIFO is not empty */
460 	if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
461 		return false;
462 
463 	/* check if TX FIFO status bit is set: */
464 	return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
465 }
466 
npcm_i2c_rx_fifo_full(struct npcm_i2c * bus)467 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
468 {
469 	u8 rx_fifo_sts;
470 
471 	rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
472 	/* check if RX FIFO is not empty: */
473 	if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
474 		return false;
475 
476 	/* check if rx fifo full status is set: */
477 	return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
478 }
479 
npcm_i2c_clear_fifo_int(struct npcm_i2c * bus)480 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
481 {
482 	u8 val;
483 
484 	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
485 	val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
486 	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
487 }
488 
npcm_i2c_clear_tx_fifo(struct npcm_i2c * bus)489 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
490 {
491 	u8 val;
492 
493 	val = ioread8(bus->reg + NPCM_I2CTXF_STS);
494 	val = val | NPCM_I2CTXF_STS_TX_THST;
495 	iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
496 }
497 
npcm_i2c_clear_rx_fifo(struct npcm_i2c * bus)498 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
499 {
500 	u8 val;
501 
502 	val = ioread8(bus->reg + NPCM_I2CRXF_STS);
503 	val = val | NPCM_I2CRXF_STS_RX_THST;
504 	iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
505 }
506 
npcm_i2c_int_enable(struct npcm_i2c * bus,bool enable)507 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
508 {
509 	u8 val;
510 
511 	val = ioread8(bus->reg + NPCM_I2CCTL1);
512 	val &= ~NPCM_I2CCTL1_RWS;
513 	if (enable)
514 		val |= NPCM_I2CCTL1_INTEN;
515 	else
516 		val &= ~NPCM_I2CCTL1_INTEN;
517 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
518 }
519 
npcm_i2c_master_start(struct npcm_i2c * bus)520 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
521 {
522 	u8 val;
523 
524 	val = ioread8(bus->reg + NPCM_I2CCTL1);
525 	val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
526 	val |= NPCM_I2CCTL1_START;
527 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
528 }
529 
npcm_i2c_master_stop(struct npcm_i2c * bus)530 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
531 {
532 	u8 val;
533 
534 	/*
535 	 * override HW issue: I2C may fail to supply stop condition in Master
536 	 * Write operation.
537 	 * Need to delay at least 5 us from the last int, before issueing a stop
538 	 */
539 	udelay(10); /* function called from interrupt, can't sleep */
540 	val = ioread8(bus->reg + NPCM_I2CCTL1);
541 	val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
542 	val |= NPCM_I2CCTL1_STOP;
543 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
544 
545 	if (!bus->fifo_use)
546 		return;
547 
548 	npcm_i2c_select_bank(bus, I2C_BANK_1);
549 
550 	if (bus->operation == I2C_READ_OPER)
551 		npcm_i2c_clear_rx_fifo(bus);
552 	else
553 		npcm_i2c_clear_tx_fifo(bus);
554 	npcm_i2c_clear_fifo_int(bus);
555 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
556 }
557 
npcm_i2c_stall_after_start(struct npcm_i2c * bus,bool stall)558 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
559 {
560 	u8 val;
561 
562 	val = ioread8(bus->reg + NPCM_I2CCTL1);
563 	val &= ~NPCM_I2CCTL1_RWS;
564 	if (stall)
565 		val |= NPCM_I2CCTL1_STASTRE;
566 	else
567 		val &= ~NPCM_I2CCTL1_STASTRE;
568 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
569 }
570 
npcm_i2c_nack(struct npcm_i2c * bus)571 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
572 {
573 	u8 val;
574 
575 	val = ioread8(bus->reg + NPCM_I2CCTL1);
576 	val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
577 	val |= NPCM_I2CCTL1_ACK;
578 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
579 }
580 
npcm_i2c_clear_master_status(struct npcm_i2c * bus)581 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
582 {
583 	u8 val;
584 
585 	/* Clear NEGACK, STASTR and BER bits */
586 	val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
587 	iowrite8(val, bus->reg + NPCM_I2CST);
588 }
589 
590 #if IS_ENABLED(CONFIG_I2C_SLAVE)
npcm_i2c_slave_int_enable(struct npcm_i2c * bus,bool enable)591 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
592 {
593 	u8 i2cctl1;
594 
595 	/* enable interrupt on slave match: */
596 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
597 	i2cctl1 &= ~NPCM_I2CCTL1_RWS;
598 	if (enable)
599 		i2cctl1 |= NPCM_I2CCTL1_NMINTE;
600 	else
601 		i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
602 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
603 }
604 
npcm_i2c_slave_enable(struct npcm_i2c * bus,enum i2c_addr addr_type,u8 addr,bool enable)605 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
606 				 u8 addr, bool enable)
607 {
608 	u8 i2cctl1;
609 	u8 i2cctl3;
610 	u8 sa_reg;
611 
612 	sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
613 	if (addr_type == I2C_GC_ADDR) {
614 		i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
615 		if (enable)
616 			i2cctl1 |= NPCM_I2CCTL1_GCMEN;
617 		else
618 			i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
619 		iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
620 		return 0;
621 	} else if (addr_type == I2C_ARP_ADDR) {
622 		i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
623 		if (enable)
624 			i2cctl3 |= I2CCTL3_ARPMEN;
625 		else
626 			i2cctl3 &= ~I2CCTL3_ARPMEN;
627 		iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
628 		return 0;
629 	}
630 	if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
631 		dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
632 
633 	if (addr_type >= I2C_ARP_ADDR)
634 		return -EFAULT;
635 
636 	/* Set and enable the address */
637 	iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
638 	npcm_i2c_slave_int_enable(bus, enable);
639 
640 	return 0;
641 }
642 #endif
643 
npcm_i2c_reset(struct npcm_i2c * bus)644 static void npcm_i2c_reset(struct npcm_i2c *bus)
645 {
646 	/*
647 	 * Save I2CCTL1 relevant bits. It is being cleared when the module
648 	 *  is disabled.
649 	 */
650 	u8 i2cctl1;
651 #if IS_ENABLED(CONFIG_I2C_SLAVE)
652 	u8 addr;
653 #endif
654 
655 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
656 
657 	npcm_i2c_disable(bus);
658 	npcm_i2c_enable(bus);
659 
660 	/* Restore NPCM_I2CCTL1 Status */
661 	i2cctl1 &= ~NPCM_I2CCTL1_RWS;
662 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
663 
664 	/* Clear BB (BUS BUSY) bit */
665 	iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
666 	iowrite8(0xFF, bus->reg + NPCM_I2CST);
667 
668 	/* Clear and disable EOB */
669 	npcm_i2c_eob_int(bus, false);
670 
671 	/* Clear all fifo bits: */
672 	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
673 
674 #if IS_ENABLED(CONFIG_I2C_SLAVE)
675 	if (bus->slave) {
676 		addr = bus->slave->addr;
677 		npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
678 	}
679 #endif
680 
681 	/* Clear status bits for spurious interrupts */
682 	npcm_i2c_clear_master_status(bus);
683 
684 	bus->state = I2C_IDLE;
685 }
686 
npcm_i2c_is_master(struct npcm_i2c * bus)687 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
688 {
689 	return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
690 }
691 
npcm_i2c_callback(struct npcm_i2c * bus,enum i2c_state_ind op_status,u16 info)692 static void npcm_i2c_callback(struct npcm_i2c *bus,
693 			      enum i2c_state_ind op_status, u16 info)
694 {
695 	struct i2c_msg *msgs;
696 	int msgs_num;
697 	bool do_complete = false;
698 
699 	msgs = bus->msgs;
700 	msgs_num = bus->msgs_num;
701 	/*
702 	 * check that transaction was not timed-out, and msgs still
703 	 * holds a valid value.
704 	 */
705 	if (!msgs)
706 		return;
707 
708 	if (completion_done(&bus->cmd_complete))
709 		return;
710 
711 	switch (op_status) {
712 	case I2C_MASTER_DONE_IND:
713 		bus->cmd_err = bus->msgs_num;
714 		if (bus->tx_complete_cnt < ULLONG_MAX)
715 			bus->tx_complete_cnt++;
716 		fallthrough;
717 	case I2C_BLOCK_BYTES_ERR_IND:
718 		/* Master tx finished and all transmit bytes were sent */
719 		if (bus->msgs) {
720 			if (msgs[0].flags & I2C_M_RD)
721 				msgs[0].len = info;
722 			else if (msgs_num == 2 &&
723 				 msgs[1].flags & I2C_M_RD)
724 				msgs[1].len = info;
725 		}
726 		do_complete = true;
727 		break;
728 	case I2C_NACK_IND:
729 		/* MASTER transmit got a NACK before tx all bytes */
730 		bus->cmd_err = -ENXIO;
731 		do_complete = true;
732 		break;
733 	case I2C_BUS_ERR_IND:
734 		/* Bus error */
735 		bus->cmd_err = -EAGAIN;
736 		do_complete = true;
737 		break;
738 	case I2C_WAKE_UP_IND:
739 		/* I2C wake up */
740 		break;
741 	default:
742 		break;
743 	}
744 
745 	bus->operation = I2C_NO_OPER;
746 #if IS_ENABLED(CONFIG_I2C_SLAVE)
747 	if (bus->slave)
748 		bus->master_or_slave = I2C_SLAVE;
749 #endif
750 	if (do_complete)
751 		complete(&bus->cmd_complete);
752 }
753 
npcm_i2c_fifo_usage(struct npcm_i2c * bus)754 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
755 {
756 	if (bus->operation == I2C_WRITE_OPER)
757 		return (bus->data->txf_sts_tx_bytes &
758 			ioread8(bus->reg + NPCM_I2CTXF_STS));
759 	if (bus->operation == I2C_READ_OPER)
760 		return (bus->data->rxf_sts_rx_bytes &
761 			ioread8(bus->reg + NPCM_I2CRXF_STS));
762 	return 0;
763 }
764 
npcm_i2c_write_to_fifo_master(struct npcm_i2c * bus,u16 max_bytes)765 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
766 {
767 	u8 size_free_fifo;
768 
769 	/*
770 	 * Fill the FIFO, while the FIFO is not full and there are more bytes
771 	 * to write
772 	 */
773 	size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
774 	while (max_bytes-- && size_free_fifo) {
775 		if (bus->wr_ind < bus->wr_size)
776 			npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
777 		else
778 			npcm_i2c_wr_byte(bus, 0xFF);
779 		size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
780 	}
781 }
782 
783 /*
784  * npcm_i2c_set_fifo:
785  * configure the FIFO before using it. If nread is -1 RX FIFO will not be
786  * configured. same for nwrite
787  */
npcm_i2c_set_fifo(struct npcm_i2c * bus,int nread,int nwrite)788 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
789 {
790 	u8 rxf_ctl = 0;
791 
792 	if (!bus->fifo_use)
793 		return;
794 	npcm_i2c_select_bank(bus, I2C_BANK_1);
795 	npcm_i2c_clear_tx_fifo(bus);
796 	npcm_i2c_clear_rx_fifo(bus);
797 
798 	/* configure RX FIFO */
799 	if (nread > 0) {
800 		rxf_ctl = min_t(int, nread, bus->data->fifo_size);
801 
802 		/* set LAST bit. if LAST is set next FIFO packet is nacked */
803 		if (nread <= bus->data->fifo_size)
804 			rxf_ctl |= bus->data->rxf_ctl_last_pec;
805 
806 		/*
807 		 * if we are about to read the first byte in blk rd mode,
808 		 * don't NACK it. If slave returns zero size HW can't NACK
809 		 * it immediately, it will read extra byte and then NACK.
810 		 */
811 		if (bus->rd_ind == 0 && bus->read_block_use) {
812 			/* set fifo to read one byte, no last: */
813 			rxf_ctl = 1;
814 		}
815 
816 		/* set fifo size: */
817 		iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
818 	}
819 
820 	/* configure TX FIFO */
821 	if (nwrite > 0) {
822 		if (nwrite > bus->data->fifo_size)
823 			/* data to send is more then FIFO size. */
824 			iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
825 		else
826 			iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
827 
828 		npcm_i2c_clear_tx_fifo(bus);
829 	}
830 }
831 
npcm_i2c_read_fifo(struct npcm_i2c * bus,u8 bytes_in_fifo)832 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
833 {
834 	u8 data;
835 
836 	while (bytes_in_fifo--) {
837 		data = npcm_i2c_rd_byte(bus);
838 		if (bus->rd_ind < bus->rd_size)
839 			bus->rd_buf[bus->rd_ind++] = data;
840 	}
841 }
842 
npcm_i2c_master_abort(struct npcm_i2c * bus)843 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
844 {
845 	/* Only current master is allowed to issue a stop condition */
846 	if (!npcm_i2c_is_master(bus))
847 		return;
848 
849 	npcm_i2c_eob_int(bus, true);
850 	npcm_i2c_master_stop(bus);
851 	npcm_i2c_clear_master_status(bus);
852 }
853 
854 #if IS_ENABLED(CONFIG_I2C_SLAVE)
npcm_i2c_get_slave_addr(struct npcm_i2c * bus,enum i2c_addr addr_type)855 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
856 {
857 	u8 slave_add;
858 
859 	if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
860 		dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
861 
862 	slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
863 
864 	return slave_add;
865 }
866 
npcm_i2c_remove_slave_addr(struct npcm_i2c * bus,u8 slave_add)867 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
868 {
869 	int i;
870 
871 	/* Set the enable bit */
872 	slave_add |= 0x80;
873 
874 	for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
875 		if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
876 			iowrite8(0, bus->reg + npcm_i2caddr[i]);
877 	}
878 
879 	return 0;
880 }
881 
npcm_i2c_write_fifo_slave(struct npcm_i2c * bus,u16 max_bytes)882 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
883 {
884 	/*
885 	 * Fill the FIFO, while the FIFO is not full and there are more bytes
886 	 * to write
887 	 */
888 	npcm_i2c_clear_fifo_int(bus);
889 	npcm_i2c_clear_tx_fifo(bus);
890 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
891 	while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
892 		if (bus->slv_wr_size <= 0)
893 			break;
894 		bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
895 		npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
896 		bus->slv_wr_ind++;
897 		bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
898 		bus->slv_wr_size--;
899 	}
900 }
901 
npcm_i2c_read_fifo_slave(struct npcm_i2c * bus,u8 bytes_in_fifo)902 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
903 {
904 	u8 data;
905 
906 	if (!bus->slave)
907 		return;
908 
909 	while (bytes_in_fifo--) {
910 		data = npcm_i2c_rd_byte(bus);
911 
912 		bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
913 		bus->slv_rd_buf[bus->slv_rd_ind] = data;
914 		bus->slv_rd_ind++;
915 
916 		/* 1st byte is length in block protocol: */
917 		if (bus->slv_rd_ind == 1 && bus->read_block_use)
918 			bus->slv_rd_size = data + bus->PEC_use + 1;
919 	}
920 }
921 
npcm_i2c_slave_get_wr_buf(struct npcm_i2c * bus)922 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
923 {
924 	int i;
925 	u8 value;
926 	int ind;
927 	int ret = bus->slv_wr_ind;
928 
929 	/* fill a cyclic buffer */
930 	for (i = 0; i < bus->data->fifo_size; i++) {
931 		if (bus->slv_wr_size >= bus->data->fifo_size)
932 			break;
933 		if (bus->state == I2C_SLAVE_MATCH) {
934 			i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
935 			bus->state = I2C_OPER_STARTED;
936 		} else {
937 			i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
938 		}
939 		ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
940 		bus->slv_wr_buf[ind] = value;
941 		bus->slv_wr_size++;
942 	}
943 	return bus->data->fifo_size - ret;
944 }
945 
npcm_i2c_slave_send_rd_buf(struct npcm_i2c * bus)946 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
947 {
948 	int i;
949 
950 	for (i = 0; i < bus->slv_rd_ind; i++)
951 		i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
952 				&bus->slv_rd_buf[i]);
953 	/*
954 	 * once we send bytes up, need to reset the counter of the wr buf
955 	 * got data from master (new offset in device), ignore wr fifo:
956 	 */
957 	if (bus->slv_rd_ind) {
958 		bus->slv_wr_size = 0;
959 		bus->slv_wr_ind = 0;
960 	}
961 
962 	bus->slv_rd_ind = 0;
963 	bus->slv_rd_size = bus->adap.quirks->max_read_len;
964 
965 	npcm_i2c_clear_fifo_int(bus);
966 	npcm_i2c_clear_rx_fifo(bus);
967 }
968 
npcm_i2c_slave_receive(struct npcm_i2c * bus,u16 nread,u8 * read_data)969 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
970 				   u8 *read_data)
971 {
972 	bus->state = I2C_OPER_STARTED;
973 	bus->operation = I2C_READ_OPER;
974 	bus->slv_rd_size = nread;
975 	bus->slv_rd_ind = 0;
976 
977 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
978 	iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
979 	npcm_i2c_clear_tx_fifo(bus);
980 	npcm_i2c_clear_rx_fifo(bus);
981 }
982 
npcm_i2c_slave_xmit(struct npcm_i2c * bus,u16 nwrite,u8 * write_data)983 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
984 				u8 *write_data)
985 {
986 	if (nwrite == 0)
987 		return;
988 
989 	bus->operation = I2C_WRITE_OPER;
990 
991 	/* get the next buffer */
992 	npcm_i2c_slave_get_wr_buf(bus);
993 	npcm_i2c_write_fifo_slave(bus, nwrite);
994 }
995 
996 /*
997  * npcm_i2c_slave_wr_buf_sync:
998  * currently slave IF only supports single byte operations.
999  * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
1000  * at a time, pack them in buffer, and then transmit them all together
1001  * to the FIFO and onward to the bus.
1002  * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1003  * sending a NACK wherever the backend requests for it is not supported.
1004  * the next two functions allow reading to local buffer before writing it all
1005  * to the HW FIFO.
1006  */
npcm_i2c_slave_wr_buf_sync(struct npcm_i2c * bus)1007 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1008 {
1009 	int left_in_fifo;
1010 
1011 	left_in_fifo = bus->data->txf_sts_tx_bytes &
1012 			ioread8(bus->reg + NPCM_I2CTXF_STS);
1013 
1014 	/* fifo already full: */
1015 	if (left_in_fifo >= bus->data->fifo_size ||
1016 	    bus->slv_wr_size >= bus->data->fifo_size)
1017 		return;
1018 
1019 	/* update the wr fifo index back to the untransmitted bytes: */
1020 	bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1021 	bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1022 
1023 	if (bus->slv_wr_ind < 0)
1024 		bus->slv_wr_ind += bus->data->fifo_size;
1025 }
1026 
npcm_i2c_slave_rd_wr(struct npcm_i2c * bus)1027 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1028 {
1029 	if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1030 		/*
1031 		 * Slave got an address match with direction bit 1 so it should
1032 		 * transmit data. Write till the master will NACK
1033 		 */
1034 		bus->operation = I2C_WRITE_OPER;
1035 		npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1036 				    bus->slv_wr_buf);
1037 	} else {
1038 		/*
1039 		 * Slave got an address match with direction bit 0 so it should
1040 		 * receive data.
1041 		 * this module does not support saying no to bytes.
1042 		 * it will always ACK.
1043 		 */
1044 		bus->operation = I2C_READ_OPER;
1045 		npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1046 		bus->stop_ind = I2C_SLAVE_RCV_IND;
1047 		npcm_i2c_slave_send_rd_buf(bus);
1048 		npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1049 				       bus->slv_rd_buf);
1050 	}
1051 }
1052 
npcm_i2c_int_slave_handler(struct npcm_i2c * bus)1053 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1054 {
1055 	u8 val;
1056 	irqreturn_t ret = IRQ_NONE;
1057 	u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1058 
1059 	/* Slave: A NACK has occurred */
1060 	if (NPCM_I2CST_NEGACK & i2cst) {
1061 		bus->stop_ind = I2C_NACK_IND;
1062 		npcm_i2c_slave_wr_buf_sync(bus);
1063 		if (bus->fifo_use)
1064 			/* clear the FIFO */
1065 			iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1066 				 bus->reg + NPCM_I2CFIF_CTS);
1067 
1068 		/* In slave write, NACK is OK, otherwise it is a problem */
1069 		bus->stop_ind = I2C_NO_STATUS_IND;
1070 		bus->operation = I2C_NO_OPER;
1071 		bus->own_slave_addr = 0xFF;
1072 
1073 		/*
1074 		 * Slave has to wait for STOP to decide this is the end
1075 		 * of the transaction. tx is not yet considered as done
1076 		 */
1077 		iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1078 
1079 		ret = IRQ_HANDLED;
1080 	}
1081 
1082 	/* Slave mode: a Bus Error (BER) has been identified */
1083 	if (NPCM_I2CST_BER & i2cst) {
1084 		/*
1085 		 * Check whether bus arbitration or Start or Stop during data
1086 		 * xfer bus arbitration problem should not result in recovery
1087 		 */
1088 		bus->stop_ind = I2C_BUS_ERR_IND;
1089 
1090 		/* wait for bus busy before clear fifo */
1091 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1092 
1093 		bus->state = I2C_IDLE;
1094 
1095 		/*
1096 		 * in BER case we might get 2 interrupts: one for slave one for
1097 		 * master ( for a channel which is master\slave switching)
1098 		 */
1099 		if (completion_done(&bus->cmd_complete) == false) {
1100 			bus->cmd_err = -EIO;
1101 			complete(&bus->cmd_complete);
1102 		}
1103 		bus->own_slave_addr = 0xFF;
1104 		iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1105 		ret = IRQ_HANDLED;
1106 	}
1107 
1108 	/* A Slave Stop Condition has been identified */
1109 	if (NPCM_I2CST_SLVSTP & i2cst) {
1110 		u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1111 
1112 		bus->stop_ind = I2C_SLAVE_DONE_IND;
1113 
1114 		if (bus->operation == I2C_READ_OPER)
1115 			npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1116 
1117 		/* if the buffer is empty nothing will be sent */
1118 		npcm_i2c_slave_send_rd_buf(bus);
1119 
1120 		/* Slave done transmitting or receiving */
1121 		bus->stop_ind = I2C_NO_STATUS_IND;
1122 
1123 		/*
1124 		 * Note, just because we got here, it doesn't mean we through
1125 		 * away the wr buffer.
1126 		 * we keep it until the next received offset.
1127 		 */
1128 		bus->operation = I2C_NO_OPER;
1129 		bus->own_slave_addr = 0xFF;
1130 		i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1131 		iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1132 		if (bus->fifo_use) {
1133 			npcm_i2c_clear_fifo_int(bus);
1134 			npcm_i2c_clear_rx_fifo(bus);
1135 			npcm_i2c_clear_tx_fifo(bus);
1136 
1137 			iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1138 				 bus->reg + NPCM_I2CFIF_CTS);
1139 		}
1140 		bus->state = I2C_IDLE;
1141 		ret = IRQ_HANDLED;
1142 	}
1143 
1144 	/* restart condition occurred and Rx-FIFO was not empty */
1145 	if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1146 				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1147 		bus->stop_ind = I2C_SLAVE_RESTART_IND;
1148 		bus->master_or_slave = I2C_SLAVE;
1149 		if (bus->operation == I2C_READ_OPER)
1150 			npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1151 		bus->operation = I2C_WRITE_OPER;
1152 		iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1153 		val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1154 		      NPCM_I2CFIF_CTS_RXF_TXE;
1155 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1156 		npcm_i2c_slave_rd_wr(bus);
1157 		ret = IRQ_HANDLED;
1158 	}
1159 
1160 	/* A Slave Address Match has been identified */
1161 	if (NPCM_I2CST_NMATCH & i2cst) {
1162 		u8 info = 0;
1163 
1164 		/* Address match automatically implies slave mode */
1165 		bus->master_or_slave = I2C_SLAVE;
1166 		npcm_i2c_clear_fifo_int(bus);
1167 		npcm_i2c_clear_rx_fifo(bus);
1168 		npcm_i2c_clear_tx_fifo(bus);
1169 		iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1170 		iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1171 		if (NPCM_I2CST_XMIT & i2cst) {
1172 			bus->operation = I2C_WRITE_OPER;
1173 		} else {
1174 			i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1175 					&info);
1176 			bus->operation = I2C_READ_OPER;
1177 		}
1178 		if (bus->own_slave_addr == 0xFF) {
1179 			/* Check which type of address match */
1180 			val = ioread8(bus->reg + NPCM_I2CCST);
1181 			if (NPCM_I2CCST_MATCH & val) {
1182 				u16 addr;
1183 				enum i2c_addr eaddr;
1184 				u8 i2ccst2;
1185 				u8 i2ccst3;
1186 
1187 				i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1188 				i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1189 
1190 				/*
1191 				 * the i2c module can response to 10 own SA.
1192 				 * check which one was addressed by the master.
1193 				 * respond to the first one.
1194 				 */
1195 				addr = ((i2ccst3 & 0x07) << 7) |
1196 					(i2ccst2 & 0x7F);
1197 				info = ffs(addr);
1198 				eaddr = (enum i2c_addr)info;
1199 				addr = npcm_i2c_get_slave_addr(bus, eaddr);
1200 				addr &= 0x7F;
1201 				bus->own_slave_addr = addr;
1202 				if (bus->PEC_mask & BIT(info))
1203 					bus->PEC_use = true;
1204 				else
1205 					bus->PEC_use = false;
1206 			} else {
1207 				if (NPCM_I2CCST_GCMATCH & val)
1208 					bus->own_slave_addr = 0;
1209 				if (NPCM_I2CCST_ARPMATCH & val)
1210 					bus->own_slave_addr = 0x61;
1211 			}
1212 		} else {
1213 			/*
1214 			 *  Slave match can happen in two options:
1215 			 *  1. Start, SA, read (slave read without further ado)
1216 			 *  2. Start, SA, read, data, restart, SA, read,  ...
1217 			 *     (slave read in fragmented mode)
1218 			 *  3. Start, SA, write, data, restart, SA, read, ..
1219 			 *     (regular write-read mode)
1220 			 */
1221 			if ((bus->state == I2C_OPER_STARTED &&
1222 			     bus->operation == I2C_READ_OPER &&
1223 			     bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1224 			     bus->stop_ind == I2C_SLAVE_RCV_IND) {
1225 				/* slave tx after slave rx w/o STOP */
1226 				bus->stop_ind = I2C_SLAVE_RESTART_IND;
1227 			}
1228 		}
1229 
1230 		if (NPCM_I2CST_XMIT & i2cst)
1231 			bus->stop_ind = I2C_SLAVE_XMIT_IND;
1232 		else
1233 			bus->stop_ind = I2C_SLAVE_RCV_IND;
1234 		bus->state = I2C_SLAVE_MATCH;
1235 		npcm_i2c_slave_rd_wr(bus);
1236 		iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1237 		ret = IRQ_HANDLED;
1238 	}
1239 
1240 	/* Slave SDA status is set - tx or rx */
1241 	if ((NPCM_I2CST_SDAST & i2cst) ||
1242 	    (bus->fifo_use &&
1243 	    (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1244 		npcm_i2c_slave_rd_wr(bus);
1245 		iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1246 		ret = IRQ_HANDLED;
1247 	} /* SDAST */
1248 
1249 	/*
1250 	 * If irq is not one of the above, make sure EOB is disabled and all
1251 	 * status bits are cleared.
1252 	 */
1253 	if (ret == IRQ_NONE) {
1254 		npcm_i2c_eob_int(bus, false);
1255 		npcm_i2c_clear_master_status(bus);
1256 	}
1257 
1258 	return IRQ_HANDLED;
1259 }
1260 
npcm_i2c_reg_slave(struct i2c_client * client)1261 static int npcm_i2c_reg_slave(struct i2c_client *client)
1262 {
1263 	unsigned long lock_flags;
1264 	struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1265 
1266 	bus->slave = client;
1267 
1268 	if (!bus->slave)
1269 		return -EINVAL;
1270 
1271 	if (client->flags & I2C_CLIENT_TEN)
1272 		return -EAFNOSUPPORT;
1273 
1274 	spin_lock_irqsave(&bus->lock, lock_flags);
1275 
1276 	npcm_i2c_init_params(bus);
1277 	bus->slv_rd_size = 0;
1278 	bus->slv_wr_size = 0;
1279 	bus->slv_rd_ind = 0;
1280 	bus->slv_wr_ind = 0;
1281 	if (client->flags & I2C_CLIENT_PEC)
1282 		bus->PEC_use = true;
1283 
1284 	dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1285 		 client->addr, bus->PEC_use);
1286 
1287 	npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1288 	npcm_i2c_clear_fifo_int(bus);
1289 	npcm_i2c_clear_rx_fifo(bus);
1290 	npcm_i2c_clear_tx_fifo(bus);
1291 	npcm_i2c_slave_int_enable(bus, true);
1292 
1293 	spin_unlock_irqrestore(&bus->lock, lock_flags);
1294 	return 0;
1295 }
1296 
npcm_i2c_unreg_slave(struct i2c_client * client)1297 static int npcm_i2c_unreg_slave(struct i2c_client *client)
1298 {
1299 	struct npcm_i2c *bus = client->adapter->algo_data;
1300 	unsigned long lock_flags;
1301 
1302 	spin_lock_irqsave(&bus->lock, lock_flags);
1303 	if (!bus->slave) {
1304 		spin_unlock_irqrestore(&bus->lock, lock_flags);
1305 		return -EINVAL;
1306 	}
1307 	npcm_i2c_slave_int_enable(bus, false);
1308 	npcm_i2c_remove_slave_addr(bus, client->addr);
1309 	bus->slave = NULL;
1310 	spin_unlock_irqrestore(&bus->lock, lock_flags);
1311 	return 0;
1312 }
1313 #endif /* CONFIG_I2C_SLAVE */
1314 
npcm_i2c_master_fifo_read(struct npcm_i2c * bus)1315 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1316 {
1317 	int rcount;
1318 	int fifo_bytes;
1319 	enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1320 
1321 	fifo_bytes = npcm_i2c_fifo_usage(bus);
1322 	rcount = bus->rd_size - bus->rd_ind;
1323 
1324 	/*
1325 	 * In order not to change the RX_TRH during transaction (we found that
1326 	 * this might be problematic if it takes too much time to read the FIFO)
1327 	 * we read the data in the following way. If the number of bytes to
1328 	 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1329 	 * and in the next int we read rest of the data.
1330 	 */
1331 	if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1332 		fifo_bytes = rcount - bus->data->fifo_size;
1333 
1334 	if (rcount <= fifo_bytes) {
1335 		/* last bytes are about to be read - end of tx */
1336 		bus->state = I2C_STOP_PENDING;
1337 		bus->stop_ind = ind;
1338 		npcm_i2c_eob_int(bus, true);
1339 		/* Stop should be set before reading last byte. */
1340 		npcm_i2c_master_stop(bus);
1341 		npcm_i2c_read_fifo(bus, fifo_bytes);
1342 	} else {
1343 		npcm_i2c_read_fifo(bus, fifo_bytes);
1344 		rcount = bus->rd_size - bus->rd_ind;
1345 		npcm_i2c_set_fifo(bus, rcount, -1);
1346 	}
1347 }
1348 
npcm_i2c_irq_master_handler_write(struct npcm_i2c * bus)1349 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1350 {
1351 	u16 wcount;
1352 
1353 	if (bus->fifo_use)
1354 		npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1355 
1356 	/* Master write operation - last byte handling */
1357 	if (bus->wr_ind == bus->wr_size) {
1358 		if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1359 			/*
1360 			 * No more bytes to send (to add to the FIFO),
1361 			 * however the FIFO is not empty yet. It is
1362 			 * still in the middle of tx. Currently there's nothing
1363 			 * to do except for waiting to the end of the tx
1364 			 * We will get an int when the FIFO will get empty.
1365 			 */
1366 			return;
1367 
1368 		if (bus->rd_size == 0) {
1369 			/* all bytes have been written, in wr only operation */
1370 			npcm_i2c_eob_int(bus, true);
1371 			bus->state = I2C_STOP_PENDING;
1372 			bus->stop_ind = I2C_MASTER_DONE_IND;
1373 			npcm_i2c_master_stop(bus);
1374 			/* Clear SDA Status bit (by writing dummy byte) */
1375 			npcm_i2c_wr_byte(bus, 0xFF);
1376 
1377 		} else {
1378 			/* last write-byte written on previous int - restart */
1379 			npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1380 			/* Generate repeated start upon next write to SDA */
1381 			npcm_i2c_master_start(bus);
1382 
1383 			/*
1384 			 * Receiving one byte only - stall after successful
1385 			 * completion of send address byte. If we NACK here, and
1386 			 * slave doesn't ACK the address, we might
1387 			 * unintentionally NACK the next multi-byte read.
1388 			 */
1389 			if (bus->rd_size == 1)
1390 				npcm_i2c_stall_after_start(bus, true);
1391 
1392 			/* Next int will occur on read */
1393 			bus->operation = I2C_READ_OPER;
1394 			/* send the slave address in read direction */
1395 			npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1396 		}
1397 	} else {
1398 		/* write next byte not last byte and not slave address */
1399 		if (!bus->fifo_use || bus->wr_size == 1) {
1400 			npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1401 		} else {
1402 			wcount = bus->wr_size - bus->wr_ind;
1403 			npcm_i2c_set_fifo(bus, -1, wcount);
1404 			if (wcount)
1405 				npcm_i2c_write_to_fifo_master(bus, wcount);
1406 		}
1407 	}
1408 }
1409 
npcm_i2c_irq_master_handler_read(struct npcm_i2c * bus)1410 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1411 {
1412 	u16 block_extra_bytes_size;
1413 	u8 data;
1414 
1415 	/* added bytes to the packet: */
1416 	block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1417 
1418 	/*
1419 	 * Perform master read, distinguishing between last byte and the rest of
1420 	 * the bytes. The last byte should be read when the clock is stopped
1421 	 */
1422 	if (bus->rd_ind == 0) { /* first byte handling: */
1423 		if (bus->read_block_use) {
1424 			/* first byte in block protocol is the size: */
1425 			data = npcm_i2c_rd_byte(bus);
1426 			data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1427 			bus->rd_size = data + block_extra_bytes_size;
1428 			bus->rd_buf[bus->rd_ind++] = data;
1429 
1430 			/* clear RX FIFO interrupt status: */
1431 			if (bus->fifo_use) {
1432 				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1433 				data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1434 				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1435 			}
1436 
1437 			npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1438 			npcm_i2c_stall_after_start(bus, false);
1439 		} else {
1440 			npcm_i2c_clear_tx_fifo(bus);
1441 			npcm_i2c_master_fifo_read(bus);
1442 		}
1443 	} else {
1444 		if (bus->rd_size == block_extra_bytes_size &&
1445 		    bus->read_block_use) {
1446 			bus->state = I2C_STOP_PENDING;
1447 			bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1448 			bus->cmd_err = -EIO;
1449 			npcm_i2c_eob_int(bus, true);
1450 			npcm_i2c_master_stop(bus);
1451 			npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1452 		} else {
1453 			npcm_i2c_master_fifo_read(bus);
1454 		}
1455 	}
1456 }
1457 
npcm_i2c_irq_handle_nmatch(struct npcm_i2c * bus)1458 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1459 {
1460 	iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1461 	npcm_i2c_nack(bus);
1462 	bus->stop_ind = I2C_BUS_ERR_IND;
1463 	npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1464 }
1465 
1466 /* A NACK has occurred */
npcm_i2c_irq_handle_nack(struct npcm_i2c * bus)1467 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1468 {
1469 	u8 val;
1470 
1471 	if (bus->nack_cnt < ULLONG_MAX)
1472 		bus->nack_cnt++;
1473 
1474 	if (bus->fifo_use) {
1475 		/*
1476 		 * if there are still untransmitted bytes in TX FIFO
1477 		 * reduce them from wr_ind
1478 		 */
1479 		if (bus->operation == I2C_WRITE_OPER)
1480 			bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1481 
1482 		/* clear the FIFO */
1483 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1484 	}
1485 
1486 	/* In master write operation, got unexpected NACK */
1487 	bus->stop_ind = I2C_NACK_IND;
1488 	/* Only current master is allowed to issue Stop Condition */
1489 	if (npcm_i2c_is_master(bus)) {
1490 		/* stopping in the middle */
1491 		npcm_i2c_eob_int(bus, false);
1492 		npcm_i2c_master_stop(bus);
1493 
1494 		/* Clear SDA Status bit (by reading dummy byte) */
1495 		npcm_i2c_rd_byte(bus);
1496 
1497 		/*
1498 		 * The bus is released from stall only after the SW clears
1499 		 * NEGACK bit. Then a Stop condition is sent.
1500 		 */
1501 		npcm_i2c_clear_master_status(bus);
1502 		readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1503 					  !(val & NPCM_I2CCST_BUSY), 10, 200);
1504 		/* Verify no status bits are still set after bus is released */
1505 		npcm_i2c_clear_master_status(bus);
1506 	}
1507 	bus->state = I2C_IDLE;
1508 
1509 	/*
1510 	 * In Master mode, NACK should be cleared only after STOP.
1511 	 * In such case, the bus is released from stall only after the
1512 	 * software clears NACK bit. Then a Stop condition is sent.
1513 	 */
1514 	npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1515 }
1516 
1517 	/* Master mode: a Bus Error has been identified */
npcm_i2c_irq_handle_ber(struct npcm_i2c * bus)1518 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1519 {
1520 	if (bus->ber_cnt < ULLONG_MAX)
1521 		bus->ber_cnt++;
1522 	bus->stop_ind = I2C_BUS_ERR_IND;
1523 	if (npcm_i2c_is_master(bus)) {
1524 		npcm_i2c_master_abort(bus);
1525 	} else {
1526 		npcm_i2c_clear_master_status(bus);
1527 
1528 		/* Clear BB (BUS BUSY) bit */
1529 		iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1530 
1531 		bus->cmd_err = -EAGAIN;
1532 		npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1533 	}
1534 	bus->state = I2C_IDLE;
1535 }
1536 
1537 	/* EOB: a master End Of Busy (meaning STOP completed) */
npcm_i2c_irq_handle_eob(struct npcm_i2c * bus)1538 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1539 {
1540 	npcm_i2c_eob_int(bus, false);
1541 	bus->state = I2C_IDLE;
1542 	npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1543 }
1544 
1545 /* Address sent and requested stall occurred (Master mode) */
npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c * bus)1546 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1547 {
1548 	if (npcm_i2c_is_quick(bus)) {
1549 		bus->state = I2C_STOP_PENDING;
1550 		bus->stop_ind = I2C_MASTER_DONE_IND;
1551 		npcm_i2c_eob_int(bus, true);
1552 		npcm_i2c_master_stop(bus);
1553 	} else if ((bus->rd_size == 1) && !bus->read_block_use) {
1554 		/*
1555 		 * Receiving one byte only - set NACK after ensuring
1556 		 * slave ACKed the address byte.
1557 		 */
1558 		npcm_i2c_nack(bus);
1559 	}
1560 
1561 	/* Reset stall-after-address-byte */
1562 	npcm_i2c_stall_after_start(bus, false);
1563 
1564 	/* Clear stall only after setting STOP */
1565 	iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1566 }
1567 
1568 /* SDA status is set - TX or RX, master */
npcm_i2c_irq_handle_sda(struct npcm_i2c * bus,u8 i2cst)1569 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1570 {
1571 	u8 fif_cts;
1572 
1573 	if (!npcm_i2c_is_master(bus))
1574 		return;
1575 
1576 	if (bus->state == I2C_IDLE) {
1577 		bus->stop_ind = I2C_WAKE_UP_IND;
1578 
1579 		if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1580 			/*
1581 			 * Need to stall after successful
1582 			 * completion of sending address byte
1583 			 */
1584 			npcm_i2c_stall_after_start(bus, true);
1585 		else
1586 			npcm_i2c_stall_after_start(bus, false);
1587 
1588 		/*
1589 		 * Receiving one byte only - stall after successful completion
1590 		 * of sending address byte If we NACK here, and slave doesn't
1591 		 * ACK the address, we might unintentionally NACK the next
1592 		 * multi-byte read
1593 		 */
1594 		if (bus->wr_size == 0 && bus->rd_size == 1)
1595 			npcm_i2c_stall_after_start(bus, true);
1596 
1597 		/* Initiate I2C master tx */
1598 
1599 		/* select bank 1 for FIFO regs */
1600 		npcm_i2c_select_bank(bus, I2C_BANK_1);
1601 
1602 		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1603 		fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1604 
1605 		/* clear FIFO and relevant status bits. */
1606 		fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1607 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1608 
1609 		/* re-enable */
1610 		fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1611 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1612 
1613 		/*
1614 		 * Configure the FIFO threshold:
1615 		 * according to the needed # of bytes to read.
1616 		 * Note: due to HW limitation can't config the rx fifo before it
1617 		 * got and ACK on the restart. LAST bit will not be reset unless
1618 		 * RX completed. It will stay set on the next tx.
1619 		 */
1620 		if (bus->wr_size)
1621 			npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1622 		else
1623 			npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1624 
1625 		bus->state = I2C_OPER_STARTED;
1626 
1627 		if (npcm_i2c_is_quick(bus) || bus->wr_size)
1628 			npcm_i2c_wr_byte(bus, bus->dest_addr);
1629 		else
1630 			npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1631 	/* SDA interrupt, after start\restart */
1632 	} else {
1633 		if (NPCM_I2CST_XMIT & i2cst) {
1634 			bus->operation = I2C_WRITE_OPER;
1635 			npcm_i2c_irq_master_handler_write(bus);
1636 		} else {
1637 			bus->operation = I2C_READ_OPER;
1638 			npcm_i2c_irq_master_handler_read(bus);
1639 		}
1640 	}
1641 }
1642 
npcm_i2c_int_master_handler(struct npcm_i2c * bus)1643 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1644 {
1645 	u8 i2cst;
1646 	int ret = -EIO;
1647 
1648 	i2cst = ioread8(bus->reg + NPCM_I2CST);
1649 
1650 	if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1651 		npcm_i2c_irq_handle_nmatch(bus);
1652 		return 0;
1653 	}
1654 	/* A NACK has occurred */
1655 	if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1656 		npcm_i2c_irq_handle_nack(bus);
1657 		return 0;
1658 	}
1659 
1660 	/* Master mode: a Bus Error has been identified */
1661 	if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1662 		npcm_i2c_irq_handle_ber(bus);
1663 		return 0;
1664 	}
1665 
1666 	/* EOB: a master End Of Busy (meaning STOP completed) */
1667 	if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1668 		       ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1669 	    (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1670 		       ioread8(bus->reg + NPCM_I2CCST3)))) {
1671 		npcm_i2c_irq_handle_eob(bus);
1672 		return 0;
1673 	}
1674 
1675 	/* Address sent and requested stall occurred (Master mode) */
1676 	if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1677 		npcm_i2c_irq_handle_stall_after_start(bus);
1678 		ret = 0;
1679 	}
1680 
1681 	/* SDA status is set - TX or RX, master */
1682 	if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1683 	    (bus->fifo_use &&
1684 	    (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1685 		npcm_i2c_irq_handle_sda(bus, i2cst);
1686 		ret = 0;
1687 	}
1688 
1689 	return ret;
1690 }
1691 
1692 /* recovery using TGCLK functionality of the module */
npcm_i2c_recovery_tgclk(struct i2c_adapter * _adap)1693 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1694 {
1695 	u8               val;
1696 	u8               fif_cts;
1697 	bool             done = false;
1698 	int              status = -ENOTRECOVERABLE;
1699 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1700 	/* Allow 3 bytes (27 toggles) to be read from the slave: */
1701 	int              iter = 27;
1702 
1703 	if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1704 		dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1705 			bus->num, bus->dest_addr);
1706 		npcm_i2c_reset(bus);
1707 		return 0;
1708 	}
1709 
1710 	npcm_i2c_int_enable(bus, false);
1711 	npcm_i2c_disable(bus);
1712 	npcm_i2c_enable(bus);
1713 	iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1714 	npcm_i2c_clear_tx_fifo(bus);
1715 	npcm_i2c_clear_rx_fifo(bus);
1716 	iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1717 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1718 	npcm_i2c_stall_after_start(bus, false);
1719 
1720 	/* select bank 1 for FIFO regs */
1721 	npcm_i2c_select_bank(bus, I2C_BANK_1);
1722 
1723 	/* clear FIFO and relevant status bits. */
1724 	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1725 	fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1726 	fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1727 	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1728 	npcm_i2c_set_fifo(bus, -1, 0);
1729 
1730 	/* Repeat the following sequence until SDA is released */
1731 	do {
1732 		/* Issue a single SCL toggle */
1733 		iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1734 		usleep_range(20, 30);
1735 		/* If SDA line is inactive (high), stop */
1736 		if (npcm_i2c_get_SDA(_adap)) {
1737 			done = true;
1738 			status = 0;
1739 		}
1740 	} while (!done && iter--);
1741 
1742 	/* If SDA line is released: send start-addr-stop, to re-sync. */
1743 	if (npcm_i2c_get_SDA(_adap)) {
1744 		/* Send an address byte in write direction: */
1745 		npcm_i2c_wr_byte(bus, bus->dest_addr);
1746 		npcm_i2c_master_start(bus);
1747 		/* Wait until START condition is sent */
1748 		status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1749 					    20, 200);
1750 		/* If START condition was sent */
1751 		if (npcm_i2c_is_master(bus) > 0) {
1752 			usleep_range(20, 30);
1753 			npcm_i2c_master_stop(bus);
1754 			usleep_range(200, 500);
1755 		}
1756 	}
1757 	npcm_i2c_reset(bus);
1758 	npcm_i2c_int_enable(bus, true);
1759 
1760 	if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1761 		status = 0;
1762 	else
1763 		status = -ENOTRECOVERABLE;
1764 	if (status) {
1765 		if (bus->rec_fail_cnt < ULLONG_MAX)
1766 			bus->rec_fail_cnt++;
1767 	} else {
1768 		if (bus->rec_succ_cnt < ULLONG_MAX)
1769 			bus->rec_succ_cnt++;
1770 	}
1771 	return status;
1772 }
1773 
1774 /* recovery using bit banging functionality of the module */
npcm_i2c_recovery_init(struct i2c_adapter * _adap)1775 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1776 {
1777 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1778 	struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1779 
1780 	rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1781 
1782 	/*
1783 	 * npcm i2c HW allows direct reading of SCL and SDA.
1784 	 * However, it does not support setting SCL and SDA directly.
1785 	 * The recovery function can toggle SCL when SDA is low (but not set)
1786 	 * Getter functions used internally, and can be used externally.
1787 	 */
1788 	rinfo->get_scl = npcm_i2c_get_SCL;
1789 	rinfo->get_sda = npcm_i2c_get_SDA;
1790 	_adap->bus_recovery_info = rinfo;
1791 }
1792 
1793 /* SCLFRQ min/max field values */
1794 #define SCLFRQ_MIN  10
1795 #define SCLFRQ_MAX  511
1796 #define clk_coef(freq, mul)	DIV_ROUND_UP((freq) * (mul), 1000000)
1797 
1798 /*
1799  * npcm_i2c_init_clk: init HW timing parameters.
1800  * NPCM7XX i2c module timing parameters are dependent on module core clk (APB)
1801  * and bus frequency.
1802  * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
1803  * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
1804  * by the HW designer, given core clock range (equations in comments below).
1805  *
1806  */
npcm_i2c_init_clk(struct npcm_i2c * bus,u32 bus_freq_hz)1807 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1808 {
1809 	u32  k1 = 0;
1810 	u32  k2 = 0;
1811 	u8   dbnct = 0;
1812 	u32  sclfrq = 0;
1813 	u8   hldt = 7;
1814 	u8   fast_mode = 0;
1815 	u32  src_clk_khz;
1816 	u32  bus_freq_khz;
1817 
1818 	src_clk_khz = bus->apb_clk / 1000;
1819 	bus_freq_khz = bus_freq_hz / 1000;
1820 	bus->bus_freq = bus_freq_hz;
1821 
1822 	/* 100KHz and below: */
1823 	if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1824 		sclfrq = src_clk_khz / (bus_freq_khz * 4);
1825 
1826 		if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1827 			return -EDOM;
1828 
1829 		if (src_clk_khz >= 40000)
1830 			hldt = 17;
1831 		else if (src_clk_khz >= 12500)
1832 			hldt = 15;
1833 		else
1834 			hldt = 7;
1835 	}
1836 
1837 	/* 400KHz: */
1838 	else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1839 		sclfrq = 0;
1840 		fast_mode = I2CCTL3_400K_MODE;
1841 
1842 		if (src_clk_khz < 7500)
1843 			/* 400KHZ cannot be supported for core clock < 7.5MHz */
1844 			return -EDOM;
1845 
1846 		else if (src_clk_khz >= 50000) {
1847 			k1 = 80;
1848 			k2 = 48;
1849 			hldt = 12;
1850 			dbnct = 7;
1851 		}
1852 
1853 		/* Master or Slave with frequency > 25MHz */
1854 		else if (src_clk_khz > 25000) {
1855 			hldt = clk_coef(src_clk_khz, 300) + 7;
1856 			k1 = clk_coef(src_clk_khz, 1600);
1857 			k2 = clk_coef(src_clk_khz, 900);
1858 		}
1859 	}
1860 
1861 	/* 1MHz: */
1862 	else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1863 		sclfrq = 0;
1864 		fast_mode = I2CCTL3_400K_MODE;
1865 
1866 		/* 1MHZ cannot be supported for core clock < 24 MHz */
1867 		if (src_clk_khz < 24000)
1868 			return -EDOM;
1869 
1870 		k1 = clk_coef(src_clk_khz, 620);
1871 		k2 = clk_coef(src_clk_khz, 380);
1872 
1873 		/* Core clk > 40 MHz */
1874 		if (src_clk_khz > 40000) {
1875 			/*
1876 			 * Set HLDT:
1877 			 * SDA hold time:  (HLDT-7) * T(CLK) >= 120
1878 			 * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1879 			 */
1880 			hldt = clk_coef(src_clk_khz, 120) + 7;
1881 		} else {
1882 			hldt = 7;
1883 			dbnct = 2;
1884 		}
1885 	}
1886 
1887 	/* Frequency larger than 1 MHz is not supported */
1888 	else
1889 		return -EINVAL;
1890 
1891 	if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1892 		k1 = round_up(k1, 2);
1893 		k2 = round_up(k2 + 1, 2);
1894 		if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1895 		    k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1896 			return -EDOM;
1897 	}
1898 
1899 	/* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1900 	iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1901 		 bus->reg + NPCM_I2CCTL2);
1902 
1903 	/* bits [8:7] are in I2CCTL3 reg */
1904 	iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1905 		 bus->reg + NPCM_I2CCTL3);
1906 
1907 	/* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1908 	npcm_i2c_select_bank(bus, I2C_BANK_0);
1909 
1910 	if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1911 		/*
1912 		 * Set SCL Low/High Time:
1913 		 * k1 = 2 * SCLLT7-0 -> Low Time  = k1 / 2
1914 		 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1915 		 */
1916 		iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1917 		iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1918 
1919 		iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1920 	}
1921 
1922 	iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1923 
1924 	/* Return to Bank 1, and stay there by default: */
1925 	npcm_i2c_select_bank(bus, I2C_BANK_1);
1926 
1927 	return 0;
1928 }
1929 
npcm_i2c_init_module(struct npcm_i2c * bus,enum i2c_mode mode,u32 bus_freq_hz)1930 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1931 				u32 bus_freq_hz)
1932 {
1933 	u8 val;
1934 	int ret;
1935 
1936 	/* Check whether module already enabled or frequency is out of bounds */
1937 	if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1938 	    bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1939 		return -EINVAL;
1940 
1941 	npcm_i2c_int_enable(bus, false);
1942 	npcm_i2c_disable(bus);
1943 
1944 	/* Configure FIFO mode : */
1945 	if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1946 		bus->fifo_use = true;
1947 		npcm_i2c_select_bank(bus, I2C_BANK_0);
1948 		val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1949 		val |= NPCM_I2CFIF_CTL_FIFO_EN;
1950 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1951 		npcm_i2c_select_bank(bus, I2C_BANK_1);
1952 	} else {
1953 		bus->fifo_use = false;
1954 	}
1955 
1956 	/* Configure I2C module clock frequency */
1957 	ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1958 	if (ret) {
1959 		dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1960 		return ret;
1961 	}
1962 
1963 	/* Enable module (before configuring CTL1) */
1964 	npcm_i2c_enable(bus);
1965 	bus->state = I2C_IDLE;
1966 	val = ioread8(bus->reg + NPCM_I2CCTL1);
1967 	val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1968 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
1969 
1970 	npcm_i2c_reset(bus);
1971 
1972 	/* Check HW is OK: SDA and SCL should be high at this point. */
1973 	if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1974 		dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1975 		dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1976 			npcm_i2c_get_SCL(&bus->adap));
1977 		return -ENXIO;
1978 	}
1979 
1980 	npcm_i2c_int_enable(bus, true);
1981 	return 0;
1982 }
1983 
__npcm_i2c_init(struct npcm_i2c * bus,struct platform_device * pdev)1984 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1985 {
1986 	u32 clk_freq_hz;
1987 	int ret;
1988 
1989 	/* Initialize the internal data structures */
1990 	bus->state = I2C_DISABLE;
1991 	bus->master_or_slave = I2C_SLAVE;
1992 	bus->int_time_stamp = 0;
1993 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1994 	bus->slave = NULL;
1995 #endif
1996 
1997 	ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1998 				       &clk_freq_hz);
1999 	if (ret) {
2000 		dev_info(&pdev->dev, "Could not read clock-frequency property");
2001 		clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
2002 	}
2003 
2004 	ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2005 	if (ret) {
2006 		dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
2007 		return ret;
2008 	}
2009 
2010 	return 0;
2011 }
2012 
npcm_i2c_bus_irq(int irq,void * dev_id)2013 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
2014 {
2015 	struct npcm_i2c *bus = dev_id;
2016 
2017 	if (npcm_i2c_is_master(bus))
2018 		bus->master_or_slave = I2C_MASTER;
2019 
2020 	if (bus->master_or_slave == I2C_MASTER) {
2021 		bus->int_time_stamp = jiffies;
2022 		if (!npcm_i2c_int_master_handler(bus))
2023 			return IRQ_HANDLED;
2024 	}
2025 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2026 	if (bus->slave) {
2027 		bus->master_or_slave = I2C_SLAVE;
2028 		if (npcm_i2c_int_slave_handler(bus))
2029 			return IRQ_HANDLED;
2030 	}
2031 #endif
2032 	/* Clear status bits for spurious interrupts */
2033 	npcm_i2c_clear_master_status(bus);
2034 
2035 	return IRQ_HANDLED;
2036 }
2037 
npcm_i2c_master_start_xmit(struct npcm_i2c * bus,u8 slave_addr,u16 nwrite,u16 nread,u8 * write_data,u8 * read_data,bool use_PEC,bool use_read_block)2038 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2039 				       u8 slave_addr, u16 nwrite, u16 nread,
2040 				       u8 *write_data, u8 *read_data,
2041 				       bool use_PEC, bool use_read_block)
2042 {
2043 	if (bus->state != I2C_IDLE) {
2044 		bus->cmd_err = -EBUSY;
2045 		return false;
2046 	}
2047 	bus->dest_addr = slave_addr << 1;
2048 	bus->wr_buf = write_data;
2049 	bus->wr_size = nwrite;
2050 	bus->wr_ind = 0;
2051 	bus->rd_buf = read_data;
2052 	bus->rd_size = nread;
2053 	bus->rd_ind = 0;
2054 	bus->PEC_use = 0;
2055 
2056 	/* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2057 	if (nread)
2058 		bus->PEC_use = use_PEC;
2059 
2060 	bus->read_block_use = use_read_block;
2061 	if (nread && !nwrite)
2062 		bus->operation = I2C_READ_OPER;
2063 	else
2064 		bus->operation = I2C_WRITE_OPER;
2065 	if (bus->fifo_use) {
2066 		u8 i2cfif_cts;
2067 
2068 		npcm_i2c_select_bank(bus, I2C_BANK_1);
2069 		/* clear FIFO and relevant status bits. */
2070 		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2071 		i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2072 		i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2073 		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2074 	}
2075 
2076 	bus->state = I2C_IDLE;
2077 	npcm_i2c_stall_after_start(bus, true);
2078 	npcm_i2c_master_start(bus);
2079 	return true;
2080 }
2081 
npcm_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)2082 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2083 				int num)
2084 {
2085 	struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2086 	struct i2c_msg *msg0, *msg1;
2087 	unsigned long time_left, flags;
2088 	u16 nwrite, nread;
2089 	u8 *write_data, *read_data;
2090 	u8 slave_addr;
2091 	unsigned long timeout;
2092 	bool read_block = false;
2093 	bool read_PEC = false;
2094 	u8 bus_busy;
2095 	unsigned long timeout_usec;
2096 
2097 	if (bus->state == I2C_DISABLE) {
2098 		dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2099 		return -EINVAL;
2100 	}
2101 
2102 	msg0 = &msgs[0];
2103 	slave_addr = msg0->addr;
2104 	if (msg0->flags & I2C_M_RD) { /* read */
2105 		nwrite = 0;
2106 		write_data = NULL;
2107 		read_data = msg0->buf;
2108 		if (msg0->flags & I2C_M_RECV_LEN) {
2109 			nread = 1;
2110 			read_block = true;
2111 			if (msg0->flags & I2C_CLIENT_PEC)
2112 				read_PEC = true;
2113 		} else {
2114 			nread = msg0->len;
2115 		}
2116 	} else { /* write */
2117 		nwrite = msg0->len;
2118 		write_data = msg0->buf;
2119 		nread = 0;
2120 		read_data = NULL;
2121 		if (num == 2) {
2122 			msg1 = &msgs[1];
2123 			read_data = msg1->buf;
2124 			if (msg1->flags & I2C_M_RECV_LEN) {
2125 				nread = 1;
2126 				read_block = true;
2127 				if (msg1->flags & I2C_CLIENT_PEC)
2128 					read_PEC = true;
2129 			} else {
2130 				nread = msg1->len;
2131 				read_block = false;
2132 			}
2133 		}
2134 	}
2135 
2136 	/*
2137 	 * Adaptive TimeOut: estimated time in usec + 100% margin:
2138 	 * 2: double the timeout for clock stretching case
2139 	 * 9: bits per transaction (including the ack/nack)
2140 	 */
2141 	timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2142 	timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2143 	if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2144 		dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2145 		return -EINVAL;
2146 	}
2147 
2148 	time_left = jiffies + timeout + 1;
2149 	do {
2150 		/*
2151 		 * we must clear slave address immediately when the bus is not
2152 		 * busy, so we spinlock it, but we don't keep the lock for the
2153 		 * entire while since it is too long.
2154 		 */
2155 		spin_lock_irqsave(&bus->lock, flags);
2156 		bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2157 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2158 		if (!bus_busy && bus->slave)
2159 			iowrite8((bus->slave->addr & 0x7F),
2160 				 bus->reg + NPCM_I2CADDR1);
2161 #endif
2162 		spin_unlock_irqrestore(&bus->lock, flags);
2163 
2164 	} while (time_is_after_jiffies(time_left) && bus_busy);
2165 
2166 	if (bus_busy) {
2167 		iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2168 		npcm_i2c_reset(bus);
2169 		i2c_recover_bus(adap);
2170 		return -EAGAIN;
2171 	}
2172 
2173 	npcm_i2c_init_params(bus);
2174 	bus->dest_addr = slave_addr;
2175 	bus->msgs = msgs;
2176 	bus->msgs_num = num;
2177 	bus->cmd_err = 0;
2178 	bus->read_block_use = read_block;
2179 
2180 	reinit_completion(&bus->cmd_complete);
2181 
2182 	npcm_i2c_int_enable(bus, true);
2183 
2184 	if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2185 				       write_data, read_data, read_PEC,
2186 				       read_block)) {
2187 		time_left = wait_for_completion_timeout(&bus->cmd_complete,
2188 							timeout);
2189 
2190 		if (time_left == 0) {
2191 			if (bus->timeout_cnt < ULLONG_MAX)
2192 				bus->timeout_cnt++;
2193 			if (bus->master_or_slave == I2C_MASTER) {
2194 				i2c_recover_bus(adap);
2195 				bus->cmd_err = -EIO;
2196 				bus->state = I2C_IDLE;
2197 			}
2198 		}
2199 	}
2200 
2201 	/* if there was BER, check if need to recover the bus: */
2202 	if (bus->cmd_err == -EAGAIN)
2203 		bus->cmd_err = i2c_recover_bus(adap);
2204 
2205 	/*
2206 	 * After any type of error, check if LAST bit is still set,
2207 	 * due to a HW issue.
2208 	 * It cannot be cleared without resetting the module.
2209 	 */
2210 	else if (bus->cmd_err &&
2211 		 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2212 		npcm_i2c_reset(bus);
2213 
2214 	/* After any xfer, successful or not, stall and EOB must be disabled */
2215 	npcm_i2c_stall_after_start(bus, false);
2216 	npcm_i2c_eob_int(bus, false);
2217 
2218 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2219 	/* reenable slave if it was enabled */
2220 	if (bus->slave)
2221 		iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2222 			 bus->reg + NPCM_I2CADDR1);
2223 #else
2224 	npcm_i2c_int_enable(bus, false);
2225 #endif
2226 	return bus->cmd_err;
2227 }
2228 
npcm_i2c_functionality(struct i2c_adapter * adap)2229 static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2230 {
2231 	return I2C_FUNC_I2C |
2232 	       I2C_FUNC_SMBUS_EMUL |
2233 	       I2C_FUNC_SMBUS_BLOCK_DATA |
2234 	       I2C_FUNC_SMBUS_PEC |
2235 	       I2C_FUNC_SLAVE;
2236 }
2237 
2238 static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2239 	.max_read_len = 32768,
2240 	.max_write_len = 32768,
2241 	.flags = I2C_AQ_COMB_WRITE_THEN_READ,
2242 };
2243 
2244 static const struct i2c_algorithm npcm_i2c_algo = {
2245 	.master_xfer = npcm_i2c_master_xfer,
2246 	.functionality = npcm_i2c_functionality,
2247 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2248 	.reg_slave	= npcm_i2c_reg_slave,
2249 	.unreg_slave	= npcm_i2c_unreg_slave,
2250 #endif
2251 };
2252 
2253 /* i2c debugfs directory: used to keep health monitor of i2c devices */
2254 static struct dentry *npcm_i2c_debugfs_dir;
2255 
npcm_i2c_init_debugfs(struct platform_device * pdev,struct npcm_i2c * bus)2256 static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2257 				  struct npcm_i2c *bus)
2258 {
2259 	struct dentry *d;
2260 
2261 	if (!npcm_i2c_debugfs_dir)
2262 		return;
2263 	d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
2264 	if (IS_ERR_OR_NULL(d))
2265 		return;
2266 	debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2267 	debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2268 	debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2269 	debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2270 	debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2271 	debugfs_create_u64("tx_complete_cnt", 0444, d, &bus->tx_complete_cnt);
2272 
2273 	bus->debugfs = d;
2274 }
2275 
npcm_i2c_probe_bus(struct platform_device * pdev)2276 static int npcm_i2c_probe_bus(struct platform_device *pdev)
2277 {
2278 	struct device_node *np = pdev->dev.of_node;
2279 	static struct regmap *gcr_regmap;
2280 	struct device *dev = &pdev->dev;
2281 	struct i2c_adapter *adap;
2282 	struct npcm_i2c *bus;
2283 	struct clk *i2c_clk;
2284 	int irq;
2285 	int ret;
2286 
2287 	bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2288 	if (!bus)
2289 		return -ENOMEM;
2290 
2291 	bus->dev = &pdev->dev;
2292 
2293 	bus->data = of_device_get_match_data(dev);
2294 	if (!bus->data) {
2295 		dev_err(dev, "OF data missing\n");
2296 		return -EINVAL;
2297 	}
2298 
2299 	bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2300 	/* core clk must be acquired to calculate module timing settings */
2301 	i2c_clk = devm_clk_get(&pdev->dev, NULL);
2302 	if (IS_ERR(i2c_clk))
2303 		return PTR_ERR(i2c_clk);
2304 	bus->apb_clk = clk_get_rate(i2c_clk);
2305 
2306 	gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr");
2307 	if (IS_ERR(gcr_regmap))
2308 		gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2309 
2310 	if (IS_ERR(gcr_regmap))
2311 		return PTR_ERR(gcr_regmap);
2312 	regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2313 
2314 	bus->reg = devm_platform_ioremap_resource(pdev, 0);
2315 	if (IS_ERR(bus->reg))
2316 		return PTR_ERR(bus->reg);
2317 
2318 	spin_lock_init(&bus->lock);
2319 	init_completion(&bus->cmd_complete);
2320 
2321 	adap = &bus->adap;
2322 	adap->owner = THIS_MODULE;
2323 	adap->retries = 3;
2324 	adap->timeout = msecs_to_jiffies(35);
2325 	adap->algo = &npcm_i2c_algo;
2326 	adap->quirks = &npcm_i2c_quirks;
2327 	adap->algo_data = bus;
2328 	adap->dev.parent = &pdev->dev;
2329 	adap->dev.of_node = pdev->dev.of_node;
2330 	adap->nr = pdev->id;
2331 
2332 	irq = platform_get_irq(pdev, 0);
2333 	if (irq < 0)
2334 		return irq;
2335 
2336 	ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2337 			       dev_name(bus->dev), bus);
2338 	if (ret)
2339 		return ret;
2340 
2341 	ret = __npcm_i2c_init(bus, pdev);
2342 	if (ret)
2343 		return ret;
2344 
2345 	npcm_i2c_recovery_init(adap);
2346 
2347 	i2c_set_adapdata(adap, bus);
2348 
2349 	snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2350 		 bus->num);
2351 	ret = i2c_add_numbered_adapter(&bus->adap);
2352 	if (ret)
2353 		return ret;
2354 
2355 	platform_set_drvdata(pdev, bus);
2356 	npcm_i2c_init_debugfs(pdev, bus);
2357 	return 0;
2358 }
2359 
npcm_i2c_remove_bus(struct platform_device * pdev)2360 static void npcm_i2c_remove_bus(struct platform_device *pdev)
2361 {
2362 	unsigned long lock_flags;
2363 	struct npcm_i2c *bus = platform_get_drvdata(pdev);
2364 
2365 	debugfs_remove_recursive(bus->debugfs);
2366 	spin_lock_irqsave(&bus->lock, lock_flags);
2367 	npcm_i2c_disable(bus);
2368 	spin_unlock_irqrestore(&bus->lock, lock_flags);
2369 	i2c_del_adapter(&bus->adap);
2370 }
2371 
2372 static const struct of_device_id npcm_i2c_bus_of_table[] = {
2373 	{ .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data },
2374 	{ .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data },
2375 	{}
2376 };
2377 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2378 
2379 static struct platform_driver npcm_i2c_bus_driver = {
2380 	.probe = npcm_i2c_probe_bus,
2381 	.remove_new = npcm_i2c_remove_bus,
2382 	.driver = {
2383 		.name = "nuvoton-i2c",
2384 		.of_match_table = npcm_i2c_bus_of_table,
2385 	}
2386 };
2387 
npcm_i2c_init(void)2388 static int __init npcm_i2c_init(void)
2389 {
2390 	int ret;
2391 
2392 	npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
2393 
2394 	ret = platform_driver_register(&npcm_i2c_bus_driver);
2395 	if (ret) {
2396 		debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2397 		return ret;
2398 	}
2399 
2400 	return 0;
2401 }
2402 module_init(npcm_i2c_init);
2403 
npcm_i2c_exit(void)2404 static void __exit npcm_i2c_exit(void)
2405 {
2406 	platform_driver_unregister(&npcm_i2c_bus_driver);
2407 	debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2408 }
2409 module_exit(npcm_i2c_exit);
2410 
2411 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2412 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2413 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2414 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2415 MODULE_LICENSE("GPL v2");
2416