1 /*
2 * ARM Versatile Express emulation.
3 *
4 * Copyright (c) 2010 - 2011 B Labs Ltd.
5 * Copyright (c) 2011 Linaro Limited
6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * Contributions after 2012-01-13 are licensed under the terms of the
21 * GNU GPL, version 2 or (at your option) any later version.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu/datadir.h"
27 #include "hw/sysbus.h"
28 #include "hw/arm/boot.h"
29 #include "hw/arm/primecell.h"
30 #include "hw/net/lan9118.h"
31 #include "hw/i2c/i2c.h"
32 #include "net/net.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/boards.h"
35 #include "hw/loader.h"
36 #include "hw/block/flash.h"
37 #include "sysemu/device_tree.h"
38 #include "qemu/error-report.h"
39 #include <libfdt.h>
40 #include "hw/char/pl011.h"
41 #include "hw/cpu/a9mpcore.h"
42 #include "hw/cpu/a15mpcore.h"
43 #include "hw/i2c/arm_sbcon_i2c.h"
44 #include "hw/sd/sd.h"
45 #include "qapi/qmp/qlist.h"
46 #include "qom/object.h"
47 #include "audio/audio.h"
48 #include "target/arm/cpu-qom.h"
49
50 #define VEXPRESS_BOARD_ID 0x8e0
51 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
52 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
53
54 /* Number of virtio transports to create (0..8; limited by
55 * number of available IRQ lines).
56 */
57 #define NUM_VIRTIO_TRANSPORTS 4
58
59 /* Address maps for peripherals:
60 * the Versatile Express motherboard has two possible maps,
61 * the "legacy" one (used for A9) and the "Cortex-A Series"
62 * map (used for newer cores).
63 * Individual daughterboards can also have different maps for
64 * their peripherals.
65 */
66
67 enum {
68 VE_SYSREGS,
69 VE_SP810,
70 VE_SERIALPCI,
71 VE_PL041,
72 VE_MMCI,
73 VE_KMI0,
74 VE_KMI1,
75 VE_UART0,
76 VE_UART1,
77 VE_UART2,
78 VE_UART3,
79 VE_WDT,
80 VE_TIMER01,
81 VE_TIMER23,
82 VE_SERIALDVI,
83 VE_RTC,
84 VE_COMPACTFLASH,
85 VE_CLCD,
86 VE_NORFLASH0,
87 VE_NORFLASH1,
88 VE_NORFLASHALIAS,
89 VE_SRAM,
90 VE_VIDEORAM,
91 VE_ETHERNET,
92 VE_USB,
93 VE_DAPROM,
94 VE_VIRTIO,
95 };
96
97 static hwaddr motherboard_legacy_map[] = {
98 [VE_NORFLASHALIAS] = 0,
99 /* CS7: 0x10000000 .. 0x10020000 */
100 [VE_SYSREGS] = 0x10000000,
101 [VE_SP810] = 0x10001000,
102 [VE_SERIALPCI] = 0x10002000,
103 [VE_PL041] = 0x10004000,
104 [VE_MMCI] = 0x10005000,
105 [VE_KMI0] = 0x10006000,
106 [VE_KMI1] = 0x10007000,
107 [VE_UART0] = 0x10009000,
108 [VE_UART1] = 0x1000a000,
109 [VE_UART2] = 0x1000b000,
110 [VE_UART3] = 0x1000c000,
111 [VE_WDT] = 0x1000f000,
112 [VE_TIMER01] = 0x10011000,
113 [VE_TIMER23] = 0x10012000,
114 [VE_VIRTIO] = 0x10013000,
115 [VE_SERIALDVI] = 0x10016000,
116 [VE_RTC] = 0x10017000,
117 [VE_COMPACTFLASH] = 0x1001a000,
118 [VE_CLCD] = 0x1001f000,
119 /* CS0: 0x40000000 .. 0x44000000 */
120 [VE_NORFLASH0] = 0x40000000,
121 /* CS1: 0x44000000 .. 0x48000000 */
122 [VE_NORFLASH1] = 0x44000000,
123 /* CS2: 0x48000000 .. 0x4a000000 */
124 [VE_SRAM] = 0x48000000,
125 /* CS3: 0x4c000000 .. 0x50000000 */
126 [VE_VIDEORAM] = 0x4c000000,
127 [VE_ETHERNET] = 0x4e000000,
128 [VE_USB] = 0x4f000000,
129 };
130
131 static hwaddr motherboard_aseries_map[] = {
132 [VE_NORFLASHALIAS] = 0,
133 /* CS0: 0x08000000 .. 0x0c000000 */
134 [VE_NORFLASH0] = 0x08000000,
135 /* CS4: 0x0c000000 .. 0x10000000 */
136 [VE_NORFLASH1] = 0x0c000000,
137 /* CS5: 0x10000000 .. 0x14000000 */
138 /* CS1: 0x14000000 .. 0x18000000 */
139 [VE_SRAM] = 0x14000000,
140 /* CS2: 0x18000000 .. 0x1c000000 */
141 [VE_VIDEORAM] = 0x18000000,
142 [VE_ETHERNET] = 0x1a000000,
143 [VE_USB] = 0x1b000000,
144 /* CS3: 0x1c000000 .. 0x20000000 */
145 [VE_DAPROM] = 0x1c000000,
146 [VE_SYSREGS] = 0x1c010000,
147 [VE_SP810] = 0x1c020000,
148 [VE_SERIALPCI] = 0x1c030000,
149 [VE_PL041] = 0x1c040000,
150 [VE_MMCI] = 0x1c050000,
151 [VE_KMI0] = 0x1c060000,
152 [VE_KMI1] = 0x1c070000,
153 [VE_UART0] = 0x1c090000,
154 [VE_UART1] = 0x1c0a0000,
155 [VE_UART2] = 0x1c0b0000,
156 [VE_UART3] = 0x1c0c0000,
157 [VE_WDT] = 0x1c0f0000,
158 [VE_TIMER01] = 0x1c110000,
159 [VE_TIMER23] = 0x1c120000,
160 [VE_VIRTIO] = 0x1c130000,
161 [VE_SERIALDVI] = 0x1c160000,
162 [VE_RTC] = 0x1c170000,
163 [VE_COMPACTFLASH] = 0x1c1a0000,
164 [VE_CLCD] = 0x1c1f0000,
165 };
166
167 /* Structure defining the peculiarities of a specific daughterboard */
168
169 typedef struct VEDBoardInfo VEDBoardInfo;
170
171 struct VexpressMachineClass {
172 MachineClass parent;
173 VEDBoardInfo *daughterboard;
174 };
175
176 struct VexpressMachineState {
177 MachineState parent;
178 MemoryRegion vram;
179 MemoryRegion sram;
180 MemoryRegion flashalias;
181 MemoryRegion a15sram;
182 bool secure;
183 bool virt;
184 };
185
186 #define TYPE_VEXPRESS_MACHINE "vexpress"
187 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
188 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
189 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
190
191 typedef void DBoardInitFn(VexpressMachineState *machine,
192 ram_addr_t ram_size,
193 const char *cpu_type,
194 qemu_irq *pic);
195
196 struct VEDBoardInfo {
197 struct arm_boot_info bootinfo;
198 const hwaddr *motherboard_map;
199 hwaddr loader_start;
200 const hwaddr gic_cpu_if_addr;
201 uint32_t proc_id;
202 uint32_t num_voltage_sensors;
203 const uint32_t *voltages;
204 uint32_t num_clocks;
205 const uint32_t *clocks;
206 DBoardInitFn *init;
207 };
208
init_cpus(MachineState * ms,const char * cpu_type,const char * privdev,hwaddr periphbase,qemu_irq * pic,bool secure,bool virt)209 static void init_cpus(MachineState *ms, const char *cpu_type,
210 const char *privdev, hwaddr periphbase,
211 qemu_irq *pic, bool secure, bool virt)
212 {
213 DeviceState *dev;
214 SysBusDevice *busdev;
215 int n;
216 unsigned int smp_cpus = ms->smp.cpus;
217
218 /* Create the actual CPUs */
219 for (n = 0; n < smp_cpus; n++) {
220 Object *cpuobj = object_new(cpu_type);
221
222 if (!secure) {
223 object_property_set_bool(cpuobj, "has_el3", false, NULL);
224 }
225 if (!virt) {
226 if (object_property_find(cpuobj, "has_el2")) {
227 object_property_set_bool(cpuobj, "has_el2", false, NULL);
228 }
229 }
230
231 if (object_property_find(cpuobj, "reset-cbar")) {
232 object_property_set_int(cpuobj, "reset-cbar", periphbase,
233 &error_abort);
234 }
235 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
236 }
237
238 /* Create the private peripheral devices (including the GIC);
239 * this must happen after the CPUs are created because a15mpcore_priv
240 * wires itself up to the CPU's generic_timer gpio out lines.
241 */
242 dev = qdev_new(privdev);
243 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
244 busdev = SYS_BUS_DEVICE(dev);
245 sysbus_realize_and_unref(busdev, &error_fatal);
246 sysbus_mmio_map(busdev, 0, periphbase);
247
248 /* Interrupts [42:0] are from the motherboard;
249 * [47:43] are reserved; [63:48] are daughterboard
250 * peripherals. Note that some documentation numbers
251 * external interrupts starting from 32 (because there
252 * are internal interrupts 0..31).
253 */
254 for (n = 0; n < 64; n++) {
255 pic[n] = qdev_get_gpio_in(dev, n);
256 }
257
258 /* Connect the CPUs to the GIC */
259 for (n = 0; n < smp_cpus; n++) {
260 DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
261
262 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
263 sysbus_connect_irq(busdev, n + smp_cpus,
264 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
265 sysbus_connect_irq(busdev, n + 2 * smp_cpus,
266 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
267 sysbus_connect_irq(busdev, n + 3 * smp_cpus,
268 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
269 }
270 }
271
a9_daughterboard_init(VexpressMachineState * vms,ram_addr_t ram_size,const char * cpu_type,qemu_irq * pic)272 static void a9_daughterboard_init(VexpressMachineState *vms,
273 ram_addr_t ram_size,
274 const char *cpu_type,
275 qemu_irq *pic)
276 {
277 MachineState *machine = MACHINE(vms);
278 MemoryRegion *sysmem = get_system_memory();
279 DeviceState *dev;
280
281 if (ram_size > 0x40000000) {
282 /* 1GB is the maximum the address space permits */
283 error_report("vexpress-a9: cannot model more than 1GB RAM");
284 exit(1);
285 }
286
287 /*
288 * RAM is from 0x60000000 upwards. The bottom 64MB of the
289 * address space should in theory be remappable to various
290 * things including ROM or RAM; we always map the flash there.
291 */
292 memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
293
294 /* 0x1e000000 A9MPCore (SCU) private memory region */
295 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
296 vms->secure, vms->virt);
297
298 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
299
300 /* 0x10020000 PL111 CLCD (daughterboard) */
301 dev = qdev_new("pl111");
302 object_property_set_link(OBJECT(dev), "framebuffer-memory",
303 OBJECT(sysmem), &error_fatal);
304 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
305 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000);
306 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[44]);
307
308 /* 0x10060000 AXI RAM */
309 /* 0x100e0000 PL341 Dynamic Memory Controller */
310 /* 0x100e1000 PL354 Static Memory Controller */
311 /* 0x100e2000 System Configuration Controller */
312
313 sysbus_create_simple("sp804", 0x100e4000, pic[48]);
314 /* 0x100e5000 SP805 Watchdog module */
315 /* 0x100e6000 BP147 TrustZone Protection Controller */
316 /* 0x100e9000 PL301 'Fast' AXI matrix */
317 /* 0x100ea000 PL301 'Slow' AXI matrix */
318 /* 0x100ec000 TrustZone Address Space Controller */
319 /* 0x10200000 CoreSight debug APB */
320 /* 0x1e00a000 PL310 L2 Cache Controller */
321 sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
322 }
323
324 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
325 * values are in microvolts.
326 */
327 static const uint32_t a9_voltages[] = {
328 1000000, /* VD10 : 1.0V : SoC internal logic voltage */
329 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
330 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
331 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
332 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
333 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
334 };
335
336 /* Reset values for daughterboard oscillators (in Hz) */
337 static const uint32_t a9_clocks[] = {
338 45000000, /* AMBA AXI ACLK: 45MHz */
339 23750000, /* daughterboard CLCD clock: 23.75MHz */
340 66670000, /* Test chip reference clock: 66.67MHz */
341 };
342
343 static VEDBoardInfo a9_daughterboard = {
344 .motherboard_map = motherboard_legacy_map,
345 .loader_start = 0x60000000,
346 .gic_cpu_if_addr = 0x1e000100,
347 .proc_id = 0x0c000191,
348 .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
349 .voltages = a9_voltages,
350 .num_clocks = ARRAY_SIZE(a9_clocks),
351 .clocks = a9_clocks,
352 .init = a9_daughterboard_init,
353 };
354
a15_daughterboard_init(VexpressMachineState * vms,ram_addr_t ram_size,const char * cpu_type,qemu_irq * pic)355 static void a15_daughterboard_init(VexpressMachineState *vms,
356 ram_addr_t ram_size,
357 const char *cpu_type,
358 qemu_irq *pic)
359 {
360 MachineState *machine = MACHINE(vms);
361 MemoryRegion *sysmem = get_system_memory();
362
363 {
364 /* We have to use a separate 64 bit variable here to avoid the gcc
365 * "comparison is always false due to limited range of data type"
366 * warning if we are on a host where ram_addr_t is 32 bits.
367 */
368 uint64_t rsz = ram_size;
369 if (rsz > (30ULL * 1024 * 1024 * 1024)) {
370 error_report("vexpress-a15: cannot model more than 30GB RAM");
371 exit(1);
372 }
373 }
374
375 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
376 memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
377
378 /* 0x2c000000 A15MPCore private memory region (GIC) */
379 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
380 0x2c000000, pic, vms->secure, vms->virt);
381
382 /* A15 daughterboard peripherals: */
383
384 /* 0x20000000: CoreSight interfaces: not modelled */
385 /* 0x2a000000: PL301 AXI interconnect: not modelled */
386 /* 0x2a420000: SCC: not modelled */
387 /* 0x2a430000: system counter: not modelled */
388 /* 0x2b000000: HDLCD controller: not modelled */
389 /* 0x2b060000: SP805 watchdog: not modelled */
390 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
391 /* 0x2e000000: system SRAM */
392 memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000,
393 &error_fatal);
394 memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram);
395
396 /* 0x7ffb0000: DMA330 DMA controller: not modelled */
397 /* 0x7ffd0000: PL354 static memory controller: not modelled */
398 }
399
400 static const uint32_t a15_voltages[] = {
401 900000, /* Vcore: 0.9V : CPU core voltage */
402 };
403
404 static const uint32_t a15_clocks[] = {
405 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
406 0, /* OSCCLK1: reserved */
407 0, /* OSCCLK2: reserved */
408 0, /* OSCCLK3: reserved */
409 40000000, /* OSCCLK4: 40MHz : external AXI master clock */
410 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
411 50000000, /* OSCCLK6: 50MHz : static memory controller clock */
412 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
413 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
414 };
415
416 static VEDBoardInfo a15_daughterboard = {
417 .motherboard_map = motherboard_aseries_map,
418 .loader_start = 0x80000000,
419 .gic_cpu_if_addr = 0x2c002000,
420 .proc_id = 0x14000237,
421 .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
422 .voltages = a15_voltages,
423 .num_clocks = ARRAY_SIZE(a15_clocks),
424 .clocks = a15_clocks,
425 .init = a15_daughterboard_init,
426 };
427
add_virtio_mmio_node(void * fdt,uint32_t acells,uint32_t scells,hwaddr addr,hwaddr size,uint32_t intc,int irq)428 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
429 hwaddr addr, hwaddr size, uint32_t intc,
430 int irq)
431 {
432 /* Add a virtio_mmio node to the device tree blob:
433 * virtio_mmio@ADDRESS {
434 * compatible = "virtio,mmio";
435 * reg = <ADDRESS, SIZE>;
436 * interrupt-parent = <&intc>;
437 * interrupts = <0, irq, 1>;
438 * }
439 * (Note that the format of the interrupts property is dependent on the
440 * interrupt controller that interrupt-parent points to; these are for
441 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
442 */
443 int rc;
444 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
445
446 rc = qemu_fdt_add_subnode(fdt, nodename);
447 rc |= qemu_fdt_setprop_string(fdt, nodename,
448 "compatible", "virtio,mmio");
449 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
450 acells, addr, scells, size);
451 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
452 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
453 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
454 g_free(nodename);
455 if (rc) {
456 return -1;
457 }
458 return 0;
459 }
460
find_int_controller(void * fdt)461 static uint32_t find_int_controller(void *fdt)
462 {
463 /* Find the FDT node corresponding to the interrupt controller
464 * for virtio-mmio devices. We do this by scanning the fdt for
465 * a node with the right compatibility, since we know there is
466 * only one GIC on a vexpress board.
467 * We return the phandle of the node, or 0 if none was found.
468 */
469 const char *compat = "arm,cortex-a9-gic";
470 int offset;
471
472 offset = fdt_node_offset_by_compatible(fdt, -1, compat);
473 if (offset >= 0) {
474 return fdt_get_phandle(fdt, offset);
475 }
476 return 0;
477 }
478
vexpress_modify_dtb(const struct arm_boot_info * info,void * fdt)479 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
480 {
481 uint32_t acells, scells, intc;
482 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
483
484 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
485 NULL, &error_fatal);
486 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
487 NULL, &error_fatal);
488 intc = find_int_controller(fdt);
489 if (!intc) {
490 /* Not fatal, we just won't provide virtio. This will
491 * happen with older device tree blobs.
492 */
493 warn_report("couldn't find interrupt controller in "
494 "dtb; will not include virtio-mmio devices in the dtb");
495 } else {
496 int i;
497 const hwaddr *map = daughterboard->motherboard_map;
498
499 /* We iterate backwards here because adding nodes
500 * to the dtb puts them in last-first.
501 */
502 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
503 add_virtio_mmio_node(fdt, acells, scells,
504 map[VE_VIRTIO] + 0x200 * i,
505 0x200, intc, 40 + i);
506 }
507 }
508 }
509
510
511 /* Open code a private version of pflash registration since we
512 * need to set non-default device width for VExpress platform.
513 */
ve_pflash_cfi01_register(hwaddr base,const char * name,DriveInfo * di)514 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
515 DriveInfo *di)
516 {
517 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
518
519 if (di) {
520 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
521 }
522
523 qdev_prop_set_uint32(dev, "num-blocks",
524 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
525 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
526 qdev_prop_set_uint8(dev, "width", 4);
527 qdev_prop_set_uint8(dev, "device-width", 2);
528 qdev_prop_set_bit(dev, "big-endian", false);
529 qdev_prop_set_uint16(dev, "id0", 0x89);
530 qdev_prop_set_uint16(dev, "id1", 0x18);
531 qdev_prop_set_uint16(dev, "id2", 0x00);
532 qdev_prop_set_uint16(dev, "id3", 0x00);
533 qdev_prop_set_string(dev, "name", name);
534 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
535
536 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
537 return PFLASH_CFI01(dev);
538 }
539
vexpress_common_init(MachineState * machine)540 static void vexpress_common_init(MachineState *machine)
541 {
542 VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
543 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
544 VEDBoardInfo *daughterboard = vmc->daughterboard;
545 DeviceState *dev, *sysctl, *pl041;
546 qemu_irq pic[64];
547 uint32_t sys_id;
548 DriveInfo *dinfo;
549 PFlashCFI01 *pflash0;
550 I2CBus *i2c;
551 ram_addr_t vram_size, sram_size;
552 MemoryRegion *sysmem = get_system_memory();
553 const hwaddr *map = daughterboard->motherboard_map;
554 QList *db_voltage, *db_clock;
555 int i;
556
557 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
558
559 /*
560 * If a bios file was provided, attempt to map it into memory
561 */
562 if (machine->firmware) {
563 char *fn;
564 int image_size;
565
566 if (drive_get(IF_PFLASH, 0, 0)) {
567 error_report("The contents of the first flash device may be "
568 "specified with -bios or with -drive if=pflash... "
569 "but you cannot use both options at once");
570 exit(1);
571 }
572 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
573 if (!fn) {
574 error_report("Could not find ROM image '%s'", machine->firmware);
575 exit(1);
576 }
577 image_size = load_image_targphys(fn, map[VE_NORFLASH0],
578 VEXPRESS_FLASH_SIZE);
579 g_free(fn);
580 if (image_size < 0) {
581 error_report("Could not load ROM image '%s'", machine->firmware);
582 exit(1);
583 }
584 }
585
586 /* Motherboard peripherals: the wiring is the same but the
587 * addresses vary between the legacy and A-Series memory maps.
588 */
589
590 sys_id = 0x1190f500;
591
592 sysctl = qdev_new("realview_sysctl");
593 qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
594 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
595
596 db_voltage = qlist_new();
597 for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
598 qlist_append_int(db_voltage, daughterboard->voltages[i]);
599 }
600 qdev_prop_set_array(sysctl, "db-voltage", db_voltage);
601
602 db_clock = qlist_new();
603 for (i = 0; i < daughterboard->num_clocks; i++) {
604 qlist_append_int(db_clock, daughterboard->clocks[i]);
605 }
606 qdev_prop_set_array(sysctl, "db-clock", db_clock);
607
608 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
609 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
610
611 /* VE_SP810: not modelled */
612 /* VE_SERIALPCI: not modelled */
613
614 pl041 = qdev_new("pl041");
615 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
616 if (machine->audiodev) {
617 qdev_prop_set_string(pl041, "audiodev", machine->audiodev);
618 }
619 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
620 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
621 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
622
623 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
624 /* Wire up MMC card detect and read-only signals */
625 qdev_connect_gpio_out_named(dev, "card-read-only", 0,
626 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
627 qdev_connect_gpio_out_named(dev, "card-inserted", 0,
628 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
629 dinfo = drive_get(IF_SD, 0, 0);
630 if (dinfo) {
631 DeviceState *card;
632
633 card = qdev_new(TYPE_SD_CARD);
634 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
635 &error_fatal);
636 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
637 &error_fatal);
638 }
639
640 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
641 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
642
643 pl011_create(map[VE_UART0], pic[5], serial_hd(0));
644 pl011_create(map[VE_UART1], pic[6], serial_hd(1));
645 pl011_create(map[VE_UART2], pic[7], serial_hd(2));
646 pl011_create(map[VE_UART3], pic[8], serial_hd(3));
647
648 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
649 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
650
651 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL);
652 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
653 i2c_slave_create_simple(i2c, "sii9022", 0x39);
654
655 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
656
657 /* VE_COMPACTFLASH: not modelled */
658
659 dev = qdev_new("pl111");
660 object_property_set_link(OBJECT(dev), "framebuffer-memory",
661 OBJECT(sysmem), &error_fatal);
662 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
663 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, map[VE_CLCD]);
664 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[14]);
665
666 dinfo = drive_get(IF_PFLASH, 0, 0);
667 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
668 dinfo);
669
670 if (map[VE_NORFLASHALIAS] != -1) {
671 /* Map flash 0 as an alias into low memory */
672 MemoryRegion *flash0mem;
673 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
674 memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias",
675 flash0mem, 0, VEXPRESS_FLASH_SIZE);
676 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias);
677 }
678
679 dinfo = drive_get(IF_PFLASH, 0, 1);
680 ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
681
682 sram_size = 0x2000000;
683 memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size,
684 &error_fatal);
685 memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram);
686
687 vram_size = 0x800000;
688 memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size,
689 &error_fatal);
690 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram);
691
692 /* 0x4e000000 LAN9118 Ethernet */
693 if (qemu_find_nic_info("lan9118", true, NULL)) {
694 lan9118_init(map[VE_ETHERNET], pic[15]);
695 }
696
697 /* VE_USB: not modelled */
698
699 /* VE_DAPROM: not modelled */
700
701 /* Create mmio transports, so the user can create virtio backends
702 * (which will be automatically plugged in to the transports). If
703 * no backend is created the transport will just sit harmlessly idle.
704 */
705 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
706 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
707 pic[40 + i]);
708 }
709
710 daughterboard->bootinfo.ram_size = machine->ram_size;
711 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
712 daughterboard->bootinfo.loader_start = daughterboard->loader_start;
713 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
714 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
715 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
716 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
717 /* When booting Linux we should be in secure state if the CPU has one. */
718 daughterboard->bootinfo.secure_boot = vms->secure;
719 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
720 }
721
vexpress_get_secure(Object * obj,Error ** errp)722 static bool vexpress_get_secure(Object *obj, Error **errp)
723 {
724 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
725
726 return vms->secure;
727 }
728
vexpress_set_secure(Object * obj,bool value,Error ** errp)729 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
730 {
731 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
732
733 vms->secure = value;
734 }
735
vexpress_get_virt(Object * obj,Error ** errp)736 static bool vexpress_get_virt(Object *obj, Error **errp)
737 {
738 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
739
740 return vms->virt;
741 }
742
vexpress_set_virt(Object * obj,bool value,Error ** errp)743 static void vexpress_set_virt(Object *obj, bool value, Error **errp)
744 {
745 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
746
747 vms->virt = value;
748 }
749
vexpress_instance_init(Object * obj)750 static void vexpress_instance_init(Object *obj)
751 {
752 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
753
754 /* EL3 is enabled by default on vexpress */
755 vms->secure = true;
756 }
757
vexpress_a15_instance_init(Object * obj)758 static void vexpress_a15_instance_init(Object *obj)
759 {
760 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
761
762 /*
763 * For the vexpress-a15, EL2 is by default enabled if EL3 is,
764 * but can also be specifically set to on or off.
765 */
766 vms->virt = true;
767 }
768
vexpress_a9_instance_init(Object * obj)769 static void vexpress_a9_instance_init(Object *obj)
770 {
771 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
772
773 /* The A9 doesn't have the virt extensions */
774 vms->virt = false;
775 }
776
vexpress_class_init(ObjectClass * oc,void * data)777 static void vexpress_class_init(ObjectClass *oc, void *data)
778 {
779 MachineClass *mc = MACHINE_CLASS(oc);
780
781 mc->desc = "ARM Versatile Express";
782 mc->init = vexpress_common_init;
783 mc->max_cpus = 4;
784 mc->ignore_memory_transaction_failures = true;
785 mc->default_ram_id = "vexpress.highmem";
786
787 machine_add_audiodev_property(mc);
788 object_class_property_add_bool(oc, "secure", vexpress_get_secure,
789 vexpress_set_secure);
790 object_class_property_set_description(oc, "secure",
791 "Set on/off to enable/disable the ARM "
792 "Security Extensions (TrustZone)");
793 }
794
vexpress_a9_class_init(ObjectClass * oc,void * data)795 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
796 {
797 static const char * const valid_cpu_types[] = {
798 ARM_CPU_TYPE_NAME("cortex-a9"),
799 NULL
800 };
801 MachineClass *mc = MACHINE_CLASS(oc);
802 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
803
804 mc->desc = "ARM Versatile Express for Cortex-A9";
805 mc->valid_cpu_types = valid_cpu_types;
806
807 vmc->daughterboard = &a9_daughterboard;
808 }
809
vexpress_a15_class_init(ObjectClass * oc,void * data)810 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
811 {
812 static const char * const valid_cpu_types[] = {
813 ARM_CPU_TYPE_NAME("cortex-a15"),
814 NULL
815 };
816 MachineClass *mc = MACHINE_CLASS(oc);
817 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
818
819 mc->desc = "ARM Versatile Express for Cortex-A15";
820 mc->valid_cpu_types = valid_cpu_types;
821
822 vmc->daughterboard = &a15_daughterboard;
823
824 object_class_property_add_bool(oc, "virtualization", vexpress_get_virt,
825 vexpress_set_virt);
826 object_class_property_set_description(oc, "virtualization",
827 "Set on/off to enable/disable the ARM "
828 "Virtualization Extensions "
829 "(defaults to same as 'secure')");
830
831 }
832
833 static const TypeInfo vexpress_info = {
834 .name = TYPE_VEXPRESS_MACHINE,
835 .parent = TYPE_MACHINE,
836 .abstract = true,
837 .instance_size = sizeof(VexpressMachineState),
838 .instance_init = vexpress_instance_init,
839 .class_size = sizeof(VexpressMachineClass),
840 .class_init = vexpress_class_init,
841 };
842
843 static const TypeInfo vexpress_a9_info = {
844 .name = TYPE_VEXPRESS_A9_MACHINE,
845 .parent = TYPE_VEXPRESS_MACHINE,
846 .class_init = vexpress_a9_class_init,
847 .instance_init = vexpress_a9_instance_init,
848 };
849
850 static const TypeInfo vexpress_a15_info = {
851 .name = TYPE_VEXPRESS_A15_MACHINE,
852 .parent = TYPE_VEXPRESS_MACHINE,
853 .class_init = vexpress_a15_class_init,
854 .instance_init = vexpress_a15_instance_init,
855 };
856
vexpress_machine_init(void)857 static void vexpress_machine_init(void)
858 {
859 type_register_static(&vexpress_info);
860 type_register_static(&vexpress_a9_info);
861 type_register_static(&vexpress_a15_info);
862 }
863
864 type_init(vexpress_machine_init);
865