1 /* 2 * Copyright © 2006-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * 27 */ 28 29 /** @file 30 * Integrated TV-out support for the 915GM and 945GM. 31 */ 32 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "intel_connector.h" 40 #include "intel_crtc.h" 41 #include "intel_de.h" 42 #include "intel_display_irq.h" 43 #include "intel_display_types.h" 44 #include "intel_dpll.h" 45 #include "intel_hotplug.h" 46 #include "intel_load_detect.h" 47 #include "intel_tv.h" 48 #include "intel_tv_regs.h" 49 50 enum tv_margin { 51 TV_MARGIN_LEFT, TV_MARGIN_TOP, 52 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM 53 }; 54 55 struct intel_tv { 56 struct intel_encoder base; 57 58 int type; 59 }; 60 61 struct video_levels { 62 u16 blank, black; 63 u8 burst; 64 }; 65 66 struct color_conversion { 67 u16 ry, gy, by, ay; 68 u16 ru, gu, bu, au; 69 u16 rv, gv, bv, av; 70 }; 71 72 static const u32 filter_table[] = { 73 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 74 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 75 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 76 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 77 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 78 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 79 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 80 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 81 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 82 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 83 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 84 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 85 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 86 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 87 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 88 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 89 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 90 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 91 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 92 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 93 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 94 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 95 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 96 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 97 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 98 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 99 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 100 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 101 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 102 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 103 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0, 104 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 105 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 106 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 107 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 108 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 109 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 110 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 111 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 112 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 113 0x28003100, 0x28002F00, 0x00003100, 0x36403000, 114 0x2D002CC0, 0x30003640, 0x2D0036C0, 115 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 116 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 117 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 118 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 119 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 120 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 121 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 122 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 123 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 124 0x28003100, 0x28002F00, 0x00003100, 125 }; 126 127 /* 128 * Color conversion values have 3 separate fixed point formats: 129 * 130 * 10 bit fields (ay, au) 131 * 1.9 fixed point (b.bbbbbbbbb) 132 * 11 bit fields (ry, by, ru, gu, gv) 133 * exp.mantissa (ee.mmmmmmmmm) 134 * ee = 00 = 10^-1 (0.mmmmmmmmm) 135 * ee = 01 = 10^-2 (0.0mmmmmmmmm) 136 * ee = 10 = 10^-3 (0.00mmmmmmmmm) 137 * ee = 11 = 10^-4 (0.000mmmmmmmmm) 138 * 12 bit fields (gy, rv, bu) 139 * exp.mantissa (eee.mmmmmmmmm) 140 * eee = 000 = 10^-1 (0.mmmmmmmmm) 141 * eee = 001 = 10^-2 (0.0mmmmmmmmm) 142 * eee = 010 = 10^-3 (0.00mmmmmmmmm) 143 * eee = 011 = 10^-4 (0.000mmmmmmmmm) 144 * eee = 100 = reserved 145 * eee = 101 = reserved 146 * eee = 110 = reserved 147 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation) 148 * 149 * Saturation and contrast are 8 bits, with their own representation: 150 * 8 bit field (saturation, contrast) 151 * exp.mantissa (ee.mmmmmm) 152 * ee = 00 = 10^-1 (0.mmmmmm) 153 * ee = 01 = 10^0 (m.mmmmm) 154 * ee = 10 = 10^1 (mm.mmmm) 155 * ee = 11 = 10^2 (mmm.mmm) 156 * 157 * Simple conversion function: 158 * 159 * static u32 160 * float_to_csc_11(float f) 161 * { 162 * u32 exp; 163 * u32 mant; 164 * u32 ret; 165 * 166 * if (f < 0) 167 * f = -f; 168 * 169 * if (f >= 1) { 170 * exp = 0x7; 171 * mant = 1 << 8; 172 * } else { 173 * for (exp = 0; exp < 3 && f < 0.5; exp++) 174 * f *= 2.0; 175 * mant = (f * (1 << 9) + 0.5); 176 * if (mant >= (1 << 9)) 177 * mant = (1 << 9) - 1; 178 * } 179 * ret = (exp << 9) | mant; 180 * return ret; 181 * } 182 */ 183 184 /* 185 * Behold, magic numbers! If we plant them they might grow a big 186 * s-video cable to the sky... or something. 187 * 188 * Pre-converted to appropriate hex value. 189 */ 190 191 /* 192 * PAL & NTSC values for composite & s-video connections 193 */ 194 static const struct color_conversion ntsc_m_csc_composite = { 195 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 196 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 197 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 198 }; 199 200 static const struct video_levels ntsc_m_levels_composite = { 201 .blank = 225, .black = 267, .burst = 113, 202 }; 203 204 static const struct color_conversion ntsc_m_csc_svideo = { 205 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 206 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 207 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 208 }; 209 210 static const struct video_levels ntsc_m_levels_svideo = { 211 .blank = 266, .black = 316, .burst = 133, 212 }; 213 214 static const struct color_conversion ntsc_j_csc_composite = { 215 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119, 216 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200, 217 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200, 218 }; 219 220 static const struct video_levels ntsc_j_levels_composite = { 221 .blank = 225, .black = 225, .burst = 113, 222 }; 223 224 static const struct color_conversion ntsc_j_csc_svideo = { 225 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c, 226 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200, 227 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200, 228 }; 229 230 static const struct video_levels ntsc_j_levels_svideo = { 231 .blank = 266, .black = 266, .burst = 133, 232 }; 233 234 static const struct color_conversion pal_csc_composite = { 235 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113, 236 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200, 237 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200, 238 }; 239 240 static const struct video_levels pal_levels_composite = { 241 .blank = 237, .black = 237, .burst = 118, 242 }; 243 244 static const struct color_conversion pal_csc_svideo = { 245 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 246 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200, 247 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200, 248 }; 249 250 static const struct video_levels pal_levels_svideo = { 251 .blank = 280, .black = 280, .burst = 139, 252 }; 253 254 static const struct color_conversion pal_m_csc_composite = { 255 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 256 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 257 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 258 }; 259 260 static const struct video_levels pal_m_levels_composite = { 261 .blank = 225, .black = 267, .burst = 113, 262 }; 263 264 static const struct color_conversion pal_m_csc_svideo = { 265 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 266 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 267 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 268 }; 269 270 static const struct video_levels pal_m_levels_svideo = { 271 .blank = 266, .black = 316, .burst = 133, 272 }; 273 274 static const struct color_conversion pal_n_csc_composite = { 275 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 276 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 277 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 278 }; 279 280 static const struct video_levels pal_n_levels_composite = { 281 .blank = 225, .black = 267, .burst = 118, 282 }; 283 284 static const struct color_conversion pal_n_csc_svideo = { 285 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 286 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 287 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 288 }; 289 290 static const struct video_levels pal_n_levels_svideo = { 291 .blank = 266, .black = 316, .burst = 139, 292 }; 293 294 /* 295 * Component connections 296 */ 297 static const struct color_conversion sdtv_csc_yprpb = { 298 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 299 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200, 300 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200, 301 }; 302 303 static const struct color_conversion hdtv_csc_yprpb = { 304 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145, 305 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200, 306 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200, 307 }; 308 309 static const struct video_levels component_levels = { 310 .blank = 279, .black = 279, .burst = 0, 311 }; 312 313 314 struct tv_mode { 315 const char *name; 316 317 u32 clock; 318 u16 refresh; /* in millihertz (for precision) */ 319 u8 oversample; 320 u8 hsync_end; 321 u16 hblank_start, hblank_end, htotal; 322 bool progressive : 1, trilevel_sync : 1, component_only : 1; 323 u8 vsync_start_f1, vsync_start_f2, vsync_len; 324 bool veq_ena : 1; 325 u8 veq_start_f1, veq_start_f2, veq_len; 326 u8 vi_end_f1, vi_end_f2; 327 u16 nbr_end; 328 bool burst_ena : 1; 329 u8 hburst_start, hburst_len; 330 u8 vburst_start_f1; 331 u16 vburst_end_f1; 332 u8 vburst_start_f2; 333 u16 vburst_end_f2; 334 u8 vburst_start_f3; 335 u16 vburst_end_f3; 336 u8 vburst_start_f4; 337 u16 vburst_end_f4; 338 /* 339 * subcarrier programming 340 */ 341 u16 dda2_size, dda3_size; 342 u8 dda1_inc; 343 u16 dda2_inc, dda3_inc; 344 u32 sc_reset; 345 bool pal_burst : 1; 346 /* 347 * blank/black levels 348 */ 349 const struct video_levels *composite_levels, *svideo_levels; 350 const struct color_conversion *composite_color, *svideo_color; 351 const u32 *filter_table; 352 }; 353 354 355 /* 356 * Sub carrier DDA 357 * 358 * I think this works as follows: 359 * 360 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096 361 * 362 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value 363 * 364 * So, 365 * dda1_ideal = subcarrier/pixel * 4096 366 * dda1_inc = floor (dda1_ideal) 367 * dda2 = dda1_ideal - dda1_inc 368 * 369 * then pick a ratio for dda2 that gives the closest approximation. If 370 * you can't get close enough, you can play with dda3 as well. This 371 * seems likely to happen when dda2 is small as the jumps would be larger 372 * 373 * To invert this, 374 * 375 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size) 376 * 377 * The constants below were all computed using a 107.520MHz clock 378 */ 379 380 /* 381 * Register programming values for TV modes. 382 * 383 * These values account for -1s required. 384 */ 385 static const struct tv_mode tv_modes[] = { 386 { 387 .name = "NTSC-M", 388 .clock = 108000, 389 .refresh = 59940, 390 .oversample = 8, 391 .component_only = false, 392 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 393 394 .hsync_end = 64, .hblank_end = 124, 395 .hblank_start = 836, .htotal = 857, 396 397 .progressive = false, .trilevel_sync = false, 398 399 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 400 .vsync_len = 6, 401 402 .veq_ena = true, .veq_start_f1 = 0, 403 .veq_start_f2 = 1, .veq_len = 18, 404 405 .vi_end_f1 = 20, .vi_end_f2 = 21, 406 .nbr_end = 240, 407 408 .burst_ena = true, 409 .hburst_start = 72, .hburst_len = 34, 410 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 411 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 412 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 413 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 414 415 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 416 .dda1_inc = 135, 417 .dda2_inc = 20800, .dda2_size = 27456, 418 .dda3_inc = 0, .dda3_size = 0, 419 .sc_reset = TV_SC_RESET_EVERY_4, 420 .pal_burst = false, 421 422 .composite_levels = &ntsc_m_levels_composite, 423 .composite_color = &ntsc_m_csc_composite, 424 .svideo_levels = &ntsc_m_levels_svideo, 425 .svideo_color = &ntsc_m_csc_svideo, 426 427 .filter_table = filter_table, 428 }, 429 { 430 .name = "NTSC-443", 431 .clock = 108000, 432 .refresh = 59940, 433 .oversample = 8, 434 .component_only = false, 435 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */ 436 .hsync_end = 64, .hblank_end = 124, 437 .hblank_start = 836, .htotal = 857, 438 439 .progressive = false, .trilevel_sync = false, 440 441 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 442 .vsync_len = 6, 443 444 .veq_ena = true, .veq_start_f1 = 0, 445 .veq_start_f2 = 1, .veq_len = 18, 446 447 .vi_end_f1 = 20, .vi_end_f2 = 21, 448 .nbr_end = 240, 449 450 .burst_ena = true, 451 .hburst_start = 72, .hburst_len = 34, 452 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 453 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 454 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 455 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 456 457 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 458 .dda1_inc = 168, 459 .dda2_inc = 4093, .dda2_size = 27456, 460 .dda3_inc = 310, .dda3_size = 525, 461 .sc_reset = TV_SC_RESET_NEVER, 462 .pal_burst = false, 463 464 .composite_levels = &ntsc_m_levels_composite, 465 .composite_color = &ntsc_m_csc_composite, 466 .svideo_levels = &ntsc_m_levels_svideo, 467 .svideo_color = &ntsc_m_csc_svideo, 468 469 .filter_table = filter_table, 470 }, 471 { 472 .name = "NTSC-J", 473 .clock = 108000, 474 .refresh = 59940, 475 .oversample = 8, 476 .component_only = false, 477 478 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 479 .hsync_end = 64, .hblank_end = 124, 480 .hblank_start = 836, .htotal = 857, 481 482 .progressive = false, .trilevel_sync = false, 483 484 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 485 .vsync_len = 6, 486 487 .veq_ena = true, .veq_start_f1 = 0, 488 .veq_start_f2 = 1, .veq_len = 18, 489 490 .vi_end_f1 = 20, .vi_end_f2 = 21, 491 .nbr_end = 240, 492 493 .burst_ena = true, 494 .hburst_start = 72, .hburst_len = 34, 495 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 496 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 497 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 498 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 499 500 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 501 .dda1_inc = 135, 502 .dda2_inc = 20800, .dda2_size = 27456, 503 .dda3_inc = 0, .dda3_size = 0, 504 .sc_reset = TV_SC_RESET_EVERY_4, 505 .pal_burst = false, 506 507 .composite_levels = &ntsc_j_levels_composite, 508 .composite_color = &ntsc_j_csc_composite, 509 .svideo_levels = &ntsc_j_levels_svideo, 510 .svideo_color = &ntsc_j_csc_svideo, 511 512 .filter_table = filter_table, 513 }, 514 { 515 .name = "PAL-M", 516 .clock = 108000, 517 .refresh = 59940, 518 .oversample = 8, 519 .component_only = false, 520 521 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 522 .hsync_end = 64, .hblank_end = 124, 523 .hblank_start = 836, .htotal = 857, 524 525 .progressive = false, .trilevel_sync = false, 526 527 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 528 .vsync_len = 6, 529 530 .veq_ena = true, .veq_start_f1 = 0, 531 .veq_start_f2 = 1, .veq_len = 18, 532 533 .vi_end_f1 = 20, .vi_end_f2 = 21, 534 .nbr_end = 240, 535 536 .burst_ena = true, 537 .hburst_start = 72, .hburst_len = 34, 538 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 539 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 540 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 541 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 542 543 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 544 .dda1_inc = 135, 545 .dda2_inc = 16704, .dda2_size = 27456, 546 .dda3_inc = 0, .dda3_size = 0, 547 .sc_reset = TV_SC_RESET_EVERY_8, 548 .pal_burst = true, 549 550 .composite_levels = &pal_m_levels_composite, 551 .composite_color = &pal_m_csc_composite, 552 .svideo_levels = &pal_m_levels_svideo, 553 .svideo_color = &pal_m_csc_svideo, 554 555 .filter_table = filter_table, 556 }, 557 { 558 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 559 .name = "PAL-N", 560 .clock = 108000, 561 .refresh = 50000, 562 .oversample = 8, 563 .component_only = false, 564 565 .hsync_end = 64, .hblank_end = 128, 566 .hblank_start = 844, .htotal = 863, 567 568 .progressive = false, .trilevel_sync = false, 569 570 571 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 572 .vsync_len = 6, 573 574 .veq_ena = true, .veq_start_f1 = 0, 575 .veq_start_f2 = 1, .veq_len = 18, 576 577 .vi_end_f1 = 24, .vi_end_f2 = 25, 578 .nbr_end = 286, 579 580 .burst_ena = true, 581 .hburst_start = 73, .hburst_len = 34, 582 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 583 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 584 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 585 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 586 587 588 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 589 .dda1_inc = 135, 590 .dda2_inc = 23578, .dda2_size = 27648, 591 .dda3_inc = 134, .dda3_size = 625, 592 .sc_reset = TV_SC_RESET_EVERY_8, 593 .pal_burst = true, 594 595 .composite_levels = &pal_n_levels_composite, 596 .composite_color = &pal_n_csc_composite, 597 .svideo_levels = &pal_n_levels_svideo, 598 .svideo_color = &pal_n_csc_svideo, 599 600 .filter_table = filter_table, 601 }, 602 { 603 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 604 .name = "PAL", 605 .clock = 108000, 606 .refresh = 50000, 607 .oversample = 8, 608 .component_only = false, 609 610 .hsync_end = 64, .hblank_end = 142, 611 .hblank_start = 844, .htotal = 863, 612 613 .progressive = false, .trilevel_sync = false, 614 615 .vsync_start_f1 = 5, .vsync_start_f2 = 6, 616 .vsync_len = 5, 617 618 .veq_ena = true, .veq_start_f1 = 0, 619 .veq_start_f2 = 1, .veq_len = 15, 620 621 .vi_end_f1 = 24, .vi_end_f2 = 25, 622 .nbr_end = 286, 623 624 .burst_ena = true, 625 .hburst_start = 73, .hburst_len = 32, 626 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 627 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 628 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 629 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 630 631 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 632 .dda1_inc = 168, 633 .dda2_inc = 4122, .dda2_size = 27648, 634 .dda3_inc = 67, .dda3_size = 625, 635 .sc_reset = TV_SC_RESET_EVERY_8, 636 .pal_burst = true, 637 638 .composite_levels = &pal_levels_composite, 639 .composite_color = &pal_csc_composite, 640 .svideo_levels = &pal_levels_svideo, 641 .svideo_color = &pal_csc_svideo, 642 643 .filter_table = filter_table, 644 }, 645 { 646 .name = "480p", 647 .clock = 108000, 648 .refresh = 59940, 649 .oversample = 4, 650 .component_only = true, 651 652 .hsync_end = 64, .hblank_end = 122, 653 .hblank_start = 842, .htotal = 857, 654 655 .progressive = true, .trilevel_sync = false, 656 657 .vsync_start_f1 = 12, .vsync_start_f2 = 12, 658 .vsync_len = 12, 659 660 .veq_ena = false, 661 662 .vi_end_f1 = 44, .vi_end_f2 = 44, 663 .nbr_end = 479, 664 665 .burst_ena = false, 666 667 .filter_table = filter_table, 668 }, 669 { 670 .name = "576p", 671 .clock = 108000, 672 .refresh = 50000, 673 .oversample = 4, 674 .component_only = true, 675 676 .hsync_end = 64, .hblank_end = 139, 677 .hblank_start = 859, .htotal = 863, 678 679 .progressive = true, .trilevel_sync = false, 680 681 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 682 .vsync_len = 10, 683 684 .veq_ena = false, 685 686 .vi_end_f1 = 48, .vi_end_f2 = 48, 687 .nbr_end = 575, 688 689 .burst_ena = false, 690 691 .filter_table = filter_table, 692 }, 693 { 694 .name = "720p@60Hz", 695 .clock = 148500, 696 .refresh = 60000, 697 .oversample = 2, 698 .component_only = true, 699 700 .hsync_end = 80, .hblank_end = 300, 701 .hblank_start = 1580, .htotal = 1649, 702 703 .progressive = true, .trilevel_sync = true, 704 705 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 706 .vsync_len = 10, 707 708 .veq_ena = false, 709 710 .vi_end_f1 = 29, .vi_end_f2 = 29, 711 .nbr_end = 719, 712 713 .burst_ena = false, 714 715 .filter_table = filter_table, 716 }, 717 { 718 .name = "720p@50Hz", 719 .clock = 148500, 720 .refresh = 50000, 721 .oversample = 2, 722 .component_only = true, 723 724 .hsync_end = 80, .hblank_end = 300, 725 .hblank_start = 1580, .htotal = 1979, 726 727 .progressive = true, .trilevel_sync = true, 728 729 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 730 .vsync_len = 10, 731 732 .veq_ena = false, 733 734 .vi_end_f1 = 29, .vi_end_f2 = 29, 735 .nbr_end = 719, 736 737 .burst_ena = false, 738 739 .filter_table = filter_table, 740 }, 741 { 742 .name = "1080i@50Hz", 743 .clock = 148500, 744 .refresh = 50000, 745 .oversample = 2, 746 .component_only = true, 747 748 .hsync_end = 88, .hblank_end = 235, 749 .hblank_start = 2155, .htotal = 2639, 750 751 .progressive = false, .trilevel_sync = true, 752 753 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 754 .vsync_len = 10, 755 756 .veq_ena = true, .veq_start_f1 = 4, 757 .veq_start_f2 = 4, .veq_len = 10, 758 759 760 .vi_end_f1 = 21, .vi_end_f2 = 22, 761 .nbr_end = 539, 762 763 .burst_ena = false, 764 765 .filter_table = filter_table, 766 }, 767 { 768 .name = "1080i@60Hz", 769 .clock = 148500, 770 .refresh = 60000, 771 .oversample = 2, 772 .component_only = true, 773 774 .hsync_end = 88, .hblank_end = 235, 775 .hblank_start = 2155, .htotal = 2199, 776 777 .progressive = false, .trilevel_sync = true, 778 779 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 780 .vsync_len = 10, 781 782 .veq_ena = true, .veq_start_f1 = 4, 783 .veq_start_f2 = 4, .veq_len = 10, 784 785 786 .vi_end_f1 = 21, .vi_end_f2 = 22, 787 .nbr_end = 539, 788 789 .burst_ena = false, 790 791 .filter_table = filter_table, 792 }, 793 794 { 795 .name = "1080p@30Hz", 796 .clock = 148500, 797 .refresh = 30000, 798 .oversample = 2, 799 .component_only = true, 800 801 .hsync_end = 88, .hblank_end = 235, 802 .hblank_start = 2155, .htotal = 2199, 803 804 .progressive = true, .trilevel_sync = true, 805 806 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 807 .vsync_len = 10, 808 809 .veq_ena = false, .veq_start_f1 = 0, 810 .veq_start_f2 = 0, .veq_len = 0, 811 812 .vi_end_f1 = 44, .vi_end_f2 = 44, 813 .nbr_end = 1079, 814 815 .burst_ena = false, 816 817 .filter_table = filter_table, 818 }, 819 820 { 821 .name = "1080p@50Hz", 822 .clock = 148500, 823 .refresh = 50000, 824 .oversample = 1, 825 .component_only = true, 826 827 .hsync_end = 88, .hblank_end = 235, 828 .hblank_start = 2155, .htotal = 2639, 829 830 .progressive = true, .trilevel_sync = true, 831 832 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 833 .vsync_len = 10, 834 835 .veq_ena = false, .veq_start_f1 = 0, 836 .veq_start_f2 = 0, .veq_len = 0, 837 838 .vi_end_f1 = 44, .vi_end_f2 = 44, 839 .nbr_end = 1079, 840 841 .burst_ena = false, 842 843 .filter_table = filter_table, 844 }, 845 846 { 847 .name = "1080p@60Hz", 848 .clock = 148500, 849 .refresh = 60000, 850 .oversample = 1, 851 .component_only = true, 852 853 .hsync_end = 88, .hblank_end = 235, 854 .hblank_start = 2155, .htotal = 2199, 855 856 .progressive = true, .trilevel_sync = true, 857 858 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 859 .vsync_len = 10, 860 861 .veq_ena = false, .veq_start_f1 = 0, 862 .veq_start_f2 = 0, .veq_len = 0, 863 864 .vi_end_f1 = 44, .vi_end_f2 = 44, 865 .nbr_end = 1079, 866 867 .burst_ena = false, 868 869 .filter_table = filter_table, 870 }, 871 }; 872 873 struct intel_tv_connector_state { 874 struct drm_connector_state base; 875 876 /* 877 * May need to override the user margins for 878 * gen3 >1024 wide source vertical centering. 879 */ 880 struct { 881 u16 top, bottom; 882 } margins; 883 884 bool bypass_vfilter; 885 }; 886 887 #define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base) 888 889 static struct drm_connector_state * intel_tv_connector_duplicate_state(struct drm_connector * connector)890 intel_tv_connector_duplicate_state(struct drm_connector *connector) 891 { 892 struct intel_tv_connector_state *state; 893 894 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 895 if (!state) 896 return NULL; 897 898 __drm_atomic_helper_connector_duplicate_state(connector, &state->base); 899 return &state->base; 900 } 901 enc_to_tv(struct intel_encoder * encoder)902 static struct intel_tv *enc_to_tv(struct intel_encoder *encoder) 903 { 904 return container_of(encoder, struct intel_tv, base); 905 } 906 intel_attached_tv(struct intel_connector * connector)907 static struct intel_tv *intel_attached_tv(struct intel_connector *connector) 908 { 909 return enc_to_tv(intel_attached_encoder(connector)); 910 } 911 912 static bool intel_tv_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)913 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) 914 { 915 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 916 u32 tmp = intel_de_read(dev_priv, TV_CTL); 917 918 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT; 919 920 return tmp & TV_ENC_ENABLE; 921 } 922 923 static void intel_enable_tv(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)924 intel_enable_tv(struct intel_atomic_state *state, 925 struct intel_encoder *encoder, 926 const struct intel_crtc_state *pipe_config, 927 const struct drm_connector_state *conn_state) 928 { 929 struct drm_device *dev = encoder->base.dev; 930 struct drm_i915_private *dev_priv = to_i915(dev); 931 932 /* Prevents vblank waits from timing out in intel_tv_detect_type() */ 933 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc)); 934 935 intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE); 936 } 937 938 static void intel_disable_tv(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)939 intel_disable_tv(struct intel_atomic_state *state, 940 struct intel_encoder *encoder, 941 const struct intel_crtc_state *old_crtc_state, 942 const struct drm_connector_state *old_conn_state) 943 { 944 struct drm_device *dev = encoder->base.dev; 945 struct drm_i915_private *dev_priv = to_i915(dev); 946 947 intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0); 948 } 949 intel_tv_mode_find(const struct drm_connector_state * conn_state)950 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state) 951 { 952 int format = conn_state->tv.legacy_mode; 953 954 return &tv_modes[format]; 955 } 956 957 static enum drm_mode_status intel_tv_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)958 intel_tv_mode_valid(struct drm_connector *connector, 959 struct drm_display_mode *mode) 960 { 961 struct drm_i915_private *i915 = to_i915(connector->dev); 962 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 963 int max_dotclk = i915->max_dotclk_freq; 964 enum drm_mode_status status; 965 966 status = intel_cpu_transcoder_mode_valid(i915, mode); 967 if (status != MODE_OK) 968 return status; 969 970 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 971 return MODE_NO_DBLESCAN; 972 973 if (mode->clock > max_dotclk) 974 return MODE_CLOCK_HIGH; 975 976 /* Ensure TV refresh is close to desired refresh */ 977 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000) 978 return MODE_CLOCK_RANGE; 979 980 return MODE_OK; 981 } 982 983 static int intel_tv_mode_vdisplay(const struct tv_mode * tv_mode)984 intel_tv_mode_vdisplay(const struct tv_mode *tv_mode) 985 { 986 if (tv_mode->progressive) 987 return tv_mode->nbr_end + 1; 988 else 989 return 2 * (tv_mode->nbr_end + 1); 990 } 991 992 static void intel_tv_mode_to_mode(struct drm_display_mode * mode,const struct tv_mode * tv_mode,int clock)993 intel_tv_mode_to_mode(struct drm_display_mode *mode, 994 const struct tv_mode *tv_mode, 995 int clock) 996 { 997 mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive); 998 999 /* 1000 * tv_mode horizontal timings: 1001 * 1002 * hsync_end 1003 * | hblank_end 1004 * | | hblank_start 1005 * | | | htotal 1006 * | _______ | 1007 * ____/ \___ 1008 * \__/ \ 1009 */ 1010 mode->hdisplay = 1011 tv_mode->hblank_start - tv_mode->hblank_end; 1012 mode->hsync_start = mode->hdisplay + 1013 tv_mode->htotal - tv_mode->hblank_start; 1014 mode->hsync_end = mode->hsync_start + 1015 tv_mode->hsync_end; 1016 mode->htotal = tv_mode->htotal + 1; 1017 1018 /* 1019 * tv_mode vertical timings: 1020 * 1021 * vsync_start 1022 * | vsync_end 1023 * | | vi_end nbr_end 1024 * | | | | 1025 * | | _______ 1026 * \__ ____/ \ 1027 * \__/ 1028 */ 1029 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode); 1030 if (tv_mode->progressive) { 1031 mode->vsync_start = mode->vdisplay + 1032 tv_mode->vsync_start_f1 + 1; 1033 mode->vsync_end = mode->vsync_start + 1034 tv_mode->vsync_len; 1035 mode->vtotal = mode->vdisplay + 1036 tv_mode->vi_end_f1 + 1; 1037 } else { 1038 mode->vsync_start = mode->vdisplay + 1039 tv_mode->vsync_start_f1 + 1 + 1040 tv_mode->vsync_start_f2 + 1; 1041 mode->vsync_end = mode->vsync_start + 1042 2 * tv_mode->vsync_len; 1043 mode->vtotal = mode->vdisplay + 1044 tv_mode->vi_end_f1 + 1 + 1045 tv_mode->vi_end_f2 + 1; 1046 } 1047 1048 /* TV has it's own notion of sync and other mode flags, so clear them. */ 1049 mode->flags = 0; 1050 1051 snprintf(mode->name, sizeof(mode->name), 1052 "%dx%d%c (%s)", 1053 mode->hdisplay, mode->vdisplay, 1054 tv_mode->progressive ? 'p' : 'i', 1055 tv_mode->name); 1056 } 1057 intel_tv_scale_mode_horiz(struct drm_display_mode * mode,int hdisplay,int left_margin,int right_margin)1058 static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode, 1059 int hdisplay, int left_margin, 1060 int right_margin) 1061 { 1062 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin; 1063 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin; 1064 int new_htotal = mode->htotal * hdisplay / 1065 (mode->hdisplay - left_margin - right_margin); 1066 1067 mode->clock = mode->clock * new_htotal / mode->htotal; 1068 1069 mode->hdisplay = hdisplay; 1070 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal; 1071 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal; 1072 mode->htotal = new_htotal; 1073 } 1074 intel_tv_scale_mode_vert(struct drm_display_mode * mode,int vdisplay,int top_margin,int bottom_margin)1075 static void intel_tv_scale_mode_vert(struct drm_display_mode *mode, 1076 int vdisplay, int top_margin, 1077 int bottom_margin) 1078 { 1079 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin; 1080 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin; 1081 int new_vtotal = mode->vtotal * vdisplay / 1082 (mode->vdisplay - top_margin - bottom_margin); 1083 1084 mode->clock = mode->clock * new_vtotal / mode->vtotal; 1085 1086 mode->vdisplay = vdisplay; 1087 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal; 1088 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal; 1089 mode->vtotal = new_vtotal; 1090 } 1091 1092 static void intel_tv_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1093 intel_tv_get_config(struct intel_encoder *encoder, 1094 struct intel_crtc_state *pipe_config) 1095 { 1096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1097 struct drm_display_mode *adjusted_mode = 1098 &pipe_config->hw.adjusted_mode; 1099 struct drm_display_mode mode = {}; 1100 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp; 1101 struct tv_mode tv_mode = {}; 1102 int hdisplay = adjusted_mode->crtc_hdisplay; 1103 int vdisplay = adjusted_mode->crtc_vdisplay; 1104 int xsize, ysize, xpos, ypos; 1105 1106 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); 1107 1108 tv_ctl = intel_de_read(dev_priv, TV_CTL); 1109 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); 1110 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); 1111 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); 1112 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); 1113 1114 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT; 1115 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT; 1116 1117 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT; 1118 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT; 1119 1120 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT; 1121 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT; 1122 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT; 1123 1124 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT; 1125 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT; 1126 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT; 1127 1128 tv_mode.clock = pipe_config->port_clock; 1129 1130 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE; 1131 1132 switch (tv_ctl & TV_OVERSAMPLE_MASK) { 1133 case TV_OVERSAMPLE_8X: 1134 tv_mode.oversample = 8; 1135 break; 1136 case TV_OVERSAMPLE_4X: 1137 tv_mode.oversample = 4; 1138 break; 1139 case TV_OVERSAMPLE_2X: 1140 tv_mode.oversample = 2; 1141 break; 1142 default: 1143 tv_mode.oversample = 1; 1144 break; 1145 } 1146 1147 tmp = intel_de_read(dev_priv, TV_WIN_POS); 1148 xpos = tmp >> 16; 1149 ypos = tmp & 0xffff; 1150 1151 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); 1152 xsize = tmp >> 16; 1153 ysize = tmp & 0xffff; 1154 1155 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); 1156 1157 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1158 DRM_MODE_ARG(&mode)); 1159 1160 intel_tv_scale_mode_horiz(&mode, hdisplay, 1161 xpos, mode.hdisplay - xsize - xpos); 1162 intel_tv_scale_mode_vert(&mode, vdisplay, 1163 ypos, mode.vdisplay - ysize - ypos); 1164 1165 adjusted_mode->crtc_clock = mode.clock; 1166 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 1167 adjusted_mode->crtc_clock /= 2; 1168 1169 /* pixel counter doesn't work on i965gm TV output */ 1170 if (IS_I965GM(dev_priv)) 1171 pipe_config->mode_flags |= 1172 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1173 } 1174 intel_tv_source_too_wide(struct drm_i915_private * dev_priv,int hdisplay)1175 static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv, 1176 int hdisplay) 1177 { 1178 return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024; 1179 } 1180 intel_tv_vert_scaling(const struct drm_display_mode * tv_mode,const struct drm_connector_state * conn_state,int vdisplay)1181 static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode, 1182 const struct drm_connector_state *conn_state, 1183 int vdisplay) 1184 { 1185 return tv_mode->crtc_vdisplay - 1186 conn_state->tv.margins.top - 1187 conn_state->tv.margins.bottom != 1188 vdisplay; 1189 } 1190 1191 static int intel_tv_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)1192 intel_tv_compute_config(struct intel_encoder *encoder, 1193 struct intel_crtc_state *pipe_config, 1194 struct drm_connector_state *conn_state) 1195 { 1196 struct intel_atomic_state *state = 1197 to_intel_atomic_state(pipe_config->uapi.state); 1198 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1199 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1200 struct intel_tv_connector_state *tv_conn_state = 1201 to_intel_tv_connector_state(conn_state); 1202 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1203 struct drm_display_mode *adjusted_mode = 1204 &pipe_config->hw.adjusted_mode; 1205 int hdisplay = adjusted_mode->crtc_hdisplay; 1206 int vdisplay = adjusted_mode->crtc_vdisplay; 1207 int ret; 1208 1209 if (!tv_mode) 1210 return -EINVAL; 1211 1212 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1213 return -EINVAL; 1214 1215 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1216 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1217 1218 drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n"); 1219 pipe_config->pipe_bpp = 8*3; 1220 1221 pipe_config->port_clock = tv_mode->clock; 1222 1223 ret = intel_dpll_crtc_compute_clock(state, crtc); 1224 if (ret) 1225 return ret; 1226 1227 pipe_config->clock_set = true; 1228 1229 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); 1230 drm_mode_set_crtcinfo(adjusted_mode, 0); 1231 1232 if (intel_tv_source_too_wide(dev_priv, hdisplay) || 1233 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) { 1234 int extra, top, bottom; 1235 1236 extra = adjusted_mode->crtc_vdisplay - vdisplay; 1237 1238 if (extra < 0) { 1239 drm_dbg_kms(&dev_priv->drm, 1240 "No vertical scaling for >1024 pixel wide modes\n"); 1241 return -EINVAL; 1242 } 1243 1244 /* Need to turn off the vertical filter and center the image */ 1245 1246 /* Attempt to maintain the relative sizes of the margins */ 1247 top = conn_state->tv.margins.top; 1248 bottom = conn_state->tv.margins.bottom; 1249 1250 if (top + bottom) 1251 top = extra * top / (top + bottom); 1252 else 1253 top = extra / 2; 1254 bottom = extra - top; 1255 1256 tv_conn_state->margins.top = top; 1257 tv_conn_state->margins.bottom = bottom; 1258 1259 tv_conn_state->bypass_vfilter = true; 1260 1261 if (!tv_mode->progressive) { 1262 adjusted_mode->clock /= 2; 1263 adjusted_mode->crtc_clock /= 2; 1264 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 1265 } 1266 } else { 1267 tv_conn_state->margins.top = conn_state->tv.margins.top; 1268 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom; 1269 1270 tv_conn_state->bypass_vfilter = false; 1271 } 1272 1273 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1274 DRM_MODE_ARG(adjusted_mode)); 1275 1276 /* 1277 * The pipe scanline counter behaviour looks as follows when 1278 * using the TV encoder: 1279 * 1280 * time -> 1281 * 1282 * dsl=vtotal-1 | | 1283 * || || 1284 * ___| | ___| | 1285 * / | / | 1286 * / | / | 1287 * dsl=0 ___/ |_____/ | 1288 * | | | | | | 1289 * ^ ^ ^ ^ ^ 1290 * | | | | pipe vblank/first part of tv vblank 1291 * | | | bottom margin 1292 * | | active 1293 * | top margin 1294 * remainder of tv vblank 1295 * 1296 * When the TV encoder is used the pipe wants to run faster 1297 * than expected rate. During the active portion the TV 1298 * encoder stalls the pipe every few lines to keep it in 1299 * check. When the TV encoder reaches the bottom margin the 1300 * pipe simply stops. Once we reach the TV vblank the pipe is 1301 * no longer stalled and it runs at the max rate (apparently 1302 * oversample clock on gen3, cdclk on gen4). Once the pipe 1303 * reaches the pipe vtotal the pipe stops for the remainder 1304 * of the TV vblank/top margin. The pipe starts up again when 1305 * the TV encoder exits the top margin. 1306 * 1307 * To avoid huge hassles for vblank timestamping we scale 1308 * the pipe timings as if the pipe always runs at the average 1309 * rate it maintains during the active period. This also 1310 * gives us a reasonable guesstimate as to the pixel rate. 1311 * Due to the variation in the actual pipe speed the scanline 1312 * counter will give us slightly erroneous results during the 1313 * TV vblank/margins. But since vtotal was selected such that 1314 * it matches the average rate of the pipe during the active 1315 * portion the error shouldn't cause any serious grief to 1316 * vblank timestamps. 1317 * 1318 * For posterity here is the empirically derived formula 1319 * that gives us the maximum length of the pipe vblank 1320 * we can use without causing display corruption. Following 1321 * this would allow us to have a ticking scanline counter 1322 * everywhere except during the bottom margin (there the 1323 * pipe always stops). Ie. this would eliminate the second 1324 * flat portion of the above graph. However this would also 1325 * complicate vblank timestamping as the pipe vtotal would 1326 * no longer match the average rate the pipe runs at during 1327 * the active portion. Hence following this formula seems 1328 * more trouble that it's worth. 1329 * 1330 * if (GRAPHICS_VER(dev_priv) == 4) { 1331 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); 1332 * den = tv_mode->clock; 1333 * } else { 1334 * num = tv_mode->oversample >> !tv_mode->progressive; 1335 * den = 1; 1336 * } 1337 * max_pipe_vblank_len ~= 1338 * (num * tv_htotal * (tv_vblank_len + top_margin)) / 1339 * (den * pipe_htotal); 1340 */ 1341 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay, 1342 conn_state->tv.margins.left, 1343 conn_state->tv.margins.right); 1344 intel_tv_scale_mode_vert(adjusted_mode, vdisplay, 1345 tv_conn_state->margins.top, 1346 tv_conn_state->margins.bottom); 1347 drm_mode_set_crtcinfo(adjusted_mode, 0); 1348 adjusted_mode->name[0] = '\0'; 1349 1350 /* pixel counter doesn't work on i965gm TV output */ 1351 if (IS_I965GM(dev_priv)) 1352 pipe_config->mode_flags |= 1353 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1354 1355 return 0; 1356 } 1357 1358 static void set_tv_mode_timings(struct drm_i915_private * dev_priv,const struct tv_mode * tv_mode,bool burst_ena)1359 set_tv_mode_timings(struct drm_i915_private *dev_priv, 1360 const struct tv_mode *tv_mode, 1361 bool burst_ena) 1362 { 1363 u32 hctl1, hctl2, hctl3; 1364 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; 1365 1366 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) | 1367 (tv_mode->htotal << TV_HTOTAL_SHIFT); 1368 1369 hctl2 = (tv_mode->hburst_start << 16) | 1370 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT); 1371 1372 if (burst_ena) 1373 hctl2 |= TV_BURST_ENA; 1374 1375 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) | 1376 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT); 1377 1378 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) | 1379 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) | 1380 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT); 1381 1382 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) | 1383 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) | 1384 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT); 1385 1386 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) | 1387 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) | 1388 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT); 1389 1390 if (tv_mode->veq_ena) 1391 vctl3 |= TV_EQUAL_ENA; 1392 1393 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) | 1394 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT); 1395 1396 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) | 1397 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT); 1398 1399 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) | 1400 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT); 1401 1402 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) | 1403 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT); 1404 1405 intel_de_write(dev_priv, TV_H_CTL_1, hctl1); 1406 intel_de_write(dev_priv, TV_H_CTL_2, hctl2); 1407 intel_de_write(dev_priv, TV_H_CTL_3, hctl3); 1408 intel_de_write(dev_priv, TV_V_CTL_1, vctl1); 1409 intel_de_write(dev_priv, TV_V_CTL_2, vctl2); 1410 intel_de_write(dev_priv, TV_V_CTL_3, vctl3); 1411 intel_de_write(dev_priv, TV_V_CTL_4, vctl4); 1412 intel_de_write(dev_priv, TV_V_CTL_5, vctl5); 1413 intel_de_write(dev_priv, TV_V_CTL_6, vctl6); 1414 intel_de_write(dev_priv, TV_V_CTL_7, vctl7); 1415 } 1416 set_color_conversion(struct drm_i915_private * dev_priv,const struct color_conversion * color_conversion)1417 static void set_color_conversion(struct drm_i915_private *dev_priv, 1418 const struct color_conversion *color_conversion) 1419 { 1420 if (!color_conversion) 1421 return; 1422 1423 intel_de_write(dev_priv, TV_CSC_Y, 1424 (color_conversion->ry << 16) | color_conversion->gy); 1425 intel_de_write(dev_priv, TV_CSC_Y2, 1426 (color_conversion->by << 16) | color_conversion->ay); 1427 intel_de_write(dev_priv, TV_CSC_U, 1428 (color_conversion->ru << 16) | color_conversion->gu); 1429 intel_de_write(dev_priv, TV_CSC_U2, 1430 (color_conversion->bu << 16) | color_conversion->au); 1431 intel_de_write(dev_priv, TV_CSC_V, 1432 (color_conversion->rv << 16) | color_conversion->gv); 1433 intel_de_write(dev_priv, TV_CSC_V2, 1434 (color_conversion->bv << 16) | color_conversion->av); 1435 } 1436 intel_tv_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)1437 static void intel_tv_pre_enable(struct intel_atomic_state *state, 1438 struct intel_encoder *encoder, 1439 const struct intel_crtc_state *pipe_config, 1440 const struct drm_connector_state *conn_state) 1441 { 1442 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1443 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1444 struct intel_tv *intel_tv = enc_to_tv(encoder); 1445 const struct intel_tv_connector_state *tv_conn_state = 1446 to_intel_tv_connector_state(conn_state); 1447 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1448 u32 tv_ctl, tv_filter_ctl; 1449 u32 scctl1, scctl2, scctl3; 1450 int i, j; 1451 const struct video_levels *video_levels; 1452 const struct color_conversion *color_conversion; 1453 bool burst_ena; 1454 int xpos, ypos; 1455 unsigned int xsize, ysize; 1456 1457 if (!tv_mode) 1458 return; /* can't happen (mode_prepare prevents this) */ 1459 1460 tv_ctl = intel_de_read(dev_priv, TV_CTL); 1461 tv_ctl &= TV_CTL_SAVE; 1462 1463 switch (intel_tv->type) { 1464 default: 1465 case DRM_MODE_CONNECTOR_Unknown: 1466 case DRM_MODE_CONNECTOR_Composite: 1467 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE; 1468 video_levels = tv_mode->composite_levels; 1469 color_conversion = tv_mode->composite_color; 1470 burst_ena = tv_mode->burst_ena; 1471 break; 1472 case DRM_MODE_CONNECTOR_Component: 1473 tv_ctl |= TV_ENC_OUTPUT_COMPONENT; 1474 video_levels = &component_levels; 1475 if (tv_mode->burst_ena) 1476 color_conversion = &sdtv_csc_yprpb; 1477 else 1478 color_conversion = &hdtv_csc_yprpb; 1479 burst_ena = false; 1480 break; 1481 case DRM_MODE_CONNECTOR_SVIDEO: 1482 tv_ctl |= TV_ENC_OUTPUT_SVIDEO; 1483 video_levels = tv_mode->svideo_levels; 1484 color_conversion = tv_mode->svideo_color; 1485 burst_ena = tv_mode->burst_ena; 1486 break; 1487 } 1488 1489 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe); 1490 1491 switch (tv_mode->oversample) { 1492 case 8: 1493 tv_ctl |= TV_OVERSAMPLE_8X; 1494 break; 1495 case 4: 1496 tv_ctl |= TV_OVERSAMPLE_4X; 1497 break; 1498 case 2: 1499 tv_ctl |= TV_OVERSAMPLE_2X; 1500 break; 1501 default: 1502 tv_ctl |= TV_OVERSAMPLE_NONE; 1503 break; 1504 } 1505 1506 if (tv_mode->progressive) 1507 tv_ctl |= TV_PROGRESSIVE; 1508 if (tv_mode->trilevel_sync) 1509 tv_ctl |= TV_TRILEVEL_SYNC; 1510 if (tv_mode->pal_burst) 1511 tv_ctl |= TV_PAL_BURST; 1512 1513 scctl1 = 0; 1514 if (tv_mode->dda1_inc) 1515 scctl1 |= TV_SC_DDA1_EN; 1516 if (tv_mode->dda2_inc) 1517 scctl1 |= TV_SC_DDA2_EN; 1518 if (tv_mode->dda3_inc) 1519 scctl1 |= TV_SC_DDA3_EN; 1520 scctl1 |= tv_mode->sc_reset; 1521 if (video_levels) 1522 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT; 1523 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT; 1524 1525 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT | 1526 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT; 1527 1528 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT | 1529 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT; 1530 1531 /* Enable two fixes for the chips that need them. */ 1532 if (IS_I915GM(dev_priv)) 1533 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; 1534 1535 set_tv_mode_timings(dev_priv, tv_mode, burst_ena); 1536 1537 intel_de_write(dev_priv, TV_SC_CTL_1, scctl1); 1538 intel_de_write(dev_priv, TV_SC_CTL_2, scctl2); 1539 intel_de_write(dev_priv, TV_SC_CTL_3, scctl3); 1540 1541 set_color_conversion(dev_priv, color_conversion); 1542 1543 if (DISPLAY_VER(dev_priv) >= 4) 1544 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000); 1545 else 1546 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000); 1547 1548 if (video_levels) 1549 intel_de_write(dev_priv, TV_CLR_LEVEL, 1550 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); 1551 1552 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder); 1553 1554 /* Filter ctl must be set before TV_WIN_SIZE */ 1555 tv_filter_ctl = TV_AUTO_SCALE; 1556 if (tv_conn_state->bypass_vfilter) 1557 tv_filter_ctl |= TV_V_FILTER_BYPASS; 1558 intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl); 1559 1560 xsize = tv_mode->hblank_start - tv_mode->hblank_end; 1561 ysize = intel_tv_mode_vdisplay(tv_mode); 1562 1563 xpos = conn_state->tv.margins.left; 1564 ypos = tv_conn_state->margins.top; 1565 xsize -= (conn_state->tv.margins.left + 1566 conn_state->tv.margins.right); 1567 ysize -= (tv_conn_state->margins.top + 1568 tv_conn_state->margins.bottom); 1569 intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos); 1570 intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize); 1571 1572 j = 0; 1573 for (i = 0; i < 60; i++) 1574 intel_de_write(dev_priv, TV_H_LUMA(i), 1575 tv_mode->filter_table[j++]); 1576 for (i = 0; i < 60; i++) 1577 intel_de_write(dev_priv, TV_H_CHROMA(i), 1578 tv_mode->filter_table[j++]); 1579 for (i = 0; i < 43; i++) 1580 intel_de_write(dev_priv, TV_V_LUMA(i), 1581 tv_mode->filter_table[j++]); 1582 for (i = 0; i < 43; i++) 1583 intel_de_write(dev_priv, TV_V_CHROMA(i), 1584 tv_mode->filter_table[j++]); 1585 intel_de_write(dev_priv, TV_DAC, 1586 intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE); 1587 intel_de_write(dev_priv, TV_CTL, tv_ctl); 1588 } 1589 1590 static int intel_tv_detect_type(struct intel_tv * intel_tv,struct drm_connector * connector)1591 intel_tv_detect_type(struct intel_tv *intel_tv, 1592 struct drm_connector *connector) 1593 { 1594 struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc); 1595 struct drm_device *dev = connector->dev; 1596 struct drm_i915_private *dev_priv = to_i915(dev); 1597 u32 tv_ctl, save_tv_ctl; 1598 u32 tv_dac, save_tv_dac; 1599 int type; 1600 1601 /* Disable TV interrupts around load detect or we'll recurse */ 1602 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1603 spin_lock_irq(&dev_priv->irq_lock); 1604 i915_disable_pipestat(dev_priv, 0, 1605 PIPE_HOTPLUG_INTERRUPT_STATUS | 1606 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1607 spin_unlock_irq(&dev_priv->irq_lock); 1608 } 1609 1610 save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC); 1611 save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL); 1612 1613 /* Poll for TV detection */ 1614 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK); 1615 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT; 1616 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe); 1617 1618 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK); 1619 tv_dac |= (TVDAC_STATE_CHG_EN | 1620 TVDAC_A_SENSE_CTL | 1621 TVDAC_B_SENSE_CTL | 1622 TVDAC_C_SENSE_CTL | 1623 DAC_CTL_OVERRIDE | 1624 DAC_A_0_7_V | 1625 DAC_B_0_7_V | 1626 DAC_C_0_7_V); 1627 1628 1629 /* 1630 * The TV sense state should be cleared to zero on cantiga platform. Otherwise 1631 * the TV is misdetected. This is hardware requirement. 1632 */ 1633 if (IS_GM45(dev_priv)) 1634 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | 1635 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); 1636 1637 intel_de_write(dev_priv, TV_CTL, tv_ctl); 1638 intel_de_write(dev_priv, TV_DAC, tv_dac); 1639 intel_de_posting_read(dev_priv, TV_DAC); 1640 1641 intel_crtc_wait_for_next_vblank(crtc); 1642 1643 type = -1; 1644 tv_dac = intel_de_read(dev_priv, TV_DAC); 1645 drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac); 1646 /* 1647 * A B C 1648 * 0 1 1 Composite 1649 * 1 0 X svideo 1650 * 0 0 0 Component 1651 */ 1652 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { 1653 drm_dbg_kms(&dev_priv->drm, 1654 "Detected Composite TV connection\n"); 1655 type = DRM_MODE_CONNECTOR_Composite; 1656 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { 1657 drm_dbg_kms(&dev_priv->drm, 1658 "Detected S-Video TV connection\n"); 1659 type = DRM_MODE_CONNECTOR_SVIDEO; 1660 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { 1661 drm_dbg_kms(&dev_priv->drm, 1662 "Detected Component TV connection\n"); 1663 type = DRM_MODE_CONNECTOR_Component; 1664 } else { 1665 drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n"); 1666 type = -1; 1667 } 1668 1669 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1670 intel_de_write(dev_priv, TV_CTL, save_tv_ctl); 1671 intel_de_posting_read(dev_priv, TV_CTL); 1672 1673 /* For unknown reasons the hw barfs if we don't do this vblank wait. */ 1674 intel_crtc_wait_for_next_vblank(crtc); 1675 1676 /* Restore interrupt config */ 1677 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1678 spin_lock_irq(&dev_priv->irq_lock); 1679 i915_enable_pipestat(dev_priv, 0, 1680 PIPE_HOTPLUG_INTERRUPT_STATUS | 1681 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1682 spin_unlock_irq(&dev_priv->irq_lock); 1683 } 1684 1685 return type; 1686 } 1687 1688 /* 1689 * Here we set accurate tv format according to connector type 1690 * i.e Component TV should not be assigned by NTSC or PAL 1691 */ intel_tv_find_better_format(struct drm_connector * connector)1692 static void intel_tv_find_better_format(struct drm_connector *connector) 1693 { 1694 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1695 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1696 int i; 1697 1698 /* Component supports everything so we can keep the current mode */ 1699 if (intel_tv->type == DRM_MODE_CONNECTOR_Component) 1700 return; 1701 1702 /* If the current mode is fine don't change it */ 1703 if (!tv_mode->component_only) 1704 return; 1705 1706 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1707 tv_mode = &tv_modes[i]; 1708 1709 if (!tv_mode->component_only) 1710 break; 1711 } 1712 1713 connector->state->tv.legacy_mode = i; 1714 } 1715 1716 static int intel_tv_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)1717 intel_tv_detect(struct drm_connector *connector, 1718 struct drm_modeset_acquire_ctx *ctx, 1719 bool force) 1720 { 1721 struct drm_i915_private *i915 = to_i915(connector->dev); 1722 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1723 enum drm_connector_status status; 1724 int type; 1725 1726 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n", 1727 connector->base.id, connector->name, force); 1728 1729 if (!INTEL_DISPLAY_ENABLED(i915)) 1730 return connector_status_disconnected; 1731 1732 if (force) { 1733 struct drm_atomic_state *state; 1734 1735 state = intel_load_detect_get_pipe(connector, ctx); 1736 if (IS_ERR(state)) 1737 return PTR_ERR(state); 1738 1739 if (state) { 1740 type = intel_tv_detect_type(intel_tv, connector); 1741 intel_load_detect_release_pipe(connector, state, ctx); 1742 status = type < 0 ? 1743 connector_status_disconnected : 1744 connector_status_connected; 1745 } else { 1746 status = connector_status_unknown; 1747 } 1748 1749 if (status == connector_status_connected) { 1750 intel_tv->type = type; 1751 intel_tv_find_better_format(connector); 1752 } 1753 1754 return status; 1755 } else 1756 return connector->status; 1757 } 1758 1759 static const struct input_res { 1760 u16 w, h; 1761 } input_res_table[] = { 1762 { 640, 480 }, 1763 { 800, 600 }, 1764 { 1024, 768 }, 1765 { 1280, 1024 }, 1766 { 848, 480 }, 1767 { 1280, 720 }, 1768 { 1920, 1080 }, 1769 }; 1770 1771 /* Choose preferred mode according to line number of TV format */ 1772 static bool intel_tv_is_preferred_mode(const struct drm_display_mode * mode,const struct tv_mode * tv_mode)1773 intel_tv_is_preferred_mode(const struct drm_display_mode *mode, 1774 const struct tv_mode *tv_mode) 1775 { 1776 int vdisplay = intel_tv_mode_vdisplay(tv_mode); 1777 1778 /* prefer 480 line modes for all SD TV modes */ 1779 if (vdisplay <= 576) 1780 vdisplay = 480; 1781 1782 return vdisplay == mode->vdisplay; 1783 } 1784 1785 static void intel_tv_set_mode_type(struct drm_display_mode * mode,const struct tv_mode * tv_mode)1786 intel_tv_set_mode_type(struct drm_display_mode *mode, 1787 const struct tv_mode *tv_mode) 1788 { 1789 mode->type = DRM_MODE_TYPE_DRIVER; 1790 1791 if (intel_tv_is_preferred_mode(mode, tv_mode)) 1792 mode->type |= DRM_MODE_TYPE_PREFERRED; 1793 } 1794 1795 static int intel_tv_get_modes(struct drm_connector * connector)1796 intel_tv_get_modes(struct drm_connector *connector) 1797 { 1798 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1799 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1800 int i, count = 0; 1801 1802 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) { 1803 const struct input_res *input = &input_res_table[i]; 1804 struct drm_display_mode *mode; 1805 1806 if (input->w > 1024 && 1807 !tv_mode->progressive && 1808 !tv_mode->component_only) 1809 continue; 1810 1811 /* no vertical scaling with wide sources on gen3 */ 1812 if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 && 1813 input->h > intel_tv_mode_vdisplay(tv_mode)) 1814 continue; 1815 1816 mode = drm_mode_create(connector->dev); 1817 if (!mode) 1818 continue; 1819 1820 /* 1821 * We take the TV mode and scale it to look 1822 * like it had the expected h/vdisplay. This 1823 * provides the most information to userspace 1824 * about the actual timings of the mode. We 1825 * do ignore the margins though. 1826 */ 1827 intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock); 1828 if (count == 0) { 1829 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1830 DRM_MODE_ARG(mode)); 1831 } 1832 intel_tv_scale_mode_horiz(mode, input->w, 0, 0); 1833 intel_tv_scale_mode_vert(mode, input->h, 0, 0); 1834 intel_tv_set_mode_type(mode, tv_mode); 1835 1836 drm_mode_set_name(mode); 1837 1838 drm_mode_probed_add(connector, mode); 1839 count++; 1840 } 1841 1842 return count; 1843 } 1844 1845 static const struct drm_connector_funcs intel_tv_connector_funcs = { 1846 .late_register = intel_connector_register, 1847 .early_unregister = intel_connector_unregister, 1848 .destroy = intel_connector_destroy, 1849 .fill_modes = drm_helper_probe_single_connector_modes, 1850 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1851 .atomic_duplicate_state = intel_tv_connector_duplicate_state, 1852 }; 1853 intel_tv_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1854 static int intel_tv_atomic_check(struct drm_connector *connector, 1855 struct drm_atomic_state *state) 1856 { 1857 struct drm_connector_state *new_state; 1858 struct drm_crtc_state *new_crtc_state; 1859 struct drm_connector_state *old_state; 1860 1861 new_state = drm_atomic_get_new_connector_state(state, connector); 1862 if (!new_state->crtc) 1863 return 0; 1864 1865 old_state = drm_atomic_get_old_connector_state(state, connector); 1866 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); 1867 1868 if (old_state->tv.legacy_mode != new_state->tv.legacy_mode || 1869 old_state->tv.margins.left != new_state->tv.margins.left || 1870 old_state->tv.margins.right != new_state->tv.margins.right || 1871 old_state->tv.margins.top != new_state->tv.margins.top || 1872 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 1873 /* Force a modeset. */ 1874 1875 new_crtc_state->connectors_changed = true; 1876 } 1877 1878 return 0; 1879 } 1880 1881 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = { 1882 .detect_ctx = intel_tv_detect, 1883 .mode_valid = intel_tv_mode_valid, 1884 .get_modes = intel_tv_get_modes, 1885 .atomic_check = intel_tv_atomic_check, 1886 }; 1887 1888 static const struct drm_encoder_funcs intel_tv_enc_funcs = { 1889 .destroy = intel_encoder_destroy, 1890 }; 1891 intel_tv_add_properties(struct drm_connector * connector)1892 static void intel_tv_add_properties(struct drm_connector *connector) 1893 { 1894 struct drm_i915_private *i915 = to_i915(connector->dev); 1895 struct drm_connector_state *conn_state = connector->state; 1896 const char *tv_format_names[ARRAY_SIZE(tv_modes)]; 1897 int i; 1898 1899 /* BIOS margin values */ 1900 conn_state->tv.margins.left = 54; 1901 conn_state->tv.margins.top = 36; 1902 conn_state->tv.margins.right = 46; 1903 conn_state->tv.margins.bottom = 37; 1904 1905 conn_state->tv.legacy_mode = 0; 1906 1907 /* Create TV properties then attach current values */ 1908 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1909 /* 1080p50/1080p60 not supported on gen3 */ 1910 if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1) 1911 break; 1912 1913 tv_format_names[i] = tv_modes[i].name; 1914 } 1915 drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names); 1916 1917 drm_object_attach_property(&connector->base, 1918 i915->drm.mode_config.legacy_tv_mode_property, 1919 conn_state->tv.legacy_mode); 1920 drm_object_attach_property(&connector->base, 1921 i915->drm.mode_config.tv_left_margin_property, 1922 conn_state->tv.margins.left); 1923 drm_object_attach_property(&connector->base, 1924 i915->drm.mode_config.tv_top_margin_property, 1925 conn_state->tv.margins.top); 1926 drm_object_attach_property(&connector->base, 1927 i915->drm.mode_config.tv_right_margin_property, 1928 conn_state->tv.margins.right); 1929 drm_object_attach_property(&connector->base, 1930 i915->drm.mode_config.tv_bottom_margin_property, 1931 conn_state->tv.margins.bottom); 1932 } 1933 1934 void intel_tv_init(struct drm_i915_private * dev_priv)1935 intel_tv_init(struct drm_i915_private *dev_priv) 1936 { 1937 struct drm_connector *connector; 1938 struct intel_tv *intel_tv; 1939 struct intel_encoder *intel_encoder; 1940 struct intel_connector *intel_connector; 1941 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1942 1943 if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1944 return; 1945 1946 if (!intel_bios_is_tv_present(dev_priv)) { 1947 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n"); 1948 return; 1949 } 1950 1951 /* 1952 * Sanity check the TV output by checking to see if the 1953 * DAC register holds a value 1954 */ 1955 save_tv_dac = intel_de_read(dev_priv, TV_DAC); 1956 1957 intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); 1958 tv_dac_on = intel_de_read(dev_priv, TV_DAC); 1959 1960 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1961 tv_dac_off = intel_de_read(dev_priv, TV_DAC); 1962 1963 intel_de_write(dev_priv, TV_DAC, save_tv_dac); 1964 1965 /* 1966 * If the register does not hold the state change enable 1967 * bit, (either as a 0 or a 1), assume it doesn't really 1968 * exist 1969 */ 1970 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 || 1971 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) 1972 return; 1973 1974 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL); 1975 if (!intel_tv) { 1976 return; 1977 } 1978 1979 intel_connector = intel_connector_alloc(); 1980 if (!intel_connector) { 1981 kfree(intel_tv); 1982 return; 1983 } 1984 1985 intel_encoder = &intel_tv->base; 1986 connector = &intel_connector->base; 1987 1988 /* 1989 * The documentation, for the older chipsets at least, recommend 1990 * using a polling method rather than hotplug detection for TVs. 1991 * This is because in order to perform the hotplug detection, the PLLs 1992 * for the TV must be kept alive increasing power drain and starving 1993 * bandwidth from other encoders. Notably for instance, it causes 1994 * pipe underruns on Crestline when this encoder is supposedly idle. 1995 * 1996 * More recent chipsets favour HDMI rather than integrated S-Video. 1997 */ 1998 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1999 2000 drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs, 2001 DRM_MODE_CONNECTOR_SVIDEO); 2002 2003 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs, 2004 DRM_MODE_ENCODER_TVDAC, "TV"); 2005 2006 intel_encoder->compute_config = intel_tv_compute_config; 2007 intel_encoder->get_config = intel_tv_get_config; 2008 intel_encoder->pre_enable = intel_tv_pre_enable; 2009 intel_encoder->enable = intel_enable_tv; 2010 intel_encoder->disable = intel_disable_tv; 2011 intel_encoder->get_hw_state = intel_tv_get_hw_state; 2012 intel_connector->get_hw_state = intel_connector_get_hw_state; 2013 2014 intel_connector_attach_encoder(intel_connector, intel_encoder); 2015 2016 intel_encoder->type = INTEL_OUTPUT_TVOUT; 2017 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 2018 intel_encoder->port = PORT_NONE; 2019 intel_encoder->pipe_mask = ~0; 2020 intel_encoder->cloneable = 0; 2021 intel_tv->type = DRM_MODE_CONNECTOR_Unknown; 2022 2023 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); 2024 2025 intel_tv_add_properties(connector); 2026 } 2027