1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Universal Flash Storage Host controller driver Core
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #include <linux/async.h>
13 #include <linux/devfreq.h>
14 #include <linux/nls.h>
15 #include <linux/of.h>
16 #include <linux/bitfield.h>
17 #include <linux/blk-pm.h>
18 #include <linux/blkdev.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/sched/clock.h>
25 #include <linux/iopoll.h>
26 #include <scsi/scsi_cmnd.h>
27 #include <scsi/scsi_dbg.h>
28 #include <scsi/scsi_driver.h>
29 #include <scsi/scsi_eh.h>
30 #include "ufshcd-priv.h"
31 #include <ufs/ufs_quirks.h>
32 #include <ufs/unipro.h>
33 #include "ufs-sysfs.h"
34 #include "ufs-debugfs.h"
35 #include "ufs-fault-injection.h"
36 #include "ufs_bsg.h"
37 #include "ufshcd-crypto.h"
38 #include <asm/unaligned.h>
39
40 #define CREATE_TRACE_POINTS
41 #include <trace/events/ufs.h>
42
43 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
44 UTP_TASK_REQ_COMPL |\
45 UFSHCD_ERROR_MASK)
46
47 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\
48 UFSHCD_ERROR_MASK |\
49 MCQ_CQ_EVENT_STATUS)
50
51
52 /* UIC command timeout, unit: ms */
53 #define UIC_CMD_TIMEOUT 500
54
55 /* NOP OUT retries waiting for NOP IN response */
56 #define NOP_OUT_RETRIES 10
57 /* Timeout after 50 msecs if NOP OUT hangs without response */
58 #define NOP_OUT_TIMEOUT 50 /* msecs */
59
60 /* Query request retries */
61 #define QUERY_REQ_RETRIES 3
62 /* Query request timeout */
63 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
64
65 /* Advanced RPMB request timeout */
66 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */
67
68 /* Task management command timeout */
69 #define TM_CMD_TIMEOUT 100 /* msecs */
70
71 /* maximum number of retries for a general UIC command */
72 #define UFS_UIC_COMMAND_RETRIES 3
73
74 /* maximum number of link-startup retries */
75 #define DME_LINKSTARTUP_RETRIES 3
76
77 /* maximum number of reset retries before giving up */
78 #define MAX_HOST_RESET_RETRIES 5
79
80 /* Maximum number of error handler retries before giving up */
81 #define MAX_ERR_HANDLER_RETRIES 5
82
83 /* Expose the flag value from utp_upiu_query.value */
84 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
85
86 /* Interrupt aggregation default timeout, unit: 40us */
87 #define INT_AGGR_DEF_TO 0x02
88
89 /* default delay of autosuspend: 2000 ms */
90 #define RPM_AUTOSUSPEND_DELAY_MS 2000
91
92 /* Default delay of RPM device flush delayed work */
93 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
94
95 /* Default value of wait time before gating device ref clock */
96 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
97
98 /* Polling time to wait for fDeviceInit */
99 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
100
101 /* UFSHC 4.0 compliant HC support this mode. */
102 static bool use_mcq_mode = true;
103
is_mcq_supported(struct ufs_hba * hba)104 static bool is_mcq_supported(struct ufs_hba *hba)
105 {
106 return hba->mcq_sup && use_mcq_mode;
107 }
108
109 module_param(use_mcq_mode, bool, 0644);
110 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default");
111
112 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
113 ({ \
114 int _ret; \
115 if (_on) \
116 _ret = ufshcd_enable_vreg(_dev, _vreg); \
117 else \
118 _ret = ufshcd_disable_vreg(_dev, _vreg); \
119 _ret; \
120 })
121
122 #define ufshcd_hex_dump(prefix_str, buf, len) do { \
123 size_t __len = (len); \
124 print_hex_dump(KERN_ERR, prefix_str, \
125 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
126 16, 4, buf, __len, false); \
127 } while (0)
128
ufshcd_dump_regs(struct ufs_hba * hba,size_t offset,size_t len,const char * prefix)129 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
130 const char *prefix)
131 {
132 u32 *regs;
133 size_t pos;
134
135 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
136 return -EINVAL;
137
138 regs = kzalloc(len, GFP_ATOMIC);
139 if (!regs)
140 return -ENOMEM;
141
142 for (pos = 0; pos < len; pos += 4) {
143 if (offset == 0 &&
144 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
145 pos <= REG_UIC_ERROR_CODE_DME)
146 continue;
147 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
148 }
149
150 ufshcd_hex_dump(prefix, regs, len);
151 kfree(regs);
152
153 return 0;
154 }
155 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
156
157 enum {
158 UFSHCD_MAX_CHANNEL = 0,
159 UFSHCD_MAX_ID = 1,
160 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
161 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
162 };
163
164 static const char *const ufshcd_state_name[] = {
165 [UFSHCD_STATE_RESET] = "reset",
166 [UFSHCD_STATE_OPERATIONAL] = "operational",
167 [UFSHCD_STATE_ERROR] = "error",
168 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal",
169 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal",
170 };
171
172 /* UFSHCD error handling flags */
173 enum {
174 UFSHCD_EH_IN_PROGRESS = (1 << 0),
175 };
176
177 /* UFSHCD UIC layer error flags */
178 enum {
179 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
180 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
181 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
182 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
183 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
184 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
185 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
186 };
187
188 #define ufshcd_set_eh_in_progress(h) \
189 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
190 #define ufshcd_eh_in_progress(h) \
191 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
192 #define ufshcd_clear_eh_in_progress(h) \
193 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
194
195 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
196 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
197 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
198 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
199 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
200 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
201 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
202 /*
203 * For DeepSleep, the link is first put in hibern8 and then off.
204 * Leaving the link in hibern8 is not supported.
205 */
206 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
207 };
208
209 static inline enum ufs_dev_pwr_mode
ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)210 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
211 {
212 return ufs_pm_lvl_states[lvl].dev_state;
213 }
214
215 static inline enum uic_link_state
ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)216 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
217 {
218 return ufs_pm_lvl_states[lvl].link_state;
219 }
220
221 static inline enum ufs_pm_level
ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,enum uic_link_state link_state)222 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
223 enum uic_link_state link_state)
224 {
225 enum ufs_pm_level lvl;
226
227 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
228 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
229 (ufs_pm_lvl_states[lvl].link_state == link_state))
230 return lvl;
231 }
232
233 /* if no match found, return the level 0 */
234 return UFS_PM_LVL_0;
235 }
236
237 static const struct ufs_dev_quirk ufs_fixups[] = {
238 /* UFS cards deviations table */
239 { .wmanufacturerid = UFS_VENDOR_MICRON,
240 .model = UFS_ANY_MODEL,
241 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
242 { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
243 .model = UFS_ANY_MODEL,
244 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
245 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
246 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
247 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
248 .model = UFS_ANY_MODEL,
249 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
250 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
251 .model = "hB8aL1" /*H28U62301AMR*/,
252 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
253 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
254 .model = UFS_ANY_MODEL,
255 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
256 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
257 .model = "THGLF2G9C8KBADG",
258 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
259 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
260 .model = "THGLF2G9D8KBADG",
261 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
262 {}
263 };
264
265 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
266 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
267 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
268 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
269 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
270 static void ufshcd_hba_exit(struct ufs_hba *hba);
271 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
272 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
273 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
274 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
275 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
276 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
277 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
278 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
279 static irqreturn_t ufshcd_intr(int irq, void *__hba);
280 static int ufshcd_change_power_mode(struct ufs_hba *hba,
281 struct ufs_pa_layer_attr *pwr_mode);
282 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
283 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
284 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
285 struct ufs_vreg *vreg);
286 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
287 bool enable);
288 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
289 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
290
ufshcd_enable_irq(struct ufs_hba * hba)291 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
292 {
293 if (!hba->is_irq_enabled) {
294 enable_irq(hba->irq);
295 hba->is_irq_enabled = true;
296 }
297 }
298
ufshcd_disable_irq(struct ufs_hba * hba)299 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
300 {
301 if (hba->is_irq_enabled) {
302 disable_irq(hba->irq);
303 hba->is_irq_enabled = false;
304 }
305 }
306
ufshcd_configure_wb(struct ufs_hba * hba)307 static void ufshcd_configure_wb(struct ufs_hba *hba)
308 {
309 if (!ufshcd_is_wb_allowed(hba))
310 return;
311
312 ufshcd_wb_toggle(hba, true);
313
314 ufshcd_wb_toggle_buf_flush_during_h8(hba, true);
315
316 if (ufshcd_is_wb_buf_flush_allowed(hba))
317 ufshcd_wb_toggle_buf_flush(hba, true);
318 }
319
ufshcd_scsi_unblock_requests(struct ufs_hba * hba)320 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
321 {
322 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
323 scsi_unblock_requests(hba->host);
324 }
325
ufshcd_scsi_block_requests(struct ufs_hba * hba)326 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
327 {
328 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
329 scsi_block_requests(hba->host);
330 }
331
ufshcd_add_cmd_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)332 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
333 enum ufs_trace_str_t str_t)
334 {
335 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
336 struct utp_upiu_header *header;
337
338 if (!trace_ufshcd_upiu_enabled())
339 return;
340
341 if (str_t == UFS_CMD_SEND)
342 header = &rq->header;
343 else
344 header = &hba->lrb[tag].ucd_rsp_ptr->header;
345
346 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
347 UFS_TSF_CDB);
348 }
349
ufshcd_add_query_upiu_trace(struct ufs_hba * hba,enum ufs_trace_str_t str_t,struct utp_upiu_req * rq_rsp)350 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
351 enum ufs_trace_str_t str_t,
352 struct utp_upiu_req *rq_rsp)
353 {
354 if (!trace_ufshcd_upiu_enabled())
355 return;
356
357 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
358 &rq_rsp->qr, UFS_TSF_OSF);
359 }
360
ufshcd_add_tm_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)361 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
362 enum ufs_trace_str_t str_t)
363 {
364 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
365
366 if (!trace_ufshcd_upiu_enabled())
367 return;
368
369 if (str_t == UFS_TM_SEND)
370 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
371 &descp->upiu_req.req_header,
372 &descp->upiu_req.input_param1,
373 UFS_TSF_TM_INPUT);
374 else
375 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
376 &descp->upiu_rsp.rsp_header,
377 &descp->upiu_rsp.output_param1,
378 UFS_TSF_TM_OUTPUT);
379 }
380
ufshcd_add_uic_command_trace(struct ufs_hba * hba,const struct uic_command * ucmd,enum ufs_trace_str_t str_t)381 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
382 const struct uic_command *ucmd,
383 enum ufs_trace_str_t str_t)
384 {
385 u32 cmd;
386
387 if (!trace_ufshcd_uic_command_enabled())
388 return;
389
390 if (str_t == UFS_CMD_SEND)
391 cmd = ucmd->command;
392 else
393 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
394
395 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
396 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
397 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
398 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
399 }
400
ufshcd_add_command_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)401 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
402 enum ufs_trace_str_t str_t)
403 {
404 u64 lba = 0;
405 u8 opcode = 0, group_id = 0;
406 u32 doorbell = 0;
407 u32 intr;
408 int hwq_id = -1;
409 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
410 struct scsi_cmnd *cmd = lrbp->cmd;
411 struct request *rq = scsi_cmd_to_rq(cmd);
412 int transfer_len = -1;
413
414 if (!cmd)
415 return;
416
417 /* trace UPIU also */
418 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
419 if (!trace_ufshcd_command_enabled())
420 return;
421
422 opcode = cmd->cmnd[0];
423
424 if (opcode == READ_10 || opcode == WRITE_10) {
425 /*
426 * Currently we only fully trace read(10) and write(10) commands
427 */
428 transfer_len =
429 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
430 lba = scsi_get_lba(cmd);
431 if (opcode == WRITE_10)
432 group_id = lrbp->cmd->cmnd[6];
433 } else if (opcode == UNMAP) {
434 /*
435 * The number of Bytes to be unmapped beginning with the lba.
436 */
437 transfer_len = blk_rq_bytes(rq);
438 lba = scsi_get_lba(cmd);
439 }
440
441 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
442
443 if (is_mcq_enabled(hba)) {
444 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq);
445
446 hwq_id = hwq->id;
447 } else {
448 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
449 }
450 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
451 doorbell, hwq_id, transfer_len, intr, lba, opcode, group_id);
452 }
453
ufshcd_print_clk_freqs(struct ufs_hba * hba)454 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
455 {
456 struct ufs_clk_info *clki;
457 struct list_head *head = &hba->clk_list_head;
458
459 if (list_empty(head))
460 return;
461
462 list_for_each_entry(clki, head, list) {
463 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
464 clki->max_freq)
465 dev_err(hba->dev, "clk: %s, rate: %u\n",
466 clki->name, clki->curr_freq);
467 }
468 }
469
ufshcd_print_evt(struct ufs_hba * hba,u32 id,const char * err_name)470 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
471 const char *err_name)
472 {
473 int i;
474 bool found = false;
475 const struct ufs_event_hist *e;
476
477 if (id >= UFS_EVT_CNT)
478 return;
479
480 e = &hba->ufs_stats.event[id];
481
482 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
483 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
484
485 if (e->tstamp[p] == 0)
486 continue;
487 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
488 e->val[p], div_u64(e->tstamp[p], 1000));
489 found = true;
490 }
491
492 if (!found)
493 dev_err(hba->dev, "No record of %s\n", err_name);
494 else
495 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
496 }
497
ufshcd_print_evt_hist(struct ufs_hba * hba)498 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
499 {
500 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
501
502 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
503 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
504 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
505 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
506 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
507 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
508 "auto_hibern8_err");
509 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
510 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
511 "link_startup_fail");
512 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
513 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
514 "suspend_fail");
515 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail");
516 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR,
517 "wlun suspend_fail");
518 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
519 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
520 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
521
522 ufshcd_vops_dbg_register_dump(hba);
523 }
524
525 static
ufshcd_print_tr(struct ufs_hba * hba,int tag,bool pr_prdt)526 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt)
527 {
528 const struct ufshcd_lrb *lrbp;
529 int prdt_length;
530
531 lrbp = &hba->lrb[tag];
532
533 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
534 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000));
535 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
536 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000));
537 dev_err(hba->dev,
538 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
539 tag, (u64)lrbp->utrd_dma_addr);
540
541 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
542 sizeof(struct utp_transfer_req_desc));
543 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
544 (u64)lrbp->ucd_req_dma_addr);
545 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
546 sizeof(struct utp_upiu_req));
547 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
548 (u64)lrbp->ucd_rsp_dma_addr);
549 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
550 sizeof(struct utp_upiu_rsp));
551
552 prdt_length = le16_to_cpu(
553 lrbp->utr_descriptor_ptr->prd_table_length);
554 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
555 prdt_length /= ufshcd_sg_entry_size(hba);
556
557 dev_err(hba->dev,
558 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
559 tag, prdt_length,
560 (u64)lrbp->ucd_prdt_dma_addr);
561
562 if (pr_prdt)
563 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
564 ufshcd_sg_entry_size(hba) * prdt_length);
565 }
566
ufshcd_print_tr_iter(struct request * req,void * priv)567 static bool ufshcd_print_tr_iter(struct request *req, void *priv)
568 {
569 struct scsi_device *sdev = req->q->queuedata;
570 struct Scsi_Host *shost = sdev->host;
571 struct ufs_hba *hba = shost_priv(shost);
572
573 ufshcd_print_tr(hba, req->tag, *(bool *)priv);
574
575 return true;
576 }
577
578 /**
579 * ufshcd_print_trs_all - print trs for all started requests.
580 * @hba: per-adapter instance.
581 * @pr_prdt: need to print prdt or not.
582 */
ufshcd_print_trs_all(struct ufs_hba * hba,bool pr_prdt)583 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt)
584 {
585 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt);
586 }
587
ufshcd_print_tmrs(struct ufs_hba * hba,unsigned long bitmap)588 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
589 {
590 int tag;
591
592 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
593 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
594
595 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
596 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
597 }
598 }
599
ufshcd_print_host_state(struct ufs_hba * hba)600 static void ufshcd_print_host_state(struct ufs_hba *hba)
601 {
602 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
603
604 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
605 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
606 hba->outstanding_reqs, hba->outstanding_tasks);
607 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
608 hba->saved_err, hba->saved_uic_err);
609 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
610 hba->curr_dev_pwr_mode, hba->uic_link_state);
611 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
612 hba->pm_op_in_progress, hba->is_sys_suspended);
613 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
614 hba->auto_bkops_enabled, hba->host->host_self_blocked);
615 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
616 dev_err(hba->dev,
617 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
618 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000),
619 hba->ufs_stats.hibern8_exit_cnt);
620 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
621 div_u64(hba->ufs_stats.last_intr_ts, 1000),
622 hba->ufs_stats.last_intr_status);
623 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
624 hba->eh_flags, hba->req_abort_count);
625 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
626 hba->ufs_version, hba->capabilities, hba->caps);
627 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
628 hba->dev_quirks);
629 if (sdev_ufs)
630 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
631 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
632
633 ufshcd_print_clk_freqs(hba);
634 }
635
636 /**
637 * ufshcd_print_pwr_info - print power params as saved in hba
638 * power info
639 * @hba: per-adapter instance
640 */
ufshcd_print_pwr_info(struct ufs_hba * hba)641 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
642 {
643 static const char * const names[] = {
644 "INVALID MODE",
645 "FAST MODE",
646 "SLOW_MODE",
647 "INVALID MODE",
648 "FASTAUTO_MODE",
649 "SLOWAUTO_MODE",
650 "INVALID MODE",
651 };
652
653 /*
654 * Using dev_dbg to avoid messages during runtime PM to avoid
655 * never-ending cycles of messages written back to storage by user space
656 * causing runtime resume, causing more messages and so on.
657 */
658 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
659 __func__,
660 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
661 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
662 names[hba->pwr_info.pwr_rx],
663 names[hba->pwr_info.pwr_tx],
664 hba->pwr_info.hs_rate);
665 }
666
ufshcd_device_reset(struct ufs_hba * hba)667 static void ufshcd_device_reset(struct ufs_hba *hba)
668 {
669 int err;
670
671 err = ufshcd_vops_device_reset(hba);
672
673 if (!err) {
674 ufshcd_set_ufs_dev_active(hba);
675 if (ufshcd_is_wb_allowed(hba)) {
676 hba->dev_info.wb_enabled = false;
677 hba->dev_info.wb_buf_flush_enabled = false;
678 }
679 }
680 if (err != -EOPNOTSUPP)
681 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
682 }
683
ufshcd_delay_us(unsigned long us,unsigned long tolerance)684 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
685 {
686 if (!us)
687 return;
688
689 if (us < 10)
690 udelay(us);
691 else
692 usleep_range(us, us + tolerance);
693 }
694 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
695
696 /**
697 * ufshcd_wait_for_register - wait for register value to change
698 * @hba: per-adapter interface
699 * @reg: mmio register offset
700 * @mask: mask to apply to the read register value
701 * @val: value to wait for
702 * @interval_us: polling interval in microseconds
703 * @timeout_ms: timeout in milliseconds
704 *
705 * Return: -ETIMEDOUT on error, zero on success.
706 */
ufshcd_wait_for_register(struct ufs_hba * hba,u32 reg,u32 mask,u32 val,unsigned long interval_us,unsigned long timeout_ms)707 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
708 u32 val, unsigned long interval_us,
709 unsigned long timeout_ms)
710 {
711 int err = 0;
712 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
713
714 /* ignore bits that we don't intend to wait on */
715 val = val & mask;
716
717 while ((ufshcd_readl(hba, reg) & mask) != val) {
718 usleep_range(interval_us, interval_us + 50);
719 if (time_after(jiffies, timeout)) {
720 if ((ufshcd_readl(hba, reg) & mask) != val)
721 err = -ETIMEDOUT;
722 break;
723 }
724 }
725
726 return err;
727 }
728
729 /**
730 * ufshcd_get_intr_mask - Get the interrupt bit mask
731 * @hba: Pointer to adapter instance
732 *
733 * Return: interrupt bit mask per version
734 */
ufshcd_get_intr_mask(struct ufs_hba * hba)735 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
736 {
737 if (hba->ufs_version == ufshci_version(1, 0))
738 return INTERRUPT_MASK_ALL_VER_10;
739 if (hba->ufs_version <= ufshci_version(2, 0))
740 return INTERRUPT_MASK_ALL_VER_11;
741
742 return INTERRUPT_MASK_ALL_VER_21;
743 }
744
745 /**
746 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
747 * @hba: Pointer to adapter instance
748 *
749 * Return: UFSHCI version supported by the controller
750 */
ufshcd_get_ufs_version(struct ufs_hba * hba)751 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
752 {
753 u32 ufshci_ver;
754
755 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
756 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
757 else
758 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
759
760 /*
761 * UFSHCI v1.x uses a different version scheme, in order
762 * to allow the use of comparisons with the ufshci_version
763 * function, we convert it to the same scheme as ufs 2.0+.
764 */
765 if (ufshci_ver & 0x00010000)
766 return ufshci_version(1, ufshci_ver & 0x00000100);
767
768 return ufshci_ver;
769 }
770
771 /**
772 * ufshcd_is_device_present - Check if any device connected to
773 * the host controller
774 * @hba: pointer to adapter instance
775 *
776 * Return: true if device present, false if no device detected
777 */
ufshcd_is_device_present(struct ufs_hba * hba)778 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
779 {
780 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
781 }
782
783 /**
784 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
785 * @lrbp: pointer to local command reference block
786 * @cqe: pointer to the completion queue entry
787 *
788 * This function is used to get the OCS field from UTRD
789 *
790 * Return: the OCS field in the UTRD.
791 */
ufshcd_get_tr_ocs(struct ufshcd_lrb * lrbp,struct cq_entry * cqe)792 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp,
793 struct cq_entry *cqe)
794 {
795 if (cqe)
796 return le32_to_cpu(cqe->status) & MASK_OCS;
797
798 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS;
799 }
800
801 /**
802 * ufshcd_utrl_clear() - Clear requests from the controller request list.
803 * @hba: per adapter instance
804 * @mask: mask with one bit set for each request to be cleared
805 */
ufshcd_utrl_clear(struct ufs_hba * hba,u32 mask)806 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
807 {
808 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
809 mask = ~mask;
810 /*
811 * From the UFSHCI specification: "UTP Transfer Request List CLear
812 * Register (UTRLCLR): This field is bit significant. Each bit
813 * corresponds to a slot in the UTP Transfer Request List, where bit 0
814 * corresponds to request slot 0. A bit in this field is set to ‘0’
815 * by host software to indicate to the host controller that a transfer
816 * request slot is cleared. The host controller
817 * shall free up any resources associated to the request slot
818 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
819 * host software indicates no change to request slots by setting the
820 * associated bits in this field to ‘1’. Bits in this field shall only
821 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
822 */
823 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
824 }
825
826 /**
827 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register
828 * @hba: per adapter instance
829 * @pos: position of the bit to be cleared
830 */
ufshcd_utmrl_clear(struct ufs_hba * hba,u32 pos)831 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
832 {
833 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
834 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
835 else
836 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
837 }
838
839 /**
840 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
841 * @reg: Register value of host controller status
842 *
843 * Return: 0 on success; a positive value if failed.
844 */
ufshcd_get_lists_status(u32 reg)845 static inline int ufshcd_get_lists_status(u32 reg)
846 {
847 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
848 }
849
850 /**
851 * ufshcd_get_uic_cmd_result - Get the UIC command result
852 * @hba: Pointer to adapter instance
853 *
854 * This function gets the result of UIC command completion
855 *
856 * Return: 0 on success; non-zero value on error.
857 */
ufshcd_get_uic_cmd_result(struct ufs_hba * hba)858 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
859 {
860 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
861 MASK_UIC_COMMAND_RESULT;
862 }
863
864 /**
865 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
866 * @hba: Pointer to adapter instance
867 *
868 * This function gets UIC command argument3
869 *
870 * Return: 0 on success; non-zero value on error.
871 */
ufshcd_get_dme_attr_val(struct ufs_hba * hba)872 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
873 {
874 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
875 }
876
877 /**
878 * ufshcd_get_req_rsp - returns the TR response transaction type
879 * @ucd_rsp_ptr: pointer to response UPIU
880 *
881 * Return: UPIU type.
882 */
883 static inline enum upiu_response_transaction
ufshcd_get_req_rsp(struct utp_upiu_rsp * ucd_rsp_ptr)884 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
885 {
886 return ucd_rsp_ptr->header.transaction_code;
887 }
888
889 /**
890 * ufshcd_is_exception_event - Check if the device raised an exception event
891 * @ucd_rsp_ptr: pointer to response UPIU
892 *
893 * The function checks if the device raised an exception event indicated in
894 * the Device Information field of response UPIU.
895 *
896 * Return: true if exception is raised, false otherwise.
897 */
ufshcd_is_exception_event(struct utp_upiu_rsp * ucd_rsp_ptr)898 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
899 {
900 return ucd_rsp_ptr->header.device_information & 1;
901 }
902
903 /**
904 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
905 * @hba: per adapter instance
906 */
907 static inline void
ufshcd_reset_intr_aggr(struct ufs_hba * hba)908 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
909 {
910 ufshcd_writel(hba, INT_AGGR_ENABLE |
911 INT_AGGR_COUNTER_AND_TIMER_RESET,
912 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
913 }
914
915 /**
916 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
917 * @hba: per adapter instance
918 * @cnt: Interrupt aggregation counter threshold
919 * @tmout: Interrupt aggregation timeout value
920 */
921 static inline void
ufshcd_config_intr_aggr(struct ufs_hba * hba,u8 cnt,u8 tmout)922 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
923 {
924 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
925 INT_AGGR_COUNTER_THLD_VAL(cnt) |
926 INT_AGGR_TIMEOUT_VAL(tmout),
927 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
928 }
929
930 /**
931 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
932 * @hba: per adapter instance
933 */
ufshcd_disable_intr_aggr(struct ufs_hba * hba)934 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
935 {
936 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
937 }
938
939 /**
940 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
941 * When run-stop registers are set to 1, it indicates the
942 * host controller that it can process the requests
943 * @hba: per adapter instance
944 */
ufshcd_enable_run_stop_reg(struct ufs_hba * hba)945 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
946 {
947 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
948 REG_UTP_TASK_REQ_LIST_RUN_STOP);
949 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
950 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
951 }
952
953 /**
954 * ufshcd_hba_start - Start controller initialization sequence
955 * @hba: per adapter instance
956 */
ufshcd_hba_start(struct ufs_hba * hba)957 static inline void ufshcd_hba_start(struct ufs_hba *hba)
958 {
959 u32 val = CONTROLLER_ENABLE;
960
961 if (ufshcd_crypto_enable(hba))
962 val |= CRYPTO_GENERAL_ENABLE;
963
964 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
965 }
966
967 /**
968 * ufshcd_is_hba_active - Get controller state
969 * @hba: per adapter instance
970 *
971 * Return: true if and only if the controller is active.
972 */
ufshcd_is_hba_active(struct ufs_hba * hba)973 bool ufshcd_is_hba_active(struct ufs_hba *hba)
974 {
975 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
976 }
977 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active);
978
ufshcd_get_local_unipro_ver(struct ufs_hba * hba)979 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
980 {
981 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
982 if (hba->ufs_version <= ufshci_version(1, 1))
983 return UFS_UNIPRO_VER_1_41;
984 else
985 return UFS_UNIPRO_VER_1_6;
986 }
987 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
988
ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba * hba)989 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
990 {
991 /*
992 * If both host and device support UniPro ver1.6 or later, PA layer
993 * parameters tuning happens during link startup itself.
994 *
995 * We can manually tune PA layer parameters if either host or device
996 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
997 * logic simple, we will only do manual tuning if local unipro version
998 * doesn't support ver1.6 or later.
999 */
1000 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6;
1001 }
1002
1003 /**
1004 * ufshcd_set_clk_freq - set UFS controller clock frequencies
1005 * @hba: per adapter instance
1006 * @scale_up: If True, set max possible frequency othewise set low frequency
1007 *
1008 * Return: 0 if successful; < 0 upon failure.
1009 */
ufshcd_set_clk_freq(struct ufs_hba * hba,bool scale_up)1010 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
1011 {
1012 int ret = 0;
1013 struct ufs_clk_info *clki;
1014 struct list_head *head = &hba->clk_list_head;
1015
1016 if (list_empty(head))
1017 goto out;
1018
1019 list_for_each_entry(clki, head, list) {
1020 if (!IS_ERR_OR_NULL(clki->clk)) {
1021 if (scale_up && clki->max_freq) {
1022 if (clki->curr_freq == clki->max_freq)
1023 continue;
1024
1025 ret = clk_set_rate(clki->clk, clki->max_freq);
1026 if (ret) {
1027 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1028 __func__, clki->name,
1029 clki->max_freq, ret);
1030 break;
1031 }
1032 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1033 "scaled up", clki->name,
1034 clki->curr_freq,
1035 clki->max_freq);
1036
1037 clki->curr_freq = clki->max_freq;
1038
1039 } else if (!scale_up && clki->min_freq) {
1040 if (clki->curr_freq == clki->min_freq)
1041 continue;
1042
1043 ret = clk_set_rate(clki->clk, clki->min_freq);
1044 if (ret) {
1045 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1046 __func__, clki->name,
1047 clki->min_freq, ret);
1048 break;
1049 }
1050 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1051 "scaled down", clki->name,
1052 clki->curr_freq,
1053 clki->min_freq);
1054 clki->curr_freq = clki->min_freq;
1055 }
1056 }
1057 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1058 clki->name, clk_get_rate(clki->clk));
1059 }
1060
1061 out:
1062 return ret;
1063 }
1064
1065 /**
1066 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1067 * @hba: per adapter instance
1068 * @scale_up: True if scaling up and false if scaling down
1069 *
1070 * Return: 0 if successful; < 0 upon failure.
1071 */
ufshcd_scale_clks(struct ufs_hba * hba,bool scale_up)1072 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1073 {
1074 int ret = 0;
1075 ktime_t start = ktime_get();
1076
1077 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1078 if (ret)
1079 goto out;
1080
1081 ret = ufshcd_set_clk_freq(hba, scale_up);
1082 if (ret)
1083 goto out;
1084
1085 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1086 if (ret)
1087 ufshcd_set_clk_freq(hba, !scale_up);
1088
1089 out:
1090 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1091 (scale_up ? "up" : "down"),
1092 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1093 return ret;
1094 }
1095
1096 /**
1097 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1098 * @hba: per adapter instance
1099 * @scale_up: True if scaling up and false if scaling down
1100 *
1101 * Return: true if scaling is required, false otherwise.
1102 */
ufshcd_is_devfreq_scaling_required(struct ufs_hba * hba,bool scale_up)1103 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1104 bool scale_up)
1105 {
1106 struct ufs_clk_info *clki;
1107 struct list_head *head = &hba->clk_list_head;
1108
1109 if (list_empty(head))
1110 return false;
1111
1112 list_for_each_entry(clki, head, list) {
1113 if (!IS_ERR_OR_NULL(clki->clk)) {
1114 if (scale_up && clki->max_freq) {
1115 if (clki->curr_freq == clki->max_freq)
1116 continue;
1117 return true;
1118 } else if (!scale_up && clki->min_freq) {
1119 if (clki->curr_freq == clki->min_freq)
1120 continue;
1121 return true;
1122 }
1123 }
1124 }
1125
1126 return false;
1127 }
1128
1129 /*
1130 * Determine the number of pending commands by counting the bits in the SCSI
1131 * device budget maps. This approach has been selected because a bit is set in
1132 * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1133 * flag. The host_self_blocked flag can be modified by calling
1134 * scsi_block_requests() or scsi_unblock_requests().
1135 */
ufshcd_pending_cmds(struct ufs_hba * hba)1136 static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1137 {
1138 const struct scsi_device *sdev;
1139 u32 pending = 0;
1140
1141 lockdep_assert_held(hba->host->host_lock);
1142 __shost_for_each_device(sdev, hba->host)
1143 pending += sbitmap_weight(&sdev->budget_map);
1144
1145 return pending;
1146 }
1147
1148 /*
1149 * Wait until all pending SCSI commands and TMFs have finished or the timeout
1150 * has expired.
1151 *
1152 * Return: 0 upon success; -EBUSY upon timeout.
1153 */
ufshcd_wait_for_doorbell_clr(struct ufs_hba * hba,u64 wait_timeout_us)1154 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1155 u64 wait_timeout_us)
1156 {
1157 unsigned long flags;
1158 int ret = 0;
1159 u32 tm_doorbell;
1160 u32 tr_pending;
1161 bool timeout = false, do_last_check = false;
1162 ktime_t start;
1163
1164 ufshcd_hold(hba);
1165 spin_lock_irqsave(hba->host->host_lock, flags);
1166 /*
1167 * Wait for all the outstanding tasks/transfer requests.
1168 * Verify by checking the doorbell registers are clear.
1169 */
1170 start = ktime_get();
1171 do {
1172 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1173 ret = -EBUSY;
1174 goto out;
1175 }
1176
1177 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1178 tr_pending = ufshcd_pending_cmds(hba);
1179 if (!tm_doorbell && !tr_pending) {
1180 timeout = false;
1181 break;
1182 } else if (do_last_check) {
1183 break;
1184 }
1185
1186 spin_unlock_irqrestore(hba->host->host_lock, flags);
1187 io_schedule_timeout(msecs_to_jiffies(20));
1188 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1189 wait_timeout_us) {
1190 timeout = true;
1191 /*
1192 * We might have scheduled out for long time so make
1193 * sure to check if doorbells are cleared by this time
1194 * or not.
1195 */
1196 do_last_check = true;
1197 }
1198 spin_lock_irqsave(hba->host->host_lock, flags);
1199 } while (tm_doorbell || tr_pending);
1200
1201 if (timeout) {
1202 dev_err(hba->dev,
1203 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1204 __func__, tm_doorbell, tr_pending);
1205 ret = -EBUSY;
1206 }
1207 out:
1208 spin_unlock_irqrestore(hba->host->host_lock, flags);
1209 ufshcd_release(hba);
1210 return ret;
1211 }
1212
1213 /**
1214 * ufshcd_scale_gear - scale up/down UFS gear
1215 * @hba: per adapter instance
1216 * @scale_up: True for scaling up gear and false for scaling down
1217 *
1218 * Return: 0 for success; -EBUSY if scaling can't happen at this time;
1219 * non-zero for any other errors.
1220 */
ufshcd_scale_gear(struct ufs_hba * hba,bool scale_up)1221 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1222 {
1223 int ret = 0;
1224 struct ufs_pa_layer_attr new_pwr_info;
1225
1226 if (scale_up) {
1227 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info,
1228 sizeof(struct ufs_pa_layer_attr));
1229 } else {
1230 memcpy(&new_pwr_info, &hba->pwr_info,
1231 sizeof(struct ufs_pa_layer_attr));
1232
1233 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1234 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1235 /* save the current power mode */
1236 memcpy(&hba->clk_scaling.saved_pwr_info,
1237 &hba->pwr_info,
1238 sizeof(struct ufs_pa_layer_attr));
1239
1240 /* scale down gear */
1241 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1242 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1243 }
1244 }
1245
1246 /* check if the power mode needs to be changed or not? */
1247 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1248 if (ret)
1249 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1250 __func__, ret,
1251 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1252 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1253
1254 return ret;
1255 }
1256
1257 /*
1258 * Wait until all pending SCSI commands and TMFs have finished or the timeout
1259 * has expired.
1260 *
1261 * Return: 0 upon success; -EBUSY upon timeout.
1262 */
ufshcd_clock_scaling_prepare(struct ufs_hba * hba,u64 timeout_us)1263 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us)
1264 {
1265 int ret = 0;
1266 /*
1267 * make sure that there are no outstanding requests when
1268 * clock scaling is in progress
1269 */
1270 blk_mq_quiesce_tagset(&hba->host->tag_set);
1271 mutex_lock(&hba->wb_mutex);
1272 down_write(&hba->clk_scaling_lock);
1273
1274 if (!hba->clk_scaling.is_allowed ||
1275 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) {
1276 ret = -EBUSY;
1277 up_write(&hba->clk_scaling_lock);
1278 mutex_unlock(&hba->wb_mutex);
1279 blk_mq_unquiesce_tagset(&hba->host->tag_set);
1280 goto out;
1281 }
1282
1283 /* let's not get into low power until clock scaling is completed */
1284 ufshcd_hold(hba);
1285
1286 out:
1287 return ret;
1288 }
1289
ufshcd_clock_scaling_unprepare(struct ufs_hba * hba,int err,bool scale_up)1290 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up)
1291 {
1292 up_write(&hba->clk_scaling_lock);
1293
1294 /* Enable Write Booster if we have scaled up else disable it */
1295 if (ufshcd_enable_wb_if_scaling_up(hba) && !err)
1296 ufshcd_wb_toggle(hba, scale_up);
1297
1298 mutex_unlock(&hba->wb_mutex);
1299
1300 blk_mq_unquiesce_tagset(&hba->host->tag_set);
1301 ufshcd_release(hba);
1302 }
1303
1304 /**
1305 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1306 * @hba: per adapter instance
1307 * @scale_up: True for scaling up and false for scalin down
1308 *
1309 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero
1310 * for any other errors.
1311 */
ufshcd_devfreq_scale(struct ufs_hba * hba,bool scale_up)1312 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1313 {
1314 int ret = 0;
1315
1316 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC);
1317 if (ret)
1318 return ret;
1319
1320 /* scale down the gear before scaling down clocks */
1321 if (!scale_up) {
1322 ret = ufshcd_scale_gear(hba, false);
1323 if (ret)
1324 goto out_unprepare;
1325 }
1326
1327 ret = ufshcd_scale_clks(hba, scale_up);
1328 if (ret) {
1329 if (!scale_up)
1330 ufshcd_scale_gear(hba, true);
1331 goto out_unprepare;
1332 }
1333
1334 /* scale up the gear after scaling up clocks */
1335 if (scale_up) {
1336 ret = ufshcd_scale_gear(hba, true);
1337 if (ret) {
1338 ufshcd_scale_clks(hba, false);
1339 goto out_unprepare;
1340 }
1341 }
1342
1343 out_unprepare:
1344 ufshcd_clock_scaling_unprepare(hba, ret, scale_up);
1345 return ret;
1346 }
1347
ufshcd_clk_scaling_suspend_work(struct work_struct * work)1348 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1349 {
1350 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1351 clk_scaling.suspend_work);
1352 unsigned long irq_flags;
1353
1354 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1355 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1356 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1357 return;
1358 }
1359 hba->clk_scaling.is_suspended = true;
1360 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1361
1362 __ufshcd_suspend_clkscaling(hba);
1363 }
1364
ufshcd_clk_scaling_resume_work(struct work_struct * work)1365 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1366 {
1367 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1368 clk_scaling.resume_work);
1369 unsigned long irq_flags;
1370
1371 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1372 if (!hba->clk_scaling.is_suspended) {
1373 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1374 return;
1375 }
1376 hba->clk_scaling.is_suspended = false;
1377 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1378
1379 devfreq_resume_device(hba->devfreq);
1380 }
1381
ufshcd_devfreq_target(struct device * dev,unsigned long * freq,u32 flags)1382 static int ufshcd_devfreq_target(struct device *dev,
1383 unsigned long *freq, u32 flags)
1384 {
1385 int ret = 0;
1386 struct ufs_hba *hba = dev_get_drvdata(dev);
1387 ktime_t start;
1388 bool scale_up, sched_clk_scaling_suspend_work = false;
1389 struct list_head *clk_list = &hba->clk_list_head;
1390 struct ufs_clk_info *clki;
1391 unsigned long irq_flags;
1392
1393 if (!ufshcd_is_clkscaling_supported(hba))
1394 return -EINVAL;
1395
1396 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1397 /* Override with the closest supported frequency */
1398 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1399 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1400 if (ufshcd_eh_in_progress(hba)) {
1401 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1402 return 0;
1403 }
1404
1405 if (!hba->clk_scaling.active_reqs)
1406 sched_clk_scaling_suspend_work = true;
1407
1408 if (list_empty(clk_list)) {
1409 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1410 goto out;
1411 }
1412
1413 /* Decide based on the rounded-off frequency and update */
1414 scale_up = *freq == clki->max_freq;
1415 if (!scale_up)
1416 *freq = clki->min_freq;
1417 /* Update the frequency */
1418 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1419 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1420 ret = 0;
1421 goto out; /* no state change required */
1422 }
1423 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1424
1425 start = ktime_get();
1426 ret = ufshcd_devfreq_scale(hba, scale_up);
1427
1428 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1429 (scale_up ? "up" : "down"),
1430 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1431
1432 out:
1433 if (sched_clk_scaling_suspend_work)
1434 queue_work(hba->clk_scaling.workq,
1435 &hba->clk_scaling.suspend_work);
1436
1437 return ret;
1438 }
1439
ufshcd_devfreq_get_dev_status(struct device * dev,struct devfreq_dev_status * stat)1440 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1441 struct devfreq_dev_status *stat)
1442 {
1443 struct ufs_hba *hba = dev_get_drvdata(dev);
1444 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1445 unsigned long flags;
1446 struct list_head *clk_list = &hba->clk_list_head;
1447 struct ufs_clk_info *clki;
1448 ktime_t curr_t;
1449
1450 if (!ufshcd_is_clkscaling_supported(hba))
1451 return -EINVAL;
1452
1453 memset(stat, 0, sizeof(*stat));
1454
1455 spin_lock_irqsave(hba->host->host_lock, flags);
1456 curr_t = ktime_get();
1457 if (!scaling->window_start_t)
1458 goto start_window;
1459
1460 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1461 /*
1462 * If current frequency is 0, then the ondemand governor considers
1463 * there's no initial frequency set. And it always requests to set
1464 * to max. frequency.
1465 */
1466 stat->current_frequency = clki->curr_freq;
1467 if (scaling->is_busy_started)
1468 scaling->tot_busy_t += ktime_us_delta(curr_t,
1469 scaling->busy_start_t);
1470
1471 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1472 stat->busy_time = scaling->tot_busy_t;
1473 start_window:
1474 scaling->window_start_t = curr_t;
1475 scaling->tot_busy_t = 0;
1476
1477 if (scaling->active_reqs) {
1478 scaling->busy_start_t = curr_t;
1479 scaling->is_busy_started = true;
1480 } else {
1481 scaling->busy_start_t = 0;
1482 scaling->is_busy_started = false;
1483 }
1484 spin_unlock_irqrestore(hba->host->host_lock, flags);
1485 return 0;
1486 }
1487
ufshcd_devfreq_init(struct ufs_hba * hba)1488 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1489 {
1490 struct list_head *clk_list = &hba->clk_list_head;
1491 struct ufs_clk_info *clki;
1492 struct devfreq *devfreq;
1493 int ret;
1494
1495 /* Skip devfreq if we don't have any clocks in the list */
1496 if (list_empty(clk_list))
1497 return 0;
1498
1499 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1500 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1501 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1502
1503 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1504 &hba->vps->ondemand_data);
1505 devfreq = devfreq_add_device(hba->dev,
1506 &hba->vps->devfreq_profile,
1507 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1508 &hba->vps->ondemand_data);
1509 if (IS_ERR(devfreq)) {
1510 ret = PTR_ERR(devfreq);
1511 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1512
1513 dev_pm_opp_remove(hba->dev, clki->min_freq);
1514 dev_pm_opp_remove(hba->dev, clki->max_freq);
1515 return ret;
1516 }
1517
1518 hba->devfreq = devfreq;
1519
1520 return 0;
1521 }
1522
ufshcd_devfreq_remove(struct ufs_hba * hba)1523 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1524 {
1525 struct list_head *clk_list = &hba->clk_list_head;
1526 struct ufs_clk_info *clki;
1527
1528 if (!hba->devfreq)
1529 return;
1530
1531 devfreq_remove_device(hba->devfreq);
1532 hba->devfreq = NULL;
1533
1534 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1535 dev_pm_opp_remove(hba->dev, clki->min_freq);
1536 dev_pm_opp_remove(hba->dev, clki->max_freq);
1537 }
1538
__ufshcd_suspend_clkscaling(struct ufs_hba * hba)1539 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1540 {
1541 unsigned long flags;
1542
1543 devfreq_suspend_device(hba->devfreq);
1544 spin_lock_irqsave(hba->host->host_lock, flags);
1545 hba->clk_scaling.window_start_t = 0;
1546 spin_unlock_irqrestore(hba->host->host_lock, flags);
1547 }
1548
ufshcd_suspend_clkscaling(struct ufs_hba * hba)1549 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1550 {
1551 unsigned long flags;
1552 bool suspend = false;
1553
1554 cancel_work_sync(&hba->clk_scaling.suspend_work);
1555 cancel_work_sync(&hba->clk_scaling.resume_work);
1556
1557 spin_lock_irqsave(hba->host->host_lock, flags);
1558 if (!hba->clk_scaling.is_suspended) {
1559 suspend = true;
1560 hba->clk_scaling.is_suspended = true;
1561 }
1562 spin_unlock_irqrestore(hba->host->host_lock, flags);
1563
1564 if (suspend)
1565 __ufshcd_suspend_clkscaling(hba);
1566 }
1567
ufshcd_resume_clkscaling(struct ufs_hba * hba)1568 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1569 {
1570 unsigned long flags;
1571 bool resume = false;
1572
1573 spin_lock_irqsave(hba->host->host_lock, flags);
1574 if (hba->clk_scaling.is_suspended) {
1575 resume = true;
1576 hba->clk_scaling.is_suspended = false;
1577 }
1578 spin_unlock_irqrestore(hba->host->host_lock, flags);
1579
1580 if (resume)
1581 devfreq_resume_device(hba->devfreq);
1582 }
1583
ufshcd_clkscale_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1584 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1585 struct device_attribute *attr, char *buf)
1586 {
1587 struct ufs_hba *hba = dev_get_drvdata(dev);
1588
1589 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1590 }
1591
ufshcd_clkscale_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1592 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1593 struct device_attribute *attr, const char *buf, size_t count)
1594 {
1595 struct ufs_hba *hba = dev_get_drvdata(dev);
1596 u32 value;
1597 int err = 0;
1598
1599 if (kstrtou32(buf, 0, &value))
1600 return -EINVAL;
1601
1602 down(&hba->host_sem);
1603 if (!ufshcd_is_user_access_allowed(hba)) {
1604 err = -EBUSY;
1605 goto out;
1606 }
1607
1608 value = !!value;
1609 if (value == hba->clk_scaling.is_enabled)
1610 goto out;
1611
1612 ufshcd_rpm_get_sync(hba);
1613 ufshcd_hold(hba);
1614
1615 hba->clk_scaling.is_enabled = value;
1616
1617 if (value) {
1618 ufshcd_resume_clkscaling(hba);
1619 } else {
1620 ufshcd_suspend_clkscaling(hba);
1621 err = ufshcd_devfreq_scale(hba, true);
1622 if (err)
1623 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1624 __func__, err);
1625 }
1626
1627 ufshcd_release(hba);
1628 ufshcd_rpm_put_sync(hba);
1629 out:
1630 up(&hba->host_sem);
1631 return err ? err : count;
1632 }
1633
ufshcd_init_clk_scaling_sysfs(struct ufs_hba * hba)1634 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1635 {
1636 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1637 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1638 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1639 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1640 hba->clk_scaling.enable_attr.attr.mode = 0644;
1641 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1642 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1643 }
1644
ufshcd_remove_clk_scaling_sysfs(struct ufs_hba * hba)1645 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1646 {
1647 if (hba->clk_scaling.enable_attr.attr.name)
1648 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1649 }
1650
ufshcd_init_clk_scaling(struct ufs_hba * hba)1651 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1652 {
1653 char wq_name[sizeof("ufs_clkscaling_00")];
1654
1655 if (!ufshcd_is_clkscaling_supported(hba))
1656 return;
1657
1658 if (!hba->clk_scaling.min_gear)
1659 hba->clk_scaling.min_gear = UFS_HS_G1;
1660
1661 INIT_WORK(&hba->clk_scaling.suspend_work,
1662 ufshcd_clk_scaling_suspend_work);
1663 INIT_WORK(&hba->clk_scaling.resume_work,
1664 ufshcd_clk_scaling_resume_work);
1665
1666 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1667 hba->host->host_no);
1668 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1669
1670 hba->clk_scaling.is_initialized = true;
1671 }
1672
ufshcd_exit_clk_scaling(struct ufs_hba * hba)1673 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1674 {
1675 if (!hba->clk_scaling.is_initialized)
1676 return;
1677
1678 ufshcd_remove_clk_scaling_sysfs(hba);
1679 destroy_workqueue(hba->clk_scaling.workq);
1680 ufshcd_devfreq_remove(hba);
1681 hba->clk_scaling.is_initialized = false;
1682 }
1683
ufshcd_ungate_work(struct work_struct * work)1684 static void ufshcd_ungate_work(struct work_struct *work)
1685 {
1686 int ret;
1687 unsigned long flags;
1688 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1689 clk_gating.ungate_work);
1690
1691 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1692
1693 spin_lock_irqsave(hba->host->host_lock, flags);
1694 if (hba->clk_gating.state == CLKS_ON) {
1695 spin_unlock_irqrestore(hba->host->host_lock, flags);
1696 return;
1697 }
1698
1699 spin_unlock_irqrestore(hba->host->host_lock, flags);
1700 ufshcd_hba_vreg_set_hpm(hba);
1701 ufshcd_setup_clocks(hba, true);
1702
1703 ufshcd_enable_irq(hba);
1704
1705 /* Exit from hibern8 */
1706 if (ufshcd_can_hibern8_during_gating(hba)) {
1707 /* Prevent gating in this path */
1708 hba->clk_gating.is_suspended = true;
1709 if (ufshcd_is_link_hibern8(hba)) {
1710 ret = ufshcd_uic_hibern8_exit(hba);
1711 if (ret)
1712 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1713 __func__, ret);
1714 else
1715 ufshcd_set_link_active(hba);
1716 }
1717 hba->clk_gating.is_suspended = false;
1718 }
1719 }
1720
1721 /**
1722 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1723 * Also, exit from hibern8 mode and set the link as active.
1724 * @hba: per adapter instance
1725 */
ufshcd_hold(struct ufs_hba * hba)1726 void ufshcd_hold(struct ufs_hba *hba)
1727 {
1728 bool flush_result;
1729 unsigned long flags;
1730
1731 if (!ufshcd_is_clkgating_allowed(hba) ||
1732 !hba->clk_gating.is_initialized)
1733 return;
1734 spin_lock_irqsave(hba->host->host_lock, flags);
1735 hba->clk_gating.active_reqs++;
1736
1737 start:
1738 switch (hba->clk_gating.state) {
1739 case CLKS_ON:
1740 /*
1741 * Wait for the ungate work to complete if in progress.
1742 * Though the clocks may be in ON state, the link could
1743 * still be in hibner8 state if hibern8 is allowed
1744 * during clock gating.
1745 * Make sure we exit hibern8 state also in addition to
1746 * clocks being ON.
1747 */
1748 if (ufshcd_can_hibern8_during_gating(hba) &&
1749 ufshcd_is_link_hibern8(hba)) {
1750 spin_unlock_irqrestore(hba->host->host_lock, flags);
1751 flush_result = flush_work(&hba->clk_gating.ungate_work);
1752 if (hba->clk_gating.is_suspended && !flush_result)
1753 return;
1754 spin_lock_irqsave(hba->host->host_lock, flags);
1755 goto start;
1756 }
1757 break;
1758 case REQ_CLKS_OFF:
1759 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1760 hba->clk_gating.state = CLKS_ON;
1761 trace_ufshcd_clk_gating(dev_name(hba->dev),
1762 hba->clk_gating.state);
1763 break;
1764 }
1765 /*
1766 * If we are here, it means gating work is either done or
1767 * currently running. Hence, fall through to cancel gating
1768 * work and to enable clocks.
1769 */
1770 fallthrough;
1771 case CLKS_OFF:
1772 hba->clk_gating.state = REQ_CLKS_ON;
1773 trace_ufshcd_clk_gating(dev_name(hba->dev),
1774 hba->clk_gating.state);
1775 queue_work(hba->clk_gating.clk_gating_workq,
1776 &hba->clk_gating.ungate_work);
1777 /*
1778 * fall through to check if we should wait for this
1779 * work to be done or not.
1780 */
1781 fallthrough;
1782 case REQ_CLKS_ON:
1783 spin_unlock_irqrestore(hba->host->host_lock, flags);
1784 flush_work(&hba->clk_gating.ungate_work);
1785 /* Make sure state is CLKS_ON before returning */
1786 spin_lock_irqsave(hba->host->host_lock, flags);
1787 goto start;
1788 default:
1789 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1790 __func__, hba->clk_gating.state);
1791 break;
1792 }
1793 spin_unlock_irqrestore(hba->host->host_lock, flags);
1794 }
1795 EXPORT_SYMBOL_GPL(ufshcd_hold);
1796
ufshcd_gate_work(struct work_struct * work)1797 static void ufshcd_gate_work(struct work_struct *work)
1798 {
1799 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1800 clk_gating.gate_work.work);
1801 unsigned long flags;
1802 int ret;
1803
1804 spin_lock_irqsave(hba->host->host_lock, flags);
1805 /*
1806 * In case you are here to cancel this work the gating state
1807 * would be marked as REQ_CLKS_ON. In this case save time by
1808 * skipping the gating work and exit after changing the clock
1809 * state to CLKS_ON.
1810 */
1811 if (hba->clk_gating.is_suspended ||
1812 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1813 hba->clk_gating.state = CLKS_ON;
1814 trace_ufshcd_clk_gating(dev_name(hba->dev),
1815 hba->clk_gating.state);
1816 goto rel_lock;
1817 }
1818
1819 if (hba->clk_gating.active_reqs
1820 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1821 || hba->outstanding_reqs || hba->outstanding_tasks
1822 || hba->active_uic_cmd || hba->uic_async_done)
1823 goto rel_lock;
1824
1825 spin_unlock_irqrestore(hba->host->host_lock, flags);
1826
1827 /* put the link into hibern8 mode before turning off clocks */
1828 if (ufshcd_can_hibern8_during_gating(hba)) {
1829 ret = ufshcd_uic_hibern8_enter(hba);
1830 if (ret) {
1831 hba->clk_gating.state = CLKS_ON;
1832 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1833 __func__, ret);
1834 trace_ufshcd_clk_gating(dev_name(hba->dev),
1835 hba->clk_gating.state);
1836 goto out;
1837 }
1838 ufshcd_set_link_hibern8(hba);
1839 }
1840
1841 ufshcd_disable_irq(hba);
1842
1843 ufshcd_setup_clocks(hba, false);
1844
1845 /* Put the host controller in low power mode if possible */
1846 ufshcd_hba_vreg_set_lpm(hba);
1847 /*
1848 * In case you are here to cancel this work the gating state
1849 * would be marked as REQ_CLKS_ON. In this case keep the state
1850 * as REQ_CLKS_ON which would anyway imply that clocks are off
1851 * and a request to turn them on is pending. By doing this way,
1852 * we keep the state machine in tact and this would ultimately
1853 * prevent from doing cancel work multiple times when there are
1854 * new requests arriving before the current cancel work is done.
1855 */
1856 spin_lock_irqsave(hba->host->host_lock, flags);
1857 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1858 hba->clk_gating.state = CLKS_OFF;
1859 trace_ufshcd_clk_gating(dev_name(hba->dev),
1860 hba->clk_gating.state);
1861 }
1862 rel_lock:
1863 spin_unlock_irqrestore(hba->host->host_lock, flags);
1864 out:
1865 return;
1866 }
1867
1868 /* host lock must be held before calling this variant */
__ufshcd_release(struct ufs_hba * hba)1869 static void __ufshcd_release(struct ufs_hba *hba)
1870 {
1871 if (!ufshcd_is_clkgating_allowed(hba))
1872 return;
1873
1874 hba->clk_gating.active_reqs--;
1875
1876 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1877 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1878 hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
1879 hba->active_uic_cmd || hba->uic_async_done ||
1880 hba->clk_gating.state == CLKS_OFF)
1881 return;
1882
1883 hba->clk_gating.state = REQ_CLKS_OFF;
1884 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1885 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1886 &hba->clk_gating.gate_work,
1887 msecs_to_jiffies(hba->clk_gating.delay_ms));
1888 }
1889
ufshcd_release(struct ufs_hba * hba)1890 void ufshcd_release(struct ufs_hba *hba)
1891 {
1892 unsigned long flags;
1893
1894 spin_lock_irqsave(hba->host->host_lock, flags);
1895 __ufshcd_release(hba);
1896 spin_unlock_irqrestore(hba->host->host_lock, flags);
1897 }
1898 EXPORT_SYMBOL_GPL(ufshcd_release);
1899
ufshcd_clkgate_delay_show(struct device * dev,struct device_attribute * attr,char * buf)1900 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1901 struct device_attribute *attr, char *buf)
1902 {
1903 struct ufs_hba *hba = dev_get_drvdata(dev);
1904
1905 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1906 }
1907
ufshcd_clkgate_delay_set(struct device * dev,unsigned long value)1908 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
1909 {
1910 struct ufs_hba *hba = dev_get_drvdata(dev);
1911 unsigned long flags;
1912
1913 spin_lock_irqsave(hba->host->host_lock, flags);
1914 hba->clk_gating.delay_ms = value;
1915 spin_unlock_irqrestore(hba->host->host_lock, flags);
1916 }
1917 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
1918
ufshcd_clkgate_delay_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1919 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1920 struct device_attribute *attr, const char *buf, size_t count)
1921 {
1922 unsigned long value;
1923
1924 if (kstrtoul(buf, 0, &value))
1925 return -EINVAL;
1926
1927 ufshcd_clkgate_delay_set(dev, value);
1928 return count;
1929 }
1930
ufshcd_clkgate_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1931 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1932 struct device_attribute *attr, char *buf)
1933 {
1934 struct ufs_hba *hba = dev_get_drvdata(dev);
1935
1936 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1937 }
1938
ufshcd_clkgate_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1939 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1940 struct device_attribute *attr, const char *buf, size_t count)
1941 {
1942 struct ufs_hba *hba = dev_get_drvdata(dev);
1943 unsigned long flags;
1944 u32 value;
1945
1946 if (kstrtou32(buf, 0, &value))
1947 return -EINVAL;
1948
1949 value = !!value;
1950
1951 spin_lock_irqsave(hba->host->host_lock, flags);
1952 if (value == hba->clk_gating.is_enabled)
1953 goto out;
1954
1955 if (value)
1956 __ufshcd_release(hba);
1957 else
1958 hba->clk_gating.active_reqs++;
1959
1960 hba->clk_gating.is_enabled = value;
1961 out:
1962 spin_unlock_irqrestore(hba->host->host_lock, flags);
1963 return count;
1964 }
1965
ufshcd_init_clk_gating_sysfs(struct ufs_hba * hba)1966 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
1967 {
1968 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1969 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1970 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1971 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1972 hba->clk_gating.delay_attr.attr.mode = 0644;
1973 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1974 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1975
1976 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1977 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1978 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1979 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1980 hba->clk_gating.enable_attr.attr.mode = 0644;
1981 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1982 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1983 }
1984
ufshcd_remove_clk_gating_sysfs(struct ufs_hba * hba)1985 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
1986 {
1987 if (hba->clk_gating.delay_attr.attr.name)
1988 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1989 if (hba->clk_gating.enable_attr.attr.name)
1990 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1991 }
1992
ufshcd_init_clk_gating(struct ufs_hba * hba)1993 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1994 {
1995 char wq_name[sizeof("ufs_clk_gating_00")];
1996
1997 if (!ufshcd_is_clkgating_allowed(hba))
1998 return;
1999
2000 hba->clk_gating.state = CLKS_ON;
2001
2002 hba->clk_gating.delay_ms = 150;
2003 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
2004 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
2005
2006 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
2007 hba->host->host_no);
2008 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
2009 WQ_MEM_RECLAIM | WQ_HIGHPRI);
2010
2011 ufshcd_init_clk_gating_sysfs(hba);
2012
2013 hba->clk_gating.is_enabled = true;
2014 hba->clk_gating.is_initialized = true;
2015 }
2016
ufshcd_exit_clk_gating(struct ufs_hba * hba)2017 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2018 {
2019 if (!hba->clk_gating.is_initialized)
2020 return;
2021
2022 ufshcd_remove_clk_gating_sysfs(hba);
2023
2024 /* Ungate the clock if necessary. */
2025 ufshcd_hold(hba);
2026 hba->clk_gating.is_initialized = false;
2027 ufshcd_release(hba);
2028
2029 destroy_workqueue(hba->clk_gating.clk_gating_workq);
2030 }
2031
ufshcd_clk_scaling_start_busy(struct ufs_hba * hba)2032 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2033 {
2034 bool queue_resume_work = false;
2035 ktime_t curr_t = ktime_get();
2036 unsigned long flags;
2037
2038 if (!ufshcd_is_clkscaling_supported(hba))
2039 return;
2040
2041 spin_lock_irqsave(hba->host->host_lock, flags);
2042 if (!hba->clk_scaling.active_reqs++)
2043 queue_resume_work = true;
2044
2045 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
2046 spin_unlock_irqrestore(hba->host->host_lock, flags);
2047 return;
2048 }
2049
2050 if (queue_resume_work)
2051 queue_work(hba->clk_scaling.workq,
2052 &hba->clk_scaling.resume_work);
2053
2054 if (!hba->clk_scaling.window_start_t) {
2055 hba->clk_scaling.window_start_t = curr_t;
2056 hba->clk_scaling.tot_busy_t = 0;
2057 hba->clk_scaling.is_busy_started = false;
2058 }
2059
2060 if (!hba->clk_scaling.is_busy_started) {
2061 hba->clk_scaling.busy_start_t = curr_t;
2062 hba->clk_scaling.is_busy_started = true;
2063 }
2064 spin_unlock_irqrestore(hba->host->host_lock, flags);
2065 }
2066
ufshcd_clk_scaling_update_busy(struct ufs_hba * hba)2067 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2068 {
2069 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2070 unsigned long flags;
2071
2072 if (!ufshcd_is_clkscaling_supported(hba))
2073 return;
2074
2075 spin_lock_irqsave(hba->host->host_lock, flags);
2076 hba->clk_scaling.active_reqs--;
2077 if (!scaling->active_reqs && scaling->is_busy_started) {
2078 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2079 scaling->busy_start_t));
2080 scaling->busy_start_t = 0;
2081 scaling->is_busy_started = false;
2082 }
2083 spin_unlock_irqrestore(hba->host->host_lock, flags);
2084 }
2085
ufshcd_monitor_opcode2dir(u8 opcode)2086 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2087 {
2088 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2089 return READ;
2090 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2091 return WRITE;
2092 else
2093 return -EINVAL;
2094 }
2095
ufshcd_should_inform_monitor(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2096 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2097 struct ufshcd_lrb *lrbp)
2098 {
2099 const struct ufs_hba_monitor *m = &hba->monitor;
2100
2101 return (m->enabled && lrbp && lrbp->cmd &&
2102 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2103 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2104 }
2105
ufshcd_start_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2106 static void ufshcd_start_monitor(struct ufs_hba *hba,
2107 const struct ufshcd_lrb *lrbp)
2108 {
2109 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2110 unsigned long flags;
2111
2112 spin_lock_irqsave(hba->host->host_lock, flags);
2113 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2114 hba->monitor.busy_start_ts[dir] = ktime_get();
2115 spin_unlock_irqrestore(hba->host->host_lock, flags);
2116 }
2117
ufshcd_update_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2118 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp)
2119 {
2120 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2121 unsigned long flags;
2122
2123 spin_lock_irqsave(hba->host->host_lock, flags);
2124 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2125 const struct request *req = scsi_cmd_to_rq(lrbp->cmd);
2126 struct ufs_hba_monitor *m = &hba->monitor;
2127 ktime_t now, inc, lat;
2128
2129 now = lrbp->compl_time_stamp;
2130 inc = ktime_sub(now, m->busy_start_ts[dir]);
2131 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2132 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2133
2134 /* Update latencies */
2135 m->nr_req[dir]++;
2136 lat = ktime_sub(now, lrbp->issue_time_stamp);
2137 m->lat_sum[dir] += lat;
2138 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2139 m->lat_max[dir] = lat;
2140 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2141 m->lat_min[dir] = lat;
2142
2143 m->nr_queued[dir]--;
2144 /* Push forward the busy start of monitor */
2145 m->busy_start_ts[dir] = now;
2146 }
2147 spin_unlock_irqrestore(hba->host->host_lock, flags);
2148 }
2149
2150 /**
2151 * ufshcd_send_command - Send SCSI or device management commands
2152 * @hba: per adapter instance
2153 * @task_tag: Task tag of the command
2154 * @hwq: pointer to hardware queue instance
2155 */
2156 static inline
ufshcd_send_command(struct ufs_hba * hba,unsigned int task_tag,struct ufs_hw_queue * hwq)2157 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag,
2158 struct ufs_hw_queue *hwq)
2159 {
2160 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2161 unsigned long flags;
2162
2163 lrbp->issue_time_stamp = ktime_get();
2164 lrbp->issue_time_stamp_local_clock = local_clock();
2165 lrbp->compl_time_stamp = ktime_set(0, 0);
2166 lrbp->compl_time_stamp_local_clock = 0;
2167 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2168 ufshcd_clk_scaling_start_busy(hba);
2169 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2170 ufshcd_start_monitor(hba, lrbp);
2171
2172 if (is_mcq_enabled(hba)) {
2173 int utrd_size = sizeof(struct utp_transfer_req_desc);
2174 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr;
2175 struct utp_transfer_req_desc *dest;
2176
2177 spin_lock(&hwq->sq_lock);
2178 dest = hwq->sqe_base_addr + hwq->sq_tail_slot;
2179 memcpy(dest, src, utrd_size);
2180 ufshcd_inc_sq_tail(hwq);
2181 spin_unlock(&hwq->sq_lock);
2182 } else {
2183 spin_lock_irqsave(&hba->outstanding_lock, flags);
2184 if (hba->vops && hba->vops->setup_xfer_req)
2185 hba->vops->setup_xfer_req(hba, lrbp->task_tag,
2186 !!lrbp->cmd);
2187 __set_bit(lrbp->task_tag, &hba->outstanding_reqs);
2188 ufshcd_writel(hba, 1 << lrbp->task_tag,
2189 REG_UTP_TRANSFER_REQ_DOOR_BELL);
2190 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2191 }
2192 }
2193
2194 /**
2195 * ufshcd_copy_sense_data - Copy sense data in case of check condition
2196 * @lrbp: pointer to local reference block
2197 */
ufshcd_copy_sense_data(struct ufshcd_lrb * lrbp)2198 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2199 {
2200 u8 *const sense_buffer = lrbp->cmd->sense_buffer;
2201 u16 resp_len;
2202 int len;
2203
2204 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length);
2205 if (sense_buffer && resp_len) {
2206 int len_to_copy;
2207
2208 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2209 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2210
2211 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2212 len_to_copy);
2213 }
2214 }
2215
2216 /**
2217 * ufshcd_copy_query_response() - Copy the Query Response and the data
2218 * descriptor
2219 * @hba: per adapter instance
2220 * @lrbp: pointer to local reference block
2221 *
2222 * Return: 0 upon success; < 0 upon failure.
2223 */
2224 static
ufshcd_copy_query_response(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2225 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2226 {
2227 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2228
2229 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2230
2231 /* Get the descriptor */
2232 if (hba->dev_cmd.query.descriptor &&
2233 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2234 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2235 GENERAL_UPIU_REQUEST_SIZE;
2236 u16 resp_len;
2237 u16 buf_len;
2238
2239 /* data segment length */
2240 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
2241 .data_segment_length);
2242 buf_len = be16_to_cpu(
2243 hba->dev_cmd.query.request.upiu_req.length);
2244 if (likely(buf_len >= resp_len)) {
2245 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2246 } else {
2247 dev_warn(hba->dev,
2248 "%s: rsp size %d is bigger than buffer size %d",
2249 __func__, resp_len, buf_len);
2250 return -EINVAL;
2251 }
2252 }
2253
2254 return 0;
2255 }
2256
2257 /**
2258 * ufshcd_hba_capabilities - Read controller capabilities
2259 * @hba: per adapter instance
2260 *
2261 * Return: 0 on success, negative on error.
2262 */
ufshcd_hba_capabilities(struct ufs_hba * hba)2263 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2264 {
2265 int err;
2266
2267 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2268 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
2269 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
2270
2271 /* nutrs and nutmrs are 0 based values */
2272 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2273 hba->nutmrs =
2274 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2275 hba->reserved_slot = hba->nutrs - 1;
2276
2277 /* Read crypto capabilities */
2278 err = ufshcd_hba_init_crypto_capabilities(hba);
2279 if (err) {
2280 dev_err(hba->dev, "crypto setup failed\n");
2281 return err;
2282 }
2283
2284 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities);
2285 if (!hba->mcq_sup)
2286 return 0;
2287
2288 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
2289 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT,
2290 hba->mcq_capabilities);
2291
2292 return 0;
2293 }
2294
2295 /**
2296 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2297 * to accept UIC commands
2298 * @hba: per adapter instance
2299 *
2300 * Return: true on success, else false.
2301 */
ufshcd_ready_for_uic_cmd(struct ufs_hba * hba)2302 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2303 {
2304 u32 val;
2305 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
2306 500, UIC_CMD_TIMEOUT * 1000, false, hba,
2307 REG_CONTROLLER_STATUS);
2308 return ret == 0 ? true : false;
2309 }
2310
2311 /**
2312 * ufshcd_get_upmcrs - Get the power mode change request status
2313 * @hba: Pointer to adapter instance
2314 *
2315 * This function gets the UPMCRS field of HCS register
2316 *
2317 * Return: value of UPMCRS field.
2318 */
ufshcd_get_upmcrs(struct ufs_hba * hba)2319 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2320 {
2321 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2322 }
2323
2324 /**
2325 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2326 * @hba: per adapter instance
2327 * @uic_cmd: UIC command
2328 */
2329 static inline void
ufshcd_dispatch_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2330 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2331 {
2332 lockdep_assert_held(&hba->uic_cmd_mutex);
2333
2334 WARN_ON(hba->active_uic_cmd);
2335
2336 hba->active_uic_cmd = uic_cmd;
2337
2338 /* Write Args */
2339 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2340 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2341 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2342
2343 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2344
2345 /* Write UIC Cmd */
2346 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2347 REG_UIC_COMMAND);
2348 }
2349
2350 /**
2351 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2352 * @hba: per adapter instance
2353 * @uic_cmd: UIC command
2354 *
2355 * Return: 0 only if success.
2356 */
2357 static int
ufshcd_wait_for_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2358 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2359 {
2360 int ret;
2361 unsigned long flags;
2362
2363 lockdep_assert_held(&hba->uic_cmd_mutex);
2364
2365 if (wait_for_completion_timeout(&uic_cmd->done,
2366 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2367 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2368 } else {
2369 ret = -ETIMEDOUT;
2370 dev_err(hba->dev,
2371 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2372 uic_cmd->command, uic_cmd->argument3);
2373
2374 if (!uic_cmd->cmd_active) {
2375 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2376 __func__);
2377 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2378 }
2379 }
2380
2381 spin_lock_irqsave(hba->host->host_lock, flags);
2382 hba->active_uic_cmd = NULL;
2383 spin_unlock_irqrestore(hba->host->host_lock, flags);
2384
2385 return ret;
2386 }
2387
2388 /**
2389 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2390 * @hba: per adapter instance
2391 * @uic_cmd: UIC command
2392 * @completion: initialize the completion only if this is set to true
2393 *
2394 * Return: 0 only if success.
2395 */
2396 static int
__ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd,bool completion)2397 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2398 bool completion)
2399 {
2400 lockdep_assert_held(&hba->uic_cmd_mutex);
2401
2402 if (!ufshcd_ready_for_uic_cmd(hba)) {
2403 dev_err(hba->dev,
2404 "Controller not ready to accept UIC commands\n");
2405 return -EIO;
2406 }
2407
2408 if (completion)
2409 init_completion(&uic_cmd->done);
2410
2411 uic_cmd->cmd_active = 1;
2412 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2413
2414 return 0;
2415 }
2416
2417 /**
2418 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2419 * @hba: per adapter instance
2420 * @uic_cmd: UIC command
2421 *
2422 * Return: 0 only if success.
2423 */
ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2424 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2425 {
2426 int ret;
2427
2428 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2429 return 0;
2430
2431 ufshcd_hold(hba);
2432 mutex_lock(&hba->uic_cmd_mutex);
2433 ufshcd_add_delay_before_dme_cmd(hba);
2434
2435 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2436 if (!ret)
2437 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2438
2439 mutex_unlock(&hba->uic_cmd_mutex);
2440
2441 ufshcd_release(hba);
2442 return ret;
2443 }
2444
2445 /**
2446 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format)
2447 * @hba: per-adapter instance
2448 * @lrbp: pointer to local reference block
2449 * @sg_entries: The number of sg lists actually used
2450 * @sg_list: Pointer to SG list
2451 */
ufshcd_sgl_to_prdt(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int sg_entries,struct scatterlist * sg_list)2452 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries,
2453 struct scatterlist *sg_list)
2454 {
2455 struct ufshcd_sg_entry *prd;
2456 struct scatterlist *sg;
2457 int i;
2458
2459 if (sg_entries) {
2460
2461 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2462 lrbp->utr_descriptor_ptr->prd_table_length =
2463 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba));
2464 else
2465 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries);
2466
2467 prd = lrbp->ucd_prdt_ptr;
2468
2469 for_each_sg(sg_list, sg, sg_entries, i) {
2470 const unsigned int len = sg_dma_len(sg);
2471
2472 /*
2473 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2474 * based value that indicates the length, in bytes, of
2475 * the data block. A maximum of length of 256KB may
2476 * exist for any entry. Bits 1:0 of this field shall be
2477 * 11b to indicate Dword granularity. A value of '3'
2478 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2479 */
2480 WARN_ONCE(len > SZ_256K, "len = %#x\n", len);
2481 prd->size = cpu_to_le32(len - 1);
2482 prd->addr = cpu_to_le64(sg->dma_address);
2483 prd->reserved = 0;
2484 prd = (void *)prd + ufshcd_sg_entry_size(hba);
2485 }
2486 } else {
2487 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2488 }
2489 }
2490
2491 /**
2492 * ufshcd_map_sg - Map scatter-gather list to prdt
2493 * @hba: per adapter instance
2494 * @lrbp: pointer to local reference block
2495 *
2496 * Return: 0 in case of success, non-zero value in case of failure.
2497 */
ufshcd_map_sg(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2498 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2499 {
2500 struct scsi_cmnd *cmd = lrbp->cmd;
2501 int sg_segments = scsi_dma_map(cmd);
2502
2503 if (sg_segments < 0)
2504 return sg_segments;
2505
2506 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd));
2507
2508 return 0;
2509 }
2510
2511 /**
2512 * ufshcd_enable_intr - enable interrupts
2513 * @hba: per adapter instance
2514 * @intrs: interrupt bits
2515 */
ufshcd_enable_intr(struct ufs_hba * hba,u32 intrs)2516 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2517 {
2518 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2519
2520 if (hba->ufs_version == ufshci_version(1, 0)) {
2521 u32 rw;
2522 rw = set & INTERRUPT_MASK_RW_VER_10;
2523 set = rw | ((set ^ intrs) & intrs);
2524 } else {
2525 set |= intrs;
2526 }
2527
2528 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2529 }
2530
2531 /**
2532 * ufshcd_disable_intr - disable interrupts
2533 * @hba: per adapter instance
2534 * @intrs: interrupt bits
2535 */
ufshcd_disable_intr(struct ufs_hba * hba,u32 intrs)2536 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2537 {
2538 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2539
2540 if (hba->ufs_version == ufshci_version(1, 0)) {
2541 u32 rw;
2542 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2543 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2544 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2545
2546 } else {
2547 set &= ~intrs;
2548 }
2549
2550 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2551 }
2552
2553 /**
2554 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request
2555 * descriptor according to request
2556 * @lrbp: pointer to local reference block
2557 * @upiu_flags: flags required in the header
2558 * @cmd_dir: requests data direction
2559 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments)
2560 */
ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb * lrbp,u8 * upiu_flags,enum dma_data_direction cmd_dir,int ehs_length)2561 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags,
2562 enum dma_data_direction cmd_dir, int ehs_length)
2563 {
2564 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2565 struct request_desc_header *h = &req_desc->header;
2566 enum utp_data_direction data_direction;
2567
2568 *h = (typeof(*h)){ };
2569
2570 if (cmd_dir == DMA_FROM_DEVICE) {
2571 data_direction = UTP_DEVICE_TO_HOST;
2572 *upiu_flags = UPIU_CMD_FLAGS_READ;
2573 } else if (cmd_dir == DMA_TO_DEVICE) {
2574 data_direction = UTP_HOST_TO_DEVICE;
2575 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2576 } else {
2577 data_direction = UTP_NO_DATA_TRANSFER;
2578 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2579 }
2580
2581 h->command_type = lrbp->command_type;
2582 h->data_direction = data_direction;
2583 h->ehs_length = ehs_length;
2584
2585 if (lrbp->intr_cmd)
2586 h->interrupt = 1;
2587
2588 /* Prepare crypto related dwords */
2589 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h);
2590
2591 /*
2592 * assigning invalid value for command status. Controller
2593 * updates OCS on command completion, with the command
2594 * status
2595 */
2596 h->ocs = OCS_INVALID_COMMAND_STATUS;
2597
2598 req_desc->prd_table_length = 0;
2599 }
2600
2601 /**
2602 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2603 * for scsi commands
2604 * @lrbp: local reference block pointer
2605 * @upiu_flags: flags
2606 */
2607 static
ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb * lrbp,u8 upiu_flags)2608 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2609 {
2610 struct scsi_cmnd *cmd = lrbp->cmd;
2611 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2612 unsigned short cdb_len;
2613
2614 ucd_req_ptr->header = (struct utp_upiu_header){
2615 .transaction_code = UPIU_TRANSACTION_COMMAND,
2616 .flags = upiu_flags,
2617 .lun = lrbp->lun,
2618 .task_tag = lrbp->task_tag,
2619 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI,
2620 };
2621
2622 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2623
2624 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2625 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2626 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2627
2628 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2629 }
2630
2631 /**
2632 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request
2633 * @hba: UFS hba
2634 * @lrbp: local reference block pointer
2635 * @upiu_flags: flags
2636 */
ufshcd_prepare_utp_query_req_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,u8 upiu_flags)2637 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2638 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2639 {
2640 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2641 struct ufs_query *query = &hba->dev_cmd.query;
2642 u16 len = be16_to_cpu(query->request.upiu_req.length);
2643
2644 /* Query request header */
2645 ucd_req_ptr->header = (struct utp_upiu_header){
2646 .transaction_code = UPIU_TRANSACTION_QUERY_REQ,
2647 .flags = upiu_flags,
2648 .lun = lrbp->lun,
2649 .task_tag = lrbp->task_tag,
2650 .query_function = query->request.query_func,
2651 /* Data segment length only need for WRITE_DESC */
2652 .data_segment_length =
2653 query->request.upiu_req.opcode ==
2654 UPIU_QUERY_OPCODE_WRITE_DESC ?
2655 cpu_to_be16(len) :
2656 0,
2657 };
2658
2659 /* Copy the Query Request buffer as is */
2660 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2661 QUERY_OSF_SIZE);
2662
2663 /* Copy the Descriptor */
2664 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2665 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2666
2667 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2668 }
2669
ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb * lrbp)2670 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2671 {
2672 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2673
2674 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2675
2676 ucd_req_ptr->header = (struct utp_upiu_header){
2677 .transaction_code = UPIU_TRANSACTION_NOP_OUT,
2678 .task_tag = lrbp->task_tag,
2679 };
2680
2681 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2682 }
2683
2684 /**
2685 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2686 * for Device Management Purposes
2687 * @hba: per adapter instance
2688 * @lrbp: pointer to local reference block
2689 *
2690 * Return: 0 upon success; < 0 upon failure.
2691 */
ufshcd_compose_devman_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2692 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2693 struct ufshcd_lrb *lrbp)
2694 {
2695 u8 upiu_flags;
2696 int ret = 0;
2697
2698 if (hba->ufs_version <= ufshci_version(1, 1))
2699 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2700 else
2701 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2702
2703 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
2704 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2705 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2706 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2707 ufshcd_prepare_utp_nop_upiu(lrbp);
2708 else
2709 ret = -EINVAL;
2710
2711 return ret;
2712 }
2713
2714 /**
2715 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2716 * for SCSI Purposes
2717 * @hba: per adapter instance
2718 * @lrbp: pointer to local reference block
2719 *
2720 * Return: 0 upon success; < 0 upon failure.
2721 */
ufshcd_comp_scsi_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2722 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2723 {
2724 u8 upiu_flags;
2725 int ret = 0;
2726
2727 if (hba->ufs_version <= ufshci_version(1, 1))
2728 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2729 else
2730 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2731
2732 if (likely(lrbp->cmd)) {
2733 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0);
2734 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2735 } else {
2736 ret = -EINVAL;
2737 }
2738
2739 return ret;
2740 }
2741
2742 /**
2743 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2744 * @upiu_wlun_id: UPIU W-LUN id
2745 *
2746 * Return: SCSI W-LUN id.
2747 */
ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)2748 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2749 {
2750 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2751 }
2752
is_device_wlun(struct scsi_device * sdev)2753 static inline bool is_device_wlun(struct scsi_device *sdev)
2754 {
2755 return sdev->lun ==
2756 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2757 }
2758
2759 /*
2760 * Associate the UFS controller queue with the default and poll HCTX types.
2761 * Initialize the mq_map[] arrays.
2762 */
ufshcd_map_queues(struct Scsi_Host * shost)2763 static void ufshcd_map_queues(struct Scsi_Host *shost)
2764 {
2765 struct ufs_hba *hba = shost_priv(shost);
2766 int i, queue_offset = 0;
2767
2768 if (!is_mcq_supported(hba)) {
2769 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1;
2770 hba->nr_queues[HCTX_TYPE_READ] = 0;
2771 hba->nr_queues[HCTX_TYPE_POLL] = 1;
2772 hba->nr_hw_queues = 1;
2773 }
2774
2775 for (i = 0; i < shost->nr_maps; i++) {
2776 struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2777
2778 map->nr_queues = hba->nr_queues[i];
2779 if (!map->nr_queues)
2780 continue;
2781 map->queue_offset = queue_offset;
2782 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba))
2783 map->queue_offset = 0;
2784
2785 blk_mq_map_queues(map);
2786 queue_offset += map->nr_queues;
2787 }
2788 }
2789
ufshcd_init_lrb(struct ufs_hba * hba,struct ufshcd_lrb * lrb,int i)2790 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2791 {
2792 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr +
2793 i * ufshcd_get_ucd_size(hba);
2794 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2795 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2796 i * ufshcd_get_ucd_size(hba);
2797 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2798 response_upiu);
2799 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2800
2801 lrb->utr_descriptor_ptr = utrdlp + i;
2802 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2803 i * sizeof(struct utp_transfer_req_desc);
2804 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu;
2805 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2806 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
2807 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2808 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
2809 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2810 }
2811
2812 /**
2813 * ufshcd_queuecommand - main entry point for SCSI requests
2814 * @host: SCSI host pointer
2815 * @cmd: command from SCSI Midlayer
2816 *
2817 * Return: 0 for success, non-zero in case of failure.
2818 */
ufshcd_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)2819 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2820 {
2821 struct ufs_hba *hba = shost_priv(host);
2822 int tag = scsi_cmd_to_rq(cmd)->tag;
2823 struct ufshcd_lrb *lrbp;
2824 int err = 0;
2825 struct ufs_hw_queue *hwq = NULL;
2826
2827 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag);
2828
2829 switch (hba->ufshcd_state) {
2830 case UFSHCD_STATE_OPERATIONAL:
2831 break;
2832 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2833 /*
2834 * SCSI error handler can call ->queuecommand() while UFS error
2835 * handler is in progress. Error interrupts could change the
2836 * state from UFSHCD_STATE_RESET to
2837 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2838 * being issued in that case.
2839 */
2840 if (ufshcd_eh_in_progress(hba)) {
2841 err = SCSI_MLQUEUE_HOST_BUSY;
2842 goto out;
2843 }
2844 break;
2845 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2846 /*
2847 * pm_runtime_get_sync() is used at error handling preparation
2848 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2849 * PM ops, it can never be finished if we let SCSI layer keep
2850 * retrying it, which gets err handler stuck forever. Neither
2851 * can we let the scsi cmd pass through, because UFS is in bad
2852 * state, the scsi cmd may eventually time out, which will get
2853 * err handler blocked for too long. So, just fail the scsi cmd
2854 * sent from PM ops, err handler can recover PM error anyways.
2855 */
2856 if (hba->pm_op_in_progress) {
2857 hba->force_reset = true;
2858 set_host_byte(cmd, DID_BAD_TARGET);
2859 scsi_done(cmd);
2860 goto out;
2861 }
2862 fallthrough;
2863 case UFSHCD_STATE_RESET:
2864 err = SCSI_MLQUEUE_HOST_BUSY;
2865 goto out;
2866 case UFSHCD_STATE_ERROR:
2867 set_host_byte(cmd, DID_ERROR);
2868 scsi_done(cmd);
2869 goto out;
2870 }
2871
2872 hba->req_abort_count = 0;
2873
2874 ufshcd_hold(hba);
2875
2876 lrbp = &hba->lrb[tag];
2877 lrbp->cmd = cmd;
2878 lrbp->task_tag = tag;
2879 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2880 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
2881
2882 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
2883
2884 lrbp->req_abort_skip = false;
2885
2886 ufshcd_comp_scsi_upiu(hba, lrbp);
2887
2888 err = ufshcd_map_sg(hba, lrbp);
2889 if (err) {
2890 ufshcd_release(hba);
2891 goto out;
2892 }
2893
2894 if (is_mcq_enabled(hba))
2895 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd));
2896
2897 ufshcd_send_command(hba, tag, hwq);
2898
2899 out:
2900 if (ufs_trigger_eh()) {
2901 unsigned long flags;
2902
2903 spin_lock_irqsave(hba->host->host_lock, flags);
2904 ufshcd_schedule_eh_work(hba);
2905 spin_unlock_irqrestore(hba->host->host_lock, flags);
2906 }
2907
2908 return err;
2909 }
2910
ufshcd_compose_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,enum dev_cmd_type cmd_type,int tag)2911 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2912 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2913 {
2914 lrbp->cmd = NULL;
2915 lrbp->task_tag = tag;
2916 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2917 lrbp->intr_cmd = true; /* No interrupt aggregation */
2918 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2919 hba->dev_cmd.type = cmd_type;
2920
2921 return ufshcd_compose_devman_upiu(hba, lrbp);
2922 }
2923
2924 /*
2925 * Check with the block layer if the command is inflight
2926 * @cmd: command to check.
2927 *
2928 * Return: true if command is inflight; false if not.
2929 */
ufshcd_cmd_inflight(struct scsi_cmnd * cmd)2930 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd)
2931 {
2932 struct request *rq;
2933
2934 if (!cmd)
2935 return false;
2936
2937 rq = scsi_cmd_to_rq(cmd);
2938 if (!blk_mq_request_started(rq))
2939 return false;
2940
2941 return true;
2942 }
2943
2944 /*
2945 * Clear the pending command in the controller and wait until
2946 * the controller confirms that the command has been cleared.
2947 * @hba: per adapter instance
2948 * @task_tag: The tag number of the command to be cleared.
2949 */
ufshcd_clear_cmd(struct ufs_hba * hba,u32 task_tag)2950 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag)
2951 {
2952 u32 mask;
2953 unsigned long flags;
2954 int err;
2955
2956 if (is_mcq_enabled(hba)) {
2957 /*
2958 * MCQ mode. Clean up the MCQ resources similar to
2959 * what the ufshcd_utrl_clear() does for SDB mode.
2960 */
2961 err = ufshcd_mcq_sq_cleanup(hba, task_tag);
2962 if (err) {
2963 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n",
2964 __func__, task_tag, err);
2965 return err;
2966 }
2967 return 0;
2968 }
2969
2970 mask = 1U << task_tag;
2971
2972 /* clear outstanding transaction before retry */
2973 spin_lock_irqsave(hba->host->host_lock, flags);
2974 ufshcd_utrl_clear(hba, mask);
2975 spin_unlock_irqrestore(hba->host->host_lock, flags);
2976
2977 /*
2978 * wait for h/w to clear corresponding bit in door-bell.
2979 * max. wait is 1 sec.
2980 */
2981 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
2982 mask, ~mask, 1000, 1000);
2983 }
2984
2985 /**
2986 * ufshcd_dev_cmd_completion() - handles device management command responses
2987 * @hba: per adapter instance
2988 * @lrbp: pointer to local reference block
2989 *
2990 * Return: 0 upon success; < 0 upon failure.
2991 */
2992 static int
ufshcd_dev_cmd_completion(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2993 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2994 {
2995 enum upiu_response_transaction resp;
2996 int err = 0;
2997
2998 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2999 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
3000
3001 switch (resp) {
3002 case UPIU_TRANSACTION_NOP_IN:
3003 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
3004 err = -EINVAL;
3005 dev_err(hba->dev, "%s: unexpected response %x\n",
3006 __func__, resp);
3007 }
3008 break;
3009 case UPIU_TRANSACTION_QUERY_RSP: {
3010 u8 response = lrbp->ucd_rsp_ptr->header.response;
3011
3012 if (response == 0)
3013 err = ufshcd_copy_query_response(hba, lrbp);
3014 break;
3015 }
3016 case UPIU_TRANSACTION_REJECT_UPIU:
3017 /* TODO: handle Reject UPIU Response */
3018 err = -EPERM;
3019 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
3020 __func__);
3021 break;
3022 case UPIU_TRANSACTION_RESPONSE:
3023 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) {
3024 err = -EINVAL;
3025 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp);
3026 }
3027 break;
3028 default:
3029 err = -EINVAL;
3030 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
3031 __func__, resp);
3032 break;
3033 }
3034
3035 return err;
3036 }
3037
ufshcd_wait_for_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int max_timeout)3038 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
3039 struct ufshcd_lrb *lrbp, int max_timeout)
3040 {
3041 unsigned long time_left = msecs_to_jiffies(max_timeout);
3042 unsigned long flags;
3043 bool pending;
3044 int err;
3045
3046 retry:
3047 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
3048 time_left);
3049
3050 if (likely(time_left)) {
3051 /*
3052 * The completion handler called complete() and the caller of
3053 * this function still owns the @lrbp tag so the code below does
3054 * not trigger any race conditions.
3055 */
3056 hba->dev_cmd.complete = NULL;
3057 err = ufshcd_get_tr_ocs(lrbp, NULL);
3058 if (!err)
3059 err = ufshcd_dev_cmd_completion(hba, lrbp);
3060 } else {
3061 err = -ETIMEDOUT;
3062 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
3063 __func__, lrbp->task_tag);
3064
3065 /* MCQ mode */
3066 if (is_mcq_enabled(hba)) {
3067 /* successfully cleared the command, retry if needed */
3068 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0)
3069 err = -EAGAIN;
3070 hba->dev_cmd.complete = NULL;
3071 return err;
3072 }
3073
3074 /* SDB mode */
3075 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) {
3076 /* successfully cleared the command, retry if needed */
3077 err = -EAGAIN;
3078 /*
3079 * Since clearing the command succeeded we also need to
3080 * clear the task tag bit from the outstanding_reqs
3081 * variable.
3082 */
3083 spin_lock_irqsave(&hba->outstanding_lock, flags);
3084 pending = test_bit(lrbp->task_tag,
3085 &hba->outstanding_reqs);
3086 if (pending) {
3087 hba->dev_cmd.complete = NULL;
3088 __clear_bit(lrbp->task_tag,
3089 &hba->outstanding_reqs);
3090 }
3091 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3092
3093 if (!pending) {
3094 /*
3095 * The completion handler ran while we tried to
3096 * clear the command.
3097 */
3098 time_left = 1;
3099 goto retry;
3100 }
3101 } else {
3102 dev_err(hba->dev, "%s: failed to clear tag %d\n",
3103 __func__, lrbp->task_tag);
3104
3105 spin_lock_irqsave(&hba->outstanding_lock, flags);
3106 pending = test_bit(lrbp->task_tag,
3107 &hba->outstanding_reqs);
3108 if (pending)
3109 hba->dev_cmd.complete = NULL;
3110 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3111
3112 if (!pending) {
3113 /*
3114 * The completion handler ran while we tried to
3115 * clear the command.
3116 */
3117 time_left = 1;
3118 goto retry;
3119 }
3120 }
3121 }
3122
3123 return err;
3124 }
3125
3126 /**
3127 * ufshcd_exec_dev_cmd - API for sending device management requests
3128 * @hba: UFS hba
3129 * @cmd_type: specifies the type (NOP, Query...)
3130 * @timeout: timeout in milliseconds
3131 *
3132 * Return: 0 upon success; < 0 upon failure.
3133 *
3134 * NOTE: Since there is only one available tag for device management commands,
3135 * it is expected you hold the hba->dev_cmd.lock mutex.
3136 */
ufshcd_exec_dev_cmd(struct ufs_hba * hba,enum dev_cmd_type cmd_type,int timeout)3137 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3138 enum dev_cmd_type cmd_type, int timeout)
3139 {
3140 DECLARE_COMPLETION_ONSTACK(wait);
3141 const u32 tag = hba->reserved_slot;
3142 struct ufshcd_lrb *lrbp;
3143 int err;
3144
3145 /* Protects use of hba->reserved_slot. */
3146 lockdep_assert_held(&hba->dev_cmd.lock);
3147
3148 down_read(&hba->clk_scaling_lock);
3149
3150 lrbp = &hba->lrb[tag];
3151 lrbp->cmd = NULL;
3152 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3153 if (unlikely(err))
3154 goto out;
3155
3156 hba->dev_cmd.complete = &wait;
3157
3158 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
3159
3160 ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
3161 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
3162 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3163 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
3164
3165 out:
3166 up_read(&hba->clk_scaling_lock);
3167 return err;
3168 }
3169
3170 /**
3171 * ufshcd_init_query() - init the query response and request parameters
3172 * @hba: per-adapter instance
3173 * @request: address of the request pointer to be initialized
3174 * @response: address of the response pointer to be initialized
3175 * @opcode: operation to perform
3176 * @idn: flag idn to access
3177 * @index: LU number to access
3178 * @selector: query/flag/descriptor further identification
3179 */
ufshcd_init_query(struct ufs_hba * hba,struct ufs_query_req ** request,struct ufs_query_res ** response,enum query_opcode opcode,u8 idn,u8 index,u8 selector)3180 static inline void ufshcd_init_query(struct ufs_hba *hba,
3181 struct ufs_query_req **request, struct ufs_query_res **response,
3182 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3183 {
3184 *request = &hba->dev_cmd.query.request;
3185 *response = &hba->dev_cmd.query.response;
3186 memset(*request, 0, sizeof(struct ufs_query_req));
3187 memset(*response, 0, sizeof(struct ufs_query_res));
3188 (*request)->upiu_req.opcode = opcode;
3189 (*request)->upiu_req.idn = idn;
3190 (*request)->upiu_req.index = index;
3191 (*request)->upiu_req.selector = selector;
3192 }
3193
ufshcd_query_flag_retry(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3194 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3195 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3196 {
3197 int ret;
3198 int retries;
3199
3200 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3201 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3202 if (ret)
3203 dev_dbg(hba->dev,
3204 "%s: failed with error %d, retries %d\n",
3205 __func__, ret, retries);
3206 else
3207 break;
3208 }
3209
3210 if (ret)
3211 dev_err(hba->dev,
3212 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n",
3213 __func__, opcode, idn, ret, retries);
3214 return ret;
3215 }
3216
3217 /**
3218 * ufshcd_query_flag() - API function for sending flag query requests
3219 * @hba: per-adapter instance
3220 * @opcode: flag query to perform
3221 * @idn: flag idn to access
3222 * @index: flag index to access
3223 * @flag_res: the flag value after the query request completes
3224 *
3225 * Return: 0 for success, non-zero in case of failure.
3226 */
ufshcd_query_flag(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3227 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3228 enum flag_idn idn, u8 index, bool *flag_res)
3229 {
3230 struct ufs_query_req *request = NULL;
3231 struct ufs_query_res *response = NULL;
3232 int err, selector = 0;
3233 int timeout = QUERY_REQ_TIMEOUT;
3234
3235 BUG_ON(!hba);
3236
3237 ufshcd_hold(hba);
3238 mutex_lock(&hba->dev_cmd.lock);
3239 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3240 selector);
3241
3242 switch (opcode) {
3243 case UPIU_QUERY_OPCODE_SET_FLAG:
3244 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3245 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3246 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3247 break;
3248 case UPIU_QUERY_OPCODE_READ_FLAG:
3249 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3250 if (!flag_res) {
3251 /* No dummy reads */
3252 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3253 __func__);
3254 err = -EINVAL;
3255 goto out_unlock;
3256 }
3257 break;
3258 default:
3259 dev_err(hba->dev,
3260 "%s: Expected query flag opcode but got = %d\n",
3261 __func__, opcode);
3262 err = -EINVAL;
3263 goto out_unlock;
3264 }
3265
3266 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3267
3268 if (err) {
3269 dev_err(hba->dev,
3270 "%s: Sending flag query for idn %d failed, err = %d\n",
3271 __func__, idn, err);
3272 goto out_unlock;
3273 }
3274
3275 if (flag_res)
3276 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3277 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3278
3279 out_unlock:
3280 mutex_unlock(&hba->dev_cmd.lock);
3281 ufshcd_release(hba);
3282 return err;
3283 }
3284
3285 /**
3286 * ufshcd_query_attr - API function for sending attribute requests
3287 * @hba: per-adapter instance
3288 * @opcode: attribute opcode
3289 * @idn: attribute idn to access
3290 * @index: index field
3291 * @selector: selector field
3292 * @attr_val: the attribute value after the query request completes
3293 *
3294 * Return: 0 for success, non-zero in case of failure.
3295 */
ufshcd_query_attr(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3296 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3297 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3298 {
3299 struct ufs_query_req *request = NULL;
3300 struct ufs_query_res *response = NULL;
3301 int err;
3302
3303 BUG_ON(!hba);
3304
3305 if (!attr_val) {
3306 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3307 __func__, opcode);
3308 return -EINVAL;
3309 }
3310
3311 ufshcd_hold(hba);
3312
3313 mutex_lock(&hba->dev_cmd.lock);
3314 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3315 selector);
3316
3317 switch (opcode) {
3318 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3319 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3320 request->upiu_req.value = cpu_to_be32(*attr_val);
3321 break;
3322 case UPIU_QUERY_OPCODE_READ_ATTR:
3323 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3324 break;
3325 default:
3326 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3327 __func__, opcode);
3328 err = -EINVAL;
3329 goto out_unlock;
3330 }
3331
3332 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3333
3334 if (err) {
3335 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3336 __func__, opcode, idn, index, err);
3337 goto out_unlock;
3338 }
3339
3340 *attr_val = be32_to_cpu(response->upiu_res.value);
3341
3342 out_unlock:
3343 mutex_unlock(&hba->dev_cmd.lock);
3344 ufshcd_release(hba);
3345 return err;
3346 }
3347
3348 /**
3349 * ufshcd_query_attr_retry() - API function for sending query
3350 * attribute with retries
3351 * @hba: per-adapter instance
3352 * @opcode: attribute opcode
3353 * @idn: attribute idn to access
3354 * @index: index field
3355 * @selector: selector field
3356 * @attr_val: the attribute value after the query request
3357 * completes
3358 *
3359 * Return: 0 for success, non-zero in case of failure.
3360 */
ufshcd_query_attr_retry(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3361 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3362 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3363 u32 *attr_val)
3364 {
3365 int ret = 0;
3366 u32 retries;
3367
3368 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3369 ret = ufshcd_query_attr(hba, opcode, idn, index,
3370 selector, attr_val);
3371 if (ret)
3372 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3373 __func__, ret, retries);
3374 else
3375 break;
3376 }
3377
3378 if (ret)
3379 dev_err(hba->dev,
3380 "%s: query attribute, idn %d, failed with error %d after %d retries\n",
3381 __func__, idn, ret, QUERY_REQ_RETRIES);
3382 return ret;
3383 }
3384
__ufshcd_query_descriptor(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3385 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3386 enum query_opcode opcode, enum desc_idn idn, u8 index,
3387 u8 selector, u8 *desc_buf, int *buf_len)
3388 {
3389 struct ufs_query_req *request = NULL;
3390 struct ufs_query_res *response = NULL;
3391 int err;
3392
3393 BUG_ON(!hba);
3394
3395 if (!desc_buf) {
3396 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3397 __func__, opcode);
3398 return -EINVAL;
3399 }
3400
3401 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3402 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3403 __func__, *buf_len);
3404 return -EINVAL;
3405 }
3406
3407 ufshcd_hold(hba);
3408
3409 mutex_lock(&hba->dev_cmd.lock);
3410 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3411 selector);
3412 hba->dev_cmd.query.descriptor = desc_buf;
3413 request->upiu_req.length = cpu_to_be16(*buf_len);
3414
3415 switch (opcode) {
3416 case UPIU_QUERY_OPCODE_WRITE_DESC:
3417 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3418 break;
3419 case UPIU_QUERY_OPCODE_READ_DESC:
3420 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3421 break;
3422 default:
3423 dev_err(hba->dev,
3424 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3425 __func__, opcode);
3426 err = -EINVAL;
3427 goto out_unlock;
3428 }
3429
3430 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3431
3432 if (err) {
3433 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3434 __func__, opcode, idn, index, err);
3435 goto out_unlock;
3436 }
3437
3438 *buf_len = be16_to_cpu(response->upiu_res.length);
3439
3440 out_unlock:
3441 hba->dev_cmd.query.descriptor = NULL;
3442 mutex_unlock(&hba->dev_cmd.lock);
3443 ufshcd_release(hba);
3444 return err;
3445 }
3446
3447 /**
3448 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3449 * @hba: per-adapter instance
3450 * @opcode: attribute opcode
3451 * @idn: attribute idn to access
3452 * @index: index field
3453 * @selector: selector field
3454 * @desc_buf: the buffer that contains the descriptor
3455 * @buf_len: length parameter passed to the device
3456 *
3457 * The buf_len parameter will contain, on return, the length parameter
3458 * received on the response.
3459 *
3460 * Return: 0 for success, non-zero in case of failure.
3461 */
ufshcd_query_descriptor_retry(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3462 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3463 enum query_opcode opcode,
3464 enum desc_idn idn, u8 index,
3465 u8 selector,
3466 u8 *desc_buf, int *buf_len)
3467 {
3468 int err;
3469 int retries;
3470
3471 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3472 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3473 selector, desc_buf, buf_len);
3474 if (!err || err == -EINVAL)
3475 break;
3476 }
3477
3478 return err;
3479 }
3480
3481 /**
3482 * ufshcd_read_desc_param - read the specified descriptor parameter
3483 * @hba: Pointer to adapter instance
3484 * @desc_id: descriptor idn value
3485 * @desc_index: descriptor index
3486 * @param_offset: offset of the parameter to read
3487 * @param_read_buf: pointer to buffer where parameter would be read
3488 * @param_size: sizeof(param_read_buf)
3489 *
3490 * Return: 0 in case of success, non-zero otherwise.
3491 */
ufshcd_read_desc_param(struct ufs_hba * hba,enum desc_idn desc_id,int desc_index,u8 param_offset,u8 * param_read_buf,u8 param_size)3492 int ufshcd_read_desc_param(struct ufs_hba *hba,
3493 enum desc_idn desc_id,
3494 int desc_index,
3495 u8 param_offset,
3496 u8 *param_read_buf,
3497 u8 param_size)
3498 {
3499 int ret;
3500 u8 *desc_buf;
3501 int buff_len = QUERY_DESC_MAX_SIZE;
3502 bool is_kmalloc = true;
3503
3504 /* Safety check */
3505 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3506 return -EINVAL;
3507
3508 /* Check whether we need temp memory */
3509 if (param_offset != 0 || param_size < buff_len) {
3510 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3511 if (!desc_buf)
3512 return -ENOMEM;
3513 } else {
3514 desc_buf = param_read_buf;
3515 is_kmalloc = false;
3516 }
3517
3518 /* Request for full descriptor */
3519 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3520 desc_id, desc_index, 0,
3521 desc_buf, &buff_len);
3522 if (ret) {
3523 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3524 __func__, desc_id, desc_index, param_offset, ret);
3525 goto out;
3526 }
3527
3528 /* Update descriptor length */
3529 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3530
3531 if (param_offset >= buff_len) {
3532 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3533 __func__, param_offset, desc_id, buff_len);
3534 ret = -EINVAL;
3535 goto out;
3536 }
3537
3538 /* Sanity check */
3539 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3540 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3541 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3542 ret = -EINVAL;
3543 goto out;
3544 }
3545
3546 if (is_kmalloc) {
3547 /* Make sure we don't copy more data than available */
3548 if (param_offset >= buff_len)
3549 ret = -EINVAL;
3550 else
3551 memcpy(param_read_buf, &desc_buf[param_offset],
3552 min_t(u32, param_size, buff_len - param_offset));
3553 }
3554 out:
3555 if (is_kmalloc)
3556 kfree(desc_buf);
3557 return ret;
3558 }
3559
3560 /**
3561 * struct uc_string_id - unicode string
3562 *
3563 * @len: size of this descriptor inclusive
3564 * @type: descriptor type
3565 * @uc: unicode string character
3566 */
3567 struct uc_string_id {
3568 u8 len;
3569 u8 type;
3570 wchar_t uc[];
3571 } __packed;
3572
3573 /* replace non-printable or non-ASCII characters with spaces */
ufshcd_remove_non_printable(u8 ch)3574 static inline char ufshcd_remove_non_printable(u8 ch)
3575 {
3576 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3577 }
3578
3579 /**
3580 * ufshcd_read_string_desc - read string descriptor
3581 * @hba: pointer to adapter instance
3582 * @desc_index: descriptor index
3583 * @buf: pointer to buffer where descriptor would be read,
3584 * the caller should free the memory.
3585 * @ascii: if true convert from unicode to ascii characters
3586 * null terminated string.
3587 *
3588 * Return:
3589 * * string size on success.
3590 * * -ENOMEM: on allocation failure
3591 * * -EINVAL: on a wrong parameter
3592 */
ufshcd_read_string_desc(struct ufs_hba * hba,u8 desc_index,u8 ** buf,bool ascii)3593 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3594 u8 **buf, bool ascii)
3595 {
3596 struct uc_string_id *uc_str;
3597 u8 *str;
3598 int ret;
3599
3600 if (!buf)
3601 return -EINVAL;
3602
3603 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3604 if (!uc_str)
3605 return -ENOMEM;
3606
3607 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3608 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3609 if (ret < 0) {
3610 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3611 QUERY_REQ_RETRIES, ret);
3612 str = NULL;
3613 goto out;
3614 }
3615
3616 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3617 dev_dbg(hba->dev, "String Desc is of zero length\n");
3618 str = NULL;
3619 ret = 0;
3620 goto out;
3621 }
3622
3623 if (ascii) {
3624 ssize_t ascii_len;
3625 int i;
3626 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3627 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3628 str = kzalloc(ascii_len, GFP_KERNEL);
3629 if (!str) {
3630 ret = -ENOMEM;
3631 goto out;
3632 }
3633
3634 /*
3635 * the descriptor contains string in UTF16 format
3636 * we need to convert to utf-8 so it can be displayed
3637 */
3638 ret = utf16s_to_utf8s(uc_str->uc,
3639 uc_str->len - QUERY_DESC_HDR_SIZE,
3640 UTF16_BIG_ENDIAN, str, ascii_len - 1);
3641
3642 /* replace non-printable or non-ASCII characters with spaces */
3643 for (i = 0; i < ret; i++)
3644 str[i] = ufshcd_remove_non_printable(str[i]);
3645
3646 str[ret++] = '\0';
3647
3648 } else {
3649 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3650 if (!str) {
3651 ret = -ENOMEM;
3652 goto out;
3653 }
3654 ret = uc_str->len;
3655 }
3656 out:
3657 *buf = str;
3658 kfree(uc_str);
3659 return ret;
3660 }
3661
3662 /**
3663 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3664 * @hba: Pointer to adapter instance
3665 * @lun: lun id
3666 * @param_offset: offset of the parameter to read
3667 * @param_read_buf: pointer to buffer where parameter would be read
3668 * @param_size: sizeof(param_read_buf)
3669 *
3670 * Return: 0 in case of success, non-zero otherwise.
3671 */
ufshcd_read_unit_desc_param(struct ufs_hba * hba,int lun,enum unit_desc_param param_offset,u8 * param_read_buf,u32 param_size)3672 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3673 int lun,
3674 enum unit_desc_param param_offset,
3675 u8 *param_read_buf,
3676 u32 param_size)
3677 {
3678 /*
3679 * Unit descriptors are only available for general purpose LUs (LUN id
3680 * from 0 to 7) and RPMB Well known LU.
3681 */
3682 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
3683 return -EOPNOTSUPP;
3684
3685 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3686 param_offset, param_read_buf, param_size);
3687 }
3688
ufshcd_get_ref_clk_gating_wait(struct ufs_hba * hba)3689 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3690 {
3691 int err = 0;
3692 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3693
3694 if (hba->dev_info.wspecversion >= 0x300) {
3695 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3696 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3697 &gating_wait);
3698 if (err)
3699 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3700 err, gating_wait);
3701
3702 if (gating_wait == 0) {
3703 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3704 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3705 gating_wait);
3706 }
3707
3708 hba->dev_info.clk_gating_wait_us = gating_wait;
3709 }
3710
3711 return err;
3712 }
3713
3714 /**
3715 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3716 * @hba: per adapter instance
3717 *
3718 * 1. Allocate DMA memory for Command Descriptor array
3719 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3720 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3721 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3722 * (UTMRDL)
3723 * 4. Allocate memory for local reference block(lrb).
3724 *
3725 * Return: 0 for success, non-zero in case of failure.
3726 */
ufshcd_memory_alloc(struct ufs_hba * hba)3727 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3728 {
3729 size_t utmrdl_size, utrdl_size, ucdl_size;
3730
3731 /* Allocate memory for UTP command descriptors */
3732 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs;
3733 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3734 ucdl_size,
3735 &hba->ucdl_dma_addr,
3736 GFP_KERNEL);
3737
3738 /*
3739 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3740 */
3741 if (!hba->ucdl_base_addr ||
3742 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) {
3743 dev_err(hba->dev,
3744 "Command Descriptor Memory allocation failed\n");
3745 goto out;
3746 }
3747
3748 /*
3749 * Allocate memory for UTP Transfer descriptors
3750 * UFSHCI requires 1KB alignment of UTRD
3751 */
3752 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3753 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3754 utrdl_size,
3755 &hba->utrdl_dma_addr,
3756 GFP_KERNEL);
3757 if (!hba->utrdl_base_addr ||
3758 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) {
3759 dev_err(hba->dev,
3760 "Transfer Descriptor Memory allocation failed\n");
3761 goto out;
3762 }
3763
3764 /*
3765 * Skip utmrdl allocation; it may have been
3766 * allocated during first pass and not released during
3767 * MCQ memory allocation.
3768 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq()
3769 */
3770 if (hba->utmrdl_base_addr)
3771 goto skip_utmrdl;
3772 /*
3773 * Allocate memory for UTP Task Management descriptors
3774 * UFSHCI requires 1KB alignment of UTMRD
3775 */
3776 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3777 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3778 utmrdl_size,
3779 &hba->utmrdl_dma_addr,
3780 GFP_KERNEL);
3781 if (!hba->utmrdl_base_addr ||
3782 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) {
3783 dev_err(hba->dev,
3784 "Task Management Descriptor Memory allocation failed\n");
3785 goto out;
3786 }
3787
3788 skip_utmrdl:
3789 /* Allocate memory for local reference block */
3790 hba->lrb = devm_kcalloc(hba->dev,
3791 hba->nutrs, sizeof(struct ufshcd_lrb),
3792 GFP_KERNEL);
3793 if (!hba->lrb) {
3794 dev_err(hba->dev, "LRB Memory allocation failed\n");
3795 goto out;
3796 }
3797 return 0;
3798 out:
3799 return -ENOMEM;
3800 }
3801
3802 /**
3803 * ufshcd_host_memory_configure - configure local reference block with
3804 * memory offsets
3805 * @hba: per adapter instance
3806 *
3807 * Configure Host memory space
3808 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3809 * address.
3810 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3811 * and PRDT offset.
3812 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3813 * into local reference block.
3814 */
ufshcd_host_memory_configure(struct ufs_hba * hba)3815 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3816 {
3817 struct utp_transfer_req_desc *utrdlp;
3818 dma_addr_t cmd_desc_dma_addr;
3819 dma_addr_t cmd_desc_element_addr;
3820 u16 response_offset;
3821 u16 prdt_offset;
3822 int cmd_desc_size;
3823 int i;
3824
3825 utrdlp = hba->utrdl_base_addr;
3826
3827 response_offset =
3828 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3829 prdt_offset =
3830 offsetof(struct utp_transfer_cmd_desc, prd_table);
3831
3832 cmd_desc_size = ufshcd_get_ucd_size(hba);
3833 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3834
3835 for (i = 0; i < hba->nutrs; i++) {
3836 /* Configure UTRD with command descriptor base address */
3837 cmd_desc_element_addr =
3838 (cmd_desc_dma_addr + (cmd_desc_size * i));
3839 utrdlp[i].command_desc_base_addr =
3840 cpu_to_le64(cmd_desc_element_addr);
3841
3842 /* Response upiu and prdt offset should be in double words */
3843 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3844 utrdlp[i].response_upiu_offset =
3845 cpu_to_le16(response_offset);
3846 utrdlp[i].prd_table_offset =
3847 cpu_to_le16(prdt_offset);
3848 utrdlp[i].response_upiu_length =
3849 cpu_to_le16(ALIGNED_UPIU_SIZE);
3850 } else {
3851 utrdlp[i].response_upiu_offset =
3852 cpu_to_le16(response_offset >> 2);
3853 utrdlp[i].prd_table_offset =
3854 cpu_to_le16(prdt_offset >> 2);
3855 utrdlp[i].response_upiu_length =
3856 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3857 }
3858
3859 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3860 }
3861 }
3862
3863 /**
3864 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3865 * @hba: per adapter instance
3866 *
3867 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3868 * in order to initialize the Unipro link startup procedure.
3869 * Once the Unipro links are up, the device connected to the controller
3870 * is detected.
3871 *
3872 * Return: 0 on success, non-zero value on failure.
3873 */
ufshcd_dme_link_startup(struct ufs_hba * hba)3874 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3875 {
3876 struct uic_command uic_cmd = {0};
3877 int ret;
3878
3879 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3880
3881 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3882 if (ret)
3883 dev_dbg(hba->dev,
3884 "dme-link-startup: error code %d\n", ret);
3885 return ret;
3886 }
3887 /**
3888 * ufshcd_dme_reset - UIC command for DME_RESET
3889 * @hba: per adapter instance
3890 *
3891 * DME_RESET command is issued in order to reset UniPro stack.
3892 * This function now deals with cold reset.
3893 *
3894 * Return: 0 on success, non-zero value on failure.
3895 */
ufshcd_dme_reset(struct ufs_hba * hba)3896 static int ufshcd_dme_reset(struct ufs_hba *hba)
3897 {
3898 struct uic_command uic_cmd = {0};
3899 int ret;
3900
3901 uic_cmd.command = UIC_CMD_DME_RESET;
3902
3903 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3904 if (ret)
3905 dev_err(hba->dev,
3906 "dme-reset: error code %d\n", ret);
3907
3908 return ret;
3909 }
3910
ufshcd_dme_configure_adapt(struct ufs_hba * hba,int agreed_gear,int adapt_val)3911 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3912 int agreed_gear,
3913 int adapt_val)
3914 {
3915 int ret;
3916
3917 if (agreed_gear < UFS_HS_G4)
3918 adapt_val = PA_NO_ADAPT;
3919
3920 ret = ufshcd_dme_set(hba,
3921 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3922 adapt_val);
3923 return ret;
3924 }
3925 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3926
3927 /**
3928 * ufshcd_dme_enable - UIC command for DME_ENABLE
3929 * @hba: per adapter instance
3930 *
3931 * DME_ENABLE command is issued in order to enable UniPro stack.
3932 *
3933 * Return: 0 on success, non-zero value on failure.
3934 */
ufshcd_dme_enable(struct ufs_hba * hba)3935 static int ufshcd_dme_enable(struct ufs_hba *hba)
3936 {
3937 struct uic_command uic_cmd = {0};
3938 int ret;
3939
3940 uic_cmd.command = UIC_CMD_DME_ENABLE;
3941
3942 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3943 if (ret)
3944 dev_err(hba->dev,
3945 "dme-enable: error code %d\n", ret);
3946
3947 return ret;
3948 }
3949
ufshcd_add_delay_before_dme_cmd(struct ufs_hba * hba)3950 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3951 {
3952 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3953 unsigned long min_sleep_time_us;
3954
3955 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3956 return;
3957
3958 /*
3959 * last_dme_cmd_tstamp will be 0 only for 1st call to
3960 * this function
3961 */
3962 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3963 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3964 } else {
3965 unsigned long delta =
3966 (unsigned long) ktime_to_us(
3967 ktime_sub(ktime_get(),
3968 hba->last_dme_cmd_tstamp));
3969
3970 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3971 min_sleep_time_us =
3972 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3973 else
3974 min_sleep_time_us = 0; /* no more delay required */
3975 }
3976
3977 if (min_sleep_time_us > 0) {
3978 /* allow sleep for extra 50us if needed */
3979 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3980 }
3981
3982 /* update the last_dme_cmd_tstamp */
3983 hba->last_dme_cmd_tstamp = ktime_get();
3984 }
3985
3986 /**
3987 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3988 * @hba: per adapter instance
3989 * @attr_sel: uic command argument1
3990 * @attr_set: attribute set type as uic command argument2
3991 * @mib_val: setting value as uic command argument3
3992 * @peer: indicate whether peer or local
3993 *
3994 * Return: 0 on success, non-zero value on failure.
3995 */
ufshcd_dme_set_attr(struct ufs_hba * hba,u32 attr_sel,u8 attr_set,u32 mib_val,u8 peer)3996 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3997 u8 attr_set, u32 mib_val, u8 peer)
3998 {
3999 struct uic_command uic_cmd = {0};
4000 static const char *const action[] = {
4001 "dme-set",
4002 "dme-peer-set"
4003 };
4004 const char *set = action[!!peer];
4005 int ret;
4006 int retries = UFS_UIC_COMMAND_RETRIES;
4007
4008 uic_cmd.command = peer ?
4009 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
4010 uic_cmd.argument1 = attr_sel;
4011 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
4012 uic_cmd.argument3 = mib_val;
4013
4014 do {
4015 /* for peer attributes we retry upon failure */
4016 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4017 if (ret)
4018 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
4019 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
4020 } while (ret && peer && --retries);
4021
4022 if (ret)
4023 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
4024 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
4025 UFS_UIC_COMMAND_RETRIES - retries);
4026
4027 return ret;
4028 }
4029 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
4030
4031 /**
4032 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
4033 * @hba: per adapter instance
4034 * @attr_sel: uic command argument1
4035 * @mib_val: the value of the attribute as returned by the UIC command
4036 * @peer: indicate whether peer or local
4037 *
4038 * Return: 0 on success, non-zero value on failure.
4039 */
ufshcd_dme_get_attr(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val,u8 peer)4040 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
4041 u32 *mib_val, u8 peer)
4042 {
4043 struct uic_command uic_cmd = {0};
4044 static const char *const action[] = {
4045 "dme-get",
4046 "dme-peer-get"
4047 };
4048 const char *get = action[!!peer];
4049 int ret;
4050 int retries = UFS_UIC_COMMAND_RETRIES;
4051 struct ufs_pa_layer_attr orig_pwr_info;
4052 struct ufs_pa_layer_attr temp_pwr_info;
4053 bool pwr_mode_change = false;
4054
4055 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
4056 orig_pwr_info = hba->pwr_info;
4057 temp_pwr_info = orig_pwr_info;
4058
4059 if (orig_pwr_info.pwr_tx == FAST_MODE ||
4060 orig_pwr_info.pwr_rx == FAST_MODE) {
4061 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
4062 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
4063 pwr_mode_change = true;
4064 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
4065 orig_pwr_info.pwr_rx == SLOW_MODE) {
4066 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
4067 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
4068 pwr_mode_change = true;
4069 }
4070 if (pwr_mode_change) {
4071 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
4072 if (ret)
4073 goto out;
4074 }
4075 }
4076
4077 uic_cmd.command = peer ?
4078 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
4079 uic_cmd.argument1 = attr_sel;
4080
4081 do {
4082 /* for peer attributes we retry upon failure */
4083 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4084 if (ret)
4085 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4086 get, UIC_GET_ATTR_ID(attr_sel), ret);
4087 } while (ret && peer && --retries);
4088
4089 if (ret)
4090 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
4091 get, UIC_GET_ATTR_ID(attr_sel),
4092 UFS_UIC_COMMAND_RETRIES - retries);
4093
4094 if (mib_val && !ret)
4095 *mib_val = uic_cmd.argument3;
4096
4097 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4098 && pwr_mode_change)
4099 ufshcd_change_power_mode(hba, &orig_pwr_info);
4100 out:
4101 return ret;
4102 }
4103 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4104
4105 /**
4106 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4107 * state) and waits for it to take effect.
4108 *
4109 * @hba: per adapter instance
4110 * @cmd: UIC command to execute
4111 *
4112 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4113 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4114 * and device UniPro link and hence it's final completion would be indicated by
4115 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4116 * addition to normal UIC command completion Status (UCCS). This function only
4117 * returns after the relevant status bits indicate the completion.
4118 *
4119 * Return: 0 on success, non-zero value on failure.
4120 */
ufshcd_uic_pwr_ctrl(struct ufs_hba * hba,struct uic_command * cmd)4121 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
4122 {
4123 DECLARE_COMPLETION_ONSTACK(uic_async_done);
4124 unsigned long flags;
4125 u8 status;
4126 int ret;
4127 bool reenable_intr = false;
4128
4129 mutex_lock(&hba->uic_cmd_mutex);
4130 ufshcd_add_delay_before_dme_cmd(hba);
4131
4132 spin_lock_irqsave(hba->host->host_lock, flags);
4133 if (ufshcd_is_link_broken(hba)) {
4134 ret = -ENOLINK;
4135 goto out_unlock;
4136 }
4137 hba->uic_async_done = &uic_async_done;
4138 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4139 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4140 /*
4141 * Make sure UIC command completion interrupt is disabled before
4142 * issuing UIC command.
4143 */
4144 ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
4145 reenable_intr = true;
4146 }
4147 spin_unlock_irqrestore(hba->host->host_lock, flags);
4148 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4149 if (ret) {
4150 dev_err(hba->dev,
4151 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4152 cmd->command, cmd->argument3, ret);
4153 goto out;
4154 }
4155
4156 if (!wait_for_completion_timeout(hba->uic_async_done,
4157 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4158 dev_err(hba->dev,
4159 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4160 cmd->command, cmd->argument3);
4161
4162 if (!cmd->cmd_active) {
4163 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4164 __func__);
4165 goto check_upmcrs;
4166 }
4167
4168 ret = -ETIMEDOUT;
4169 goto out;
4170 }
4171
4172 check_upmcrs:
4173 status = ufshcd_get_upmcrs(hba);
4174 if (status != PWR_LOCAL) {
4175 dev_err(hba->dev,
4176 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4177 cmd->command, status);
4178 ret = (status != PWR_OK) ? status : -1;
4179 }
4180 out:
4181 if (ret) {
4182 ufshcd_print_host_state(hba);
4183 ufshcd_print_pwr_info(hba);
4184 ufshcd_print_evt_hist(hba);
4185 }
4186
4187 spin_lock_irqsave(hba->host->host_lock, flags);
4188 hba->active_uic_cmd = NULL;
4189 hba->uic_async_done = NULL;
4190 if (reenable_intr)
4191 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4192 if (ret) {
4193 ufshcd_set_link_broken(hba);
4194 ufshcd_schedule_eh_work(hba);
4195 }
4196 out_unlock:
4197 spin_unlock_irqrestore(hba->host->host_lock, flags);
4198 mutex_unlock(&hba->uic_cmd_mutex);
4199
4200 return ret;
4201 }
4202
4203 /**
4204 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4205 * using DME_SET primitives.
4206 * @hba: per adapter instance
4207 * @mode: powr mode value
4208 *
4209 * Return: 0 on success, non-zero value on failure.
4210 */
ufshcd_uic_change_pwr_mode(struct ufs_hba * hba,u8 mode)4211 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4212 {
4213 struct uic_command uic_cmd = {0};
4214 int ret;
4215
4216 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4217 ret = ufshcd_dme_set(hba,
4218 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4219 if (ret) {
4220 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4221 __func__, ret);
4222 goto out;
4223 }
4224 }
4225
4226 uic_cmd.command = UIC_CMD_DME_SET;
4227 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4228 uic_cmd.argument3 = mode;
4229 ufshcd_hold(hba);
4230 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4231 ufshcd_release(hba);
4232
4233 out:
4234 return ret;
4235 }
4236 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode);
4237
ufshcd_link_recovery(struct ufs_hba * hba)4238 int ufshcd_link_recovery(struct ufs_hba *hba)
4239 {
4240 int ret;
4241 unsigned long flags;
4242
4243 spin_lock_irqsave(hba->host->host_lock, flags);
4244 hba->ufshcd_state = UFSHCD_STATE_RESET;
4245 ufshcd_set_eh_in_progress(hba);
4246 spin_unlock_irqrestore(hba->host->host_lock, flags);
4247
4248 /* Reset the attached device */
4249 ufshcd_device_reset(hba);
4250
4251 ret = ufshcd_host_reset_and_restore(hba);
4252
4253 spin_lock_irqsave(hba->host->host_lock, flags);
4254 if (ret)
4255 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4256 ufshcd_clear_eh_in_progress(hba);
4257 spin_unlock_irqrestore(hba->host->host_lock, flags);
4258
4259 if (ret)
4260 dev_err(hba->dev, "%s: link recovery failed, err %d",
4261 __func__, ret);
4262
4263 return ret;
4264 }
4265 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4266
ufshcd_uic_hibern8_enter(struct ufs_hba * hba)4267 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4268 {
4269 int ret;
4270 struct uic_command uic_cmd = {0};
4271 ktime_t start = ktime_get();
4272
4273 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4274
4275 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4276 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4277 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4278 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4279
4280 if (ret)
4281 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4282 __func__, ret);
4283 else
4284 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4285 POST_CHANGE);
4286
4287 return ret;
4288 }
4289 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
4290
ufshcd_uic_hibern8_exit(struct ufs_hba * hba)4291 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4292 {
4293 struct uic_command uic_cmd = {0};
4294 int ret;
4295 ktime_t start = ktime_get();
4296
4297 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4298
4299 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4300 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4301 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4302 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4303
4304 if (ret) {
4305 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4306 __func__, ret);
4307 } else {
4308 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4309 POST_CHANGE);
4310 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock();
4311 hba->ufs_stats.hibern8_exit_cnt++;
4312 }
4313
4314 return ret;
4315 }
4316 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4317
ufshcd_auto_hibern8_update(struct ufs_hba * hba,u32 ahit)4318 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4319 {
4320 unsigned long flags;
4321 bool update = false;
4322
4323 if (!ufshcd_is_auto_hibern8_supported(hba))
4324 return;
4325
4326 spin_lock_irqsave(hba->host->host_lock, flags);
4327 if (hba->ahit != ahit) {
4328 hba->ahit = ahit;
4329 update = true;
4330 }
4331 spin_unlock_irqrestore(hba->host->host_lock, flags);
4332
4333 if (update &&
4334 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
4335 ufshcd_rpm_get_sync(hba);
4336 ufshcd_hold(hba);
4337 ufshcd_auto_hibern8_enable(hba);
4338 ufshcd_release(hba);
4339 ufshcd_rpm_put_sync(hba);
4340 }
4341 }
4342 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4343
ufshcd_auto_hibern8_enable(struct ufs_hba * hba)4344 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4345 {
4346 if (!ufshcd_is_auto_hibern8_supported(hba))
4347 return;
4348
4349 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4350 }
4351
4352 /**
4353 * ufshcd_init_pwr_info - setting the POR (power on reset)
4354 * values in hba power info
4355 * @hba: per-adapter instance
4356 */
ufshcd_init_pwr_info(struct ufs_hba * hba)4357 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4358 {
4359 hba->pwr_info.gear_rx = UFS_PWM_G1;
4360 hba->pwr_info.gear_tx = UFS_PWM_G1;
4361 hba->pwr_info.lane_rx = UFS_LANE_1;
4362 hba->pwr_info.lane_tx = UFS_LANE_1;
4363 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4364 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4365 hba->pwr_info.hs_rate = 0;
4366 }
4367
4368 /**
4369 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4370 * @hba: per-adapter instance
4371 *
4372 * Return: 0 upon success; < 0 upon failure.
4373 */
ufshcd_get_max_pwr_mode(struct ufs_hba * hba)4374 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4375 {
4376 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4377
4378 if (hba->max_pwr_info.is_valid)
4379 return 0;
4380
4381 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
4382 pwr_info->pwr_tx = FASTAUTO_MODE;
4383 pwr_info->pwr_rx = FASTAUTO_MODE;
4384 } else {
4385 pwr_info->pwr_tx = FAST_MODE;
4386 pwr_info->pwr_rx = FAST_MODE;
4387 }
4388 pwr_info->hs_rate = PA_HS_MODE_B;
4389
4390 /* Get the connected lane count */
4391 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4392 &pwr_info->lane_rx);
4393 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4394 &pwr_info->lane_tx);
4395
4396 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4397 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4398 __func__,
4399 pwr_info->lane_rx,
4400 pwr_info->lane_tx);
4401 return -EINVAL;
4402 }
4403
4404 /*
4405 * First, get the maximum gears of HS speed.
4406 * If a zero value, it means there is no HSGEAR capability.
4407 * Then, get the maximum gears of PWM speed.
4408 */
4409 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4410 if (!pwr_info->gear_rx) {
4411 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4412 &pwr_info->gear_rx);
4413 if (!pwr_info->gear_rx) {
4414 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4415 __func__, pwr_info->gear_rx);
4416 return -EINVAL;
4417 }
4418 pwr_info->pwr_rx = SLOW_MODE;
4419 }
4420
4421 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4422 &pwr_info->gear_tx);
4423 if (!pwr_info->gear_tx) {
4424 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4425 &pwr_info->gear_tx);
4426 if (!pwr_info->gear_tx) {
4427 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4428 __func__, pwr_info->gear_tx);
4429 return -EINVAL;
4430 }
4431 pwr_info->pwr_tx = SLOW_MODE;
4432 }
4433
4434 hba->max_pwr_info.is_valid = true;
4435 return 0;
4436 }
4437
ufshcd_change_power_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_mode)4438 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4439 struct ufs_pa_layer_attr *pwr_mode)
4440 {
4441 int ret;
4442
4443 /* if already configured to the requested pwr_mode */
4444 if (!hba->force_pmc &&
4445 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4446 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4447 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4448 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4449 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4450 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4451 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4452 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4453 return 0;
4454 }
4455
4456 /*
4457 * Configure attributes for power mode change with below.
4458 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4459 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4460 * - PA_HSSERIES
4461 */
4462 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4463 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4464 pwr_mode->lane_rx);
4465 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4466 pwr_mode->pwr_rx == FAST_MODE)
4467 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
4468 else
4469 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
4470
4471 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4472 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4473 pwr_mode->lane_tx);
4474 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4475 pwr_mode->pwr_tx == FAST_MODE)
4476 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
4477 else
4478 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
4479
4480 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4481 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4482 pwr_mode->pwr_rx == FAST_MODE ||
4483 pwr_mode->pwr_tx == FAST_MODE)
4484 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4485 pwr_mode->hs_rate);
4486
4487 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4488 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4489 DL_FC0ProtectionTimeOutVal_Default);
4490 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4491 DL_TC0ReplayTimeOutVal_Default);
4492 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4493 DL_AFC0ReqTimeOutVal_Default);
4494 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4495 DL_FC1ProtectionTimeOutVal_Default);
4496 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4497 DL_TC1ReplayTimeOutVal_Default);
4498 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4499 DL_AFC1ReqTimeOutVal_Default);
4500
4501 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4502 DL_FC0ProtectionTimeOutVal_Default);
4503 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4504 DL_TC0ReplayTimeOutVal_Default);
4505 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4506 DL_AFC0ReqTimeOutVal_Default);
4507 }
4508
4509 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4510 | pwr_mode->pwr_tx);
4511
4512 if (ret) {
4513 dev_err(hba->dev,
4514 "%s: power mode change failed %d\n", __func__, ret);
4515 } else {
4516 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4517 pwr_mode);
4518
4519 memcpy(&hba->pwr_info, pwr_mode,
4520 sizeof(struct ufs_pa_layer_attr));
4521 }
4522
4523 return ret;
4524 }
4525
4526 /**
4527 * ufshcd_config_pwr_mode - configure a new power mode
4528 * @hba: per-adapter instance
4529 * @desired_pwr_mode: desired power configuration
4530 *
4531 * Return: 0 upon success; < 0 upon failure.
4532 */
ufshcd_config_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * desired_pwr_mode)4533 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4534 struct ufs_pa_layer_attr *desired_pwr_mode)
4535 {
4536 struct ufs_pa_layer_attr final_params = { 0 };
4537 int ret;
4538
4539 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4540 desired_pwr_mode, &final_params);
4541
4542 if (ret)
4543 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4544
4545 ret = ufshcd_change_power_mode(hba, &final_params);
4546
4547 return ret;
4548 }
4549 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4550
4551 /**
4552 * ufshcd_complete_dev_init() - checks device readiness
4553 * @hba: per-adapter instance
4554 *
4555 * Set fDeviceInit flag and poll until device toggles it.
4556 *
4557 * Return: 0 upon success; < 0 upon failure.
4558 */
ufshcd_complete_dev_init(struct ufs_hba * hba)4559 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4560 {
4561 int err;
4562 bool flag_res = true;
4563 ktime_t timeout;
4564
4565 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4566 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4567 if (err) {
4568 dev_err(hba->dev,
4569 "%s: setting fDeviceInit flag failed with error %d\n",
4570 __func__, err);
4571 goto out;
4572 }
4573
4574 /* Poll fDeviceInit flag to be cleared */
4575 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4576 do {
4577 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4578 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4579 if (!flag_res)
4580 break;
4581 usleep_range(500, 1000);
4582 } while (ktime_before(ktime_get(), timeout));
4583
4584 if (err) {
4585 dev_err(hba->dev,
4586 "%s: reading fDeviceInit flag failed with error %d\n",
4587 __func__, err);
4588 } else if (flag_res) {
4589 dev_err(hba->dev,
4590 "%s: fDeviceInit was not cleared by the device\n",
4591 __func__);
4592 err = -EBUSY;
4593 }
4594 out:
4595 return err;
4596 }
4597
4598 /**
4599 * ufshcd_make_hba_operational - Make UFS controller operational
4600 * @hba: per adapter instance
4601 *
4602 * To bring UFS host controller to operational state,
4603 * 1. Enable required interrupts
4604 * 2. Configure interrupt aggregation
4605 * 3. Program UTRL and UTMRL base address
4606 * 4. Configure run-stop-registers
4607 *
4608 * Return: 0 on success, non-zero value on failure.
4609 */
ufshcd_make_hba_operational(struct ufs_hba * hba)4610 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4611 {
4612 int err = 0;
4613 u32 reg;
4614
4615 /* Enable required interrupts */
4616 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4617
4618 /* Configure interrupt aggregation */
4619 if (ufshcd_is_intr_aggr_allowed(hba))
4620 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4621 else
4622 ufshcd_disable_intr_aggr(hba);
4623
4624 /* Configure UTRL and UTMRL base address registers */
4625 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4626 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4627 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4628 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4629 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4630 REG_UTP_TASK_REQ_LIST_BASE_L);
4631 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4632 REG_UTP_TASK_REQ_LIST_BASE_H);
4633
4634 /*
4635 * Make sure base address and interrupt setup are updated before
4636 * enabling the run/stop registers below.
4637 */
4638 wmb();
4639
4640 /*
4641 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4642 */
4643 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4644 if (!(ufshcd_get_lists_status(reg))) {
4645 ufshcd_enable_run_stop_reg(hba);
4646 } else {
4647 dev_err(hba->dev,
4648 "Host controller not ready to process requests");
4649 err = -EIO;
4650 }
4651
4652 return err;
4653 }
4654 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4655
4656 /**
4657 * ufshcd_hba_stop - Send controller to reset state
4658 * @hba: per adapter instance
4659 */
ufshcd_hba_stop(struct ufs_hba * hba)4660 void ufshcd_hba_stop(struct ufs_hba *hba)
4661 {
4662 unsigned long flags;
4663 int err;
4664
4665 /*
4666 * Obtain the host lock to prevent that the controller is disabled
4667 * while the UFS interrupt handler is active on another CPU.
4668 */
4669 spin_lock_irqsave(hba->host->host_lock, flags);
4670 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4671 spin_unlock_irqrestore(hba->host->host_lock, flags);
4672
4673 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4674 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4675 10, 1);
4676 if (err)
4677 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4678 }
4679 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4680
4681 /**
4682 * ufshcd_hba_execute_hce - initialize the controller
4683 * @hba: per adapter instance
4684 *
4685 * The controller resets itself and controller firmware initialization
4686 * sequence kicks off. When controller is ready it will set
4687 * the Host Controller Enable bit to 1.
4688 *
4689 * Return: 0 on success, non-zero value on failure.
4690 */
ufshcd_hba_execute_hce(struct ufs_hba * hba)4691 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4692 {
4693 int retry_outer = 3;
4694 int retry_inner;
4695
4696 start:
4697 if (ufshcd_is_hba_active(hba))
4698 /* change controller state to "reset state" */
4699 ufshcd_hba_stop(hba);
4700
4701 /* UniPro link is disabled at this point */
4702 ufshcd_set_link_off(hba);
4703
4704 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4705
4706 /* start controller initialization sequence */
4707 ufshcd_hba_start(hba);
4708
4709 /*
4710 * To initialize a UFS host controller HCE bit must be set to 1.
4711 * During initialization the HCE bit value changes from 1->0->1.
4712 * When the host controller completes initialization sequence
4713 * it sets the value of HCE bit to 1. The same HCE bit is read back
4714 * to check if the controller has completed initialization sequence.
4715 * So without this delay the value HCE = 1, set in the previous
4716 * instruction might be read back.
4717 * This delay can be changed based on the controller.
4718 */
4719 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4720
4721 /* wait for the host controller to complete initialization */
4722 retry_inner = 50;
4723 while (!ufshcd_is_hba_active(hba)) {
4724 if (retry_inner) {
4725 retry_inner--;
4726 } else {
4727 dev_err(hba->dev,
4728 "Controller enable failed\n");
4729 if (retry_outer) {
4730 retry_outer--;
4731 goto start;
4732 }
4733 return -EIO;
4734 }
4735 usleep_range(1000, 1100);
4736 }
4737
4738 /* enable UIC related interrupts */
4739 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4740
4741 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4742
4743 return 0;
4744 }
4745
ufshcd_hba_enable(struct ufs_hba * hba)4746 int ufshcd_hba_enable(struct ufs_hba *hba)
4747 {
4748 int ret;
4749
4750 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4751 ufshcd_set_link_off(hba);
4752 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4753
4754 /* enable UIC related interrupts */
4755 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4756 ret = ufshcd_dme_reset(hba);
4757 if (ret) {
4758 dev_err(hba->dev, "DME_RESET failed\n");
4759 return ret;
4760 }
4761
4762 ret = ufshcd_dme_enable(hba);
4763 if (ret) {
4764 dev_err(hba->dev, "Enabling DME failed\n");
4765 return ret;
4766 }
4767
4768 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4769 } else {
4770 ret = ufshcd_hba_execute_hce(hba);
4771 }
4772
4773 return ret;
4774 }
4775 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4776
ufshcd_disable_tx_lcc(struct ufs_hba * hba,bool peer)4777 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4778 {
4779 int tx_lanes = 0, i, err = 0;
4780
4781 if (!peer)
4782 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4783 &tx_lanes);
4784 else
4785 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4786 &tx_lanes);
4787 for (i = 0; i < tx_lanes; i++) {
4788 if (!peer)
4789 err = ufshcd_dme_set(hba,
4790 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4791 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4792 0);
4793 else
4794 err = ufshcd_dme_peer_set(hba,
4795 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4796 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4797 0);
4798 if (err) {
4799 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4800 __func__, peer, i, err);
4801 break;
4802 }
4803 }
4804
4805 return err;
4806 }
4807
ufshcd_disable_device_tx_lcc(struct ufs_hba * hba)4808 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4809 {
4810 return ufshcd_disable_tx_lcc(hba, true);
4811 }
4812
ufshcd_update_evt_hist(struct ufs_hba * hba,u32 id,u32 val)4813 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4814 {
4815 struct ufs_event_hist *e;
4816
4817 if (id >= UFS_EVT_CNT)
4818 return;
4819
4820 e = &hba->ufs_stats.event[id];
4821 e->val[e->pos] = val;
4822 e->tstamp[e->pos] = local_clock();
4823 e->cnt += 1;
4824 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4825
4826 ufshcd_vops_event_notify(hba, id, &val);
4827 }
4828 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4829
4830 /**
4831 * ufshcd_link_startup - Initialize unipro link startup
4832 * @hba: per adapter instance
4833 *
4834 * Return: 0 for success, non-zero in case of failure.
4835 */
ufshcd_link_startup(struct ufs_hba * hba)4836 static int ufshcd_link_startup(struct ufs_hba *hba)
4837 {
4838 int ret;
4839 int retries = DME_LINKSTARTUP_RETRIES;
4840 bool link_startup_again = false;
4841
4842 /*
4843 * If UFS device isn't active then we will have to issue link startup
4844 * 2 times to make sure the device state move to active.
4845 */
4846 if (!ufshcd_is_ufs_dev_active(hba))
4847 link_startup_again = true;
4848
4849 link_startup:
4850 do {
4851 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4852
4853 ret = ufshcd_dme_link_startup(hba);
4854
4855 /* check if device is detected by inter-connect layer */
4856 if (!ret && !ufshcd_is_device_present(hba)) {
4857 ufshcd_update_evt_hist(hba,
4858 UFS_EVT_LINK_STARTUP_FAIL,
4859 0);
4860 dev_err(hba->dev, "%s: Device not present\n", __func__);
4861 ret = -ENXIO;
4862 goto out;
4863 }
4864
4865 /*
4866 * DME link lost indication is only received when link is up,
4867 * but we can't be sure if the link is up until link startup
4868 * succeeds. So reset the local Uni-Pro and try again.
4869 */
4870 if (ret && retries && ufshcd_hba_enable(hba)) {
4871 ufshcd_update_evt_hist(hba,
4872 UFS_EVT_LINK_STARTUP_FAIL,
4873 (u32)ret);
4874 goto out;
4875 }
4876 } while (ret && retries--);
4877
4878 if (ret) {
4879 /* failed to get the link up... retire */
4880 ufshcd_update_evt_hist(hba,
4881 UFS_EVT_LINK_STARTUP_FAIL,
4882 (u32)ret);
4883 goto out;
4884 }
4885
4886 if (link_startup_again) {
4887 link_startup_again = false;
4888 retries = DME_LINKSTARTUP_RETRIES;
4889 goto link_startup;
4890 }
4891
4892 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4893 ufshcd_init_pwr_info(hba);
4894 ufshcd_print_pwr_info(hba);
4895
4896 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4897 ret = ufshcd_disable_device_tx_lcc(hba);
4898 if (ret)
4899 goto out;
4900 }
4901
4902 /* Include any host controller configuration via UIC commands */
4903 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4904 if (ret)
4905 goto out;
4906
4907 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4908 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4909 ret = ufshcd_make_hba_operational(hba);
4910 out:
4911 if (ret) {
4912 dev_err(hba->dev, "link startup failed %d\n", ret);
4913 ufshcd_print_host_state(hba);
4914 ufshcd_print_pwr_info(hba);
4915 ufshcd_print_evt_hist(hba);
4916 }
4917 return ret;
4918 }
4919
4920 /**
4921 * ufshcd_verify_dev_init() - Verify device initialization
4922 * @hba: per-adapter instance
4923 *
4924 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4925 * device Transport Protocol (UTP) layer is ready after a reset.
4926 * If the UTP layer at the device side is not initialized, it may
4927 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4928 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4929 *
4930 * Return: 0 upon success; < 0 upon failure.
4931 */
ufshcd_verify_dev_init(struct ufs_hba * hba)4932 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4933 {
4934 int err = 0;
4935 int retries;
4936
4937 ufshcd_hold(hba);
4938 mutex_lock(&hba->dev_cmd.lock);
4939 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4940 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4941 hba->nop_out_timeout);
4942
4943 if (!err || err == -ETIMEDOUT)
4944 break;
4945
4946 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4947 }
4948 mutex_unlock(&hba->dev_cmd.lock);
4949 ufshcd_release(hba);
4950
4951 if (err)
4952 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4953 return err;
4954 }
4955
4956 /**
4957 * ufshcd_setup_links - associate link b/w device wlun and other luns
4958 * @sdev: pointer to SCSI device
4959 * @hba: pointer to ufs hba
4960 */
ufshcd_setup_links(struct ufs_hba * hba,struct scsi_device * sdev)4961 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4962 {
4963 struct device_link *link;
4964
4965 /*
4966 * Device wlun is the supplier & rest of the luns are consumers.
4967 * This ensures that device wlun suspends after all other luns.
4968 */
4969 if (hba->ufs_device_wlun) {
4970 link = device_link_add(&sdev->sdev_gendev,
4971 &hba->ufs_device_wlun->sdev_gendev,
4972 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4973 if (!link) {
4974 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4975 dev_name(&hba->ufs_device_wlun->sdev_gendev));
4976 return;
4977 }
4978 hba->luns_avail--;
4979 /* Ignore REPORT_LUN wlun probing */
4980 if (hba->luns_avail == 1) {
4981 ufshcd_rpm_put(hba);
4982 return;
4983 }
4984 } else {
4985 /*
4986 * Device wlun is probed. The assumption is that WLUNs are
4987 * scanned before other LUNs.
4988 */
4989 hba->luns_avail--;
4990 }
4991 }
4992
4993 /**
4994 * ufshcd_lu_init - Initialize the relevant parameters of the LU
4995 * @hba: per-adapter instance
4996 * @sdev: pointer to SCSI device
4997 */
ufshcd_lu_init(struct ufs_hba * hba,struct scsi_device * sdev)4998 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev)
4999 {
5000 int len = QUERY_DESC_MAX_SIZE;
5001 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun);
5002 u8 lun_qdepth = hba->nutrs;
5003 u8 *desc_buf;
5004 int ret;
5005
5006 desc_buf = kzalloc(len, GFP_KERNEL);
5007 if (!desc_buf)
5008 goto set_qdepth;
5009
5010 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len);
5011 if (ret < 0) {
5012 if (ret == -EOPNOTSUPP)
5013 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */
5014 lun_qdepth = 1;
5015 kfree(desc_buf);
5016 goto set_qdepth;
5017 }
5018
5019 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) {
5020 /*
5021 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will
5022 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth
5023 */
5024 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs);
5025 }
5026 /*
5027 * According to UFS device specification, the write protection mode is only supported by
5028 * normal LU, not supported by WLUN.
5029 */
5030 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported &&
5031 !hba->dev_info.is_lu_power_on_wp &&
5032 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP)
5033 hba->dev_info.is_lu_power_on_wp = true;
5034
5035 /* In case of RPMB LU, check if advanced RPMB mode is enabled */
5036 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN &&
5037 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4))
5038 hba->dev_info.b_advanced_rpmb_en = true;
5039
5040
5041 kfree(desc_buf);
5042 set_qdepth:
5043 /*
5044 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose
5045 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue.
5046 */
5047 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth);
5048 scsi_change_queue_depth(sdev, lun_qdepth);
5049 }
5050
5051 /**
5052 * ufshcd_slave_alloc - handle initial SCSI device configurations
5053 * @sdev: pointer to SCSI device
5054 *
5055 * Return: success.
5056 */
ufshcd_slave_alloc(struct scsi_device * sdev)5057 static int ufshcd_slave_alloc(struct scsi_device *sdev)
5058 {
5059 struct ufs_hba *hba;
5060
5061 hba = shost_priv(sdev->host);
5062
5063 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
5064 sdev->use_10_for_ms = 1;
5065
5066 /* DBD field should be set to 1 in mode sense(10) */
5067 sdev->set_dbd_for_ms = 1;
5068
5069 /* allow SCSI layer to restart the device in case of errors */
5070 sdev->allow_restart = 1;
5071
5072 /* REPORT SUPPORTED OPERATION CODES is not supported */
5073 sdev->no_report_opcodes = 1;
5074
5075 /* WRITE_SAME command is not supported */
5076 sdev->no_write_same = 1;
5077
5078 ufshcd_lu_init(hba, sdev);
5079
5080 ufshcd_setup_links(hba, sdev);
5081
5082 return 0;
5083 }
5084
5085 /**
5086 * ufshcd_change_queue_depth - change queue depth
5087 * @sdev: pointer to SCSI device
5088 * @depth: required depth to set
5089 *
5090 * Change queue depth and make sure the max. limits are not crossed.
5091 *
5092 * Return: new queue depth.
5093 */
ufshcd_change_queue_depth(struct scsi_device * sdev,int depth)5094 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
5095 {
5096 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
5097 }
5098
5099 /**
5100 * ufshcd_slave_configure - adjust SCSI device configurations
5101 * @sdev: pointer to SCSI device
5102 *
5103 * Return: 0 (success).
5104 */
ufshcd_slave_configure(struct scsi_device * sdev)5105 static int ufshcd_slave_configure(struct scsi_device *sdev)
5106 {
5107 struct ufs_hba *hba = shost_priv(sdev->host);
5108 struct request_queue *q = sdev->request_queue;
5109
5110 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
5111 if (hba->quirks & UFSHCD_QUIRK_4KB_DMA_ALIGNMENT)
5112 blk_queue_update_dma_alignment(q, SZ_4K - 1);
5113 /*
5114 * Block runtime-pm until all consumers are added.
5115 * Refer ufshcd_setup_links().
5116 */
5117 if (is_device_wlun(sdev))
5118 pm_runtime_get_noresume(&sdev->sdev_gendev);
5119 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5120 sdev->rpm_autosuspend = 1;
5121 /*
5122 * Do not print messages during runtime PM to avoid never-ending cycles
5123 * of messages written back to storage by user space causing runtime
5124 * resume, causing more messages and so on.
5125 */
5126 sdev->silence_suspend = 1;
5127
5128 ufshcd_crypto_register(hba, q);
5129
5130 return 0;
5131 }
5132
5133 /**
5134 * ufshcd_slave_destroy - remove SCSI device configurations
5135 * @sdev: pointer to SCSI device
5136 */
ufshcd_slave_destroy(struct scsi_device * sdev)5137 static void ufshcd_slave_destroy(struct scsi_device *sdev)
5138 {
5139 struct ufs_hba *hba;
5140 unsigned long flags;
5141
5142 hba = shost_priv(sdev->host);
5143
5144 /* Drop the reference as it won't be needed anymore */
5145 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5146 spin_lock_irqsave(hba->host->host_lock, flags);
5147 hba->ufs_device_wlun = NULL;
5148 spin_unlock_irqrestore(hba->host->host_lock, flags);
5149 } else if (hba->ufs_device_wlun) {
5150 struct device *supplier = NULL;
5151
5152 /* Ensure UFS Device WLUN exists and does not disappear */
5153 spin_lock_irqsave(hba->host->host_lock, flags);
5154 if (hba->ufs_device_wlun) {
5155 supplier = &hba->ufs_device_wlun->sdev_gendev;
5156 get_device(supplier);
5157 }
5158 spin_unlock_irqrestore(hba->host->host_lock, flags);
5159
5160 if (supplier) {
5161 /*
5162 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5163 * device will not have been registered but can still
5164 * have a device link holding a reference to the device.
5165 */
5166 device_link_remove(&sdev->sdev_gendev, supplier);
5167 put_device(supplier);
5168 }
5169 }
5170 }
5171
5172 /**
5173 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5174 * @lrbp: pointer to local reference block of completed command
5175 * @scsi_status: SCSI command status
5176 *
5177 * Return: value base on SCSI command status.
5178 */
5179 static inline int
ufshcd_scsi_cmd_status(struct ufshcd_lrb * lrbp,int scsi_status)5180 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5181 {
5182 int result = 0;
5183
5184 switch (scsi_status) {
5185 case SAM_STAT_CHECK_CONDITION:
5186 ufshcd_copy_sense_data(lrbp);
5187 fallthrough;
5188 case SAM_STAT_GOOD:
5189 result |= DID_OK << 16 | scsi_status;
5190 break;
5191 case SAM_STAT_TASK_SET_FULL:
5192 case SAM_STAT_BUSY:
5193 case SAM_STAT_TASK_ABORTED:
5194 ufshcd_copy_sense_data(lrbp);
5195 result |= scsi_status;
5196 break;
5197 default:
5198 result |= DID_ERROR << 16;
5199 break;
5200 } /* end of switch */
5201
5202 return result;
5203 }
5204
5205 /**
5206 * ufshcd_transfer_rsp_status - Get overall status of the response
5207 * @hba: per adapter instance
5208 * @lrbp: pointer to local reference block of completed command
5209 * @cqe: pointer to the completion queue entry
5210 *
5211 * Return: result of the command to notify SCSI midlayer.
5212 */
5213 static inline int
ufshcd_transfer_rsp_status(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,struct cq_entry * cqe)5214 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
5215 struct cq_entry *cqe)
5216 {
5217 int result = 0;
5218 int scsi_status;
5219 enum utp_ocs ocs;
5220 u8 upiu_flags;
5221 u32 resid;
5222
5223 upiu_flags = lrbp->ucd_rsp_ptr->header.flags;
5224 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count);
5225 /*
5226 * Test !overflow instead of underflow to support UFS devices that do
5227 * not set either flag.
5228 */
5229 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW))
5230 scsi_set_resid(lrbp->cmd, resid);
5231
5232 /* overall command status of utrd */
5233 ocs = ufshcd_get_tr_ocs(lrbp, cqe);
5234
5235 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5236 if (lrbp->ucd_rsp_ptr->header.response ||
5237 lrbp->ucd_rsp_ptr->header.status)
5238 ocs = OCS_SUCCESS;
5239 }
5240
5241 switch (ocs) {
5242 case OCS_SUCCESS:
5243 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5244 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) {
5245 case UPIU_TRANSACTION_RESPONSE:
5246 /*
5247 * get the result based on SCSI status response
5248 * to notify the SCSI midlayer of the command status
5249 */
5250 scsi_status = lrbp->ucd_rsp_ptr->header.status;
5251 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5252
5253 /*
5254 * Currently we are only supporting BKOPs exception
5255 * events hence we can ignore BKOPs exception event
5256 * during power management callbacks. BKOPs exception
5257 * event is not expected to be raised in runtime suspend
5258 * callback as it allows the urgent bkops.
5259 * During system suspend, we are anyway forcefully
5260 * disabling the bkops and if urgent bkops is needed
5261 * it will be enabled on system resume. Long term
5262 * solution could be to abort the system suspend if
5263 * UFS device needs urgent BKOPs.
5264 */
5265 if (!hba->pm_op_in_progress &&
5266 !ufshcd_eh_in_progress(hba) &&
5267 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5268 /* Flushed in suspend */
5269 schedule_work(&hba->eeh_work);
5270 break;
5271 case UPIU_TRANSACTION_REJECT_UPIU:
5272 /* TODO: handle Reject UPIU Response */
5273 result = DID_ERROR << 16;
5274 dev_err(hba->dev,
5275 "Reject UPIU not fully implemented\n");
5276 break;
5277 default:
5278 dev_err(hba->dev,
5279 "Unexpected request response code = %x\n",
5280 result);
5281 result = DID_ERROR << 16;
5282 break;
5283 }
5284 break;
5285 case OCS_ABORTED:
5286 result |= DID_ABORT << 16;
5287 break;
5288 case OCS_INVALID_COMMAND_STATUS:
5289 result |= DID_REQUEUE << 16;
5290 break;
5291 case OCS_INVALID_CMD_TABLE_ATTR:
5292 case OCS_INVALID_PRDT_ATTR:
5293 case OCS_MISMATCH_DATA_BUF_SIZE:
5294 case OCS_MISMATCH_RESP_UPIU_SIZE:
5295 case OCS_PEER_COMM_FAILURE:
5296 case OCS_FATAL_ERROR:
5297 case OCS_DEVICE_FATAL_ERROR:
5298 case OCS_INVALID_CRYPTO_CONFIG:
5299 case OCS_GENERAL_CRYPTO_ERROR:
5300 default:
5301 result |= DID_ERROR << 16;
5302 dev_err(hba->dev,
5303 "OCS error from controller = %x for tag %d\n",
5304 ocs, lrbp->task_tag);
5305 ufshcd_print_evt_hist(hba);
5306 ufshcd_print_host_state(hba);
5307 break;
5308 } /* end of switch */
5309
5310 if ((host_byte(result) != DID_OK) &&
5311 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5312 ufshcd_print_tr(hba, lrbp->task_tag, true);
5313 return result;
5314 }
5315
ufshcd_is_auto_hibern8_error(struct ufs_hba * hba,u32 intr_mask)5316 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5317 u32 intr_mask)
5318 {
5319 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5320 !ufshcd_is_auto_hibern8_enabled(hba))
5321 return false;
5322
5323 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5324 return false;
5325
5326 if (hba->active_uic_cmd &&
5327 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5328 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5329 return false;
5330
5331 return true;
5332 }
5333
5334 /**
5335 * ufshcd_uic_cmd_compl - handle completion of uic command
5336 * @hba: per adapter instance
5337 * @intr_status: interrupt status generated by the controller
5338 *
5339 * Return:
5340 * IRQ_HANDLED - If interrupt is valid
5341 * IRQ_NONE - If invalid interrupt
5342 */
ufshcd_uic_cmd_compl(struct ufs_hba * hba,u32 intr_status)5343 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5344 {
5345 irqreturn_t retval = IRQ_NONE;
5346
5347 spin_lock(hba->host->host_lock);
5348 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5349 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5350
5351 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5352 hba->active_uic_cmd->argument2 |=
5353 ufshcd_get_uic_cmd_result(hba);
5354 hba->active_uic_cmd->argument3 =
5355 ufshcd_get_dme_attr_val(hba);
5356 if (!hba->uic_async_done)
5357 hba->active_uic_cmd->cmd_active = 0;
5358 complete(&hba->active_uic_cmd->done);
5359 retval = IRQ_HANDLED;
5360 }
5361
5362 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5363 hba->active_uic_cmd->cmd_active = 0;
5364 complete(hba->uic_async_done);
5365 retval = IRQ_HANDLED;
5366 }
5367
5368 if (retval == IRQ_HANDLED)
5369 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5370 UFS_CMD_COMP);
5371 spin_unlock(hba->host->host_lock);
5372 return retval;
5373 }
5374
5375 /* Release the resources allocated for processing a SCSI command. */
ufshcd_release_scsi_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)5376 void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5377 struct ufshcd_lrb *lrbp)
5378 {
5379 struct scsi_cmnd *cmd = lrbp->cmd;
5380
5381 scsi_dma_unmap(cmd);
5382 ufshcd_release(hba);
5383 ufshcd_clk_scaling_update_busy(hba);
5384 }
5385
5386 /**
5387 * ufshcd_compl_one_cqe - handle a completion queue entry
5388 * @hba: per adapter instance
5389 * @task_tag: the task tag of the request to be completed
5390 * @cqe: pointer to the completion queue entry
5391 */
ufshcd_compl_one_cqe(struct ufs_hba * hba,int task_tag,struct cq_entry * cqe)5392 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag,
5393 struct cq_entry *cqe)
5394 {
5395 struct ufshcd_lrb *lrbp;
5396 struct scsi_cmnd *cmd;
5397 enum utp_ocs ocs;
5398
5399 lrbp = &hba->lrb[task_tag];
5400 lrbp->compl_time_stamp = ktime_get();
5401 cmd = lrbp->cmd;
5402 if (cmd) {
5403 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5404 ufshcd_update_monitor(hba, lrbp);
5405 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP);
5406 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe);
5407 ufshcd_release_scsi_cmd(hba, lrbp);
5408 /* Do not touch lrbp after scsi done */
5409 scsi_done(cmd);
5410 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5411 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5412 if (hba->dev_cmd.complete) {
5413 if (cqe) {
5414 ocs = le32_to_cpu(cqe->status) & MASK_OCS;
5415 lrbp->utr_descriptor_ptr->header.ocs = ocs;
5416 }
5417 complete(hba->dev_cmd.complete);
5418 ufshcd_clk_scaling_update_busy(hba);
5419 }
5420 }
5421 }
5422
5423 /**
5424 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5425 * @hba: per adapter instance
5426 * @completed_reqs: bitmask that indicates which requests to complete
5427 */
__ufshcd_transfer_req_compl(struct ufs_hba * hba,unsigned long completed_reqs)5428 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5429 unsigned long completed_reqs)
5430 {
5431 int tag;
5432
5433 for_each_set_bit(tag, &completed_reqs, hba->nutrs)
5434 ufshcd_compl_one_cqe(hba, tag, NULL);
5435 }
5436
5437 /* Any value that is not an existing queue number is fine for this constant. */
5438 enum {
5439 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1
5440 };
5441
ufshcd_clear_polled(struct ufs_hba * hba,unsigned long * completed_reqs)5442 static void ufshcd_clear_polled(struct ufs_hba *hba,
5443 unsigned long *completed_reqs)
5444 {
5445 int tag;
5446
5447 for_each_set_bit(tag, completed_reqs, hba->nutrs) {
5448 struct scsi_cmnd *cmd = hba->lrb[tag].cmd;
5449
5450 if (!cmd)
5451 continue;
5452 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED)
5453 __clear_bit(tag, completed_reqs);
5454 }
5455 }
5456
5457 /*
5458 * Return: > 0 if one or more commands have been completed or 0 if no
5459 * requests have been completed.
5460 */
ufshcd_poll(struct Scsi_Host * shost,unsigned int queue_num)5461 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5462 {
5463 struct ufs_hba *hba = shost_priv(shost);
5464 unsigned long completed_reqs, flags;
5465 u32 tr_doorbell;
5466 struct ufs_hw_queue *hwq;
5467
5468 if (is_mcq_enabled(hba)) {
5469 hwq = &hba->uhq[queue_num];
5470
5471 return ufshcd_mcq_poll_cqe_lock(hba, hwq);
5472 }
5473
5474 spin_lock_irqsave(&hba->outstanding_lock, flags);
5475 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5476 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5477 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5478 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5479 hba->outstanding_reqs);
5480 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) {
5481 /* Do not complete polled requests from interrupt context. */
5482 ufshcd_clear_polled(hba, &completed_reqs);
5483 }
5484 hba->outstanding_reqs &= ~completed_reqs;
5485 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5486
5487 if (completed_reqs)
5488 __ufshcd_transfer_req_compl(hba, completed_reqs);
5489
5490 return completed_reqs != 0;
5491 }
5492
5493 /**
5494 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is
5495 * invoked from the error handler context or ufshcd_host_reset_and_restore()
5496 * to complete the pending transfers and free the resources associated with
5497 * the scsi command.
5498 *
5499 * @hba: per adapter instance
5500 * @force_compl: This flag is set to true when invoked
5501 * from ufshcd_host_reset_and_restore() in which case it requires special
5502 * handling because the host controller has been reset by ufshcd_hba_stop().
5503 */
ufshcd_mcq_compl_pending_transfer(struct ufs_hba * hba,bool force_compl)5504 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba,
5505 bool force_compl)
5506 {
5507 struct ufs_hw_queue *hwq;
5508 struct ufshcd_lrb *lrbp;
5509 struct scsi_cmnd *cmd;
5510 unsigned long flags;
5511 u32 hwq_num, utag;
5512 int tag;
5513
5514 for (tag = 0; tag < hba->nutrs; tag++) {
5515 lrbp = &hba->lrb[tag];
5516 cmd = lrbp->cmd;
5517 if (!ufshcd_cmd_inflight(cmd) ||
5518 test_bit(SCMD_STATE_COMPLETE, &cmd->state))
5519 continue;
5520
5521 utag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
5522 hwq_num = blk_mq_unique_tag_to_hwq(utag);
5523 hwq = &hba->uhq[hwq_num];
5524
5525 if (force_compl) {
5526 ufshcd_mcq_compl_all_cqes_lock(hba, hwq);
5527 /*
5528 * For those cmds of which the cqes are not present
5529 * in the cq, complete them explicitly.
5530 */
5531 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) {
5532 spin_lock_irqsave(&hwq->cq_lock, flags);
5533 set_host_byte(cmd, DID_REQUEUE);
5534 ufshcd_release_scsi_cmd(hba, lrbp);
5535 scsi_done(cmd);
5536 spin_unlock_irqrestore(&hwq->cq_lock, flags);
5537 }
5538 } else {
5539 ufshcd_mcq_poll_cqe_lock(hba, hwq);
5540 }
5541 }
5542 }
5543
5544 /**
5545 * ufshcd_transfer_req_compl - handle SCSI and query command completion
5546 * @hba: per adapter instance
5547 *
5548 * Return:
5549 * IRQ_HANDLED - If interrupt is valid
5550 * IRQ_NONE - If invalid interrupt
5551 */
ufshcd_transfer_req_compl(struct ufs_hba * hba)5552 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5553 {
5554 /* Resetting interrupt aggregation counters first and reading the
5555 * DOOR_BELL afterward allows us to handle all the completed requests.
5556 * In order to prevent other interrupts starvation the DB is read once
5557 * after reset. The down side of this solution is the possibility of
5558 * false interrupt if device completes another request after resetting
5559 * aggregation and before reading the DB.
5560 */
5561 if (ufshcd_is_intr_aggr_allowed(hba) &&
5562 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5563 ufshcd_reset_intr_aggr(hba);
5564
5565 if (ufs_fail_completion())
5566 return IRQ_HANDLED;
5567
5568 /*
5569 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5570 * do not want polling to trigger spurious interrupt complaints.
5571 */
5572 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT);
5573
5574 return IRQ_HANDLED;
5575 }
5576
__ufshcd_write_ee_control(struct ufs_hba * hba,u32 ee_ctrl_mask)5577 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5578 {
5579 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5580 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5581 &ee_ctrl_mask);
5582 }
5583
ufshcd_write_ee_control(struct ufs_hba * hba)5584 int ufshcd_write_ee_control(struct ufs_hba *hba)
5585 {
5586 int err;
5587
5588 mutex_lock(&hba->ee_ctrl_mutex);
5589 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5590 mutex_unlock(&hba->ee_ctrl_mutex);
5591 if (err)
5592 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5593 __func__, err);
5594 return err;
5595 }
5596
ufshcd_update_ee_control(struct ufs_hba * hba,u16 * mask,const u16 * other_mask,u16 set,u16 clr)5597 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
5598 const u16 *other_mask, u16 set, u16 clr)
5599 {
5600 u16 new_mask, ee_ctrl_mask;
5601 int err = 0;
5602
5603 mutex_lock(&hba->ee_ctrl_mutex);
5604 new_mask = (*mask & ~clr) | set;
5605 ee_ctrl_mask = new_mask | *other_mask;
5606 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5607 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5608 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5609 if (!err) {
5610 hba->ee_ctrl_mask = ee_ctrl_mask;
5611 *mask = new_mask;
5612 }
5613 mutex_unlock(&hba->ee_ctrl_mutex);
5614 return err;
5615 }
5616
5617 /**
5618 * ufshcd_disable_ee - disable exception event
5619 * @hba: per-adapter instance
5620 * @mask: exception event to disable
5621 *
5622 * Disables exception event in the device so that the EVENT_ALERT
5623 * bit is not set.
5624 *
5625 * Return: zero on success, non-zero error value on failure.
5626 */
ufshcd_disable_ee(struct ufs_hba * hba,u16 mask)5627 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5628 {
5629 return ufshcd_update_ee_drv_mask(hba, 0, mask);
5630 }
5631
5632 /**
5633 * ufshcd_enable_ee - enable exception event
5634 * @hba: per-adapter instance
5635 * @mask: exception event to enable
5636 *
5637 * Enable corresponding exception event in the device to allow
5638 * device to alert host in critical scenarios.
5639 *
5640 * Return: zero on success, non-zero error value on failure.
5641 */
ufshcd_enable_ee(struct ufs_hba * hba,u16 mask)5642 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5643 {
5644 return ufshcd_update_ee_drv_mask(hba, mask, 0);
5645 }
5646
5647 /**
5648 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5649 * @hba: per-adapter instance
5650 *
5651 * Allow device to manage background operations on its own. Enabling
5652 * this might lead to inconsistent latencies during normal data transfers
5653 * as the device is allowed to manage its own way of handling background
5654 * operations.
5655 *
5656 * Return: zero on success, non-zero on failure.
5657 */
ufshcd_enable_auto_bkops(struct ufs_hba * hba)5658 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5659 {
5660 int err = 0;
5661
5662 if (hba->auto_bkops_enabled)
5663 goto out;
5664
5665 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5666 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5667 if (err) {
5668 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5669 __func__, err);
5670 goto out;
5671 }
5672
5673 hba->auto_bkops_enabled = true;
5674 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5675
5676 /* No need of URGENT_BKOPS exception from the device */
5677 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5678 if (err)
5679 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5680 __func__, err);
5681 out:
5682 return err;
5683 }
5684
5685 /**
5686 * ufshcd_disable_auto_bkops - block device in doing background operations
5687 * @hba: per-adapter instance
5688 *
5689 * Disabling background operations improves command response latency but
5690 * has drawback of device moving into critical state where the device is
5691 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5692 * host is idle so that BKOPS are managed effectively without any negative
5693 * impacts.
5694 *
5695 * Return: zero on success, non-zero on failure.
5696 */
ufshcd_disable_auto_bkops(struct ufs_hba * hba)5697 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5698 {
5699 int err = 0;
5700
5701 if (!hba->auto_bkops_enabled)
5702 goto out;
5703
5704 /*
5705 * If host assisted BKOPs is to be enabled, make sure
5706 * urgent bkops exception is allowed.
5707 */
5708 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5709 if (err) {
5710 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5711 __func__, err);
5712 goto out;
5713 }
5714
5715 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5716 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5717 if (err) {
5718 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5719 __func__, err);
5720 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5721 goto out;
5722 }
5723
5724 hba->auto_bkops_enabled = false;
5725 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5726 hba->is_urgent_bkops_lvl_checked = false;
5727 out:
5728 return err;
5729 }
5730
5731 /**
5732 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5733 * @hba: per adapter instance
5734 *
5735 * After a device reset the device may toggle the BKOPS_EN flag
5736 * to default value. The s/w tracking variables should be updated
5737 * as well. This function would change the auto-bkops state based on
5738 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5739 */
ufshcd_force_reset_auto_bkops(struct ufs_hba * hba)5740 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5741 {
5742 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5743 hba->auto_bkops_enabled = false;
5744 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5745 ufshcd_enable_auto_bkops(hba);
5746 } else {
5747 hba->auto_bkops_enabled = true;
5748 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5749 ufshcd_disable_auto_bkops(hba);
5750 }
5751 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5752 hba->is_urgent_bkops_lvl_checked = false;
5753 }
5754
ufshcd_get_bkops_status(struct ufs_hba * hba,u32 * status)5755 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5756 {
5757 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5758 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5759 }
5760
5761 /**
5762 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5763 * @hba: per-adapter instance
5764 * @status: bkops_status value
5765 *
5766 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5767 * flag in the device to permit background operations if the device
5768 * bkops_status is greater than or equal to "status" argument passed to
5769 * this function, disable otherwise.
5770 *
5771 * Return: 0 for success, non-zero in case of failure.
5772 *
5773 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5774 * to know whether auto bkops is enabled or disabled after this function
5775 * returns control to it.
5776 */
ufshcd_bkops_ctrl(struct ufs_hba * hba,enum bkops_status status)5777 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5778 enum bkops_status status)
5779 {
5780 int err;
5781 u32 curr_status = 0;
5782
5783 err = ufshcd_get_bkops_status(hba, &curr_status);
5784 if (err) {
5785 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5786 __func__, err);
5787 goto out;
5788 } else if (curr_status > BKOPS_STATUS_MAX) {
5789 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5790 __func__, curr_status);
5791 err = -EINVAL;
5792 goto out;
5793 }
5794
5795 if (curr_status >= status)
5796 err = ufshcd_enable_auto_bkops(hba);
5797 else
5798 err = ufshcd_disable_auto_bkops(hba);
5799 out:
5800 return err;
5801 }
5802
5803 /**
5804 * ufshcd_urgent_bkops - handle urgent bkops exception event
5805 * @hba: per-adapter instance
5806 *
5807 * Enable fBackgroundOpsEn flag in the device to permit background
5808 * operations.
5809 *
5810 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5811 * and negative error value for any other failure.
5812 *
5813 * Return: 0 upon success; < 0 upon failure.
5814 */
ufshcd_urgent_bkops(struct ufs_hba * hba)5815 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5816 {
5817 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5818 }
5819
ufshcd_get_ee_status(struct ufs_hba * hba,u32 * status)5820 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5821 {
5822 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5823 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5824 }
5825
ufshcd_bkops_exception_event_handler(struct ufs_hba * hba)5826 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5827 {
5828 int err;
5829 u32 curr_status = 0;
5830
5831 if (hba->is_urgent_bkops_lvl_checked)
5832 goto enable_auto_bkops;
5833
5834 err = ufshcd_get_bkops_status(hba, &curr_status);
5835 if (err) {
5836 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5837 __func__, err);
5838 goto out;
5839 }
5840
5841 /*
5842 * We are seeing that some devices are raising the urgent bkops
5843 * exception events even when BKOPS status doesn't indicate performace
5844 * impacted or critical. Handle these device by determining their urgent
5845 * bkops status at runtime.
5846 */
5847 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5848 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5849 __func__, curr_status);
5850 /* update the current status as the urgent bkops level */
5851 hba->urgent_bkops_lvl = curr_status;
5852 hba->is_urgent_bkops_lvl_checked = true;
5853 }
5854
5855 enable_auto_bkops:
5856 err = ufshcd_enable_auto_bkops(hba);
5857 out:
5858 if (err < 0)
5859 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5860 __func__, err);
5861 }
5862
ufshcd_temp_exception_event_handler(struct ufs_hba * hba,u16 status)5863 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
5864 {
5865 u32 value;
5866
5867 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5868 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
5869 return;
5870
5871 dev_info(hba->dev, "exception Tcase %d\n", value - 80);
5872
5873 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
5874
5875 /*
5876 * A placeholder for the platform vendors to add whatever additional
5877 * steps required
5878 */
5879 }
5880
__ufshcd_wb_toggle(struct ufs_hba * hba,bool set,enum flag_idn idn)5881 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5882 {
5883 u8 index;
5884 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5885 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5886
5887 index = ufshcd_wb_get_query_index(hba);
5888 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5889 }
5890
ufshcd_wb_toggle(struct ufs_hba * hba,bool enable)5891 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5892 {
5893 int ret;
5894
5895 if (!ufshcd_is_wb_allowed(hba) ||
5896 hba->dev_info.wb_enabled == enable)
5897 return 0;
5898
5899 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5900 if (ret) {
5901 dev_err(hba->dev, "%s: Write Booster %s failed %d\n",
5902 __func__, enable ? "enabling" : "disabling", ret);
5903 return ret;
5904 }
5905
5906 hba->dev_info.wb_enabled = enable;
5907 dev_dbg(hba->dev, "%s: Write Booster %s\n",
5908 __func__, enable ? "enabled" : "disabled");
5909
5910 return ret;
5911 }
5912
ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba * hba,bool enable)5913 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
5914 bool enable)
5915 {
5916 int ret;
5917
5918 ret = __ufshcd_wb_toggle(hba, enable,
5919 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5920 if (ret) {
5921 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n",
5922 __func__, enable ? "enabling" : "disabling", ret);
5923 return;
5924 }
5925 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n",
5926 __func__, enable ? "enabled" : "disabled");
5927 }
5928
ufshcd_wb_toggle_buf_flush(struct ufs_hba * hba,bool enable)5929 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable)
5930 {
5931 int ret;
5932
5933 if (!ufshcd_is_wb_allowed(hba) ||
5934 hba->dev_info.wb_buf_flush_enabled == enable)
5935 return 0;
5936
5937 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5938 if (ret) {
5939 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n",
5940 __func__, enable ? "enabling" : "disabling", ret);
5941 return ret;
5942 }
5943
5944 hba->dev_info.wb_buf_flush_enabled = enable;
5945 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n",
5946 __func__, enable ? "enabled" : "disabled");
5947
5948 return ret;
5949 }
5950
ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba * hba,u32 avail_buf)5951 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5952 u32 avail_buf)
5953 {
5954 u32 cur_buf;
5955 int ret;
5956 u8 index;
5957
5958 index = ufshcd_wb_get_query_index(hba);
5959 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5960 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5961 index, 0, &cur_buf);
5962 if (ret) {
5963 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n",
5964 __func__, ret);
5965 return false;
5966 }
5967
5968 if (!cur_buf) {
5969 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5970 cur_buf);
5971 return false;
5972 }
5973 /* Let it continue to flush when available buffer exceeds threshold */
5974 return avail_buf < hba->vps->wb_flush_threshold;
5975 }
5976
ufshcd_wb_force_disable(struct ufs_hba * hba)5977 static void ufshcd_wb_force_disable(struct ufs_hba *hba)
5978 {
5979 if (ufshcd_is_wb_buf_flush_allowed(hba))
5980 ufshcd_wb_toggle_buf_flush(hba, false);
5981
5982 ufshcd_wb_toggle_buf_flush_during_h8(hba, false);
5983 ufshcd_wb_toggle(hba, false);
5984 hba->caps &= ~UFSHCD_CAP_WB_EN;
5985
5986 dev_info(hba->dev, "%s: WB force disabled\n", __func__);
5987 }
5988
ufshcd_is_wb_buf_lifetime_available(struct ufs_hba * hba)5989 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
5990 {
5991 u32 lifetime;
5992 int ret;
5993 u8 index;
5994
5995 index = ufshcd_wb_get_query_index(hba);
5996 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5997 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
5998 index, 0, &lifetime);
5999 if (ret) {
6000 dev_err(hba->dev,
6001 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
6002 __func__, ret);
6003 return false;
6004 }
6005
6006 if (lifetime == UFS_WB_EXCEED_LIFETIME) {
6007 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
6008 __func__, lifetime);
6009 return false;
6010 }
6011
6012 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
6013 __func__, lifetime);
6014
6015 return true;
6016 }
6017
ufshcd_wb_need_flush(struct ufs_hba * hba)6018 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
6019 {
6020 int ret;
6021 u32 avail_buf;
6022 u8 index;
6023
6024 if (!ufshcd_is_wb_allowed(hba))
6025 return false;
6026
6027 if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
6028 ufshcd_wb_force_disable(hba);
6029 return false;
6030 }
6031
6032 /*
6033 * The ufs device needs the vcc to be ON to flush.
6034 * With user-space reduction enabled, it's enough to enable flush
6035 * by checking only the available buffer. The threshold
6036 * defined here is > 90% full.
6037 * With user-space preserved enabled, the current-buffer
6038 * should be checked too because the wb buffer size can reduce
6039 * when disk tends to be full. This info is provided by current
6040 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
6041 * keeping vcc on when current buffer is empty.
6042 */
6043 index = ufshcd_wb_get_query_index(hba);
6044 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6045 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
6046 index, 0, &avail_buf);
6047 if (ret) {
6048 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n",
6049 __func__, ret);
6050 return false;
6051 }
6052
6053 if (!hba->dev_info.b_presrv_uspc_en)
6054 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
6055
6056 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
6057 }
6058
ufshcd_rpm_dev_flush_recheck_work(struct work_struct * work)6059 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
6060 {
6061 struct ufs_hba *hba = container_of(to_delayed_work(work),
6062 struct ufs_hba,
6063 rpm_dev_flush_recheck_work);
6064 /*
6065 * To prevent unnecessary VCC power drain after device finishes
6066 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
6067 * after a certain delay to recheck the threshold by next runtime
6068 * suspend.
6069 */
6070 ufshcd_rpm_get_sync(hba);
6071 ufshcd_rpm_put_sync(hba);
6072 }
6073
6074 /**
6075 * ufshcd_exception_event_handler - handle exceptions raised by device
6076 * @work: pointer to work data
6077 *
6078 * Read bExceptionEventStatus attribute from the device and handle the
6079 * exception event accordingly.
6080 */
ufshcd_exception_event_handler(struct work_struct * work)6081 static void ufshcd_exception_event_handler(struct work_struct *work)
6082 {
6083 struct ufs_hba *hba;
6084 int err;
6085 u32 status = 0;
6086 hba = container_of(work, struct ufs_hba, eeh_work);
6087
6088 ufshcd_scsi_block_requests(hba);
6089 err = ufshcd_get_ee_status(hba, &status);
6090 if (err) {
6091 dev_err(hba->dev, "%s: failed to get exception status %d\n",
6092 __func__, err);
6093 goto out;
6094 }
6095
6096 trace_ufshcd_exception_event(dev_name(hba->dev), status);
6097
6098 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
6099 ufshcd_bkops_exception_event_handler(hba);
6100
6101 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
6102 ufshcd_temp_exception_event_handler(hba, status);
6103
6104 ufs_debugfs_exception_event(hba, status);
6105 out:
6106 ufshcd_scsi_unblock_requests(hba);
6107 }
6108
6109 /* Complete requests that have door-bell cleared */
ufshcd_complete_requests(struct ufs_hba * hba,bool force_compl)6110 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl)
6111 {
6112 if (is_mcq_enabled(hba))
6113 ufshcd_mcq_compl_pending_transfer(hba, force_compl);
6114 else
6115 ufshcd_transfer_req_compl(hba);
6116
6117 ufshcd_tmc_handler(hba);
6118 }
6119
6120 /**
6121 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
6122 * to recover from the DL NAC errors or not.
6123 * @hba: per-adapter instance
6124 *
6125 * Return: true if error handling is required, false otherwise.
6126 */
ufshcd_quirk_dl_nac_errors(struct ufs_hba * hba)6127 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
6128 {
6129 unsigned long flags;
6130 bool err_handling = true;
6131
6132 spin_lock_irqsave(hba->host->host_lock, flags);
6133 /*
6134 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
6135 * device fatal error and/or DL NAC & REPLAY timeout errors.
6136 */
6137 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
6138 goto out;
6139
6140 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
6141 ((hba->saved_err & UIC_ERROR) &&
6142 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
6143 goto out;
6144
6145 if ((hba->saved_err & UIC_ERROR) &&
6146 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
6147 int err;
6148 /*
6149 * wait for 50ms to see if we can get any other errors or not.
6150 */
6151 spin_unlock_irqrestore(hba->host->host_lock, flags);
6152 msleep(50);
6153 spin_lock_irqsave(hba->host->host_lock, flags);
6154
6155 /*
6156 * now check if we have got any other severe errors other than
6157 * DL NAC error?
6158 */
6159 if ((hba->saved_err & INT_FATAL_ERRORS) ||
6160 ((hba->saved_err & UIC_ERROR) &&
6161 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6162 goto out;
6163
6164 /*
6165 * As DL NAC is the only error received so far, send out NOP
6166 * command to confirm if link is still active or not.
6167 * - If we don't get any response then do error recovery.
6168 * - If we get response then clear the DL NAC error bit.
6169 */
6170
6171 spin_unlock_irqrestore(hba->host->host_lock, flags);
6172 err = ufshcd_verify_dev_init(hba);
6173 spin_lock_irqsave(hba->host->host_lock, flags);
6174
6175 if (err)
6176 goto out;
6177
6178 /* Link seems to be alive hence ignore the DL NAC errors */
6179 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6180 hba->saved_err &= ~UIC_ERROR;
6181 /* clear NAC error */
6182 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6183 if (!hba->saved_uic_err)
6184 err_handling = false;
6185 }
6186 out:
6187 spin_unlock_irqrestore(hba->host->host_lock, flags);
6188 return err_handling;
6189 }
6190
6191 /* host lock must be held before calling this func */
ufshcd_is_saved_err_fatal(struct ufs_hba * hba)6192 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6193 {
6194 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6195 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6196 }
6197
ufshcd_schedule_eh_work(struct ufs_hba * hba)6198 void ufshcd_schedule_eh_work(struct ufs_hba *hba)
6199 {
6200 lockdep_assert_held(hba->host->host_lock);
6201
6202 /* handle fatal errors only when link is not in error state */
6203 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6204 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6205 ufshcd_is_saved_err_fatal(hba))
6206 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6207 else
6208 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6209 queue_work(hba->eh_wq, &hba->eh_work);
6210 }
6211 }
6212
ufshcd_force_error_recovery(struct ufs_hba * hba)6213 static void ufshcd_force_error_recovery(struct ufs_hba *hba)
6214 {
6215 spin_lock_irq(hba->host->host_lock);
6216 hba->force_reset = true;
6217 ufshcd_schedule_eh_work(hba);
6218 spin_unlock_irq(hba->host->host_lock);
6219 }
6220
ufshcd_clk_scaling_allow(struct ufs_hba * hba,bool allow)6221 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6222 {
6223 mutex_lock(&hba->wb_mutex);
6224 down_write(&hba->clk_scaling_lock);
6225 hba->clk_scaling.is_allowed = allow;
6226 up_write(&hba->clk_scaling_lock);
6227 mutex_unlock(&hba->wb_mutex);
6228 }
6229
ufshcd_clk_scaling_suspend(struct ufs_hba * hba,bool suspend)6230 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6231 {
6232 if (suspend) {
6233 if (hba->clk_scaling.is_enabled)
6234 ufshcd_suspend_clkscaling(hba);
6235 ufshcd_clk_scaling_allow(hba, false);
6236 } else {
6237 ufshcd_clk_scaling_allow(hba, true);
6238 if (hba->clk_scaling.is_enabled)
6239 ufshcd_resume_clkscaling(hba);
6240 }
6241 }
6242
ufshcd_err_handling_prepare(struct ufs_hba * hba)6243 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6244 {
6245 ufshcd_rpm_get_sync(hba);
6246 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
6247 hba->is_sys_suspended) {
6248 enum ufs_pm_op pm_op;
6249
6250 /*
6251 * Don't assume anything of resume, if
6252 * resume fails, irq and clocks can be OFF, and powers
6253 * can be OFF or in LPM.
6254 */
6255 ufshcd_setup_hba_vreg(hba, true);
6256 ufshcd_enable_irq(hba);
6257 ufshcd_setup_vreg(hba, true);
6258 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6259 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6260 ufshcd_hold(hba);
6261 if (!ufshcd_is_clkgating_allowed(hba))
6262 ufshcd_setup_clocks(hba, true);
6263 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6264 ufshcd_vops_resume(hba, pm_op);
6265 } else {
6266 ufshcd_hold(hba);
6267 if (ufshcd_is_clkscaling_supported(hba) &&
6268 hba->clk_scaling.is_enabled)
6269 ufshcd_suspend_clkscaling(hba);
6270 ufshcd_clk_scaling_allow(hba, false);
6271 }
6272 ufshcd_scsi_block_requests(hba);
6273 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */
6274 blk_mq_wait_quiesce_done(&hba->host->tag_set);
6275 cancel_work_sync(&hba->eeh_work);
6276 }
6277
ufshcd_err_handling_unprepare(struct ufs_hba * hba)6278 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6279 {
6280 ufshcd_scsi_unblock_requests(hba);
6281 ufshcd_release(hba);
6282 if (ufshcd_is_clkscaling_supported(hba))
6283 ufshcd_clk_scaling_suspend(hba, false);
6284 ufshcd_rpm_put(hba);
6285 }
6286
ufshcd_err_handling_should_stop(struct ufs_hba * hba)6287 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6288 {
6289 return (!hba->is_powered || hba->shutting_down ||
6290 !hba->ufs_device_wlun ||
6291 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
6292 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
6293 ufshcd_is_link_broken(hba))));
6294 }
6295
6296 #ifdef CONFIG_PM
ufshcd_recover_pm_error(struct ufs_hba * hba)6297 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6298 {
6299 struct Scsi_Host *shost = hba->host;
6300 struct scsi_device *sdev;
6301 struct request_queue *q;
6302 int ret;
6303
6304 hba->is_sys_suspended = false;
6305 /*
6306 * Set RPM status of wlun device to RPM_ACTIVE,
6307 * this also clears its runtime error.
6308 */
6309 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
6310
6311 /* hba device might have a runtime error otherwise */
6312 if (ret)
6313 ret = pm_runtime_set_active(hba->dev);
6314 /*
6315 * If wlun device had runtime error, we also need to resume those
6316 * consumer scsi devices in case any of them has failed to be
6317 * resumed due to supplier runtime resume failure. This is to unblock
6318 * blk_queue_enter in case there are bios waiting inside it.
6319 */
6320 if (!ret) {
6321 shost_for_each_device(sdev, shost) {
6322 q = sdev->request_queue;
6323 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6324 q->rpm_status == RPM_SUSPENDING))
6325 pm_request_resume(q->dev);
6326 }
6327 }
6328 }
6329 #else
ufshcd_recover_pm_error(struct ufs_hba * hba)6330 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6331 {
6332 }
6333 #endif
6334
ufshcd_is_pwr_mode_restore_needed(struct ufs_hba * hba)6335 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6336 {
6337 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6338 u32 mode;
6339
6340 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6341
6342 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6343 return true;
6344
6345 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6346 return true;
6347
6348 return false;
6349 }
6350
ufshcd_abort_one(struct request * rq,void * priv)6351 static bool ufshcd_abort_one(struct request *rq, void *priv)
6352 {
6353 int *ret = priv;
6354 u32 tag = rq->tag;
6355 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq);
6356 struct scsi_device *sdev = cmd->device;
6357 struct Scsi_Host *shost = sdev->host;
6358 struct ufs_hba *hba = shost_priv(shost);
6359 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6360 struct ufs_hw_queue *hwq;
6361 unsigned long flags;
6362
6363 *ret = ufshcd_try_to_abort_task(hba, tag);
6364 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag,
6365 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1,
6366 *ret ? "failed" : "succeeded");
6367
6368 /* Release cmd in MCQ mode if abort succeeds */
6369 if (is_mcq_enabled(hba) && (*ret == 0)) {
6370 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd));
6371 if (!hwq)
6372 return 0;
6373 spin_lock_irqsave(&hwq->cq_lock, flags);
6374 if (ufshcd_cmd_inflight(lrbp->cmd))
6375 ufshcd_release_scsi_cmd(hba, lrbp);
6376 spin_unlock_irqrestore(&hwq->cq_lock, flags);
6377 }
6378
6379 return *ret == 0;
6380 }
6381
6382 /**
6383 * ufshcd_abort_all - Abort all pending commands.
6384 * @hba: Host bus adapter pointer.
6385 *
6386 * Return: true if and only if the host controller needs to be reset.
6387 */
ufshcd_abort_all(struct ufs_hba * hba)6388 static bool ufshcd_abort_all(struct ufs_hba *hba)
6389 {
6390 int tag, ret = 0;
6391
6392 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret);
6393 if (ret)
6394 goto out;
6395
6396 /* Clear pending task management requests */
6397 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6398 ret = ufshcd_clear_tm_cmd(hba, tag);
6399 if (ret)
6400 goto out;
6401 }
6402
6403 out:
6404 /* Complete the requests that are cleared by s/w */
6405 ufshcd_complete_requests(hba, false);
6406
6407 return ret != 0;
6408 }
6409
6410 /**
6411 * ufshcd_err_handler - handle UFS errors that require s/w attention
6412 * @work: pointer to work structure
6413 */
ufshcd_err_handler(struct work_struct * work)6414 static void ufshcd_err_handler(struct work_struct *work)
6415 {
6416 int retries = MAX_ERR_HANDLER_RETRIES;
6417 struct ufs_hba *hba;
6418 unsigned long flags;
6419 bool needs_restore;
6420 bool needs_reset;
6421 int pmc_err;
6422
6423 hba = container_of(work, struct ufs_hba, eh_work);
6424
6425 dev_info(hba->dev,
6426 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6427 __func__, ufshcd_state_name[hba->ufshcd_state],
6428 hba->is_powered, hba->shutting_down, hba->saved_err,
6429 hba->saved_uic_err, hba->force_reset,
6430 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6431
6432 down(&hba->host_sem);
6433 spin_lock_irqsave(hba->host->host_lock, flags);
6434 if (ufshcd_err_handling_should_stop(hba)) {
6435 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6436 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6437 spin_unlock_irqrestore(hba->host->host_lock, flags);
6438 up(&hba->host_sem);
6439 return;
6440 }
6441 ufshcd_set_eh_in_progress(hba);
6442 spin_unlock_irqrestore(hba->host->host_lock, flags);
6443 ufshcd_err_handling_prepare(hba);
6444 /* Complete requests that have door-bell cleared by h/w */
6445 ufshcd_complete_requests(hba, false);
6446 spin_lock_irqsave(hba->host->host_lock, flags);
6447 again:
6448 needs_restore = false;
6449 needs_reset = false;
6450
6451 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6452 hba->ufshcd_state = UFSHCD_STATE_RESET;
6453 /*
6454 * A full reset and restore might have happened after preparation
6455 * is finished, double check whether we should stop.
6456 */
6457 if (ufshcd_err_handling_should_stop(hba))
6458 goto skip_err_handling;
6459
6460 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6461 bool ret;
6462
6463 spin_unlock_irqrestore(hba->host->host_lock, flags);
6464 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6465 ret = ufshcd_quirk_dl_nac_errors(hba);
6466 spin_lock_irqsave(hba->host->host_lock, flags);
6467 if (!ret && ufshcd_err_handling_should_stop(hba))
6468 goto skip_err_handling;
6469 }
6470
6471 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6472 (hba->saved_uic_err &&
6473 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6474 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6475
6476 spin_unlock_irqrestore(hba->host->host_lock, flags);
6477 ufshcd_print_host_state(hba);
6478 ufshcd_print_pwr_info(hba);
6479 ufshcd_print_evt_hist(hba);
6480 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6481 ufshcd_print_trs_all(hba, pr_prdt);
6482 spin_lock_irqsave(hba->host->host_lock, flags);
6483 }
6484
6485 /*
6486 * if host reset is required then skip clearing the pending
6487 * transfers forcefully because they will get cleared during
6488 * host reset and restore
6489 */
6490 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6491 ufshcd_is_saved_err_fatal(hba) ||
6492 ((hba->saved_err & UIC_ERROR) &&
6493 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6494 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6495 needs_reset = true;
6496 goto do_reset;
6497 }
6498
6499 /*
6500 * If LINERESET was caught, UFS might have been put to PWM mode,
6501 * check if power mode restore is needed.
6502 */
6503 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6504 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6505 if (!hba->saved_uic_err)
6506 hba->saved_err &= ~UIC_ERROR;
6507 spin_unlock_irqrestore(hba->host->host_lock, flags);
6508 if (ufshcd_is_pwr_mode_restore_needed(hba))
6509 needs_restore = true;
6510 spin_lock_irqsave(hba->host->host_lock, flags);
6511 if (!hba->saved_err && !needs_restore)
6512 goto skip_err_handling;
6513 }
6514
6515 hba->silence_err_logs = true;
6516 /* release lock as clear command might sleep */
6517 spin_unlock_irqrestore(hba->host->host_lock, flags);
6518
6519 needs_reset = ufshcd_abort_all(hba);
6520
6521 spin_lock_irqsave(hba->host->host_lock, flags);
6522 hba->silence_err_logs = false;
6523 if (needs_reset)
6524 goto do_reset;
6525
6526 /*
6527 * After all reqs and tasks are cleared from doorbell,
6528 * now it is safe to retore power mode.
6529 */
6530 if (needs_restore) {
6531 spin_unlock_irqrestore(hba->host->host_lock, flags);
6532 /*
6533 * Hold the scaling lock just in case dev cmds
6534 * are sent via bsg and/or sysfs.
6535 */
6536 down_write(&hba->clk_scaling_lock);
6537 hba->force_pmc = true;
6538 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6539 if (pmc_err) {
6540 needs_reset = true;
6541 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6542 __func__, pmc_err);
6543 }
6544 hba->force_pmc = false;
6545 ufshcd_print_pwr_info(hba);
6546 up_write(&hba->clk_scaling_lock);
6547 spin_lock_irqsave(hba->host->host_lock, flags);
6548 }
6549
6550 do_reset:
6551 /* Fatal errors need reset */
6552 if (needs_reset) {
6553 int err;
6554
6555 hba->force_reset = false;
6556 spin_unlock_irqrestore(hba->host->host_lock, flags);
6557 err = ufshcd_reset_and_restore(hba);
6558 if (err)
6559 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6560 __func__, err);
6561 else
6562 ufshcd_recover_pm_error(hba);
6563 spin_lock_irqsave(hba->host->host_lock, flags);
6564 }
6565
6566 skip_err_handling:
6567 if (!needs_reset) {
6568 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6569 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6570 if (hba->saved_err || hba->saved_uic_err)
6571 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6572 __func__, hba->saved_err, hba->saved_uic_err);
6573 }
6574 /* Exit in an operational state or dead */
6575 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6576 hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6577 if (--retries)
6578 goto again;
6579 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6580 }
6581 ufshcd_clear_eh_in_progress(hba);
6582 spin_unlock_irqrestore(hba->host->host_lock, flags);
6583 ufshcd_err_handling_unprepare(hba);
6584 up(&hba->host_sem);
6585
6586 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6587 ufshcd_state_name[hba->ufshcd_state]);
6588 }
6589
6590 /**
6591 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6592 * @hba: per-adapter instance
6593 *
6594 * Return:
6595 * IRQ_HANDLED - If interrupt is valid
6596 * IRQ_NONE - If invalid interrupt
6597 */
ufshcd_update_uic_error(struct ufs_hba * hba)6598 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6599 {
6600 u32 reg;
6601 irqreturn_t retval = IRQ_NONE;
6602
6603 /* PHY layer error */
6604 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6605 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6606 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6607 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6608 /*
6609 * To know whether this error is fatal or not, DB timeout
6610 * must be checked but this error is handled separately.
6611 */
6612 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6613 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6614 __func__);
6615
6616 /* Got a LINERESET indication. */
6617 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6618 struct uic_command *cmd = NULL;
6619
6620 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6621 if (hba->uic_async_done && hba->active_uic_cmd)
6622 cmd = hba->active_uic_cmd;
6623 /*
6624 * Ignore the LINERESET during power mode change
6625 * operation via DME_SET command.
6626 */
6627 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6628 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6629 }
6630 retval |= IRQ_HANDLED;
6631 }
6632
6633 /* PA_INIT_ERROR is fatal and needs UIC reset */
6634 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6635 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6636 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6637 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6638
6639 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6640 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6641 else if (hba->dev_quirks &
6642 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6643 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6644 hba->uic_error |=
6645 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6646 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6647 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6648 }
6649 retval |= IRQ_HANDLED;
6650 }
6651
6652 /* UIC NL/TL/DME errors needs software retry */
6653 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6654 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6655 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6656 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6657 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6658 retval |= IRQ_HANDLED;
6659 }
6660
6661 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6662 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6663 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6664 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6665 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6666 retval |= IRQ_HANDLED;
6667 }
6668
6669 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6670 if ((reg & UIC_DME_ERROR) &&
6671 (reg & UIC_DME_ERROR_CODE_MASK)) {
6672 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6673 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6674 retval |= IRQ_HANDLED;
6675 }
6676
6677 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6678 __func__, hba->uic_error);
6679 return retval;
6680 }
6681
6682 /**
6683 * ufshcd_check_errors - Check for errors that need s/w attention
6684 * @hba: per-adapter instance
6685 * @intr_status: interrupt status generated by the controller
6686 *
6687 * Return:
6688 * IRQ_HANDLED - If interrupt is valid
6689 * IRQ_NONE - If invalid interrupt
6690 */
ufshcd_check_errors(struct ufs_hba * hba,u32 intr_status)6691 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6692 {
6693 bool queue_eh_work = false;
6694 irqreturn_t retval = IRQ_NONE;
6695
6696 spin_lock(hba->host->host_lock);
6697 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6698
6699 if (hba->errors & INT_FATAL_ERRORS) {
6700 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6701 hba->errors);
6702 queue_eh_work = true;
6703 }
6704
6705 if (hba->errors & UIC_ERROR) {
6706 hba->uic_error = 0;
6707 retval = ufshcd_update_uic_error(hba);
6708 if (hba->uic_error)
6709 queue_eh_work = true;
6710 }
6711
6712 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6713 dev_err(hba->dev,
6714 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6715 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6716 "Enter" : "Exit",
6717 hba->errors, ufshcd_get_upmcrs(hba));
6718 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6719 hba->errors);
6720 ufshcd_set_link_broken(hba);
6721 queue_eh_work = true;
6722 }
6723
6724 if (queue_eh_work) {
6725 /*
6726 * update the transfer error masks to sticky bits, let's do this
6727 * irrespective of current ufshcd_state.
6728 */
6729 hba->saved_err |= hba->errors;
6730 hba->saved_uic_err |= hba->uic_error;
6731
6732 /* dump controller state before resetting */
6733 if ((hba->saved_err &
6734 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6735 (hba->saved_uic_err &&
6736 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6737 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6738 __func__, hba->saved_err,
6739 hba->saved_uic_err);
6740 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6741 "host_regs: ");
6742 ufshcd_print_pwr_info(hba);
6743 }
6744 ufshcd_schedule_eh_work(hba);
6745 retval |= IRQ_HANDLED;
6746 }
6747 /*
6748 * if (!queue_eh_work) -
6749 * Other errors are either non-fatal where host recovers
6750 * itself without s/w intervention or errors that will be
6751 * handled by the SCSI core layer.
6752 */
6753 hba->errors = 0;
6754 hba->uic_error = 0;
6755 spin_unlock(hba->host->host_lock);
6756 return retval;
6757 }
6758
6759 /**
6760 * ufshcd_tmc_handler - handle task management function completion
6761 * @hba: per adapter instance
6762 *
6763 * Return:
6764 * IRQ_HANDLED - If interrupt is valid
6765 * IRQ_NONE - If invalid interrupt
6766 */
ufshcd_tmc_handler(struct ufs_hba * hba)6767 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6768 {
6769 unsigned long flags, pending, issued;
6770 irqreturn_t ret = IRQ_NONE;
6771 int tag;
6772
6773 spin_lock_irqsave(hba->host->host_lock, flags);
6774 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6775 issued = hba->outstanding_tasks & ~pending;
6776 for_each_set_bit(tag, &issued, hba->nutmrs) {
6777 struct request *req = hba->tmf_rqs[tag];
6778 struct completion *c = req->end_io_data;
6779
6780 complete(c);
6781 ret = IRQ_HANDLED;
6782 }
6783 spin_unlock_irqrestore(hba->host->host_lock, flags);
6784
6785 return ret;
6786 }
6787
6788 /**
6789 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events
6790 * @hba: per adapter instance
6791 *
6792 * Return: IRQ_HANDLED if interrupt is handled.
6793 */
ufshcd_handle_mcq_cq_events(struct ufs_hba * hba)6794 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba)
6795 {
6796 struct ufs_hw_queue *hwq;
6797 unsigned long outstanding_cqs;
6798 unsigned int nr_queues;
6799 int i, ret;
6800 u32 events;
6801
6802 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs);
6803 if (ret)
6804 outstanding_cqs = (1U << hba->nr_hw_queues) - 1;
6805
6806 /* Exclude the poll queues */
6807 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
6808 for_each_set_bit(i, &outstanding_cqs, nr_queues) {
6809 hwq = &hba->uhq[i];
6810
6811 events = ufshcd_mcq_read_cqis(hba, i);
6812 if (events)
6813 ufshcd_mcq_write_cqis(hba, events, i);
6814
6815 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
6816 ufshcd_mcq_poll_cqe_lock(hba, hwq);
6817 }
6818
6819 return IRQ_HANDLED;
6820 }
6821
6822 /**
6823 * ufshcd_sl_intr - Interrupt service routine
6824 * @hba: per adapter instance
6825 * @intr_status: contains interrupts generated by the controller
6826 *
6827 * Return:
6828 * IRQ_HANDLED - If interrupt is valid
6829 * IRQ_NONE - If invalid interrupt
6830 */
ufshcd_sl_intr(struct ufs_hba * hba,u32 intr_status)6831 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6832 {
6833 irqreturn_t retval = IRQ_NONE;
6834
6835 if (intr_status & UFSHCD_UIC_MASK)
6836 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6837
6838 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6839 retval |= ufshcd_check_errors(hba, intr_status);
6840
6841 if (intr_status & UTP_TASK_REQ_COMPL)
6842 retval |= ufshcd_tmc_handler(hba);
6843
6844 if (intr_status & UTP_TRANSFER_REQ_COMPL)
6845 retval |= ufshcd_transfer_req_compl(hba);
6846
6847 if (intr_status & MCQ_CQ_EVENT_STATUS)
6848 retval |= ufshcd_handle_mcq_cq_events(hba);
6849
6850 return retval;
6851 }
6852
6853 /**
6854 * ufshcd_intr - Main interrupt service routine
6855 * @irq: irq number
6856 * @__hba: pointer to adapter instance
6857 *
6858 * Return:
6859 * IRQ_HANDLED - If interrupt is valid
6860 * IRQ_NONE - If invalid interrupt
6861 */
ufshcd_intr(int irq,void * __hba)6862 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6863 {
6864 u32 intr_status, enabled_intr_status = 0;
6865 irqreturn_t retval = IRQ_NONE;
6866 struct ufs_hba *hba = __hba;
6867 int retries = hba->nutrs;
6868
6869 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6870 hba->ufs_stats.last_intr_status = intr_status;
6871 hba->ufs_stats.last_intr_ts = local_clock();
6872
6873 /*
6874 * There could be max of hba->nutrs reqs in flight and in worst case
6875 * if the reqs get finished 1 by 1 after the interrupt status is
6876 * read, make sure we handle them by checking the interrupt status
6877 * again in a loop until we process all of the reqs before returning.
6878 */
6879 while (intr_status && retries--) {
6880 enabled_intr_status =
6881 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6882 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6883 if (enabled_intr_status)
6884 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6885
6886 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6887 }
6888
6889 if (enabled_intr_status && retval == IRQ_NONE &&
6890 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6891 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6892 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6893 __func__,
6894 intr_status,
6895 hba->ufs_stats.last_intr_status,
6896 enabled_intr_status);
6897 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6898 }
6899
6900 return retval;
6901 }
6902
ufshcd_clear_tm_cmd(struct ufs_hba * hba,int tag)6903 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6904 {
6905 int err = 0;
6906 u32 mask = 1 << tag;
6907 unsigned long flags;
6908
6909 if (!test_bit(tag, &hba->outstanding_tasks))
6910 goto out;
6911
6912 spin_lock_irqsave(hba->host->host_lock, flags);
6913 ufshcd_utmrl_clear(hba, tag);
6914 spin_unlock_irqrestore(hba->host->host_lock, flags);
6915
6916 /* poll for max. 1 sec to clear door bell register by h/w */
6917 err = ufshcd_wait_for_register(hba,
6918 REG_UTP_TASK_REQ_DOOR_BELL,
6919 mask, 0, 1000, 1000);
6920
6921 dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
6922 tag, err < 0 ? "failed" : "succeeded");
6923
6924 out:
6925 return err;
6926 }
6927
__ufshcd_issue_tm_cmd(struct ufs_hba * hba,struct utp_task_req_desc * treq,u8 tm_function)6928 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6929 struct utp_task_req_desc *treq, u8 tm_function)
6930 {
6931 struct request_queue *q = hba->tmf_queue;
6932 struct Scsi_Host *host = hba->host;
6933 DECLARE_COMPLETION_ONSTACK(wait);
6934 struct request *req;
6935 unsigned long flags;
6936 int task_tag, err;
6937
6938 /*
6939 * blk_mq_alloc_request() is used here only to get a free tag.
6940 */
6941 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
6942 if (IS_ERR(req))
6943 return PTR_ERR(req);
6944
6945 req->end_io_data = &wait;
6946 ufshcd_hold(hba);
6947
6948 spin_lock_irqsave(host->host_lock, flags);
6949
6950 task_tag = req->tag;
6951 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n",
6952 task_tag);
6953 hba->tmf_rqs[req->tag] = req;
6954 treq->upiu_req.req_header.task_tag = task_tag;
6955
6956 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6957 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6958
6959 /* send command to the controller */
6960 __set_bit(task_tag, &hba->outstanding_tasks);
6961
6962 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6963 /* Make sure that doorbell is committed immediately */
6964 wmb();
6965
6966 spin_unlock_irqrestore(host->host_lock, flags);
6967
6968 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6969
6970 /* wait until the task management command is completed */
6971 err = wait_for_completion_io_timeout(&wait,
6972 msecs_to_jiffies(TM_CMD_TIMEOUT));
6973 if (!err) {
6974 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6975 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6976 __func__, tm_function);
6977 if (ufshcd_clear_tm_cmd(hba, task_tag))
6978 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6979 __func__, task_tag);
6980 err = -ETIMEDOUT;
6981 } else {
6982 err = 0;
6983 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6984
6985 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6986 }
6987
6988 spin_lock_irqsave(hba->host->host_lock, flags);
6989 hba->tmf_rqs[req->tag] = NULL;
6990 __clear_bit(task_tag, &hba->outstanding_tasks);
6991 spin_unlock_irqrestore(hba->host->host_lock, flags);
6992
6993 ufshcd_release(hba);
6994 blk_mq_free_request(req);
6995
6996 return err;
6997 }
6998
6999 /**
7000 * ufshcd_issue_tm_cmd - issues task management commands to controller
7001 * @hba: per adapter instance
7002 * @lun_id: LUN ID to which TM command is sent
7003 * @task_id: task ID to which the TM command is applicable
7004 * @tm_function: task management function opcode
7005 * @tm_response: task management service response return value
7006 *
7007 * Return: non-zero value on error, zero on success.
7008 */
ufshcd_issue_tm_cmd(struct ufs_hba * hba,int lun_id,int task_id,u8 tm_function,u8 * tm_response)7009 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
7010 u8 tm_function, u8 *tm_response)
7011 {
7012 struct utp_task_req_desc treq = { };
7013 enum utp_ocs ocs_value;
7014 int err;
7015
7016 /* Configure task request descriptor */
7017 treq.header.interrupt = 1;
7018 treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7019
7020 /* Configure task request UPIU */
7021 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ;
7022 treq.upiu_req.req_header.lun = lun_id;
7023 treq.upiu_req.req_header.tm_function = tm_function;
7024
7025 /*
7026 * The host shall provide the same value for LUN field in the basic
7027 * header and for Input Parameter.
7028 */
7029 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
7030 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
7031
7032 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
7033 if (err == -ETIMEDOUT)
7034 return err;
7035
7036 ocs_value = treq.header.ocs & MASK_OCS;
7037 if (ocs_value != OCS_SUCCESS)
7038 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
7039 __func__, ocs_value);
7040 else if (tm_response)
7041 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
7042 MASK_TM_SERVICE_RESP;
7043 return err;
7044 }
7045
7046 /**
7047 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
7048 * @hba: per-adapter instance
7049 * @req_upiu: upiu request
7050 * @rsp_upiu: upiu reply
7051 * @desc_buff: pointer to descriptor buffer, NULL if NA
7052 * @buff_len: descriptor size, 0 if NA
7053 * @cmd_type: specifies the type (NOP, Query...)
7054 * @desc_op: descriptor operation
7055 *
7056 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
7057 * Therefore, it "rides" the device management infrastructure: uses its tag and
7058 * tasks work queues.
7059 *
7060 * Since there is only one available tag for device management commands,
7061 * the caller is expected to hold the hba->dev_cmd.lock mutex.
7062 *
7063 * Return: 0 upon success; < 0 upon failure.
7064 */
ufshcd_issue_devman_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,u8 * desc_buff,int * buff_len,enum dev_cmd_type cmd_type,enum query_opcode desc_op)7065 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
7066 struct utp_upiu_req *req_upiu,
7067 struct utp_upiu_req *rsp_upiu,
7068 u8 *desc_buff, int *buff_len,
7069 enum dev_cmd_type cmd_type,
7070 enum query_opcode desc_op)
7071 {
7072 DECLARE_COMPLETION_ONSTACK(wait);
7073 const u32 tag = hba->reserved_slot;
7074 struct ufshcd_lrb *lrbp;
7075 int err = 0;
7076 u8 upiu_flags;
7077
7078 /* Protects use of hba->reserved_slot. */
7079 lockdep_assert_held(&hba->dev_cmd.lock);
7080
7081 down_read(&hba->clk_scaling_lock);
7082
7083 lrbp = &hba->lrb[tag];
7084 lrbp->cmd = NULL;
7085 lrbp->task_tag = tag;
7086 lrbp->lun = 0;
7087 lrbp->intr_cmd = true;
7088 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7089 hba->dev_cmd.type = cmd_type;
7090
7091 if (hba->ufs_version <= ufshci_version(1, 1))
7092 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
7093 else
7094 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7095
7096 /* update the task tag in the request upiu */
7097 req_upiu->header.task_tag = tag;
7098
7099 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
7100
7101 /* just copy the upiu request as it is */
7102 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7103 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
7104 /* The Data Segment Area is optional depending upon the query
7105 * function value. for WRITE DESCRIPTOR, the data segment
7106 * follows right after the tsf.
7107 */
7108 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
7109 *buff_len = 0;
7110 }
7111
7112 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7113
7114 hba->dev_cmd.complete = &wait;
7115
7116 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
7117
7118 ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7119 /*
7120 * ignore the returning value here - ufshcd_check_query_response is
7121 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
7122 * read the response directly ignoring all errors.
7123 */
7124 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
7125
7126 /* just copy the upiu response as it is */
7127 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7128 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
7129 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
7130 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
7131 .data_segment_length);
7132
7133 if (*buff_len >= resp_len) {
7134 memcpy(desc_buff, descp, resp_len);
7135 *buff_len = resp_len;
7136 } else {
7137 dev_warn(hba->dev,
7138 "%s: rsp size %d is bigger than buffer size %d",
7139 __func__, resp_len, *buff_len);
7140 *buff_len = 0;
7141 err = -EINVAL;
7142 }
7143 }
7144 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
7145 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
7146
7147 up_read(&hba->clk_scaling_lock);
7148 return err;
7149 }
7150
7151 /**
7152 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
7153 * @hba: per-adapter instance
7154 * @req_upiu: upiu request
7155 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
7156 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
7157 * @desc_buff: pointer to descriptor buffer, NULL if NA
7158 * @buff_len: descriptor size, 0 if NA
7159 * @desc_op: descriptor operation
7160 *
7161 * Supports UTP Transfer requests (nop and query), and UTP Task
7162 * Management requests.
7163 * It is up to the caller to fill the upiu conent properly, as it will
7164 * be copied without any further input validations.
7165 *
7166 * Return: 0 upon success; < 0 upon failure.
7167 */
ufshcd_exec_raw_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,enum upiu_request_transaction msgcode,u8 * desc_buff,int * buff_len,enum query_opcode desc_op)7168 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
7169 struct utp_upiu_req *req_upiu,
7170 struct utp_upiu_req *rsp_upiu,
7171 enum upiu_request_transaction msgcode,
7172 u8 *desc_buff, int *buff_len,
7173 enum query_opcode desc_op)
7174 {
7175 int err;
7176 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
7177 struct utp_task_req_desc treq = { };
7178 enum utp_ocs ocs_value;
7179 u8 tm_f = req_upiu->header.tm_function;
7180
7181 switch (msgcode) {
7182 case UPIU_TRANSACTION_NOP_OUT:
7183 cmd_type = DEV_CMD_TYPE_NOP;
7184 fallthrough;
7185 case UPIU_TRANSACTION_QUERY_REQ:
7186 ufshcd_hold(hba);
7187 mutex_lock(&hba->dev_cmd.lock);
7188 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
7189 desc_buff, buff_len,
7190 cmd_type, desc_op);
7191 mutex_unlock(&hba->dev_cmd.lock);
7192 ufshcd_release(hba);
7193
7194 break;
7195 case UPIU_TRANSACTION_TASK_REQ:
7196 treq.header.interrupt = 1;
7197 treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7198
7199 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
7200
7201 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
7202 if (err == -ETIMEDOUT)
7203 break;
7204
7205 ocs_value = treq.header.ocs & MASK_OCS;
7206 if (ocs_value != OCS_SUCCESS) {
7207 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
7208 ocs_value);
7209 break;
7210 }
7211
7212 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
7213
7214 break;
7215 default:
7216 err = -EINVAL;
7217
7218 break;
7219 }
7220
7221 return err;
7222 }
7223
7224 /**
7225 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request
7226 * @hba: per adapter instance
7227 * @req_upiu: upiu request
7228 * @rsp_upiu: upiu reply
7229 * @req_ehs: EHS field which contains Advanced RPMB Request Message
7230 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message
7231 * @sg_cnt: The number of sg lists actually used
7232 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation
7233 * @dir: DMA direction
7234 *
7235 * Return: zero on success, non-zero on failure.
7236 */
ufshcd_advanced_rpmb_req_handler(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,struct ufs_ehs * req_ehs,struct ufs_ehs * rsp_ehs,int sg_cnt,struct scatterlist * sg_list,enum dma_data_direction dir)7237 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
7238 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs,
7239 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list,
7240 enum dma_data_direction dir)
7241 {
7242 DECLARE_COMPLETION_ONSTACK(wait);
7243 const u32 tag = hba->reserved_slot;
7244 struct ufshcd_lrb *lrbp;
7245 int err = 0;
7246 int result;
7247 u8 upiu_flags;
7248 u8 *ehs_data;
7249 u16 ehs_len;
7250
7251 /* Protects use of hba->reserved_slot. */
7252 ufshcd_hold(hba);
7253 mutex_lock(&hba->dev_cmd.lock);
7254 down_read(&hba->clk_scaling_lock);
7255
7256 lrbp = &hba->lrb[tag];
7257 lrbp->cmd = NULL;
7258 lrbp->task_tag = tag;
7259 lrbp->lun = UFS_UPIU_RPMB_WLUN;
7260
7261 lrbp->intr_cmd = true;
7262 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7263 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB;
7264
7265 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */
7266 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7267
7268 /*
7269 * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes
7270 * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1,
7271 * HW controller takes EHS length from UTRD.
7272 */
7273 if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED)
7274 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2);
7275 else
7276 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0);
7277
7278 /* update the task tag */
7279 req_upiu->header.task_tag = tag;
7280
7281 /* copy the UPIU(contains CDB) request as it is */
7282 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7283 /* Copy EHS, starting with byte32, immediately after the CDB package */
7284 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs));
7285
7286 if (dir != DMA_NONE && sg_list)
7287 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list);
7288
7289 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7290
7291 hba->dev_cmd.complete = &wait;
7292
7293 ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7294
7295 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT);
7296
7297 if (!err) {
7298 /* Just copy the upiu response as it is */
7299 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7300 /* Get the response UPIU result */
7301 result = (lrbp->ucd_rsp_ptr->header.response << 8) |
7302 lrbp->ucd_rsp_ptr->header.status;
7303
7304 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length;
7305 /*
7306 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data
7307 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB
7308 * Message is 02h
7309 */
7310 if (ehs_len == 2 && rsp_ehs) {
7311 /*
7312 * ucd_rsp_ptr points to a buffer with a length of 512 bytes
7313 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32
7314 */
7315 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE;
7316 memcpy(rsp_ehs, ehs_data, ehs_len * 32);
7317 }
7318 }
7319
7320 up_read(&hba->clk_scaling_lock);
7321 mutex_unlock(&hba->dev_cmd.lock);
7322 ufshcd_release(hba);
7323 return err ? : result;
7324 }
7325
7326 /**
7327 * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
7328 * @cmd: SCSI command pointer
7329 *
7330 * Return: SUCCESS or FAILED.
7331 */
ufshcd_eh_device_reset_handler(struct scsi_cmnd * cmd)7332 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7333 {
7334 unsigned long flags, pending_reqs = 0, not_cleared = 0;
7335 struct Scsi_Host *host;
7336 struct ufs_hba *hba;
7337 struct ufs_hw_queue *hwq;
7338 struct ufshcd_lrb *lrbp;
7339 u32 pos, not_cleared_mask = 0;
7340 int err;
7341 u8 resp = 0xF, lun;
7342
7343 host = cmd->device->host;
7344 hba = shost_priv(host);
7345
7346 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
7347 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
7348 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7349 if (!err)
7350 err = resp;
7351 goto out;
7352 }
7353
7354 if (is_mcq_enabled(hba)) {
7355 for (pos = 0; pos < hba->nutrs; pos++) {
7356 lrbp = &hba->lrb[pos];
7357 if (ufshcd_cmd_inflight(lrbp->cmd) &&
7358 lrbp->lun == lun) {
7359 ufshcd_clear_cmd(hba, pos);
7360 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd));
7361 ufshcd_mcq_poll_cqe_lock(hba, hwq);
7362 }
7363 }
7364 err = 0;
7365 goto out;
7366 }
7367
7368 /* clear the commands that were pending for corresponding LUN */
7369 spin_lock_irqsave(&hba->outstanding_lock, flags);
7370 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
7371 if (hba->lrb[pos].lun == lun)
7372 __set_bit(pos, &pending_reqs);
7373 hba->outstanding_reqs &= ~pending_reqs;
7374 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7375
7376 for_each_set_bit(pos, &pending_reqs, hba->nutrs) {
7377 if (ufshcd_clear_cmd(hba, pos) < 0) {
7378 spin_lock_irqsave(&hba->outstanding_lock, flags);
7379 not_cleared = 1U << pos &
7380 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7381 hba->outstanding_reqs |= not_cleared;
7382 not_cleared_mask |= not_cleared;
7383 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7384
7385 dev_err(hba->dev, "%s: failed to clear request %d\n",
7386 __func__, pos);
7387 }
7388 }
7389 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask);
7390
7391 out:
7392 hba->req_abort_count = 0;
7393 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
7394 if (!err) {
7395 err = SUCCESS;
7396 } else {
7397 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7398 err = FAILED;
7399 }
7400 return err;
7401 }
7402
ufshcd_set_req_abort_skip(struct ufs_hba * hba,unsigned long bitmap)7403 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7404 {
7405 struct ufshcd_lrb *lrbp;
7406 int tag;
7407
7408 for_each_set_bit(tag, &bitmap, hba->nutrs) {
7409 lrbp = &hba->lrb[tag];
7410 lrbp->req_abort_skip = true;
7411 }
7412 }
7413
7414 /**
7415 * ufshcd_try_to_abort_task - abort a specific task
7416 * @hba: Pointer to adapter instance
7417 * @tag: Task tag/index to be aborted
7418 *
7419 * Abort the pending command in device by sending UFS_ABORT_TASK task management
7420 * command, and in host controller by clearing the door-bell register. There can
7421 * be race between controller sending the command to the device while abort is
7422 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7423 * really issued and then try to abort it.
7424 *
7425 * Return: zero on success, non-zero on failure.
7426 */
ufshcd_try_to_abort_task(struct ufs_hba * hba,int tag)7427 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7428 {
7429 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7430 int err = 0;
7431 int poll_cnt;
7432 u8 resp = 0xF;
7433 u32 reg;
7434
7435 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7436 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7437 UFS_QUERY_TASK, &resp);
7438 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7439 /* cmd pending in the device */
7440 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7441 __func__, tag);
7442 break;
7443 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7444 /*
7445 * cmd not pending in the device, check if it is
7446 * in transition.
7447 */
7448 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7449 __func__, tag);
7450 if (is_mcq_enabled(hba)) {
7451 /* MCQ mode */
7452 if (ufshcd_cmd_inflight(lrbp->cmd)) {
7453 /* sleep for max. 200us same delay as in SDB mode */
7454 usleep_range(100, 200);
7455 continue;
7456 }
7457 /* command completed already */
7458 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n",
7459 __func__, tag);
7460 goto out;
7461 }
7462
7463 /* Single Doorbell Mode */
7464 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7465 if (reg & (1 << tag)) {
7466 /* sleep for max. 200us to stabilize */
7467 usleep_range(100, 200);
7468 continue;
7469 }
7470 /* command completed already */
7471 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7472 __func__, tag);
7473 goto out;
7474 } else {
7475 dev_err(hba->dev,
7476 "%s: no response from device. tag = %d, err %d\n",
7477 __func__, tag, err);
7478 if (!err)
7479 err = resp; /* service response error */
7480 goto out;
7481 }
7482 }
7483
7484 if (!poll_cnt) {
7485 err = -EBUSY;
7486 goto out;
7487 }
7488
7489 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7490 UFS_ABORT_TASK, &resp);
7491 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7492 if (!err) {
7493 err = resp; /* service response error */
7494 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7495 __func__, tag, err);
7496 }
7497 goto out;
7498 }
7499
7500 err = ufshcd_clear_cmd(hba, tag);
7501 if (err)
7502 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7503 __func__, tag, err);
7504
7505 out:
7506 return err;
7507 }
7508
7509 /**
7510 * ufshcd_abort - scsi host template eh_abort_handler callback
7511 * @cmd: SCSI command pointer
7512 *
7513 * Return: SUCCESS or FAILED.
7514 */
ufshcd_abort(struct scsi_cmnd * cmd)7515 static int ufshcd_abort(struct scsi_cmnd *cmd)
7516 {
7517 struct Scsi_Host *host = cmd->device->host;
7518 struct ufs_hba *hba = shost_priv(host);
7519 int tag = scsi_cmd_to_rq(cmd)->tag;
7520 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7521 unsigned long flags;
7522 int err = FAILED;
7523 bool outstanding;
7524 u32 reg;
7525
7526 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7527
7528 ufshcd_hold(hba);
7529
7530 if (!is_mcq_enabled(hba)) {
7531 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7532 if (!test_bit(tag, &hba->outstanding_reqs)) {
7533 /* If command is already aborted/completed, return FAILED. */
7534 dev_err(hba->dev,
7535 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7536 __func__, tag, hba->outstanding_reqs, reg);
7537 goto release;
7538 }
7539 }
7540
7541 /* Print Transfer Request of aborted task */
7542 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
7543
7544 /*
7545 * Print detailed info about aborted request.
7546 * As more than one request might get aborted at the same time,
7547 * print full information only for the first aborted request in order
7548 * to reduce repeated printouts. For other aborted requests only print
7549 * basic details.
7550 */
7551 scsi_print_command(cmd);
7552 if (!hba->req_abort_count) {
7553 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7554 ufshcd_print_evt_hist(hba);
7555 ufshcd_print_host_state(hba);
7556 ufshcd_print_pwr_info(hba);
7557 ufshcd_print_tr(hba, tag, true);
7558 } else {
7559 ufshcd_print_tr(hba, tag, false);
7560 }
7561 hba->req_abort_count++;
7562
7563 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) {
7564 /* only execute this code in single doorbell mode */
7565 dev_err(hba->dev,
7566 "%s: cmd was completed, but without a notifying intr, tag = %d",
7567 __func__, tag);
7568 __ufshcd_transfer_req_compl(hba, 1UL << tag);
7569 goto release;
7570 }
7571
7572 /*
7573 * Task abort to the device W-LUN is illegal. When this command
7574 * will fail, due to spec violation, scsi err handling next step
7575 * will be to send LU reset which, again, is a spec violation.
7576 * To avoid these unnecessary/illegal steps, first we clean up
7577 * the lrb taken by this cmd and re-set it in outstanding_reqs,
7578 * then queue the eh_work and bail.
7579 */
7580 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7581 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7582
7583 spin_lock_irqsave(host->host_lock, flags);
7584 hba->force_reset = true;
7585 ufshcd_schedule_eh_work(hba);
7586 spin_unlock_irqrestore(host->host_lock, flags);
7587 goto release;
7588 }
7589
7590 if (is_mcq_enabled(hba)) {
7591 /* MCQ mode. Branch off to handle abort for mcq mode */
7592 err = ufshcd_mcq_abort(cmd);
7593 goto release;
7594 }
7595
7596 /* Skip task abort in case previous aborts failed and report failure */
7597 if (lrbp->req_abort_skip) {
7598 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7599 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7600 goto release;
7601 }
7602
7603 err = ufshcd_try_to_abort_task(hba, tag);
7604 if (err) {
7605 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7606 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7607 err = FAILED;
7608 goto release;
7609 }
7610
7611 /*
7612 * Clear the corresponding bit from outstanding_reqs since the command
7613 * has been aborted successfully.
7614 */
7615 spin_lock_irqsave(&hba->outstanding_lock, flags);
7616 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7617 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7618
7619 if (outstanding)
7620 ufshcd_release_scsi_cmd(hba, lrbp);
7621
7622 err = SUCCESS;
7623
7624 release:
7625 /* Matches the ufshcd_hold() call at the start of this function. */
7626 ufshcd_release(hba);
7627 return err;
7628 }
7629
7630 /**
7631 * ufshcd_host_reset_and_restore - reset and restore host controller
7632 * @hba: per-adapter instance
7633 *
7634 * Note that host controller reset may issue DME_RESET to
7635 * local and remote (device) Uni-Pro stack and the attributes
7636 * are reset to default state.
7637 *
7638 * Return: zero on success, non-zero on failure.
7639 */
ufshcd_host_reset_and_restore(struct ufs_hba * hba)7640 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7641 {
7642 int err;
7643
7644 /*
7645 * Stop the host controller and complete the requests
7646 * cleared by h/w
7647 */
7648 ufshcd_hba_stop(hba);
7649 hba->silence_err_logs = true;
7650 ufshcd_complete_requests(hba, true);
7651 hba->silence_err_logs = false;
7652
7653 /* scale up clocks to max frequency before full reinitialization */
7654 ufshcd_scale_clks(hba, true);
7655
7656 err = ufshcd_hba_enable(hba);
7657
7658 /* Establish the link again and restore the device */
7659 if (!err)
7660 err = ufshcd_probe_hba(hba, false);
7661
7662 if (err)
7663 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7664 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7665 return err;
7666 }
7667
7668 /**
7669 * ufshcd_reset_and_restore - reset and re-initialize host/device
7670 * @hba: per-adapter instance
7671 *
7672 * Reset and recover device, host and re-establish link. This
7673 * is helpful to recover the communication in fatal error conditions.
7674 *
7675 * Return: zero on success, non-zero on failure.
7676 */
ufshcd_reset_and_restore(struct ufs_hba * hba)7677 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7678 {
7679 u32 saved_err = 0;
7680 u32 saved_uic_err = 0;
7681 int err = 0;
7682 unsigned long flags;
7683 int retries = MAX_HOST_RESET_RETRIES;
7684
7685 spin_lock_irqsave(hba->host->host_lock, flags);
7686 do {
7687 /*
7688 * This is a fresh start, cache and clear saved error first,
7689 * in case new error generated during reset and restore.
7690 */
7691 saved_err |= hba->saved_err;
7692 saved_uic_err |= hba->saved_uic_err;
7693 hba->saved_err = 0;
7694 hba->saved_uic_err = 0;
7695 hba->force_reset = false;
7696 hba->ufshcd_state = UFSHCD_STATE_RESET;
7697 spin_unlock_irqrestore(hba->host->host_lock, flags);
7698
7699 /* Reset the attached device */
7700 ufshcd_device_reset(hba);
7701
7702 err = ufshcd_host_reset_and_restore(hba);
7703
7704 spin_lock_irqsave(hba->host->host_lock, flags);
7705 if (err)
7706 continue;
7707 /* Do not exit unless operational or dead */
7708 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7709 hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7710 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7711 err = -EAGAIN;
7712 } while (err && --retries);
7713
7714 /*
7715 * Inform scsi mid-layer that we did reset and allow to handle
7716 * Unit Attention properly.
7717 */
7718 scsi_report_bus_reset(hba->host, 0);
7719 if (err) {
7720 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7721 hba->saved_err |= saved_err;
7722 hba->saved_uic_err |= saved_uic_err;
7723 }
7724 spin_unlock_irqrestore(hba->host->host_lock, flags);
7725
7726 return err;
7727 }
7728
7729 /**
7730 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7731 * @cmd: SCSI command pointer
7732 *
7733 * Return: SUCCESS or FAILED.
7734 */
ufshcd_eh_host_reset_handler(struct scsi_cmnd * cmd)7735 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7736 {
7737 int err = SUCCESS;
7738 unsigned long flags;
7739 struct ufs_hba *hba;
7740
7741 hba = shost_priv(cmd->device->host);
7742
7743 spin_lock_irqsave(hba->host->host_lock, flags);
7744 hba->force_reset = true;
7745 ufshcd_schedule_eh_work(hba);
7746 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7747 spin_unlock_irqrestore(hba->host->host_lock, flags);
7748
7749 flush_work(&hba->eh_work);
7750
7751 spin_lock_irqsave(hba->host->host_lock, flags);
7752 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7753 err = FAILED;
7754 spin_unlock_irqrestore(hba->host->host_lock, flags);
7755
7756 return err;
7757 }
7758
7759 /**
7760 * ufshcd_get_max_icc_level - calculate the ICC level
7761 * @sup_curr_uA: max. current supported by the regulator
7762 * @start_scan: row at the desc table to start scan from
7763 * @buff: power descriptor buffer
7764 *
7765 * Return: calculated max ICC level for specific regulator.
7766 */
ufshcd_get_max_icc_level(int sup_curr_uA,u32 start_scan,const char * buff)7767 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan,
7768 const char *buff)
7769 {
7770 int i;
7771 int curr_uA;
7772 u16 data;
7773 u16 unit;
7774
7775 for (i = start_scan; i >= 0; i--) {
7776 data = get_unaligned_be16(&buff[2 * i]);
7777 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7778 ATTR_ICC_LVL_UNIT_OFFSET;
7779 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7780 switch (unit) {
7781 case UFSHCD_NANO_AMP:
7782 curr_uA = curr_uA / 1000;
7783 break;
7784 case UFSHCD_MILI_AMP:
7785 curr_uA = curr_uA * 1000;
7786 break;
7787 case UFSHCD_AMP:
7788 curr_uA = curr_uA * 1000 * 1000;
7789 break;
7790 case UFSHCD_MICRO_AMP:
7791 default:
7792 break;
7793 }
7794 if (sup_curr_uA >= curr_uA)
7795 break;
7796 }
7797 if (i < 0) {
7798 i = 0;
7799 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7800 }
7801
7802 return (u32)i;
7803 }
7804
7805 /**
7806 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7807 * In case regulators are not initialized we'll return 0
7808 * @hba: per-adapter instance
7809 * @desc_buf: power descriptor buffer to extract ICC levels from.
7810 *
7811 * Return: calculated ICC level.
7812 */
ufshcd_find_max_sup_active_icc_level(struct ufs_hba * hba,const u8 * desc_buf)7813 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7814 const u8 *desc_buf)
7815 {
7816 u32 icc_level = 0;
7817
7818 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7819 !hba->vreg_info.vccq2) {
7820 /*
7821 * Using dev_dbg to avoid messages during runtime PM to avoid
7822 * never-ending cycles of messages written back to storage by
7823 * user space causing runtime resume, causing more messages and
7824 * so on.
7825 */
7826 dev_dbg(hba->dev,
7827 "%s: Regulator capability was not set, actvIccLevel=%d",
7828 __func__, icc_level);
7829 goto out;
7830 }
7831
7832 if (hba->vreg_info.vcc->max_uA)
7833 icc_level = ufshcd_get_max_icc_level(
7834 hba->vreg_info.vcc->max_uA,
7835 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7836 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7837
7838 if (hba->vreg_info.vccq->max_uA)
7839 icc_level = ufshcd_get_max_icc_level(
7840 hba->vreg_info.vccq->max_uA,
7841 icc_level,
7842 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7843
7844 if (hba->vreg_info.vccq2->max_uA)
7845 icc_level = ufshcd_get_max_icc_level(
7846 hba->vreg_info.vccq2->max_uA,
7847 icc_level,
7848 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7849 out:
7850 return icc_level;
7851 }
7852
ufshcd_set_active_icc_lvl(struct ufs_hba * hba)7853 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7854 {
7855 int ret;
7856 u8 *desc_buf;
7857 u32 icc_level;
7858
7859 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7860 if (!desc_buf)
7861 return;
7862
7863 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7864 desc_buf, QUERY_DESC_MAX_SIZE);
7865 if (ret) {
7866 dev_err(hba->dev,
7867 "%s: Failed reading power descriptor ret = %d",
7868 __func__, ret);
7869 goto out;
7870 }
7871
7872 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf);
7873 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7874
7875 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7876 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7877
7878 if (ret)
7879 dev_err(hba->dev,
7880 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7881 __func__, icc_level, ret);
7882
7883 out:
7884 kfree(desc_buf);
7885 }
7886
ufshcd_blk_pm_runtime_init(struct scsi_device * sdev)7887 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7888 {
7889 scsi_autopm_get_device(sdev);
7890 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7891 if (sdev->rpm_autosuspend)
7892 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7893 RPM_AUTOSUSPEND_DELAY_MS);
7894 scsi_autopm_put_device(sdev);
7895 }
7896
7897 /**
7898 * ufshcd_scsi_add_wlus - Adds required W-LUs
7899 * @hba: per-adapter instance
7900 *
7901 * UFS device specification requires the UFS devices to support 4 well known
7902 * logical units:
7903 * "REPORT_LUNS" (address: 01h)
7904 * "UFS Device" (address: 50h)
7905 * "RPMB" (address: 44h)
7906 * "BOOT" (address: 30h)
7907 * UFS device's power management needs to be controlled by "POWER CONDITION"
7908 * field of SSU (START STOP UNIT) command. But this "power condition" field
7909 * will take effect only when its sent to "UFS device" well known logical unit
7910 * hence we require the scsi_device instance to represent this logical unit in
7911 * order for the UFS host driver to send the SSU command for power management.
7912 *
7913 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7914 * Block) LU so user space process can control this LU. User space may also
7915 * want to have access to BOOT LU.
7916 *
7917 * This function adds scsi device instances for each of all well known LUs
7918 * (except "REPORT LUNS" LU).
7919 *
7920 * Return: zero on success (all required W-LUs are added successfully),
7921 * non-zero error value on failure (if failed to add any of the required W-LU).
7922 */
ufshcd_scsi_add_wlus(struct ufs_hba * hba)7923 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7924 {
7925 int ret = 0;
7926 struct scsi_device *sdev_boot, *sdev_rpmb;
7927
7928 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
7929 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7930 if (IS_ERR(hba->ufs_device_wlun)) {
7931 ret = PTR_ERR(hba->ufs_device_wlun);
7932 hba->ufs_device_wlun = NULL;
7933 goto out;
7934 }
7935 scsi_device_put(hba->ufs_device_wlun);
7936
7937 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7938 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7939 if (IS_ERR(sdev_rpmb)) {
7940 ret = PTR_ERR(sdev_rpmb);
7941 goto remove_ufs_device_wlun;
7942 }
7943 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7944 scsi_device_put(sdev_rpmb);
7945
7946 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7947 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7948 if (IS_ERR(sdev_boot)) {
7949 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7950 } else {
7951 ufshcd_blk_pm_runtime_init(sdev_boot);
7952 scsi_device_put(sdev_boot);
7953 }
7954 goto out;
7955
7956 remove_ufs_device_wlun:
7957 scsi_remove_device(hba->ufs_device_wlun);
7958 out:
7959 return ret;
7960 }
7961
ufshcd_wb_probe(struct ufs_hba * hba,const u8 * desc_buf)7962 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf)
7963 {
7964 struct ufs_dev_info *dev_info = &hba->dev_info;
7965 u8 lun;
7966 u32 d_lu_wb_buf_alloc;
7967 u32 ext_ufs_feature;
7968
7969 if (!ufshcd_is_wb_allowed(hba))
7970 return;
7971
7972 /*
7973 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7974 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7975 * enabled
7976 */
7977 if (!(dev_info->wspecversion >= 0x310 ||
7978 dev_info->wspecversion == 0x220 ||
7979 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7980 goto wb_disabled;
7981
7982 ext_ufs_feature = get_unaligned_be32(desc_buf +
7983 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7984
7985 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7986 goto wb_disabled;
7987
7988 /*
7989 * WB may be supported but not configured while provisioning. The spec
7990 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7991 * buffer configured.
7992 */
7993 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7994
7995 dev_info->b_presrv_uspc_en =
7996 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7997
7998 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
7999 if (!get_unaligned_be32(desc_buf +
8000 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
8001 goto wb_disabled;
8002 } else {
8003 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
8004 d_lu_wb_buf_alloc = 0;
8005 ufshcd_read_unit_desc_param(hba,
8006 lun,
8007 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
8008 (u8 *)&d_lu_wb_buf_alloc,
8009 sizeof(d_lu_wb_buf_alloc));
8010 if (d_lu_wb_buf_alloc) {
8011 dev_info->wb_dedicated_lu = lun;
8012 break;
8013 }
8014 }
8015
8016 if (!d_lu_wb_buf_alloc)
8017 goto wb_disabled;
8018 }
8019
8020 if (!ufshcd_is_wb_buf_lifetime_available(hba))
8021 goto wb_disabled;
8022
8023 return;
8024
8025 wb_disabled:
8026 hba->caps &= ~UFSHCD_CAP_WB_EN;
8027 }
8028
ufshcd_temp_notif_probe(struct ufs_hba * hba,const u8 * desc_buf)8029 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf)
8030 {
8031 struct ufs_dev_info *dev_info = &hba->dev_info;
8032 u32 ext_ufs_feature;
8033 u8 mask = 0;
8034
8035 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
8036 return;
8037
8038 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8039
8040 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
8041 mask |= MASK_EE_TOO_LOW_TEMP;
8042
8043 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
8044 mask |= MASK_EE_TOO_HIGH_TEMP;
8045
8046 if (mask) {
8047 ufshcd_enable_ee(hba, mask);
8048 ufs_hwmon_probe(hba, mask);
8049 }
8050 }
8051
ufshcd_ext_iid_probe(struct ufs_hba * hba,u8 * desc_buf)8052 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf)
8053 {
8054 struct ufs_dev_info *dev_info = &hba->dev_info;
8055 u32 ext_ufs_feature;
8056 u32 ext_iid_en = 0;
8057 int err;
8058
8059 /* Only UFS-4.0 and above may support EXT_IID */
8060 if (dev_info->wspecversion < 0x400)
8061 goto out;
8062
8063 ext_ufs_feature = get_unaligned_be32(desc_buf +
8064 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8065 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP))
8066 goto out;
8067
8068 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8069 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en);
8070 if (err)
8071 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err);
8072
8073 out:
8074 dev_info->b_ext_iid_en = ext_iid_en;
8075 }
8076
ufshcd_fixup_dev_quirks(struct ufs_hba * hba,const struct ufs_dev_quirk * fixups)8077 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
8078 const struct ufs_dev_quirk *fixups)
8079 {
8080 const struct ufs_dev_quirk *f;
8081 struct ufs_dev_info *dev_info = &hba->dev_info;
8082
8083 if (!fixups)
8084 return;
8085
8086 for (f = fixups; f->quirk; f++) {
8087 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
8088 f->wmanufacturerid == UFS_ANY_VENDOR) &&
8089 ((dev_info->model &&
8090 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
8091 !strcmp(f->model, UFS_ANY_MODEL)))
8092 hba->dev_quirks |= f->quirk;
8093 }
8094 }
8095 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
8096
ufs_fixup_device_setup(struct ufs_hba * hba)8097 static void ufs_fixup_device_setup(struct ufs_hba *hba)
8098 {
8099 /* fix by general quirk table */
8100 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
8101
8102 /* allow vendors to fix quirks */
8103 ufshcd_vops_fixup_dev_quirks(hba);
8104 }
8105
ufs_get_device_desc(struct ufs_hba * hba)8106 static int ufs_get_device_desc(struct ufs_hba *hba)
8107 {
8108 int err;
8109 u8 model_index;
8110 u8 *desc_buf;
8111 struct ufs_dev_info *dev_info = &hba->dev_info;
8112
8113 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8114 if (!desc_buf) {
8115 err = -ENOMEM;
8116 goto out;
8117 }
8118
8119 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
8120 QUERY_DESC_MAX_SIZE);
8121 if (err) {
8122 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
8123 __func__, err);
8124 goto out;
8125 }
8126
8127 /*
8128 * getting vendor (manufacturerID) and Bank Index in big endian
8129 * format
8130 */
8131 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
8132 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
8133
8134 /* getting Specification Version in big endian format */
8135 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
8136 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
8137 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH];
8138
8139 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
8140
8141 err = ufshcd_read_string_desc(hba, model_index,
8142 &dev_info->model, SD_ASCII_STD);
8143 if (err < 0) {
8144 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
8145 __func__, err);
8146 goto out;
8147 }
8148
8149 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
8150 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
8151
8152 ufs_fixup_device_setup(hba);
8153
8154 ufshcd_wb_probe(hba, desc_buf);
8155
8156 ufshcd_temp_notif_probe(hba, desc_buf);
8157
8158 if (hba->ext_iid_sup)
8159 ufshcd_ext_iid_probe(hba, desc_buf);
8160
8161 /*
8162 * ufshcd_read_string_desc returns size of the string
8163 * reset the error value
8164 */
8165 err = 0;
8166
8167 out:
8168 kfree(desc_buf);
8169 return err;
8170 }
8171
ufs_put_device_desc(struct ufs_hba * hba)8172 static void ufs_put_device_desc(struct ufs_hba *hba)
8173 {
8174 struct ufs_dev_info *dev_info = &hba->dev_info;
8175
8176 kfree(dev_info->model);
8177 dev_info->model = NULL;
8178 }
8179
8180 /**
8181 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
8182 * @hba: per-adapter instance
8183 *
8184 * PA_TActivate parameter can be tuned manually if UniPro version is less than
8185 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
8186 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
8187 * the hibern8 exit latency.
8188 *
8189 * Return: zero on success, non-zero error value on failure.
8190 */
ufshcd_tune_pa_tactivate(struct ufs_hba * hba)8191 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
8192 {
8193 int ret = 0;
8194 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
8195
8196 ret = ufshcd_dme_peer_get(hba,
8197 UIC_ARG_MIB_SEL(
8198 RX_MIN_ACTIVATETIME_CAPABILITY,
8199 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8200 &peer_rx_min_activatetime);
8201 if (ret)
8202 goto out;
8203
8204 /* make sure proper unit conversion is applied */
8205 tuned_pa_tactivate =
8206 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
8207 / PA_TACTIVATE_TIME_UNIT_US);
8208 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8209 tuned_pa_tactivate);
8210
8211 out:
8212 return ret;
8213 }
8214
8215 /**
8216 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
8217 * @hba: per-adapter instance
8218 *
8219 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
8220 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
8221 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
8222 * This optimal value can help reduce the hibern8 exit latency.
8223 *
8224 * Return: zero on success, non-zero error value on failure.
8225 */
ufshcd_tune_pa_hibern8time(struct ufs_hba * hba)8226 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
8227 {
8228 int ret = 0;
8229 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
8230 u32 max_hibern8_time, tuned_pa_hibern8time;
8231
8232 ret = ufshcd_dme_get(hba,
8233 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
8234 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
8235 &local_tx_hibern8_time_cap);
8236 if (ret)
8237 goto out;
8238
8239 ret = ufshcd_dme_peer_get(hba,
8240 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
8241 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8242 &peer_rx_hibern8_time_cap);
8243 if (ret)
8244 goto out;
8245
8246 max_hibern8_time = max(local_tx_hibern8_time_cap,
8247 peer_rx_hibern8_time_cap);
8248 /* make sure proper unit conversion is applied */
8249 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
8250 / PA_HIBERN8_TIME_UNIT_US);
8251 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
8252 tuned_pa_hibern8time);
8253 out:
8254 return ret;
8255 }
8256
8257 /**
8258 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
8259 * less than device PA_TACTIVATE time.
8260 * @hba: per-adapter instance
8261 *
8262 * Some UFS devices require host PA_TACTIVATE to be lower than device
8263 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
8264 * for such devices.
8265 *
8266 * Return: zero on success, non-zero error value on failure.
8267 */
ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba * hba)8268 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
8269 {
8270 int ret = 0;
8271 u32 granularity, peer_granularity;
8272 u32 pa_tactivate, peer_pa_tactivate;
8273 u32 pa_tactivate_us, peer_pa_tactivate_us;
8274 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
8275
8276 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8277 &granularity);
8278 if (ret)
8279 goto out;
8280
8281 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8282 &peer_granularity);
8283 if (ret)
8284 goto out;
8285
8286 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
8287 (granularity > PA_GRANULARITY_MAX_VAL)) {
8288 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
8289 __func__, granularity);
8290 return -EINVAL;
8291 }
8292
8293 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
8294 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
8295 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
8296 __func__, peer_granularity);
8297 return -EINVAL;
8298 }
8299
8300 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
8301 if (ret)
8302 goto out;
8303
8304 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
8305 &peer_pa_tactivate);
8306 if (ret)
8307 goto out;
8308
8309 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
8310 peer_pa_tactivate_us = peer_pa_tactivate *
8311 gran_to_us_table[peer_granularity - 1];
8312
8313 if (pa_tactivate_us >= peer_pa_tactivate_us) {
8314 u32 new_peer_pa_tactivate;
8315
8316 new_peer_pa_tactivate = pa_tactivate_us /
8317 gran_to_us_table[peer_granularity - 1];
8318 new_peer_pa_tactivate++;
8319 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8320 new_peer_pa_tactivate);
8321 }
8322
8323 out:
8324 return ret;
8325 }
8326
ufshcd_tune_unipro_params(struct ufs_hba * hba)8327 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
8328 {
8329 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
8330 ufshcd_tune_pa_tactivate(hba);
8331 ufshcd_tune_pa_hibern8time(hba);
8332 }
8333
8334 ufshcd_vops_apply_dev_quirks(hba);
8335
8336 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
8337 /* set 1ms timeout for PA_TACTIVATE */
8338 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
8339
8340 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
8341 ufshcd_quirk_tune_host_pa_tactivate(hba);
8342 }
8343
ufshcd_clear_dbg_ufs_stats(struct ufs_hba * hba)8344 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
8345 {
8346 hba->ufs_stats.hibern8_exit_cnt = 0;
8347 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
8348 hba->req_abort_count = 0;
8349 }
8350
ufshcd_device_geo_params_init(struct ufs_hba * hba)8351 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
8352 {
8353 int err;
8354 u8 *desc_buf;
8355
8356 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8357 if (!desc_buf) {
8358 err = -ENOMEM;
8359 goto out;
8360 }
8361
8362 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
8363 desc_buf, QUERY_DESC_MAX_SIZE);
8364 if (err) {
8365 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
8366 __func__, err);
8367 goto out;
8368 }
8369
8370 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
8371 hba->dev_info.max_lu_supported = 32;
8372 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
8373 hba->dev_info.max_lu_supported = 8;
8374
8375 out:
8376 kfree(desc_buf);
8377 return err;
8378 }
8379
8380 struct ufs_ref_clk {
8381 unsigned long freq_hz;
8382 enum ufs_ref_clk_freq val;
8383 };
8384
8385 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = {
8386 {19200000, REF_CLK_FREQ_19_2_MHZ},
8387 {26000000, REF_CLK_FREQ_26_MHZ},
8388 {38400000, REF_CLK_FREQ_38_4_MHZ},
8389 {52000000, REF_CLK_FREQ_52_MHZ},
8390 {0, REF_CLK_FREQ_INVAL},
8391 };
8392
8393 static enum ufs_ref_clk_freq
ufs_get_bref_clk_from_hz(unsigned long freq)8394 ufs_get_bref_clk_from_hz(unsigned long freq)
8395 {
8396 int i;
8397
8398 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8399 if (ufs_ref_clk_freqs[i].freq_hz == freq)
8400 return ufs_ref_clk_freqs[i].val;
8401
8402 return REF_CLK_FREQ_INVAL;
8403 }
8404
ufshcd_parse_dev_ref_clk_freq(struct ufs_hba * hba,struct clk * refclk)8405 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8406 {
8407 unsigned long freq;
8408
8409 freq = clk_get_rate(refclk);
8410
8411 hba->dev_ref_clk_freq =
8412 ufs_get_bref_clk_from_hz(freq);
8413
8414 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8415 dev_err(hba->dev,
8416 "invalid ref_clk setting = %ld\n", freq);
8417 }
8418
ufshcd_set_dev_ref_clk(struct ufs_hba * hba)8419 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8420 {
8421 int err;
8422 u32 ref_clk;
8423 u32 freq = hba->dev_ref_clk_freq;
8424
8425 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8426 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8427
8428 if (err) {
8429 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8430 err);
8431 goto out;
8432 }
8433
8434 if (ref_clk == freq)
8435 goto out; /* nothing to update */
8436
8437 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8438 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8439
8440 if (err) {
8441 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8442 ufs_ref_clk_freqs[freq].freq_hz);
8443 goto out;
8444 }
8445
8446 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8447 ufs_ref_clk_freqs[freq].freq_hz);
8448
8449 out:
8450 return err;
8451 }
8452
ufshcd_device_params_init(struct ufs_hba * hba)8453 static int ufshcd_device_params_init(struct ufs_hba *hba)
8454 {
8455 bool flag;
8456 int ret;
8457
8458 /* Init UFS geometry descriptor related parameters */
8459 ret = ufshcd_device_geo_params_init(hba);
8460 if (ret)
8461 goto out;
8462
8463 /* Check and apply UFS device quirks */
8464 ret = ufs_get_device_desc(hba);
8465 if (ret) {
8466 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8467 __func__, ret);
8468 goto out;
8469 }
8470
8471 ufshcd_get_ref_clk_gating_wait(hba);
8472
8473 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
8474 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
8475 hba->dev_info.f_power_on_wp_en = flag;
8476
8477 /* Probe maximum power mode co-supported by both UFS host and device */
8478 if (ufshcd_get_max_pwr_mode(hba))
8479 dev_err(hba->dev,
8480 "%s: Failed getting max supported power mode\n",
8481 __func__);
8482 out:
8483 return ret;
8484 }
8485
ufshcd_set_timestamp_attr(struct ufs_hba * hba)8486 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)
8487 {
8488 int err;
8489 struct ufs_query_req *request = NULL;
8490 struct ufs_query_res *response = NULL;
8491 struct ufs_dev_info *dev_info = &hba->dev_info;
8492 struct utp_upiu_query_v4_0 *upiu_data;
8493
8494 if (dev_info->wspecversion < 0x400)
8495 return;
8496
8497 ufshcd_hold(hba);
8498
8499 mutex_lock(&hba->dev_cmd.lock);
8500
8501 ufshcd_init_query(hba, &request, &response,
8502 UPIU_QUERY_OPCODE_WRITE_ATTR,
8503 QUERY_ATTR_IDN_TIMESTAMP, 0, 0);
8504
8505 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
8506
8507 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req;
8508
8509 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3);
8510
8511 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
8512
8513 if (err)
8514 dev_err(hba->dev, "%s: failed to set timestamp %d\n",
8515 __func__, err);
8516
8517 mutex_unlock(&hba->dev_cmd.lock);
8518 ufshcd_release(hba);
8519 }
8520
8521 /**
8522 * ufshcd_add_lus - probe and add UFS logical units
8523 * @hba: per-adapter instance
8524 *
8525 * Return: 0 upon success; < 0 upon failure.
8526 */
ufshcd_add_lus(struct ufs_hba * hba)8527 static int ufshcd_add_lus(struct ufs_hba *hba)
8528 {
8529 int ret;
8530
8531 /* Add required well known logical units to scsi mid layer */
8532 ret = ufshcd_scsi_add_wlus(hba);
8533 if (ret)
8534 goto out;
8535
8536 /* Initialize devfreq after UFS device is detected */
8537 if (ufshcd_is_clkscaling_supported(hba)) {
8538 memcpy(&hba->clk_scaling.saved_pwr_info,
8539 &hba->pwr_info,
8540 sizeof(struct ufs_pa_layer_attr));
8541 hba->clk_scaling.is_allowed = true;
8542
8543 ret = ufshcd_devfreq_init(hba);
8544 if (ret)
8545 goto out;
8546
8547 hba->clk_scaling.is_enabled = true;
8548 ufshcd_init_clk_scaling_sysfs(hba);
8549 }
8550
8551 ufs_bsg_probe(hba);
8552 scsi_scan_host(hba->host);
8553
8554 out:
8555 return ret;
8556 }
8557
8558 /* SDB - Single Doorbell */
ufshcd_release_sdb_queue(struct ufs_hba * hba,int nutrs)8559 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs)
8560 {
8561 size_t ucdl_size, utrdl_size;
8562
8563 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs;
8564 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr,
8565 hba->ucdl_dma_addr);
8566
8567 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs;
8568 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr,
8569 hba->utrdl_dma_addr);
8570
8571 devm_kfree(hba->dev, hba->lrb);
8572 }
8573
ufshcd_alloc_mcq(struct ufs_hba * hba)8574 static int ufshcd_alloc_mcq(struct ufs_hba *hba)
8575 {
8576 int ret;
8577 int old_nutrs = hba->nutrs;
8578
8579 ret = ufshcd_mcq_decide_queue_depth(hba);
8580 if (ret < 0)
8581 return ret;
8582
8583 hba->nutrs = ret;
8584 ret = ufshcd_mcq_init(hba);
8585 if (ret)
8586 goto err;
8587
8588 /*
8589 * Previously allocated memory for nutrs may not be enough in MCQ mode.
8590 * Number of supported tags in MCQ mode may be larger than SDB mode.
8591 */
8592 if (hba->nutrs != old_nutrs) {
8593 ufshcd_release_sdb_queue(hba, old_nutrs);
8594 ret = ufshcd_memory_alloc(hba);
8595 if (ret)
8596 goto err;
8597 ufshcd_host_memory_configure(hba);
8598 }
8599
8600 ret = ufshcd_mcq_memory_alloc(hba);
8601 if (ret)
8602 goto err;
8603
8604 return 0;
8605 err:
8606 hba->nutrs = old_nutrs;
8607 return ret;
8608 }
8609
ufshcd_config_mcq(struct ufs_hba * hba)8610 static void ufshcd_config_mcq(struct ufs_hba *hba)
8611 {
8612 int ret;
8613 u32 intrs;
8614
8615 ret = ufshcd_mcq_vops_config_esi(hba);
8616 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
8617
8618 intrs = UFSHCD_ENABLE_MCQ_INTRS;
8619 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
8620 intrs &= ~MCQ_CQ_EVENT_STATUS;
8621 ufshcd_enable_intr(hba, intrs);
8622 ufshcd_mcq_make_queues_operational(hba);
8623 ufshcd_mcq_config_mac(hba, hba->nutrs);
8624
8625 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
8626 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED;
8627
8628 /* Select MCQ mode */
8629 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1,
8630 REG_UFS_MEM_CFG);
8631 hba->mcq_enabled = true;
8632
8633 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n",
8634 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT],
8635 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL],
8636 hba->nutrs);
8637 }
8638
ufshcd_device_init(struct ufs_hba * hba,bool init_dev_params)8639 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
8640 {
8641 int ret;
8642 struct Scsi_Host *host = hba->host;
8643
8644 hba->ufshcd_state = UFSHCD_STATE_RESET;
8645
8646 ret = ufshcd_link_startup(hba);
8647 if (ret)
8648 return ret;
8649
8650 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8651 return ret;
8652
8653 /* Debug counters initialization */
8654 ufshcd_clear_dbg_ufs_stats(hba);
8655
8656 /* UniPro link is active now */
8657 ufshcd_set_link_active(hba);
8658
8659 /* Reconfigure MCQ upon reset */
8660 if (is_mcq_enabled(hba) && !init_dev_params)
8661 ufshcd_config_mcq(hba);
8662
8663 /* Verify device initialization by sending NOP OUT UPIU */
8664 ret = ufshcd_verify_dev_init(hba);
8665 if (ret)
8666 return ret;
8667
8668 /* Initiate UFS initialization, and waiting until completion */
8669 ret = ufshcd_complete_dev_init(hba);
8670 if (ret)
8671 return ret;
8672
8673 /*
8674 * Initialize UFS device parameters used by driver, these
8675 * parameters are associated with UFS descriptors.
8676 */
8677 if (init_dev_params) {
8678 ret = ufshcd_device_params_init(hba);
8679 if (ret)
8680 return ret;
8681 if (is_mcq_supported(hba) && !hba->scsi_host_added) {
8682 ret = ufshcd_alloc_mcq(hba);
8683 if (!ret) {
8684 ufshcd_config_mcq(hba);
8685 } else {
8686 /* Continue with SDB mode */
8687 use_mcq_mode = false;
8688 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n",
8689 ret);
8690 }
8691 ret = scsi_add_host(host, hba->dev);
8692 if (ret) {
8693 dev_err(hba->dev, "scsi_add_host failed\n");
8694 return ret;
8695 }
8696 hba->scsi_host_added = true;
8697 } else if (is_mcq_supported(hba)) {
8698 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */
8699 ufshcd_config_mcq(hba);
8700 }
8701 }
8702
8703 ufshcd_tune_unipro_params(hba);
8704
8705 /* UFS device is also active now */
8706 ufshcd_set_ufs_dev_active(hba);
8707 ufshcd_force_reset_auto_bkops(hba);
8708
8709 ufshcd_set_timestamp_attr(hba);
8710
8711 /* Gear up to HS gear if supported */
8712 if (hba->max_pwr_info.is_valid) {
8713 /*
8714 * Set the right value to bRefClkFreq before attempting to
8715 * switch to HS gears.
8716 */
8717 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8718 ufshcd_set_dev_ref_clk(hba);
8719 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8720 if (ret) {
8721 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8722 __func__, ret);
8723 return ret;
8724 }
8725 }
8726
8727 return 0;
8728 }
8729
8730 /**
8731 * ufshcd_probe_hba - probe hba to detect device and initialize it
8732 * @hba: per-adapter instance
8733 * @init_dev_params: whether or not to call ufshcd_device_params_init().
8734 *
8735 * Execute link-startup and verify device initialization
8736 *
8737 * Return: 0 upon success; < 0 upon failure.
8738 */
ufshcd_probe_hba(struct ufs_hba * hba,bool init_dev_params)8739 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8740 {
8741 ktime_t start = ktime_get();
8742 unsigned long flags;
8743 int ret;
8744
8745 ret = ufshcd_device_init(hba, init_dev_params);
8746 if (ret)
8747 goto out;
8748
8749 if (!hba->pm_op_in_progress &&
8750 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) {
8751 /* Reset the device and controller before doing reinit */
8752 ufshcd_device_reset(hba);
8753 ufs_put_device_desc(hba);
8754 ufshcd_hba_stop(hba);
8755 ufshcd_vops_reinit_notify(hba);
8756 ret = ufshcd_hba_enable(hba);
8757 if (ret) {
8758 dev_err(hba->dev, "Host controller enable failed\n");
8759 ufshcd_print_evt_hist(hba);
8760 ufshcd_print_host_state(hba);
8761 goto out;
8762 }
8763
8764 /* Reinit the device */
8765 ret = ufshcd_device_init(hba, init_dev_params);
8766 if (ret)
8767 goto out;
8768 }
8769
8770 ufshcd_print_pwr_info(hba);
8771
8772 /*
8773 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8774 * and for removable UFS card as well, hence always set the parameter.
8775 * Note: Error handler may issue the device reset hence resetting
8776 * bActiveICCLevel as well so it is always safe to set this here.
8777 */
8778 ufshcd_set_active_icc_lvl(hba);
8779
8780 /* Enable UFS Write Booster if supported */
8781 ufshcd_configure_wb(hba);
8782
8783 if (hba->ee_usr_mask)
8784 ufshcd_write_ee_control(hba);
8785 /* Enable Auto-Hibernate if configured */
8786 ufshcd_auto_hibern8_enable(hba);
8787
8788 out:
8789 spin_lock_irqsave(hba->host->host_lock, flags);
8790 if (ret)
8791 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8792 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8793 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8794 spin_unlock_irqrestore(hba->host->host_lock, flags);
8795
8796 trace_ufshcd_init(dev_name(hba->dev), ret,
8797 ktime_to_us(ktime_sub(ktime_get(), start)),
8798 hba->curr_dev_pwr_mode, hba->uic_link_state);
8799 return ret;
8800 }
8801
8802 /**
8803 * ufshcd_async_scan - asynchronous execution for probing hba
8804 * @data: data pointer to pass to this function
8805 * @cookie: cookie data
8806 */
ufshcd_async_scan(void * data,async_cookie_t cookie)8807 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8808 {
8809 struct ufs_hba *hba = (struct ufs_hba *)data;
8810 int ret;
8811
8812 down(&hba->host_sem);
8813 /* Initialize hba, detect and initialize UFS device */
8814 ret = ufshcd_probe_hba(hba, true);
8815 up(&hba->host_sem);
8816 if (ret)
8817 goto out;
8818
8819 /* Probe and add UFS logical units */
8820 ret = ufshcd_add_lus(hba);
8821
8822 out:
8823 pm_runtime_put_sync(hba->dev);
8824
8825 if (ret)
8826 dev_err(hba->dev, "%s failed: %d\n", __func__, ret);
8827 }
8828
ufshcd_eh_timed_out(struct scsi_cmnd * scmd)8829 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
8830 {
8831 struct ufs_hba *hba = shost_priv(scmd->device->host);
8832
8833 if (!hba->system_suspending) {
8834 /* Activate the error handler in the SCSI core. */
8835 return SCSI_EH_NOT_HANDLED;
8836 }
8837
8838 /*
8839 * If we get here we know that no TMFs are outstanding and also that
8840 * the only pending command is a START STOP UNIT command. Handle the
8841 * timeout of that command directly to prevent a deadlock between
8842 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler().
8843 */
8844 ufshcd_link_recovery(hba);
8845 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n",
8846 __func__, hba->outstanding_tasks);
8847
8848 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE;
8849 }
8850
8851 static const struct attribute_group *ufshcd_driver_groups[] = {
8852 &ufs_sysfs_unit_descriptor_group,
8853 &ufs_sysfs_lun_attributes_group,
8854 NULL,
8855 };
8856
8857 static struct ufs_hba_variant_params ufs_hba_vps = {
8858 .hba_enable_delay_us = 1000,
8859 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
8860 .devfreq_profile.polling_ms = 100,
8861 .devfreq_profile.target = ufshcd_devfreq_target,
8862 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8863 .ondemand_data.upthreshold = 70,
8864 .ondemand_data.downdifferential = 5,
8865 };
8866
8867 static const struct scsi_host_template ufshcd_driver_template = {
8868 .module = THIS_MODULE,
8869 .name = UFSHCD,
8870 .proc_name = UFSHCD,
8871 .map_queues = ufshcd_map_queues,
8872 .queuecommand = ufshcd_queuecommand,
8873 .mq_poll = ufshcd_poll,
8874 .slave_alloc = ufshcd_slave_alloc,
8875 .slave_configure = ufshcd_slave_configure,
8876 .slave_destroy = ufshcd_slave_destroy,
8877 .change_queue_depth = ufshcd_change_queue_depth,
8878 .eh_abort_handler = ufshcd_abort,
8879 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8880 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
8881 .eh_timed_out = ufshcd_eh_timed_out,
8882 .this_id = -1,
8883 .sg_tablesize = SG_ALL,
8884 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8885 .can_queue = UFSHCD_CAN_QUEUE,
8886 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
8887 .max_sectors = SZ_1M / SECTOR_SIZE,
8888 .max_host_blocked = 1,
8889 .track_queue_depth = 1,
8890 .skip_settle_delay = 1,
8891 .sdev_groups = ufshcd_driver_groups,
8892 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
8893 };
8894
ufshcd_config_vreg_load(struct device * dev,struct ufs_vreg * vreg,int ua)8895 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8896 int ua)
8897 {
8898 int ret;
8899
8900 if (!vreg)
8901 return 0;
8902
8903 /*
8904 * "set_load" operation shall be required on those regulators
8905 * which specifically configured current limitation. Otherwise
8906 * zero max_uA may cause unexpected behavior when regulator is
8907 * enabled or set as high power mode.
8908 */
8909 if (!vreg->max_uA)
8910 return 0;
8911
8912 ret = regulator_set_load(vreg->reg, ua);
8913 if (ret < 0) {
8914 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8915 __func__, vreg->name, ua, ret);
8916 }
8917
8918 return ret;
8919 }
8920
ufshcd_config_vreg_lpm(struct ufs_hba * hba,struct ufs_vreg * vreg)8921 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8922 struct ufs_vreg *vreg)
8923 {
8924 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8925 }
8926
ufshcd_config_vreg_hpm(struct ufs_hba * hba,struct ufs_vreg * vreg)8927 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8928 struct ufs_vreg *vreg)
8929 {
8930 if (!vreg)
8931 return 0;
8932
8933 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8934 }
8935
ufshcd_config_vreg(struct device * dev,struct ufs_vreg * vreg,bool on)8936 static int ufshcd_config_vreg(struct device *dev,
8937 struct ufs_vreg *vreg, bool on)
8938 {
8939 if (regulator_count_voltages(vreg->reg) <= 0)
8940 return 0;
8941
8942 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
8943 }
8944
ufshcd_enable_vreg(struct device * dev,struct ufs_vreg * vreg)8945 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8946 {
8947 int ret = 0;
8948
8949 if (!vreg || vreg->enabled)
8950 goto out;
8951
8952 ret = ufshcd_config_vreg(dev, vreg, true);
8953 if (!ret)
8954 ret = regulator_enable(vreg->reg);
8955
8956 if (!ret)
8957 vreg->enabled = true;
8958 else
8959 dev_err(dev, "%s: %s enable failed, err=%d\n",
8960 __func__, vreg->name, ret);
8961 out:
8962 return ret;
8963 }
8964
ufshcd_disable_vreg(struct device * dev,struct ufs_vreg * vreg)8965 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8966 {
8967 int ret = 0;
8968
8969 if (!vreg || !vreg->enabled || vreg->always_on)
8970 goto out;
8971
8972 ret = regulator_disable(vreg->reg);
8973
8974 if (!ret) {
8975 /* ignore errors on applying disable config */
8976 ufshcd_config_vreg(dev, vreg, false);
8977 vreg->enabled = false;
8978 } else {
8979 dev_err(dev, "%s: %s disable failed, err=%d\n",
8980 __func__, vreg->name, ret);
8981 }
8982 out:
8983 return ret;
8984 }
8985
ufshcd_setup_vreg(struct ufs_hba * hba,bool on)8986 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8987 {
8988 int ret = 0;
8989 struct device *dev = hba->dev;
8990 struct ufs_vreg_info *info = &hba->vreg_info;
8991
8992 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8993 if (ret)
8994 goto out;
8995
8996 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8997 if (ret)
8998 goto out;
8999
9000 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
9001
9002 out:
9003 if (ret) {
9004 ufshcd_toggle_vreg(dev, info->vccq2, false);
9005 ufshcd_toggle_vreg(dev, info->vccq, false);
9006 ufshcd_toggle_vreg(dev, info->vcc, false);
9007 }
9008 return ret;
9009 }
9010
ufshcd_setup_hba_vreg(struct ufs_hba * hba,bool on)9011 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
9012 {
9013 struct ufs_vreg_info *info = &hba->vreg_info;
9014
9015 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
9016 }
9017
ufshcd_get_vreg(struct device * dev,struct ufs_vreg * vreg)9018 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
9019 {
9020 int ret = 0;
9021
9022 if (!vreg)
9023 goto out;
9024
9025 vreg->reg = devm_regulator_get(dev, vreg->name);
9026 if (IS_ERR(vreg->reg)) {
9027 ret = PTR_ERR(vreg->reg);
9028 dev_err(dev, "%s: %s get failed, err=%d\n",
9029 __func__, vreg->name, ret);
9030 }
9031 out:
9032 return ret;
9033 }
9034 EXPORT_SYMBOL_GPL(ufshcd_get_vreg);
9035
ufshcd_init_vreg(struct ufs_hba * hba)9036 static int ufshcd_init_vreg(struct ufs_hba *hba)
9037 {
9038 int ret = 0;
9039 struct device *dev = hba->dev;
9040 struct ufs_vreg_info *info = &hba->vreg_info;
9041
9042 ret = ufshcd_get_vreg(dev, info->vcc);
9043 if (ret)
9044 goto out;
9045
9046 ret = ufshcd_get_vreg(dev, info->vccq);
9047 if (!ret)
9048 ret = ufshcd_get_vreg(dev, info->vccq2);
9049 out:
9050 return ret;
9051 }
9052
ufshcd_init_hba_vreg(struct ufs_hba * hba)9053 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
9054 {
9055 struct ufs_vreg_info *info = &hba->vreg_info;
9056
9057 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
9058 }
9059
ufshcd_setup_clocks(struct ufs_hba * hba,bool on)9060 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
9061 {
9062 int ret = 0;
9063 struct ufs_clk_info *clki;
9064 struct list_head *head = &hba->clk_list_head;
9065 unsigned long flags;
9066 ktime_t start = ktime_get();
9067 bool clk_state_changed = false;
9068
9069 if (list_empty(head))
9070 goto out;
9071
9072 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
9073 if (ret)
9074 return ret;
9075
9076 list_for_each_entry(clki, head, list) {
9077 if (!IS_ERR_OR_NULL(clki->clk)) {
9078 /*
9079 * Don't disable clocks which are needed
9080 * to keep the link active.
9081 */
9082 if (ufshcd_is_link_active(hba) &&
9083 clki->keep_link_active)
9084 continue;
9085
9086 clk_state_changed = on ^ clki->enabled;
9087 if (on && !clki->enabled) {
9088 ret = clk_prepare_enable(clki->clk);
9089 if (ret) {
9090 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
9091 __func__, clki->name, ret);
9092 goto out;
9093 }
9094 } else if (!on && clki->enabled) {
9095 clk_disable_unprepare(clki->clk);
9096 }
9097 clki->enabled = on;
9098 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
9099 clki->name, on ? "en" : "dis");
9100 }
9101 }
9102
9103 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
9104 if (ret)
9105 return ret;
9106
9107 out:
9108 if (ret) {
9109 list_for_each_entry(clki, head, list) {
9110 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
9111 clk_disable_unprepare(clki->clk);
9112 }
9113 } else if (!ret && on) {
9114 spin_lock_irqsave(hba->host->host_lock, flags);
9115 hba->clk_gating.state = CLKS_ON;
9116 trace_ufshcd_clk_gating(dev_name(hba->dev),
9117 hba->clk_gating.state);
9118 spin_unlock_irqrestore(hba->host->host_lock, flags);
9119 }
9120
9121 if (clk_state_changed)
9122 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
9123 (on ? "on" : "off"),
9124 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
9125 return ret;
9126 }
9127
ufshcd_parse_ref_clk_property(struct ufs_hba * hba)9128 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba)
9129 {
9130 u32 freq;
9131 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq);
9132
9133 if (ret) {
9134 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret);
9135 return REF_CLK_FREQ_INVAL;
9136 }
9137
9138 return ufs_get_bref_clk_from_hz(freq);
9139 }
9140
ufshcd_init_clocks(struct ufs_hba * hba)9141 static int ufshcd_init_clocks(struct ufs_hba *hba)
9142 {
9143 int ret = 0;
9144 struct ufs_clk_info *clki;
9145 struct device *dev = hba->dev;
9146 struct list_head *head = &hba->clk_list_head;
9147
9148 if (list_empty(head))
9149 goto out;
9150
9151 list_for_each_entry(clki, head, list) {
9152 if (!clki->name)
9153 continue;
9154
9155 clki->clk = devm_clk_get(dev, clki->name);
9156 if (IS_ERR(clki->clk)) {
9157 ret = PTR_ERR(clki->clk);
9158 dev_err(dev, "%s: %s clk get failed, %d\n",
9159 __func__, clki->name, ret);
9160 goto out;
9161 }
9162
9163 /*
9164 * Parse device ref clk freq as per device tree "ref_clk".
9165 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
9166 * in ufshcd_alloc_host().
9167 */
9168 if (!strcmp(clki->name, "ref_clk"))
9169 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
9170
9171 if (clki->max_freq) {
9172 ret = clk_set_rate(clki->clk, clki->max_freq);
9173 if (ret) {
9174 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
9175 __func__, clki->name,
9176 clki->max_freq, ret);
9177 goto out;
9178 }
9179 clki->curr_freq = clki->max_freq;
9180 }
9181 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
9182 clki->name, clk_get_rate(clki->clk));
9183 }
9184 out:
9185 return ret;
9186 }
9187
ufshcd_variant_hba_init(struct ufs_hba * hba)9188 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
9189 {
9190 int err = 0;
9191
9192 if (!hba->vops)
9193 goto out;
9194
9195 err = ufshcd_vops_init(hba);
9196 if (err)
9197 dev_err_probe(hba->dev, err,
9198 "%s: variant %s init failed with err %d\n",
9199 __func__, ufshcd_get_var_name(hba), err);
9200 out:
9201 return err;
9202 }
9203
ufshcd_variant_hba_exit(struct ufs_hba * hba)9204 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
9205 {
9206 if (!hba->vops)
9207 return;
9208
9209 ufshcd_vops_exit(hba);
9210 }
9211
ufshcd_hba_init(struct ufs_hba * hba)9212 static int ufshcd_hba_init(struct ufs_hba *hba)
9213 {
9214 int err;
9215
9216 /*
9217 * Handle host controller power separately from the UFS device power
9218 * rails as it will help controlling the UFS host controller power
9219 * collapse easily which is different than UFS device power collapse.
9220 * Also, enable the host controller power before we go ahead with rest
9221 * of the initialization here.
9222 */
9223 err = ufshcd_init_hba_vreg(hba);
9224 if (err)
9225 goto out;
9226
9227 err = ufshcd_setup_hba_vreg(hba, true);
9228 if (err)
9229 goto out;
9230
9231 err = ufshcd_init_clocks(hba);
9232 if (err)
9233 goto out_disable_hba_vreg;
9234
9235 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
9236 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba);
9237
9238 err = ufshcd_setup_clocks(hba, true);
9239 if (err)
9240 goto out_disable_hba_vreg;
9241
9242 err = ufshcd_init_vreg(hba);
9243 if (err)
9244 goto out_disable_clks;
9245
9246 err = ufshcd_setup_vreg(hba, true);
9247 if (err)
9248 goto out_disable_clks;
9249
9250 err = ufshcd_variant_hba_init(hba);
9251 if (err)
9252 goto out_disable_vreg;
9253
9254 ufs_debugfs_hba_init(hba);
9255
9256 hba->is_powered = true;
9257 goto out;
9258
9259 out_disable_vreg:
9260 ufshcd_setup_vreg(hba, false);
9261 out_disable_clks:
9262 ufshcd_setup_clocks(hba, false);
9263 out_disable_hba_vreg:
9264 ufshcd_setup_hba_vreg(hba, false);
9265 out:
9266 return err;
9267 }
9268
ufshcd_hba_exit(struct ufs_hba * hba)9269 static void ufshcd_hba_exit(struct ufs_hba *hba)
9270 {
9271 if (hba->is_powered) {
9272 ufshcd_exit_clk_scaling(hba);
9273 ufshcd_exit_clk_gating(hba);
9274 if (hba->eh_wq)
9275 destroy_workqueue(hba->eh_wq);
9276 ufs_debugfs_hba_exit(hba);
9277 ufshcd_variant_hba_exit(hba);
9278 ufshcd_setup_vreg(hba, false);
9279 ufshcd_setup_clocks(hba, false);
9280 ufshcd_setup_hba_vreg(hba, false);
9281 hba->is_powered = false;
9282 ufs_put_device_desc(hba);
9283 }
9284 }
9285
ufshcd_execute_start_stop(struct scsi_device * sdev,enum ufs_dev_pwr_mode pwr_mode,struct scsi_sense_hdr * sshdr)9286 static int ufshcd_execute_start_stop(struct scsi_device *sdev,
9287 enum ufs_dev_pwr_mode pwr_mode,
9288 struct scsi_sense_hdr *sshdr)
9289 {
9290 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 };
9291 const struct scsi_exec_args args = {
9292 .sshdr = sshdr,
9293 .req_flags = BLK_MQ_REQ_PM,
9294 .scmd_flags = SCMD_FAIL_IF_RECOVERING,
9295 };
9296
9297 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL,
9298 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0,
9299 &args);
9300 }
9301
9302 /**
9303 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
9304 * power mode
9305 * @hba: per adapter instance
9306 * @pwr_mode: device power mode to set
9307 *
9308 * Return: 0 if requested power mode is set successfully;
9309 * < 0 if failed to set the requested power mode.
9310 */
ufshcd_set_dev_pwr_mode(struct ufs_hba * hba,enum ufs_dev_pwr_mode pwr_mode)9311 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
9312 enum ufs_dev_pwr_mode pwr_mode)
9313 {
9314 struct scsi_sense_hdr sshdr;
9315 struct scsi_device *sdp;
9316 unsigned long flags;
9317 int ret, retries;
9318
9319 spin_lock_irqsave(hba->host->host_lock, flags);
9320 sdp = hba->ufs_device_wlun;
9321 if (sdp && scsi_device_online(sdp))
9322 ret = scsi_device_get(sdp);
9323 else
9324 ret = -ENODEV;
9325 spin_unlock_irqrestore(hba->host->host_lock, flags);
9326
9327 if (ret)
9328 return ret;
9329
9330 /*
9331 * If scsi commands fail, the scsi mid-layer schedules scsi error-
9332 * handling, which would wait for host to be resumed. Since we know
9333 * we are functional while we are here, skip host resume in error
9334 * handling context.
9335 */
9336 hba->host->eh_noresume = 1;
9337
9338 /*
9339 * Current function would be generally called from the power management
9340 * callbacks hence set the RQF_PM flag so that it doesn't resume the
9341 * already suspended childs.
9342 */
9343 for (retries = 3; retries > 0; --retries) {
9344 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr);
9345 /*
9346 * scsi_execute() only returns a negative value if the request
9347 * queue is dying.
9348 */
9349 if (ret <= 0)
9350 break;
9351 }
9352 if (ret) {
9353 sdev_printk(KERN_WARNING, sdp,
9354 "START_STOP failed for power mode: %d, result %x\n",
9355 pwr_mode, ret);
9356 if (ret > 0) {
9357 if (scsi_sense_valid(&sshdr))
9358 scsi_print_sense_hdr(sdp, NULL, &sshdr);
9359 ret = -EIO;
9360 }
9361 } else {
9362 hba->curr_dev_pwr_mode = pwr_mode;
9363 }
9364
9365 scsi_device_put(sdp);
9366 hba->host->eh_noresume = 0;
9367 return ret;
9368 }
9369
ufshcd_link_state_transition(struct ufs_hba * hba,enum uic_link_state req_link_state,bool check_for_bkops)9370 static int ufshcd_link_state_transition(struct ufs_hba *hba,
9371 enum uic_link_state req_link_state,
9372 bool check_for_bkops)
9373 {
9374 int ret = 0;
9375
9376 if (req_link_state == hba->uic_link_state)
9377 return 0;
9378
9379 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
9380 ret = ufshcd_uic_hibern8_enter(hba);
9381 if (!ret) {
9382 ufshcd_set_link_hibern8(hba);
9383 } else {
9384 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9385 __func__, ret);
9386 goto out;
9387 }
9388 }
9389 /*
9390 * If autobkops is enabled, link can't be turned off because
9391 * turning off the link would also turn off the device, except in the
9392 * case of DeepSleep where the device is expected to remain powered.
9393 */
9394 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
9395 (!check_for_bkops || !hba->auto_bkops_enabled)) {
9396 /*
9397 * Let's make sure that link is in low power mode, we are doing
9398 * this currently by putting the link in Hibern8. Otherway to
9399 * put the link in low power mode is to send the DME end point
9400 * to device and then send the DME reset command to local
9401 * unipro. But putting the link in hibern8 is much faster.
9402 *
9403 * Note also that putting the link in Hibern8 is a requirement
9404 * for entering DeepSleep.
9405 */
9406 ret = ufshcd_uic_hibern8_enter(hba);
9407 if (ret) {
9408 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9409 __func__, ret);
9410 goto out;
9411 }
9412 /*
9413 * Change controller state to "reset state" which
9414 * should also put the link in off/reset state
9415 */
9416 ufshcd_hba_stop(hba);
9417 /*
9418 * TODO: Check if we need any delay to make sure that
9419 * controller is reset
9420 */
9421 ufshcd_set_link_off(hba);
9422 }
9423
9424 out:
9425 return ret;
9426 }
9427
ufshcd_vreg_set_lpm(struct ufs_hba * hba)9428 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
9429 {
9430 bool vcc_off = false;
9431
9432 /*
9433 * It seems some UFS devices may keep drawing more than sleep current
9434 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
9435 * To avoid this situation, add 2ms delay before putting these UFS
9436 * rails in LPM mode.
9437 */
9438 if (!ufshcd_is_link_active(hba) &&
9439 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
9440 usleep_range(2000, 2100);
9441
9442 /*
9443 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
9444 * power.
9445 *
9446 * If UFS device and link is in OFF state, all power supplies (VCC,
9447 * VCCQ, VCCQ2) can be turned off if power on write protect is not
9448 * required. If UFS link is inactive (Hibern8 or OFF state) and device
9449 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
9450 *
9451 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
9452 * in low power state which would save some power.
9453 *
9454 * If Write Booster is enabled and the device needs to flush the WB
9455 * buffer OR if bkops status is urgent for WB, keep Vcc on.
9456 */
9457 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9458 !hba->dev_info.is_lu_power_on_wp) {
9459 ufshcd_setup_vreg(hba, false);
9460 vcc_off = true;
9461 } else if (!ufshcd_is_ufs_dev_active(hba)) {
9462 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9463 vcc_off = true;
9464 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
9465 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9466 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
9467 }
9468 }
9469
9470 /*
9471 * Some UFS devices require delay after VCC power rail is turned-off.
9472 */
9473 if (vcc_off && hba->vreg_info.vcc &&
9474 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
9475 usleep_range(5000, 5100);
9476 }
9477
9478 #ifdef CONFIG_PM
ufshcd_vreg_set_hpm(struct ufs_hba * hba)9479 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
9480 {
9481 int ret = 0;
9482
9483 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9484 !hba->dev_info.is_lu_power_on_wp) {
9485 ret = ufshcd_setup_vreg(hba, true);
9486 } else if (!ufshcd_is_ufs_dev_active(hba)) {
9487 if (!ufshcd_is_link_active(hba)) {
9488 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
9489 if (ret)
9490 goto vcc_disable;
9491 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
9492 if (ret)
9493 goto vccq_lpm;
9494 }
9495 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
9496 }
9497 goto out;
9498
9499 vccq_lpm:
9500 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9501 vcc_disable:
9502 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9503 out:
9504 return ret;
9505 }
9506 #endif /* CONFIG_PM */
9507
ufshcd_hba_vreg_set_lpm(struct ufs_hba * hba)9508 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
9509 {
9510 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9511 ufshcd_setup_hba_vreg(hba, false);
9512 }
9513
ufshcd_hba_vreg_set_hpm(struct ufs_hba * hba)9514 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
9515 {
9516 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9517 ufshcd_setup_hba_vreg(hba, true);
9518 }
9519
__ufshcd_wl_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)9520 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9521 {
9522 int ret = 0;
9523 bool check_for_bkops;
9524 enum ufs_pm_level pm_lvl;
9525 enum ufs_dev_pwr_mode req_dev_pwr_mode;
9526 enum uic_link_state req_link_state;
9527
9528 hba->pm_op_in_progress = true;
9529 if (pm_op != UFS_SHUTDOWN_PM) {
9530 pm_lvl = pm_op == UFS_RUNTIME_PM ?
9531 hba->rpm_lvl : hba->spm_lvl;
9532 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
9533 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
9534 } else {
9535 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
9536 req_link_state = UIC_LINK_OFF_STATE;
9537 }
9538
9539 /*
9540 * If we can't transition into any of the low power modes
9541 * just gate the clocks.
9542 */
9543 ufshcd_hold(hba);
9544 hba->clk_gating.is_suspended = true;
9545
9546 if (ufshcd_is_clkscaling_supported(hba))
9547 ufshcd_clk_scaling_suspend(hba, true);
9548
9549 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
9550 req_link_state == UIC_LINK_ACTIVE_STATE) {
9551 goto vops_suspend;
9552 }
9553
9554 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
9555 (req_link_state == hba->uic_link_state))
9556 goto enable_scaling;
9557
9558 /* UFS device & link must be active before we enter in this function */
9559 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
9560 /* Wait err handler finish or trigger err recovery */
9561 if (!ufshcd_eh_in_progress(hba))
9562 ufshcd_force_error_recovery(hba);
9563 ret = -EBUSY;
9564 goto enable_scaling;
9565 }
9566
9567 if (pm_op == UFS_RUNTIME_PM) {
9568 if (ufshcd_can_autobkops_during_suspend(hba)) {
9569 /*
9570 * The device is idle with no requests in the queue,
9571 * allow background operations if bkops status shows
9572 * that performance might be impacted.
9573 */
9574 ret = ufshcd_urgent_bkops(hba);
9575 if (ret) {
9576 /*
9577 * If return err in suspend flow, IO will hang.
9578 * Trigger error handler and break suspend for
9579 * error recovery.
9580 */
9581 ufshcd_force_error_recovery(hba);
9582 ret = -EBUSY;
9583 goto enable_scaling;
9584 }
9585 } else {
9586 /* make sure that auto bkops is disabled */
9587 ufshcd_disable_auto_bkops(hba);
9588 }
9589 /*
9590 * If device needs to do BKOP or WB buffer flush during
9591 * Hibern8, keep device power mode as "active power mode"
9592 * and VCC supply.
9593 */
9594 hba->dev_info.b_rpm_dev_flush_capable =
9595 hba->auto_bkops_enabled ||
9596 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
9597 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
9598 ufshcd_is_auto_hibern8_enabled(hba))) &&
9599 ufshcd_wb_need_flush(hba));
9600 }
9601
9602 flush_work(&hba->eeh_work);
9603
9604 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9605 if (ret)
9606 goto enable_scaling;
9607
9608 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
9609 if (pm_op != UFS_RUNTIME_PM)
9610 /* ensure that bkops is disabled */
9611 ufshcd_disable_auto_bkops(hba);
9612
9613 if (!hba->dev_info.b_rpm_dev_flush_capable) {
9614 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
9615 if (ret && pm_op != UFS_SHUTDOWN_PM) {
9616 /*
9617 * If return err in suspend flow, IO will hang.
9618 * Trigger error handler and break suspend for
9619 * error recovery.
9620 */
9621 ufshcd_force_error_recovery(hba);
9622 ret = -EBUSY;
9623 }
9624 if (ret)
9625 goto enable_scaling;
9626 }
9627 }
9628
9629 /*
9630 * In the case of DeepSleep, the device is expected to remain powered
9631 * with the link off, so do not check for bkops.
9632 */
9633 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
9634 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
9635 if (ret && pm_op != UFS_SHUTDOWN_PM) {
9636 /*
9637 * If return err in suspend flow, IO will hang.
9638 * Trigger error handler and break suspend for
9639 * error recovery.
9640 */
9641 ufshcd_force_error_recovery(hba);
9642 ret = -EBUSY;
9643 }
9644 if (ret)
9645 goto set_dev_active;
9646
9647 vops_suspend:
9648 /*
9649 * Call vendor specific suspend callback. As these callbacks may access
9650 * vendor specific host controller register space call them before the
9651 * host clocks are ON.
9652 */
9653 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9654 if (ret)
9655 goto set_link_active;
9656 goto out;
9657
9658 set_link_active:
9659 /*
9660 * Device hardware reset is required to exit DeepSleep. Also, for
9661 * DeepSleep, the link is off so host reset and restore will be done
9662 * further below.
9663 */
9664 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9665 ufshcd_device_reset(hba);
9666 WARN_ON(!ufshcd_is_link_off(hba));
9667 }
9668 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9669 ufshcd_set_link_active(hba);
9670 else if (ufshcd_is_link_off(hba))
9671 ufshcd_host_reset_and_restore(hba);
9672 set_dev_active:
9673 /* Can also get here needing to exit DeepSleep */
9674 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9675 ufshcd_device_reset(hba);
9676 ufshcd_host_reset_and_restore(hba);
9677 }
9678 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9679 ufshcd_disable_auto_bkops(hba);
9680 enable_scaling:
9681 if (ufshcd_is_clkscaling_supported(hba))
9682 ufshcd_clk_scaling_suspend(hba, false);
9683
9684 hba->dev_info.b_rpm_dev_flush_capable = false;
9685 out:
9686 if (hba->dev_info.b_rpm_dev_flush_capable) {
9687 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9688 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9689 }
9690
9691 if (ret) {
9692 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9693 hba->clk_gating.is_suspended = false;
9694 ufshcd_release(hba);
9695 }
9696 hba->pm_op_in_progress = false;
9697 return ret;
9698 }
9699
9700 #ifdef CONFIG_PM
__ufshcd_wl_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)9701 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9702 {
9703 int ret;
9704 enum uic_link_state old_link_state = hba->uic_link_state;
9705
9706 hba->pm_op_in_progress = true;
9707
9708 /*
9709 * Call vendor specific resume callback. As these callbacks may access
9710 * vendor specific host controller register space call them when the
9711 * host clocks are ON.
9712 */
9713 ret = ufshcd_vops_resume(hba, pm_op);
9714 if (ret)
9715 goto out;
9716
9717 /* For DeepSleep, the only supported option is to have the link off */
9718 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9719
9720 if (ufshcd_is_link_hibern8(hba)) {
9721 ret = ufshcd_uic_hibern8_exit(hba);
9722 if (!ret) {
9723 ufshcd_set_link_active(hba);
9724 } else {
9725 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9726 __func__, ret);
9727 goto vendor_suspend;
9728 }
9729 } else if (ufshcd_is_link_off(hba)) {
9730 /*
9731 * A full initialization of the host and the device is
9732 * required since the link was put to off during suspend.
9733 * Note, in the case of DeepSleep, the device will exit
9734 * DeepSleep due to device reset.
9735 */
9736 ret = ufshcd_reset_and_restore(hba);
9737 /*
9738 * ufshcd_reset_and_restore() should have already
9739 * set the link state as active
9740 */
9741 if (ret || !ufshcd_is_link_active(hba))
9742 goto vendor_suspend;
9743 }
9744
9745 if (!ufshcd_is_ufs_dev_active(hba)) {
9746 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9747 if (ret)
9748 goto set_old_link_state;
9749 ufshcd_set_timestamp_attr(hba);
9750 }
9751
9752 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9753 ufshcd_enable_auto_bkops(hba);
9754 else
9755 /*
9756 * If BKOPs operations are urgently needed at this moment then
9757 * keep auto-bkops enabled or else disable it.
9758 */
9759 ufshcd_urgent_bkops(hba);
9760
9761 if (hba->ee_usr_mask)
9762 ufshcd_write_ee_control(hba);
9763
9764 if (ufshcd_is_clkscaling_supported(hba))
9765 ufshcd_clk_scaling_suspend(hba, false);
9766
9767 if (hba->dev_info.b_rpm_dev_flush_capable) {
9768 hba->dev_info.b_rpm_dev_flush_capable = false;
9769 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9770 }
9771
9772 /* Enable Auto-Hibernate if configured */
9773 ufshcd_auto_hibern8_enable(hba);
9774
9775 goto out;
9776
9777 set_old_link_state:
9778 ufshcd_link_state_transition(hba, old_link_state, 0);
9779 vendor_suspend:
9780 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9781 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9782 out:
9783 if (ret)
9784 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9785 hba->clk_gating.is_suspended = false;
9786 ufshcd_release(hba);
9787 hba->pm_op_in_progress = false;
9788 return ret;
9789 }
9790
ufshcd_wl_runtime_suspend(struct device * dev)9791 static int ufshcd_wl_runtime_suspend(struct device *dev)
9792 {
9793 struct scsi_device *sdev = to_scsi_device(dev);
9794 struct ufs_hba *hba;
9795 int ret;
9796 ktime_t start = ktime_get();
9797
9798 hba = shost_priv(sdev->host);
9799
9800 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9801 if (ret)
9802 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9803
9804 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9805 ktime_to_us(ktime_sub(ktime_get(), start)),
9806 hba->curr_dev_pwr_mode, hba->uic_link_state);
9807
9808 return ret;
9809 }
9810
ufshcd_wl_runtime_resume(struct device * dev)9811 static int ufshcd_wl_runtime_resume(struct device *dev)
9812 {
9813 struct scsi_device *sdev = to_scsi_device(dev);
9814 struct ufs_hba *hba;
9815 int ret = 0;
9816 ktime_t start = ktime_get();
9817
9818 hba = shost_priv(sdev->host);
9819
9820 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9821 if (ret)
9822 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9823
9824 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9825 ktime_to_us(ktime_sub(ktime_get(), start)),
9826 hba->curr_dev_pwr_mode, hba->uic_link_state);
9827
9828 return ret;
9829 }
9830 #endif
9831
9832 #ifdef CONFIG_PM_SLEEP
ufshcd_wl_suspend(struct device * dev)9833 static int ufshcd_wl_suspend(struct device *dev)
9834 {
9835 struct scsi_device *sdev = to_scsi_device(dev);
9836 struct ufs_hba *hba;
9837 int ret = 0;
9838 ktime_t start = ktime_get();
9839
9840 hba = shost_priv(sdev->host);
9841 down(&hba->host_sem);
9842 hba->system_suspending = true;
9843
9844 if (pm_runtime_suspended(dev))
9845 goto out;
9846
9847 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9848 if (ret) {
9849 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9850 up(&hba->host_sem);
9851 }
9852
9853 out:
9854 if (!ret)
9855 hba->is_sys_suspended = true;
9856 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9857 ktime_to_us(ktime_sub(ktime_get(), start)),
9858 hba->curr_dev_pwr_mode, hba->uic_link_state);
9859
9860 return ret;
9861 }
9862
ufshcd_wl_resume(struct device * dev)9863 static int ufshcd_wl_resume(struct device *dev)
9864 {
9865 struct scsi_device *sdev = to_scsi_device(dev);
9866 struct ufs_hba *hba;
9867 int ret = 0;
9868 ktime_t start = ktime_get();
9869
9870 hba = shost_priv(sdev->host);
9871
9872 if (pm_runtime_suspended(dev))
9873 goto out;
9874
9875 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9876 if (ret)
9877 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9878 out:
9879 trace_ufshcd_wl_resume(dev_name(dev), ret,
9880 ktime_to_us(ktime_sub(ktime_get(), start)),
9881 hba->curr_dev_pwr_mode, hba->uic_link_state);
9882 if (!ret)
9883 hba->is_sys_suspended = false;
9884 hba->system_suspending = false;
9885 up(&hba->host_sem);
9886 return ret;
9887 }
9888 #endif
9889
9890 /**
9891 * ufshcd_suspend - helper function for suspend operations
9892 * @hba: per adapter instance
9893 *
9894 * This function will put disable irqs, turn off clocks
9895 * and set vreg and hba-vreg in lpm mode.
9896 *
9897 * Return: 0 upon success; < 0 upon failure.
9898 */
ufshcd_suspend(struct ufs_hba * hba)9899 static int ufshcd_suspend(struct ufs_hba *hba)
9900 {
9901 int ret;
9902
9903 if (!hba->is_powered)
9904 return 0;
9905 /*
9906 * Disable the host irq as host controller as there won't be any
9907 * host controller transaction expected till resume.
9908 */
9909 ufshcd_disable_irq(hba);
9910 ret = ufshcd_setup_clocks(hba, false);
9911 if (ret) {
9912 ufshcd_enable_irq(hba);
9913 return ret;
9914 }
9915 if (ufshcd_is_clkgating_allowed(hba)) {
9916 hba->clk_gating.state = CLKS_OFF;
9917 trace_ufshcd_clk_gating(dev_name(hba->dev),
9918 hba->clk_gating.state);
9919 }
9920
9921 ufshcd_vreg_set_lpm(hba);
9922 /* Put the host controller in low power mode if possible */
9923 ufshcd_hba_vreg_set_lpm(hba);
9924 return ret;
9925 }
9926
9927 #ifdef CONFIG_PM
9928 /**
9929 * ufshcd_resume - helper function for resume operations
9930 * @hba: per adapter instance
9931 *
9932 * This function basically turns on the regulators, clocks and
9933 * irqs of the hba.
9934 *
9935 * Return: 0 for success and non-zero for failure.
9936 */
ufshcd_resume(struct ufs_hba * hba)9937 static int ufshcd_resume(struct ufs_hba *hba)
9938 {
9939 int ret;
9940
9941 if (!hba->is_powered)
9942 return 0;
9943
9944 ufshcd_hba_vreg_set_hpm(hba);
9945 ret = ufshcd_vreg_set_hpm(hba);
9946 if (ret)
9947 goto out;
9948
9949 /* Make sure clocks are enabled before accessing controller */
9950 ret = ufshcd_setup_clocks(hba, true);
9951 if (ret)
9952 goto disable_vreg;
9953
9954 /* enable the host irq as host controller would be active soon */
9955 ufshcd_enable_irq(hba);
9956
9957 goto out;
9958
9959 disable_vreg:
9960 ufshcd_vreg_set_lpm(hba);
9961 out:
9962 if (ret)
9963 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9964 return ret;
9965 }
9966 #endif /* CONFIG_PM */
9967
9968 #ifdef CONFIG_PM_SLEEP
9969 /**
9970 * ufshcd_system_suspend - system suspend callback
9971 * @dev: Device associated with the UFS controller.
9972 *
9973 * Executed before putting the system into a sleep state in which the contents
9974 * of main memory are preserved.
9975 *
9976 * Return: 0 for success and non-zero for failure.
9977 */
ufshcd_system_suspend(struct device * dev)9978 int ufshcd_system_suspend(struct device *dev)
9979 {
9980 struct ufs_hba *hba = dev_get_drvdata(dev);
9981 int ret = 0;
9982 ktime_t start = ktime_get();
9983
9984 if (pm_runtime_suspended(hba->dev))
9985 goto out;
9986
9987 ret = ufshcd_suspend(hba);
9988 out:
9989 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9990 ktime_to_us(ktime_sub(ktime_get(), start)),
9991 hba->curr_dev_pwr_mode, hba->uic_link_state);
9992 return ret;
9993 }
9994 EXPORT_SYMBOL(ufshcd_system_suspend);
9995
9996 /**
9997 * ufshcd_system_resume - system resume callback
9998 * @dev: Device associated with the UFS controller.
9999 *
10000 * Executed after waking the system up from a sleep state in which the contents
10001 * of main memory were preserved.
10002 *
10003 * Return: 0 for success and non-zero for failure.
10004 */
ufshcd_system_resume(struct device * dev)10005 int ufshcd_system_resume(struct device *dev)
10006 {
10007 struct ufs_hba *hba = dev_get_drvdata(dev);
10008 ktime_t start = ktime_get();
10009 int ret = 0;
10010
10011 if (pm_runtime_suspended(hba->dev))
10012 goto out;
10013
10014 ret = ufshcd_resume(hba);
10015
10016 out:
10017 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
10018 ktime_to_us(ktime_sub(ktime_get(), start)),
10019 hba->curr_dev_pwr_mode, hba->uic_link_state);
10020
10021 return ret;
10022 }
10023 EXPORT_SYMBOL(ufshcd_system_resume);
10024 #endif /* CONFIG_PM_SLEEP */
10025
10026 #ifdef CONFIG_PM
10027 /**
10028 * ufshcd_runtime_suspend - runtime suspend callback
10029 * @dev: Device associated with the UFS controller.
10030 *
10031 * Check the description of ufshcd_suspend() function for more details.
10032 *
10033 * Return: 0 for success and non-zero for failure.
10034 */
ufshcd_runtime_suspend(struct device * dev)10035 int ufshcd_runtime_suspend(struct device *dev)
10036 {
10037 struct ufs_hba *hba = dev_get_drvdata(dev);
10038 int ret;
10039 ktime_t start = ktime_get();
10040
10041 ret = ufshcd_suspend(hba);
10042
10043 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
10044 ktime_to_us(ktime_sub(ktime_get(), start)),
10045 hba->curr_dev_pwr_mode, hba->uic_link_state);
10046 return ret;
10047 }
10048 EXPORT_SYMBOL(ufshcd_runtime_suspend);
10049
10050 /**
10051 * ufshcd_runtime_resume - runtime resume routine
10052 * @dev: Device associated with the UFS controller.
10053 *
10054 * This function basically brings controller
10055 * to active state. Following operations are done in this function:
10056 *
10057 * 1. Turn on all the controller related clocks
10058 * 2. Turn ON VCC rail
10059 *
10060 * Return: 0 upon success; < 0 upon failure.
10061 */
ufshcd_runtime_resume(struct device * dev)10062 int ufshcd_runtime_resume(struct device *dev)
10063 {
10064 struct ufs_hba *hba = dev_get_drvdata(dev);
10065 int ret;
10066 ktime_t start = ktime_get();
10067
10068 ret = ufshcd_resume(hba);
10069
10070 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
10071 ktime_to_us(ktime_sub(ktime_get(), start)),
10072 hba->curr_dev_pwr_mode, hba->uic_link_state);
10073 return ret;
10074 }
10075 EXPORT_SYMBOL(ufshcd_runtime_resume);
10076 #endif /* CONFIG_PM */
10077
ufshcd_wl_shutdown(struct device * dev)10078 static void ufshcd_wl_shutdown(struct device *dev)
10079 {
10080 struct scsi_device *sdev = to_scsi_device(dev);
10081 struct ufs_hba *hba = shost_priv(sdev->host);
10082
10083 down(&hba->host_sem);
10084 hba->shutting_down = true;
10085 up(&hba->host_sem);
10086
10087 /* Turn on everything while shutting down */
10088 ufshcd_rpm_get_sync(hba);
10089 scsi_device_quiesce(sdev);
10090 shost_for_each_device(sdev, hba->host) {
10091 if (sdev == hba->ufs_device_wlun)
10092 continue;
10093 scsi_device_quiesce(sdev);
10094 }
10095 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10096
10097 /*
10098 * Next, turn off the UFS controller and the UFS regulators. Disable
10099 * clocks.
10100 */
10101 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
10102 ufshcd_suspend(hba);
10103
10104 hba->is_powered = false;
10105 }
10106
10107 /**
10108 * ufshcd_remove - de-allocate SCSI host and host memory space
10109 * data structure memory
10110 * @hba: per adapter instance
10111 */
ufshcd_remove(struct ufs_hba * hba)10112 void ufshcd_remove(struct ufs_hba *hba)
10113 {
10114 if (hba->ufs_device_wlun)
10115 ufshcd_rpm_get_sync(hba);
10116 ufs_hwmon_remove(hba);
10117 ufs_bsg_remove(hba);
10118 ufs_sysfs_remove_nodes(hba->dev);
10119 blk_mq_destroy_queue(hba->tmf_queue);
10120 blk_put_queue(hba->tmf_queue);
10121 blk_mq_free_tag_set(&hba->tmf_tag_set);
10122 scsi_remove_host(hba->host);
10123 /* disable interrupts */
10124 ufshcd_disable_intr(hba, hba->intr_mask);
10125 ufshcd_hba_stop(hba);
10126 ufshcd_hba_exit(hba);
10127 }
10128 EXPORT_SYMBOL_GPL(ufshcd_remove);
10129
10130 #ifdef CONFIG_PM_SLEEP
ufshcd_system_freeze(struct device * dev)10131 int ufshcd_system_freeze(struct device *dev)
10132 {
10133
10134 return ufshcd_system_suspend(dev);
10135
10136 }
10137 EXPORT_SYMBOL_GPL(ufshcd_system_freeze);
10138
ufshcd_system_restore(struct device * dev)10139 int ufshcd_system_restore(struct device *dev)
10140 {
10141
10142 struct ufs_hba *hba = dev_get_drvdata(dev);
10143 int ret;
10144
10145 ret = ufshcd_system_resume(dev);
10146 if (ret)
10147 return ret;
10148
10149 /* Configure UTRL and UTMRL base address registers */
10150 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
10151 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
10152 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
10153 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
10154 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
10155 REG_UTP_TASK_REQ_LIST_BASE_L);
10156 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
10157 REG_UTP_TASK_REQ_LIST_BASE_H);
10158 /*
10159 * Make sure that UTRL and UTMRL base address registers
10160 * are updated with the latest queue addresses. Only after
10161 * updating these addresses, we can queue the new commands.
10162 */
10163 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H);
10164
10165 return 0;
10166
10167 }
10168 EXPORT_SYMBOL_GPL(ufshcd_system_restore);
10169
ufshcd_system_thaw(struct device * dev)10170 int ufshcd_system_thaw(struct device *dev)
10171 {
10172 return ufshcd_system_resume(dev);
10173 }
10174 EXPORT_SYMBOL_GPL(ufshcd_system_thaw);
10175 #endif /* CONFIG_PM_SLEEP */
10176
10177 /**
10178 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
10179 * @hba: pointer to Host Bus Adapter (HBA)
10180 */
ufshcd_dealloc_host(struct ufs_hba * hba)10181 void ufshcd_dealloc_host(struct ufs_hba *hba)
10182 {
10183 scsi_host_put(hba->host);
10184 }
10185 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
10186
10187 /**
10188 * ufshcd_set_dma_mask - Set dma mask based on the controller
10189 * addressing capability
10190 * @hba: per adapter instance
10191 *
10192 * Return: 0 for success, non-zero for failure.
10193 */
ufshcd_set_dma_mask(struct ufs_hba * hba)10194 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
10195 {
10196 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
10197 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
10198 return 0;
10199 }
10200 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
10201 }
10202
10203 /**
10204 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
10205 * @dev: pointer to device handle
10206 * @hba_handle: driver private handle
10207 *
10208 * Return: 0 on success, non-zero value on failure.
10209 */
ufshcd_alloc_host(struct device * dev,struct ufs_hba ** hba_handle)10210 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
10211 {
10212 struct Scsi_Host *host;
10213 struct ufs_hba *hba;
10214 int err = 0;
10215
10216 if (!dev) {
10217 dev_err(dev,
10218 "Invalid memory reference for dev is NULL\n");
10219 err = -ENODEV;
10220 goto out_error;
10221 }
10222
10223 host = scsi_host_alloc(&ufshcd_driver_template,
10224 sizeof(struct ufs_hba));
10225 if (!host) {
10226 dev_err(dev, "scsi_host_alloc failed\n");
10227 err = -ENOMEM;
10228 goto out_error;
10229 }
10230 host->nr_maps = HCTX_TYPE_POLL + 1;
10231 hba = shost_priv(host);
10232 hba->host = host;
10233 hba->dev = dev;
10234 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
10235 hba->nop_out_timeout = NOP_OUT_TIMEOUT;
10236 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry));
10237 INIT_LIST_HEAD(&hba->clk_list_head);
10238 spin_lock_init(&hba->outstanding_lock);
10239
10240 *hba_handle = hba;
10241
10242 out_error:
10243 return err;
10244 }
10245 EXPORT_SYMBOL(ufshcd_alloc_host);
10246
10247 /* This function exists because blk_mq_alloc_tag_set() requires this. */
ufshcd_queue_tmf(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * qd)10248 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
10249 const struct blk_mq_queue_data *qd)
10250 {
10251 WARN_ON_ONCE(true);
10252 return BLK_STS_NOTSUPP;
10253 }
10254
10255 static const struct blk_mq_ops ufshcd_tmf_ops = {
10256 .queue_rq = ufshcd_queue_tmf,
10257 };
10258
10259 /**
10260 * ufshcd_init - Driver initialization routine
10261 * @hba: per-adapter instance
10262 * @mmio_base: base register address
10263 * @irq: Interrupt line of device
10264 *
10265 * Return: 0 on success, non-zero value on failure.
10266 */
ufshcd_init(struct ufs_hba * hba,void __iomem * mmio_base,unsigned int irq)10267 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
10268 {
10269 int err;
10270 struct Scsi_Host *host = hba->host;
10271 struct device *dev = hba->dev;
10272 char eh_wq_name[sizeof("ufs_eh_wq_00")];
10273
10274 /*
10275 * dev_set_drvdata() must be called before any callbacks are registered
10276 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
10277 * sysfs).
10278 */
10279 dev_set_drvdata(dev, hba);
10280
10281 if (!mmio_base) {
10282 dev_err(hba->dev,
10283 "Invalid memory reference for mmio_base is NULL\n");
10284 err = -ENODEV;
10285 goto out_error;
10286 }
10287
10288 hba->mmio_base = mmio_base;
10289 hba->irq = irq;
10290 hba->vps = &ufs_hba_vps;
10291
10292 err = ufshcd_hba_init(hba);
10293 if (err)
10294 goto out_error;
10295
10296 /* Read capabilities registers */
10297 err = ufshcd_hba_capabilities(hba);
10298 if (err)
10299 goto out_disable;
10300
10301 /* Get UFS version supported by the controller */
10302 hba->ufs_version = ufshcd_get_ufs_version(hba);
10303
10304 /* Get Interrupt bit mask per version */
10305 hba->intr_mask = ufshcd_get_intr_mask(hba);
10306
10307 err = ufshcd_set_dma_mask(hba);
10308 if (err) {
10309 dev_err(hba->dev, "set dma mask failed\n");
10310 goto out_disable;
10311 }
10312
10313 /* Allocate memory for host memory space */
10314 err = ufshcd_memory_alloc(hba);
10315 if (err) {
10316 dev_err(hba->dev, "Memory allocation failed\n");
10317 goto out_disable;
10318 }
10319
10320 /* Configure LRB */
10321 ufshcd_host_memory_configure(hba);
10322
10323 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
10324 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
10325 host->max_id = UFSHCD_MAX_ID;
10326 host->max_lun = UFS_MAX_LUNS;
10327 host->max_channel = UFSHCD_MAX_CHANNEL;
10328 host->unique_id = host->host_no;
10329 host->max_cmd_len = UFS_CDB_SIZE;
10330 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING);
10331
10332 hba->max_pwr_info.is_valid = false;
10333
10334 /* Initialize work queues */
10335 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
10336 hba->host->host_no);
10337 hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
10338 if (!hba->eh_wq) {
10339 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
10340 __func__);
10341 err = -ENOMEM;
10342 goto out_disable;
10343 }
10344 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
10345 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
10346
10347 sema_init(&hba->host_sem, 1);
10348
10349 /* Initialize UIC command mutex */
10350 mutex_init(&hba->uic_cmd_mutex);
10351
10352 /* Initialize mutex for device management commands */
10353 mutex_init(&hba->dev_cmd.lock);
10354
10355 /* Initialize mutex for exception event control */
10356 mutex_init(&hba->ee_ctrl_mutex);
10357
10358 mutex_init(&hba->wb_mutex);
10359 init_rwsem(&hba->clk_scaling_lock);
10360
10361 ufshcd_init_clk_gating(hba);
10362
10363 ufshcd_init_clk_scaling(hba);
10364
10365 /*
10366 * In order to avoid any spurious interrupt immediately after
10367 * registering UFS controller interrupt handler, clear any pending UFS
10368 * interrupt status and disable all the UFS interrupts.
10369 */
10370 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
10371 REG_INTERRUPT_STATUS);
10372 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
10373 /*
10374 * Make sure that UFS interrupts are disabled and any pending interrupt
10375 * status is cleared before registering UFS interrupt handler.
10376 */
10377 ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
10378
10379 /* IRQ registration */
10380 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
10381 if (err) {
10382 dev_err(hba->dev, "request irq failed\n");
10383 goto out_disable;
10384 } else {
10385 hba->is_irq_enabled = true;
10386 }
10387
10388 if (!is_mcq_supported(hba)) {
10389 err = scsi_add_host(host, hba->dev);
10390 if (err) {
10391 dev_err(hba->dev, "scsi_add_host failed\n");
10392 goto out_disable;
10393 }
10394 }
10395
10396 hba->tmf_tag_set = (struct blk_mq_tag_set) {
10397 .nr_hw_queues = 1,
10398 .queue_depth = hba->nutmrs,
10399 .ops = &ufshcd_tmf_ops,
10400 .flags = BLK_MQ_F_NO_SCHED,
10401 };
10402 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
10403 if (err < 0)
10404 goto out_remove_scsi_host;
10405 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
10406 if (IS_ERR(hba->tmf_queue)) {
10407 err = PTR_ERR(hba->tmf_queue);
10408 goto free_tmf_tag_set;
10409 }
10410 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
10411 sizeof(*hba->tmf_rqs), GFP_KERNEL);
10412 if (!hba->tmf_rqs) {
10413 err = -ENOMEM;
10414 goto free_tmf_queue;
10415 }
10416
10417 /* Reset the attached device */
10418 ufshcd_device_reset(hba);
10419
10420 ufshcd_init_crypto(hba);
10421
10422 /* Host controller enable */
10423 err = ufshcd_hba_enable(hba);
10424 if (err) {
10425 dev_err(hba->dev, "Host controller enable failed\n");
10426 ufshcd_print_evt_hist(hba);
10427 ufshcd_print_host_state(hba);
10428 goto free_tmf_queue;
10429 }
10430
10431 /*
10432 * Set the default power management level for runtime and system PM.
10433 * Default power saving mode is to keep UFS link in Hibern8 state
10434 * and UFS device in sleep state.
10435 */
10436 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10437 UFS_SLEEP_PWR_MODE,
10438 UIC_LINK_HIBERN8_STATE);
10439 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10440 UFS_SLEEP_PWR_MODE,
10441 UIC_LINK_HIBERN8_STATE);
10442
10443 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
10444 ufshcd_rpm_dev_flush_recheck_work);
10445
10446 /* Set the default auto-hiberate idle timer value to 150 ms */
10447 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
10448 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
10449 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
10450 }
10451
10452 /* Hold auto suspend until async scan completes */
10453 pm_runtime_get_sync(dev);
10454 atomic_set(&hba->scsi_block_reqs_cnt, 0);
10455 /*
10456 * We are assuming that device wasn't put in sleep/power-down
10457 * state exclusively during the boot stage before kernel.
10458 * This assumption helps avoid doing link startup twice during
10459 * ufshcd_probe_hba().
10460 */
10461 ufshcd_set_ufs_dev_active(hba);
10462
10463 async_schedule(ufshcd_async_scan, hba);
10464 ufs_sysfs_add_nodes(hba->dev);
10465
10466 device_enable_async_suspend(dev);
10467 return 0;
10468
10469 free_tmf_queue:
10470 blk_mq_destroy_queue(hba->tmf_queue);
10471 blk_put_queue(hba->tmf_queue);
10472 free_tmf_tag_set:
10473 blk_mq_free_tag_set(&hba->tmf_tag_set);
10474 out_remove_scsi_host:
10475 scsi_remove_host(hba->host);
10476 out_disable:
10477 hba->is_irq_enabled = false;
10478 ufshcd_hba_exit(hba);
10479 out_error:
10480 return err;
10481 }
10482 EXPORT_SYMBOL_GPL(ufshcd_init);
10483
ufshcd_resume_complete(struct device * dev)10484 void ufshcd_resume_complete(struct device *dev)
10485 {
10486 struct ufs_hba *hba = dev_get_drvdata(dev);
10487
10488 if (hba->complete_put) {
10489 ufshcd_rpm_put(hba);
10490 hba->complete_put = false;
10491 }
10492 }
10493 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
10494
ufshcd_rpm_ok_for_spm(struct ufs_hba * hba)10495 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
10496 {
10497 struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
10498 enum ufs_dev_pwr_mode dev_pwr_mode;
10499 enum uic_link_state link_state;
10500 unsigned long flags;
10501 bool res;
10502
10503 spin_lock_irqsave(&dev->power.lock, flags);
10504 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
10505 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
10506 res = pm_runtime_suspended(dev) &&
10507 hba->curr_dev_pwr_mode == dev_pwr_mode &&
10508 hba->uic_link_state == link_state &&
10509 !hba->dev_info.b_rpm_dev_flush_capable;
10510 spin_unlock_irqrestore(&dev->power.lock, flags);
10511
10512 return res;
10513 }
10514
__ufshcd_suspend_prepare(struct device * dev,bool rpm_ok_for_spm)10515 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
10516 {
10517 struct ufs_hba *hba = dev_get_drvdata(dev);
10518 int ret;
10519
10520 /*
10521 * SCSI assumes that runtime-pm and system-pm for scsi drivers
10522 * are same. And it doesn't wake up the device for system-suspend
10523 * if it's runtime suspended. But ufs doesn't follow that.
10524 * Refer ufshcd_resume_complete()
10525 */
10526 if (hba->ufs_device_wlun) {
10527 /* Prevent runtime suspend */
10528 ufshcd_rpm_get_noresume(hba);
10529 /*
10530 * Check if already runtime suspended in same state as system
10531 * suspend would be.
10532 */
10533 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
10534 /* RPM state is not ok for SPM, so runtime resume */
10535 ret = ufshcd_rpm_resume(hba);
10536 if (ret < 0 && ret != -EACCES) {
10537 ufshcd_rpm_put(hba);
10538 return ret;
10539 }
10540 }
10541 hba->complete_put = true;
10542 }
10543 return 0;
10544 }
10545 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
10546
ufshcd_suspend_prepare(struct device * dev)10547 int ufshcd_suspend_prepare(struct device *dev)
10548 {
10549 return __ufshcd_suspend_prepare(dev, true);
10550 }
10551 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
10552
10553 #ifdef CONFIG_PM_SLEEP
ufshcd_wl_poweroff(struct device * dev)10554 static int ufshcd_wl_poweroff(struct device *dev)
10555 {
10556 struct scsi_device *sdev = to_scsi_device(dev);
10557 struct ufs_hba *hba = shost_priv(sdev->host);
10558
10559 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10560 return 0;
10561 }
10562 #endif
10563
ufshcd_wl_probe(struct device * dev)10564 static int ufshcd_wl_probe(struct device *dev)
10565 {
10566 struct scsi_device *sdev = to_scsi_device(dev);
10567
10568 if (!is_device_wlun(sdev))
10569 return -ENODEV;
10570
10571 blk_pm_runtime_init(sdev->request_queue, dev);
10572 pm_runtime_set_autosuspend_delay(dev, 0);
10573 pm_runtime_allow(dev);
10574
10575 return 0;
10576 }
10577
ufshcd_wl_remove(struct device * dev)10578 static int ufshcd_wl_remove(struct device *dev)
10579 {
10580 pm_runtime_forbid(dev);
10581 return 0;
10582 }
10583
10584 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
10585 #ifdef CONFIG_PM_SLEEP
10586 .suspend = ufshcd_wl_suspend,
10587 .resume = ufshcd_wl_resume,
10588 .freeze = ufshcd_wl_suspend,
10589 .thaw = ufshcd_wl_resume,
10590 .poweroff = ufshcd_wl_poweroff,
10591 .restore = ufshcd_wl_resume,
10592 #endif
10593 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
10594 };
10595
ufshcd_check_header_layout(void)10596 static void ufshcd_check_header_layout(void)
10597 {
10598 /*
10599 * gcc compilers before version 10 cannot do constant-folding for
10600 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and
10601 * before.
10602 */
10603 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000)
10604 return;
10605
10606 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10607 .cci = 3})[0] != 3);
10608
10609 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10610 .ehs_length = 2})[1] != 2);
10611
10612 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10613 .enable_crypto = 1})[2]
10614 != 0x80);
10615
10616 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){
10617 .command_type = 5,
10618 .data_direction = 3,
10619 .interrupt = 1,
10620 })[3]) != ((5 << 4) | (3 << 1) | 1));
10621
10622 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10623 .dunl = cpu_to_le32(0xdeadbeef)})[1] !=
10624 cpu_to_le32(0xdeadbeef));
10625
10626 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10627 .ocs = 4})[8] != 4);
10628
10629 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10630 .cds = 5})[9] != 5);
10631
10632 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10633 .dunu = cpu_to_le32(0xbadcafe)})[3] !=
10634 cpu_to_le32(0xbadcafe));
10635
10636 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10637 .iid = 0xf })[4] != 0xf0);
10638
10639 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10640 .command_set_type = 0xf })[4] != 0xf);
10641 }
10642
10643 /*
10644 * ufs_dev_wlun_template - describes ufs device wlun
10645 * ufs-device wlun - used to send pm commands
10646 * All luns are consumers of ufs-device wlun.
10647 *
10648 * Currently, no sd driver is present for wluns.
10649 * Hence the no specific pm operations are performed.
10650 * With ufs design, SSU should be sent to ufs-device wlun.
10651 * Hence register a scsi driver for ufs wluns only.
10652 */
10653 static struct scsi_driver ufs_dev_wlun_template = {
10654 .gendrv = {
10655 .name = "ufs_device_wlun",
10656 .owner = THIS_MODULE,
10657 .probe = ufshcd_wl_probe,
10658 .remove = ufshcd_wl_remove,
10659 .pm = &ufshcd_wl_pm_ops,
10660 .shutdown = ufshcd_wl_shutdown,
10661 },
10662 };
10663
ufshcd_core_init(void)10664 static int __init ufshcd_core_init(void)
10665 {
10666 int ret;
10667
10668 ufshcd_check_header_layout();
10669
10670 ufs_debugfs_init();
10671
10672 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
10673 if (ret)
10674 ufs_debugfs_exit();
10675 return ret;
10676 }
10677
ufshcd_core_exit(void)10678 static void __exit ufshcd_core_exit(void)
10679 {
10680 ufs_debugfs_exit();
10681 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
10682 }
10683
10684 module_init(ufshcd_core_init);
10685 module_exit(ufshcd_core_exit);
10686
10687 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
10688 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
10689 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
10690 MODULE_SOFTDEP("pre: governor_simpleondemand");
10691 MODULE_LICENSE("GPL");
10692