1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom,rpmhpd.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8450.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <76800000>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32000>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 CPU0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo780"; 54 reg = <0x0 0x0>; 55 enable-method = "psci"; 56 next-level-cache = <&L2_0>; 57 power-domains = <&CPU_PD0>; 58 power-domain-names = "psci"; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 #cooling-cells = <2>; 61 clocks = <&cpufreq_hw 0>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&L3_0>; 67 L3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 CPU1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo780"; 78 reg = <0x0 0x100>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_100>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 #cooling-cells = <2>; 85 clocks = <&cpufreq_hw 0>; 86 L2_100: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 cache-unified; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo780"; 97 reg = <0x0 0x200>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_200>; 100 power-domains = <&CPU_PD2>; 101 power-domain-names = "psci"; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 #cooling-cells = <2>; 104 clocks = <&cpufreq_hw 0>; 105 L2_200: l2-cache { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo780"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 next-level-cache = <&L2_300>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 #cooling-cells = <2>; 123 clocks = <&cpufreq_hw 0>; 124 L2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo780"; 135 reg = <0x0 0x400>; 136 enable-method = "psci"; 137 next-level-cache = <&L2_400>; 138 power-domains = <&CPU_PD4>; 139 power-domain-names = "psci"; 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 #cooling-cells = <2>; 142 clocks = <&cpufreq_hw 1>; 143 L2_400: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU5: cpu@500 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo780"; 154 reg = <0x0 0x500>; 155 enable-method = "psci"; 156 next-level-cache = <&L2_500>; 157 power-domains = <&CPU_PD5>; 158 power-domain-names = "psci"; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 #cooling-cells = <2>; 161 clocks = <&cpufreq_hw 1>; 162 L2_500: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU6: cpu@600 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo780"; 173 reg = <0x0 0x600>; 174 enable-method = "psci"; 175 next-level-cache = <&L2_600>; 176 power-domains = <&CPU_PD6>; 177 power-domain-names = "psci"; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 #cooling-cells = <2>; 180 clocks = <&cpufreq_hw 1>; 181 L2_600: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&L3_0>; 186 }; 187 }; 188 189 CPU7: cpu@700 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo780"; 192 reg = <0x0 0x700>; 193 enable-method = "psci"; 194 next-level-cache = <&L2_700>; 195 power-domains = <&CPU_PD7>; 196 power-domain-names = "psci"; 197 qcom,freq-domain = <&cpufreq_hw 2>; 198 #cooling-cells = <2>; 199 clocks = <&cpufreq_hw 2>; 200 L2_700: l2-cache { 201 compatible = "cache"; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 cpu-map { 209 cluster0 { 210 core0 { 211 cpu = <&CPU0>; 212 }; 213 214 core1 { 215 cpu = <&CPU1>; 216 }; 217 218 core2 { 219 cpu = <&CPU2>; 220 }; 221 222 core3 { 223 cpu = <&CPU3>; 224 }; 225 226 core4 { 227 cpu = <&CPU4>; 228 }; 229 230 core5 { 231 cpu = <&CPU5>; 232 }; 233 234 core6 { 235 cpu = <&CPU6>; 236 }; 237 238 core7 { 239 cpu = <&CPU7>; 240 }; 241 }; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "silver-rail-power-collapse"; 250 arm,psci-suspend-param = <0x40000004>; 251 entry-latency-us = <800>; 252 exit-latency-us = <750>; 253 min-residency-us = <4090>; 254 local-timer-stop; 255 }; 256 257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "gold-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <600>; 262 exit-latency-us = <1550>; 263 min-residency-us = <4791>; 264 local-timer-stop; 265 }; 266 }; 267 268 domain-idle-states { 269 CLUSTER_SLEEP_0: cluster-sleep-0 { 270 compatible = "domain-idle-state"; 271 arm,psci-suspend-param = <0x41000044>; 272 entry-latency-us = <1050>; 273 exit-latency-us = <2500>; 274 min-residency-us = <5309>; 275 }; 276 277 CLUSTER_SLEEP_1: cluster-sleep-1 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x4100c344>; 280 entry-latency-us = <2700>; 281 exit-latency-us = <3500>; 282 min-residency-us = <13959>; 283 }; 284 }; 285 }; 286 287 firmware { 288 scm: scm { 289 compatible = "qcom,scm-sm8450", "qcom,scm"; 290 qcom,dload-mode = <&tcsr 0x13000>; 291 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 292 #reset-cells = <1>; 293 }; 294 }; 295 296 clk_virt: interconnect-0 { 297 compatible = "qcom,sm8450-clk-virt"; 298 #interconnect-cells = <2>; 299 qcom,bcm-voters = <&apps_bcm_voter>; 300 }; 301 302 mc_virt: interconnect-1 { 303 compatible = "qcom,sm8450-mc-virt"; 304 #interconnect-cells = <2>; 305 qcom,bcm-voters = <&apps_bcm_voter>; 306 }; 307 308 memory@a0000000 { 309 device_type = "memory"; 310 /* We expect the bootloader to fill in the size */ 311 reg = <0x0 0xa0000000 0x0 0x0>; 312 }; 313 314 pmu { 315 compatible = "arm,armv8-pmuv3"; 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 323 CPU_PD0: power-domain-cpu0 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD1: power-domain-cpu1 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD2: power-domain-cpu2 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD3: power-domain-cpu3 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD4: power-domain-cpu4 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CPU_PD5: power-domain-cpu5 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0>; 357 }; 358 359 CPU_PD6: power-domain-cpu6 { 360 #power-domain-cells = <0>; 361 power-domains = <&CLUSTER_PD>; 362 domain-idle-states = <&BIG_CPU_SLEEP_0>; 363 }; 364 365 CPU_PD7: power-domain-cpu7 { 366 #power-domain-cells = <0>; 367 power-domains = <&CLUSTER_PD>; 368 domain-idle-states = <&BIG_CPU_SLEEP_0>; 369 }; 370 371 CLUSTER_PD: power-domain-cpu-cluster0 { 372 #power-domain-cells = <0>; 373 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 374 }; 375 }; 376 377 qup_opp_table_100mhz: opp-table-qup { 378 compatible = "operating-points-v2"; 379 380 opp-50000000 { 381 opp-hz = /bits/ 64 <50000000>; 382 required-opps = <&rpmhpd_opp_min_svs>; 383 }; 384 385 opp-75000000 { 386 opp-hz = /bits/ 64 <75000000>; 387 required-opps = <&rpmhpd_opp_low_svs>; 388 }; 389 390 opp-100000000 { 391 opp-hz = /bits/ 64 <100000000>; 392 required-opps = <&rpmhpd_opp_svs>; 393 }; 394 }; 395 396 reserved_memory: reserved-memory { 397 #address-cells = <2>; 398 #size-cells = <2>; 399 ranges; 400 401 hyp_mem: memory@80000000 { 402 reg = <0x0 0x80000000 0x0 0x600000>; 403 no-map; 404 }; 405 406 xbl_dt_log_mem: memory@80600000 { 407 reg = <0x0 0x80600000 0x0 0x40000>; 408 no-map; 409 }; 410 411 xbl_ramdump_mem: memory@80640000 { 412 reg = <0x0 0x80640000 0x0 0x180000>; 413 no-map; 414 }; 415 416 xbl_sc_mem: memory@807c0000 { 417 reg = <0x0 0x807c0000 0x0 0x40000>; 418 no-map; 419 }; 420 421 aop_image_mem: memory@80800000 { 422 reg = <0x0 0x80800000 0x0 0x60000>; 423 no-map; 424 }; 425 426 aop_cmd_db_mem: memory@80860000 { 427 compatible = "qcom,cmd-db"; 428 reg = <0x0 0x80860000 0x0 0x20000>; 429 no-map; 430 }; 431 432 aop_config_mem: memory@80880000 { 433 reg = <0x0 0x80880000 0x0 0x20000>; 434 no-map; 435 }; 436 437 tme_crash_dump_mem: memory@808a0000 { 438 reg = <0x0 0x808a0000 0x0 0x40000>; 439 no-map; 440 }; 441 442 tme_log_mem: memory@808e0000 { 443 reg = <0x0 0x808e0000 0x0 0x4000>; 444 no-map; 445 }; 446 447 uefi_log_mem: memory@808e4000 { 448 reg = <0x0 0x808e4000 0x0 0x10000>; 449 no-map; 450 }; 451 452 /* secdata region can be reused by apps */ 453 smem: memory@80900000 { 454 compatible = "qcom,smem"; 455 reg = <0x0 0x80900000 0x0 0x200000>; 456 hwlocks = <&tcsr_mutex 3>; 457 no-map; 458 }; 459 460 cpucp_fw_mem: memory@80b00000 { 461 reg = <0x0 0x80b00000 0x0 0x100000>; 462 no-map; 463 }; 464 465 cdsp_secure_heap: memory@80c00000 { 466 reg = <0x0 0x80c00000 0x0 0x4600000>; 467 no-map; 468 }; 469 470 video_mem: memory@85700000 { 471 reg = <0x0 0x85700000 0x0 0x700000>; 472 no-map; 473 }; 474 475 adsp_mem: memory@85e00000 { 476 reg = <0x0 0x85e00000 0x0 0x2100000>; 477 no-map; 478 }; 479 480 slpi_mem: memory@88000000 { 481 reg = <0x0 0x88000000 0x0 0x1900000>; 482 no-map; 483 }; 484 485 cdsp_mem: memory@89900000 { 486 reg = <0x0 0x89900000 0x0 0x2000000>; 487 no-map; 488 }; 489 490 ipa_fw_mem: memory@8b900000 { 491 reg = <0x0 0x8b900000 0x0 0x10000>; 492 no-map; 493 }; 494 495 ipa_gsi_mem: memory@8b910000 { 496 reg = <0x0 0x8b910000 0x0 0xa000>; 497 no-map; 498 }; 499 500 gpu_micro_code_mem: memory@8b91a000 { 501 reg = <0x0 0x8b91a000 0x0 0x2000>; 502 no-map; 503 }; 504 505 spss_region_mem: memory@8ba00000 { 506 reg = <0x0 0x8ba00000 0x0 0x180000>; 507 no-map; 508 }; 509 510 /* First part of the "SPU secure shared memory" region */ 511 spu_tz_shared_mem: memory@8bb80000 { 512 reg = <0x0 0x8bb80000 0x0 0x60000>; 513 no-map; 514 }; 515 516 /* Second part of the "SPU secure shared memory" region */ 517 spu_modem_shared_mem: memory@8bbe0000 { 518 reg = <0x0 0x8bbe0000 0x0 0x20000>; 519 no-map; 520 }; 521 522 mpss_mem: memory@8bc00000 { 523 reg = <0x0 0x8bc00000 0x0 0x13200000>; 524 no-map; 525 }; 526 527 cvp_mem: memory@9ee00000 { 528 reg = <0x0 0x9ee00000 0x0 0x700000>; 529 no-map; 530 }; 531 532 camera_mem: memory@9f500000 { 533 reg = <0x0 0x9f500000 0x0 0x800000>; 534 no-map; 535 }; 536 537 rmtfs_mem: memory@9fd00000 { 538 compatible = "qcom,rmtfs-mem"; 539 reg = <0x0 0x9fd00000 0x0 0x280000>; 540 no-map; 541 542 qcom,client-id = <1>; 543 qcom,vmid = <15>; 544 }; 545 546 xbl_sc_mem2: memory@a6e00000 { 547 reg = <0x0 0xa6e00000 0x0 0x40000>; 548 no-map; 549 }; 550 551 global_sync_mem: memory@a6f00000 { 552 reg = <0x0 0xa6f00000 0x0 0x100000>; 553 no-map; 554 }; 555 556 /* uefi region can be reused by APPS */ 557 558 /* Linux kernel image is loaded at 0xa0000000 */ 559 560 oem_vm_mem: memory@bb000000 { 561 reg = <0x0 0xbb000000 0x0 0x5000000>; 562 no-map; 563 }; 564 565 mte_mem: memory@c0000000 { 566 reg = <0x0 0xc0000000 0x0 0x20000000>; 567 no-map; 568 }; 569 570 qheebsp_reserved_mem: memory@e0000000 { 571 reg = <0x0 0xe0000000 0x0 0x600000>; 572 no-map; 573 }; 574 575 cpusys_vm_mem: memory@e0600000 { 576 reg = <0x0 0xe0600000 0x0 0x400000>; 577 no-map; 578 }; 579 580 hyp_reserved_mem: memory@e0a00000 { 581 reg = <0x0 0xe0a00000 0x0 0x100000>; 582 no-map; 583 }; 584 585 trust_ui_vm_mem: memory@e0b00000 { 586 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 587 no-map; 588 }; 589 590 trust_ui_vm_qrtr: memory@e55f3000 { 591 reg = <0x0 0xe55f3000 0x0 0x9000>; 592 no-map; 593 }; 594 595 trust_ui_vm_vblk0_ring: memory@e55fc000 { 596 reg = <0x0 0xe55fc000 0x0 0x4000>; 597 no-map; 598 }; 599 600 trust_ui_vm_swiotlb: memory@e5600000 { 601 reg = <0x0 0xe5600000 0x0 0x100000>; 602 no-map; 603 }; 604 605 tz_stat_mem: memory@e8800000 { 606 reg = <0x0 0xe8800000 0x0 0x100000>; 607 no-map; 608 }; 609 610 tags_mem: memory@e8900000 { 611 reg = <0x0 0xe8900000 0x0 0x1200000>; 612 no-map; 613 }; 614 615 qtee_mem: memory@e9b00000 { 616 reg = <0x0 0xe9b00000 0x0 0x500000>; 617 no-map; 618 }; 619 620 trusted_apps_mem: memory@ea000000 { 621 reg = <0x0 0xea000000 0x0 0x3900000>; 622 no-map; 623 }; 624 625 trusted_apps_ext_mem: memory@ed900000 { 626 reg = <0x0 0xed900000 0x0 0x3b00000>; 627 no-map; 628 }; 629 }; 630 631 smp2p-adsp { 632 compatible = "qcom,smp2p"; 633 qcom,smem = <443>, <429>; 634 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 635 IPCC_MPROC_SIGNAL_SMP2P 636 IRQ_TYPE_EDGE_RISING>; 637 mboxes = <&ipcc IPCC_CLIENT_LPASS 638 IPCC_MPROC_SIGNAL_SMP2P>; 639 640 qcom,local-pid = <0>; 641 qcom,remote-pid = <2>; 642 643 smp2p_adsp_out: master-kernel { 644 qcom,entry-name = "master-kernel"; 645 #qcom,smem-state-cells = <1>; 646 }; 647 648 smp2p_adsp_in: slave-kernel { 649 qcom,entry-name = "slave-kernel"; 650 interrupt-controller; 651 #interrupt-cells = <2>; 652 }; 653 }; 654 655 smp2p-cdsp { 656 compatible = "qcom,smp2p"; 657 qcom,smem = <94>, <432>; 658 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 659 IPCC_MPROC_SIGNAL_SMP2P 660 IRQ_TYPE_EDGE_RISING>; 661 mboxes = <&ipcc IPCC_CLIENT_CDSP 662 IPCC_MPROC_SIGNAL_SMP2P>; 663 664 qcom,local-pid = <0>; 665 qcom,remote-pid = <5>; 666 667 smp2p_cdsp_out: master-kernel { 668 qcom,entry-name = "master-kernel"; 669 #qcom,smem-state-cells = <1>; 670 }; 671 672 smp2p_cdsp_in: slave-kernel { 673 qcom,entry-name = "slave-kernel"; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 }; 677 }; 678 679 smp2p-modem { 680 compatible = "qcom,smp2p"; 681 qcom,smem = <435>, <428>; 682 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 683 IPCC_MPROC_SIGNAL_SMP2P 684 IRQ_TYPE_EDGE_RISING>; 685 mboxes = <&ipcc IPCC_CLIENT_MPSS 686 IPCC_MPROC_SIGNAL_SMP2P>; 687 688 qcom,local-pid = <0>; 689 qcom,remote-pid = <1>; 690 691 smp2p_modem_out: master-kernel { 692 qcom,entry-name = "master-kernel"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 smp2p_modem_in: slave-kernel { 697 qcom,entry-name = "slave-kernel"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 702 ipa_smp2p_out: ipa-ap-to-modem { 703 qcom,entry-name = "ipa"; 704 #qcom,smem-state-cells = <1>; 705 }; 706 707 ipa_smp2p_in: ipa-modem-to-ap { 708 qcom,entry-name = "ipa"; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 }; 713 714 smp2p-slpi { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <481>, <430>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_SLPI 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <3>; 725 726 smp2p_slpi_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_slpi_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 }; 737 738 soc: soc@0 { 739 #address-cells = <2>; 740 #size-cells = <2>; 741 ranges = <0 0 0 0 0x10 0>; 742 dma-ranges = <0 0 0 0 0x10 0>; 743 compatible = "simple-bus"; 744 745 gcc: clock-controller@100000 { 746 compatible = "qcom,gcc-sm8450"; 747 reg = <0x0 0x00100000 0x0 0x1f4200>; 748 #clock-cells = <1>; 749 #reset-cells = <1>; 750 #power-domain-cells = <1>; 751 clocks = <&rpmhcc RPMH_CXO_CLK>, 752 <&sleep_clk>, 753 <&pcie0_lane>, 754 <&pcie1_lane>, 755 <0>, 756 <&ufs_mem_phy_lanes 0>, 757 <&ufs_mem_phy_lanes 1>, 758 <&ufs_mem_phy_lanes 2>, 759 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 760 clock-names = "bi_tcxo", 761 "sleep_clk", 762 "pcie_0_pipe_clk", 763 "pcie_1_pipe_clk", 764 "pcie_1_phy_aux_clk", 765 "ufs_phy_rx_symbol_0_clk", 766 "ufs_phy_rx_symbol_1_clk", 767 "ufs_phy_tx_symbol_0_clk", 768 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 769 }; 770 771 gpi_dma2: dma-controller@800000 { 772 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 773 #dma-cells = <3>; 774 reg = <0 0x00800000 0 0x60000>; 775 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 787 dma-channels = <12>; 788 dma-channel-mask = <0x7e>; 789 iommus = <&apps_smmu 0x496 0x0>; 790 status = "disabled"; 791 }; 792 793 qupv3_id_2: geniqup@8c0000 { 794 compatible = "qcom,geni-se-qup"; 795 reg = <0x0 0x008c0000 0x0 0x2000>; 796 clock-names = "m-ahb", "s-ahb"; 797 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 798 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 799 iommus = <&apps_smmu 0x483 0x0>; 800 #address-cells = <2>; 801 #size-cells = <2>; 802 ranges; 803 status = "disabled"; 804 805 i2c15: i2c@880000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0x0 0x00880000 0x0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_i2c15_data_clk>; 812 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 816 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 817 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 818 interconnect-names = "qup-core", "qup-config", "qup-memory"; 819 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 820 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 821 dma-names = "tx", "rx"; 822 status = "disabled"; 823 }; 824 825 spi15: spi@880000 { 826 compatible = "qcom,geni-spi"; 827 reg = <0x0 0x00880000 0x0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 833 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 834 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 837 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 838 dma-names = "tx", "rx"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 status = "disabled"; 842 }; 843 844 i2c16: i2c@884000 { 845 compatible = "qcom,geni-i2c"; 846 reg = <0x0 0x00884000 0x0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&qup_i2c16_data_clk>; 851 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 855 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 856 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 857 interconnect-names = "qup-core", "qup-config", "qup-memory"; 858 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 859 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 860 dma-names = "tx", "rx"; 861 status = "disabled"; 862 }; 863 864 spi16: spi@884000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0x0 0x00884000 0x0 0x4000>; 867 clock-names = "se"; 868 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 869 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 870 pinctrl-names = "default"; 871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 873 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 874 interconnect-names = "qup-core", "qup-config"; 875 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 876 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 877 dma-names = "tx", "rx"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 status = "disabled"; 881 }; 882 883 i2c17: i2c@888000 { 884 compatible = "qcom,geni-i2c"; 885 reg = <0x0 0x00888000 0x0 0x4000>; 886 clock-names = "se"; 887 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&qup_i2c17_data_clk>; 890 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 894 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 896 interconnect-names = "qup-core", "qup-config", "qup-memory"; 897 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 898 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 899 dma-names = "tx", "rx"; 900 status = "disabled"; 901 }; 902 903 spi17: spi@888000 { 904 compatible = "qcom,geni-spi"; 905 reg = <0x0 0x00888000 0x0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 908 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 912 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 913 interconnect-names = "qup-core", "qup-config"; 914 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 i2c18: i2c@88c000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0x0 0x0088c000 0x0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_i2c18_data_clk>; 929 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 933 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", "qup-memory"; 936 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 937 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 938 dma-names = "tx", "rx"; 939 status = "disabled"; 940 }; 941 942 spi18: spi@88c000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x0088c000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 947 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 952 interconnect-names = "qup-core", "qup-config"; 953 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 954 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 955 dma-names = "tx", "rx"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 i2c19: i2c@890000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0x0 0x00890000 0x0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_i2c19_data_clk>; 968 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 974 interconnect-names = "qup-core", "qup-config", "qup-memory"; 975 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 976 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 status = "disabled"; 979 }; 980 981 spi19: spi@890000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0 0x00890000 0 0x4000>; 984 clock-names = "se"; 985 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 986 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 990 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 993 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 994 dma-names = "tx", "rx"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c20: i2c@894000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0x0 0x00894000 0x0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c20_data_clk>; 1007 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1011 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1012 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1013 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1014 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1015 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1016 dma-names = "tx", "rx"; 1017 status = "disabled"; 1018 }; 1019 1020 uart20: serial@894000 { 1021 compatible = "qcom,geni-uart"; 1022 reg = <0 0x00894000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_uart20_default>; 1027 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1030 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 status = "disabled"; 1035 }; 1036 1037 spi20: spi@894000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00894000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1042 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1046 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1049 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c21: i2c@898000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0x0 0x00898000 0x0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c21_data_clk>; 1063 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1070 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1071 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 status = "disabled"; 1074 }; 1075 1076 spi21: spi@898000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00898000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1081 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1084 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1085 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1086 interconnect-names = "qup-core", "qup-config"; 1087 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1088 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 }; 1095 1096 gpi_dma0: dma-controller@900000 { 1097 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1098 #dma-cells = <3>; 1099 reg = <0 0x00900000 0 0x60000>; 1100 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1112 dma-channels = <12>; 1113 dma-channel-mask = <0x7e>; 1114 iommus = <&apps_smmu 0x5b6 0x0>; 1115 status = "disabled"; 1116 }; 1117 1118 qupv3_id_0: geniqup@9c0000 { 1119 compatible = "qcom,geni-se-qup"; 1120 reg = <0x0 0x009c0000 0x0 0x2000>; 1121 clock-names = "m-ahb", "s-ahb"; 1122 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1123 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1124 iommus = <&apps_smmu 0x5a3 0x0>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1126 interconnect-names = "qup-core"; 1127 #address-cells = <2>; 1128 #size-cells = <2>; 1129 ranges; 1130 status = "disabled"; 1131 1132 i2c0: i2c@980000 { 1133 compatible = "qcom,geni-i2c"; 1134 reg = <0x0 0x00980000 0x0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&qup_i2c0_data_clk>; 1139 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1143 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1144 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1145 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1146 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1147 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1148 dma-names = "tx", "rx"; 1149 status = "disabled"; 1150 }; 1151 1152 spi0: spi@980000 { 1153 compatible = "qcom,geni-spi"; 1154 reg = <0x0 0x00980000 0x0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1157 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1160 power-domains = <&rpmhpd RPMHPD_CX>; 1161 operating-points-v2 = <&qup_opp_table_100mhz>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1164 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1166 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1167 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1168 dma-names = "tx", "rx"; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c1: i2c@984000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0x0 0x00984000 0x0 0x4000>; 1177 clock-names = "se"; 1178 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c1_data_clk>; 1181 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1185 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1186 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1187 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1188 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1189 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1190 dma-names = "tx", "rx"; 1191 status = "disabled"; 1192 }; 1193 1194 spi1: spi@984000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0x0 0x00984000 0x0 0x4000>; 1197 clock-names = "se"; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1199 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1203 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1204 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1205 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1206 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1207 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1208 dma-names = "tx", "rx"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 i2c2: i2c@988000 { 1215 compatible = "qcom,geni-i2c"; 1216 reg = <0x0 0x00988000 0x0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1219 pinctrl-names = "default"; 1220 pinctrl-0 = <&qup_i2c2_data_clk>; 1221 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1227 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1228 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1229 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1230 dma-names = "tx", "rx"; 1231 status = "disabled"; 1232 }; 1233 1234 spi2: spi@988000 { 1235 compatible = "qcom,geni-spi"; 1236 reg = <0x0 0x00988000 0x0 0x4000>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1239 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1244 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1246 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1247 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1248 dma-names = "tx", "rx"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 1255 i2c3: i2c@98c000 { 1256 compatible = "qcom,geni-i2c"; 1257 reg = <0x0 0x0098c000 0x0 0x4000>; 1258 clock-names = "se"; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_i2c3_data_clk>; 1262 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1267 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1268 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1269 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1270 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1271 dma-names = "tx", "rx"; 1272 status = "disabled"; 1273 }; 1274 1275 spi3: spi@98c000 { 1276 compatible = "qcom,geni-spi"; 1277 reg = <0x0 0x0098c000 0x0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1284 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1285 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1286 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1287 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1288 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1289 dma-names = "tx", "rx"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 i2c4: i2c@990000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0x0 0x00990000 0x0 0x4000>; 1298 clock-names = "se"; 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&qup_i2c4_data_clk>; 1302 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1306 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1307 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1309 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 spi4: spi@990000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0x0 0x00990000 0x0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1320 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1323 power-domains = <&rpmhpd RPMHPD_CX>; 1324 operating-points-v2 = <&qup_opp_table_100mhz>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1326 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1327 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1328 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1329 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1330 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c5: i2c@994000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0x0 0x00994000 0x0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_i2c5_data_clk>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1350 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1351 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1352 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1353 dma-names = "tx", "rx"; 1354 status = "disabled"; 1355 }; 1356 1357 spi5: spi@994000 { 1358 compatible = "qcom,geni-spi"; 1359 reg = <0x0 0x00994000 0x0 0x4000>; 1360 clock-names = "se"; 1361 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1362 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1363 pinctrl-names = "default"; 1364 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1366 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1367 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1368 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1369 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1370 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1371 dma-names = "tx", "rx"; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 status = "disabled"; 1375 }; 1376 1377 1378 i2c6: i2c@998000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0x0 0x00998000 0x0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c6_data_clk>; 1385 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1390 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1391 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1393 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1394 dma-names = "tx", "rx"; 1395 status = "disabled"; 1396 }; 1397 1398 spi6: spi@998000 { 1399 compatible = "qcom,geni-spi"; 1400 reg = <0x0 0x00998000 0x0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1403 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1407 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1408 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1409 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1410 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1411 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1412 dma-names = "tx", "rx"; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 uart7: serial@99c000 { 1419 compatible = "qcom,geni-debug-uart"; 1420 reg = <0 0x0099c000 0 0x4000>; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1425 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1427 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1429 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1430 interconnect-names = "qup-core", 1431 "qup-config"; 1432 status = "disabled"; 1433 }; 1434 }; 1435 1436 gpi_dma1: dma-controller@a00000 { 1437 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1438 #dma-cells = <3>; 1439 reg = <0 0x00a00000 0 0x60000>; 1440 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1452 dma-channels = <12>; 1453 dma-channel-mask = <0x7e>; 1454 iommus = <&apps_smmu 0x56 0x0>; 1455 status = "disabled"; 1456 }; 1457 1458 qupv3_id_1: geniqup@ac0000 { 1459 compatible = "qcom,geni-se-qup"; 1460 reg = <0x0 0x00ac0000 0x0 0x6000>; 1461 clock-names = "m-ahb", "s-ahb"; 1462 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1463 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1464 iommus = <&apps_smmu 0x43 0x0>; 1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1466 interconnect-names = "qup-core"; 1467 #address-cells = <2>; 1468 #size-cells = <2>; 1469 ranges; 1470 status = "disabled"; 1471 1472 i2c8: i2c@a80000 { 1473 compatible = "qcom,geni-i2c"; 1474 reg = <0x0 0x00a80000 0x0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_i2c8_data_clk>; 1479 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1483 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1484 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1485 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1486 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1487 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1488 dma-names = "tx", "rx"; 1489 status = "disabled"; 1490 }; 1491 1492 spi8: spi@a80000 { 1493 compatible = "qcom,geni-spi"; 1494 reg = <0x0 0x00a80000 0x0 0x4000>; 1495 clock-names = "se"; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1497 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1501 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1503 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1504 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1505 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1506 dma-names = "tx", "rx"; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 1512 i2c9: i2c@a84000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0x0 0x00a84000 0x0 0x4000>; 1515 clock-names = "se"; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c9_data_clk>; 1519 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi9: spi@a84000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0x0 0x00a84000 0x0 0x4000>; 1535 clock-names = "se"; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1537 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1541 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1543 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1544 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1545 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1546 dma-names = "tx", "rx"; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 i2c10: i2c@a88000 { 1553 compatible = "qcom,geni-i2c"; 1554 reg = <0x0 0x00a88000 0x0 0x4000>; 1555 clock-names = "se"; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_i2c10_data_clk>; 1559 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1564 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1565 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1566 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1567 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1568 dma-names = "tx", "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 spi10: spi@a88000 { 1573 compatible = "qcom,geni-spi"; 1574 reg = <0x0 0x00a88000 0x0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1577 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1578 pinctrl-names = "default"; 1579 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1581 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1583 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1585 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1586 dma-names = "tx", "rx"; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 i2c11: i2c@a8c000 { 1593 compatible = "qcom,geni-i2c"; 1594 reg = <0x0 0x00a8c000 0x0 0x4000>; 1595 clock-names = "se"; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_i2c11_data_clk>; 1599 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1604 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1607 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 spi11: spi@a8c000 { 1613 compatible = "qcom,geni-spi"; 1614 reg = <0x0 0x00a8c000 0x0 0x4000>; 1615 clock-names = "se"; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1623 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1624 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1625 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1626 dma-names = "tx", "rx"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c12: i2c@a90000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0x0 0x00a90000 0x0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c12_data_clk>; 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1643 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1644 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1645 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1646 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1647 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1648 dma-names = "tx", "rx"; 1649 status = "disabled"; 1650 }; 1651 1652 spi12: spi@a90000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0x0 0x00a90000 0x0 0x4000>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1657 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1658 pinctrl-names = "default"; 1659 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1663 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1664 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1666 dma-names = "tx", "rx"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 i2c13: i2c@a94000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a94000 0 0x4000>; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_i2c13_data_clk>; 1679 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1683 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1684 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1685 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1686 dma-names = "tx", "rx"; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 status = "disabled"; 1690 }; 1691 1692 spi13: spi@a94000 { 1693 compatible = "qcom,geni-spi"; 1694 reg = <0x0 0x00a94000 0x0 0x4000>; 1695 clock-names = "se"; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1697 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1703 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1704 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1705 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 i2c14: i2c@a98000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x00a98000 0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_i2c14_data_clk>; 1719 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1721 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1723 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1724 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1725 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1726 dma-names = "tx", "rx"; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 spi14: spi@a98000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0x0 0x00a98000 0x0 0x4000>; 1735 clock-names = "se"; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1737 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1741 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1742 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1743 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1744 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1745 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1746 dma-names = "tx", "rx"; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 }; 1752 1753 rng: rng@10c3000 { 1754 compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee"; 1755 reg = <0 0x010c3000 0 0x1000>; 1756 }; 1757 1758 pcie0: pci@1c00000 { 1759 compatible = "qcom,pcie-sm8450-pcie0"; 1760 reg = <0 0x01c00000 0 0x3000>, 1761 <0 0x60000000 0 0xf1d>, 1762 <0 0x60000f20 0 0xa8>, 1763 <0 0x60001000 0 0x1000>, 1764 <0 0x60100000 0 0x100000>; 1765 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1766 device_type = "pci"; 1767 linux,pci-domain = <0>; 1768 bus-range = <0x00 0xff>; 1769 num-lanes = <1>; 1770 1771 #address-cells = <3>; 1772 #size-cells = <2>; 1773 1774 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1775 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1776 1777 msi-map = <0x0 &gic_its 0x5980 0x1>, 1778 <0x100 &gic_its 0x5981 0x1>; 1779 msi-map-mask = <0xff00>; 1780 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1781 interrupt-names = "msi"; 1782 #interrupt-cells = <1>; 1783 interrupt-map-mask = <0 0 0 0x7>; 1784 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1785 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1786 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1787 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1788 1789 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1790 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1791 <&pcie0_lane>, 1792 <&rpmhcc RPMH_CXO_CLK>, 1793 <&gcc GCC_PCIE_0_AUX_CLK>, 1794 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1795 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1796 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1797 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1798 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1799 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1800 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1801 clock-names = "pipe", 1802 "pipe_mux", 1803 "phy_pipe", 1804 "ref", 1805 "aux", 1806 "cfg", 1807 "bus_master", 1808 "bus_slave", 1809 "slave_q2a", 1810 "ddrss_sf_tbu", 1811 "aggre0", 1812 "aggre1"; 1813 1814 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1815 <0x100 &apps_smmu 0x1c01 0x1>; 1816 1817 resets = <&gcc GCC_PCIE_0_BCR>; 1818 reset-names = "pci"; 1819 1820 power-domains = <&gcc PCIE_0_GDSC>; 1821 1822 phys = <&pcie0_lane>; 1823 phy-names = "pciephy"; 1824 1825 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1826 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1827 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&pcie0_default_state>; 1830 1831 status = "disabled"; 1832 }; 1833 1834 pcie0_phy: phy@1c06000 { 1835 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1836 reg = <0 0x01c06000 0 0x200>; 1837 #address-cells = <2>; 1838 #size-cells = <2>; 1839 ranges; 1840 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1841 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1842 <&gcc GCC_PCIE_0_CLKREF_EN>, 1843 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1844 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1845 1846 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1847 reset-names = "phy"; 1848 1849 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1850 assigned-clock-rates = <100000000>; 1851 1852 status = "disabled"; 1853 1854 pcie0_lane: phy@1c06200 { 1855 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1856 <0 0x01c07000 0 0x200>, /* rx */ 1857 <0 0x01c06200 0 0x200>, /* pcs */ 1858 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1859 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1860 clock-names = "pipe0"; 1861 1862 #clock-cells = <0>; 1863 #phy-cells = <0>; 1864 clock-output-names = "pcie_0_pipe_clk"; 1865 }; 1866 }; 1867 1868 pcie1: pci@1c08000 { 1869 compatible = "qcom,pcie-sm8450-pcie1"; 1870 reg = <0 0x01c08000 0 0x3000>, 1871 <0 0x40000000 0 0xf1d>, 1872 <0 0x40000f20 0 0xa8>, 1873 <0 0x40001000 0 0x1000>, 1874 <0 0x40100000 0 0x100000>; 1875 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1876 device_type = "pci"; 1877 linux,pci-domain = <1>; 1878 bus-range = <0x00 0xff>; 1879 num-lanes = <2>; 1880 1881 #address-cells = <3>; 1882 #size-cells = <2>; 1883 1884 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1885 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1886 1887 msi-map = <0x0 &gic_its 0x5a00 0x1>, 1888 <0x100 &gic_its 0x5a01 0x1>; 1889 msi-map-mask = <0xff00>; 1890 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1891 interrupt-names = "msi"; 1892 #interrupt-cells = <1>; 1893 interrupt-map-mask = <0 0 0 0x7>; 1894 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1895 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1896 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1897 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1898 1899 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1900 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1901 <&pcie1_lane>, 1902 <&rpmhcc RPMH_CXO_CLK>, 1903 <&gcc GCC_PCIE_1_AUX_CLK>, 1904 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1905 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1906 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1907 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1908 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1909 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1910 clock-names = "pipe", 1911 "pipe_mux", 1912 "phy_pipe", 1913 "ref", 1914 "aux", 1915 "cfg", 1916 "bus_master", 1917 "bus_slave", 1918 "slave_q2a", 1919 "ddrss_sf_tbu", 1920 "aggre1"; 1921 1922 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1923 <0x100 &apps_smmu 0x1c81 0x1>; 1924 1925 resets = <&gcc GCC_PCIE_1_BCR>; 1926 reset-names = "pci"; 1927 1928 power-domains = <&gcc PCIE_1_GDSC>; 1929 1930 phys = <&pcie1_lane>; 1931 phy-names = "pciephy"; 1932 1933 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1934 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1935 1936 pinctrl-names = "default"; 1937 pinctrl-0 = <&pcie1_default_state>; 1938 1939 status = "disabled"; 1940 }; 1941 1942 pcie1_phy: phy@1c0f000 { 1943 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1944 reg = <0 0x01c0f000 0 0x200>; 1945 #address-cells = <2>; 1946 #size-cells = <2>; 1947 ranges; 1948 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1949 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1950 <&gcc GCC_PCIE_1_CLKREF_EN>, 1951 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1952 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1953 1954 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1955 reset-names = "phy"; 1956 1957 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1958 assigned-clock-rates = <100000000>; 1959 1960 status = "disabled"; 1961 1962 pcie1_lane: phy@1c0e000 { 1963 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1964 <0 0x01c0e200 0 0x300>, /* rx */ 1965 <0 0x01c0f200 0 0x200>, /* pcs */ 1966 <0 0x01c0e800 0 0x200>, /* tx */ 1967 <0 0x01c0ea00 0 0x300>, /* rx */ 1968 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1969 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1970 clock-names = "pipe0"; 1971 1972 #clock-cells = <0>; 1973 #phy-cells = <0>; 1974 clock-output-names = "pcie_1_pipe_clk"; 1975 }; 1976 }; 1977 1978 config_noc: interconnect@1500000 { 1979 compatible = "qcom,sm8450-config-noc"; 1980 reg = <0 0x01500000 0 0x1c000>; 1981 #interconnect-cells = <2>; 1982 qcom,bcm-voters = <&apps_bcm_voter>; 1983 }; 1984 1985 system_noc: interconnect@1680000 { 1986 compatible = "qcom,sm8450-system-noc"; 1987 reg = <0 0x01680000 0 0x1e200>; 1988 #interconnect-cells = <2>; 1989 qcom,bcm-voters = <&apps_bcm_voter>; 1990 }; 1991 1992 pcie_noc: interconnect@16c0000 { 1993 compatible = "qcom,sm8450-pcie-anoc"; 1994 reg = <0 0x016c0000 0 0xe280>; 1995 #interconnect-cells = <2>; 1996 qcom,bcm-voters = <&apps_bcm_voter>; 1997 }; 1998 1999 aggre1_noc: interconnect@16e0000 { 2000 compatible = "qcom,sm8450-aggre1-noc"; 2001 reg = <0 0x016e0000 0 0x1c080>; 2002 #interconnect-cells = <2>; 2003 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2004 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2005 qcom,bcm-voters = <&apps_bcm_voter>; 2006 }; 2007 2008 aggre2_noc: interconnect@1700000 { 2009 compatible = "qcom,sm8450-aggre2-noc"; 2010 reg = <0 0x01700000 0 0x31080>; 2011 #interconnect-cells = <2>; 2012 qcom,bcm-voters = <&apps_bcm_voter>; 2013 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2014 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2015 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2016 <&rpmhcc RPMH_IPA_CLK>; 2017 }; 2018 2019 mmss_noc: interconnect@1740000 { 2020 compatible = "qcom,sm8450-mmss-noc"; 2021 reg = <0 0x01740000 0 0x1f080>; 2022 #interconnect-cells = <2>; 2023 qcom,bcm-voters = <&apps_bcm_voter>; 2024 }; 2025 2026 tcsr_mutex: hwlock@1f40000 { 2027 compatible = "qcom,tcsr-mutex"; 2028 reg = <0x0 0x01f40000 0x0 0x40000>; 2029 #hwlock-cells = <1>; 2030 }; 2031 2032 tcsr: syscon@1fc0000 { 2033 compatible = "qcom,sm8450-tcsr", "syscon"; 2034 reg = <0x0 0x1fc0000 0x0 0x30000>; 2035 }; 2036 2037 usb_1_hsphy: phy@88e3000 { 2038 compatible = "qcom,sm8450-usb-hs-phy", 2039 "qcom,usb-snps-hs-7nm-phy"; 2040 reg = <0 0x088e3000 0 0x400>; 2041 status = "disabled"; 2042 #phy-cells = <0>; 2043 2044 clocks = <&rpmhcc RPMH_CXO_CLK>; 2045 clock-names = "ref"; 2046 2047 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2048 }; 2049 2050 usb_1_qmpphy: phy@88e8000 { 2051 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2052 reg = <0 0x088e8000 0 0x3000>; 2053 2054 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2055 <&rpmhcc RPMH_CXO_CLK>, 2056 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2057 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2058 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2059 2060 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2061 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2062 reset-names = "phy", "common"; 2063 2064 #clock-cells = <1>; 2065 #phy-cells = <1>; 2066 2067 status = "disabled"; 2068 2069 ports { 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 2073 port@0 { 2074 reg = <0>; 2075 2076 usb_1_qmpphy_out: endpoint { 2077 }; 2078 }; 2079 2080 port@1 { 2081 reg = <1>; 2082 2083 usb_1_qmpphy_usb_ss_in: endpoint { 2084 }; 2085 }; 2086 2087 port@2 { 2088 reg = <2>; 2089 2090 usb_1_qmpphy_dp_in: endpoint { 2091 }; 2092 }; 2093 }; 2094 }; 2095 2096 remoteproc_slpi: remoteproc@2400000 { 2097 compatible = "qcom,sm8450-slpi-pas"; 2098 reg = <0 0x02400000 0 0x4000>; 2099 2100 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2101 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2102 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2103 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2104 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2105 interrupt-names = "wdog", "fatal", "ready", 2106 "handover", "stop-ack"; 2107 2108 clocks = <&rpmhcc RPMH_CXO_CLK>; 2109 clock-names = "xo"; 2110 2111 power-domains = <&rpmhpd RPMHPD_LCX>, 2112 <&rpmhpd RPMHPD_LMX>; 2113 power-domain-names = "lcx", "lmx"; 2114 2115 memory-region = <&slpi_mem>; 2116 2117 qcom,qmp = <&aoss_qmp>; 2118 2119 qcom,smem-states = <&smp2p_slpi_out 0>; 2120 qcom,smem-state-names = "stop"; 2121 2122 status = "disabled"; 2123 2124 glink-edge { 2125 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2126 IPCC_MPROC_SIGNAL_GLINK_QMP 2127 IRQ_TYPE_EDGE_RISING>; 2128 mboxes = <&ipcc IPCC_CLIENT_SLPI 2129 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2130 2131 label = "slpi"; 2132 qcom,remote-pid = <3>; 2133 2134 fastrpc { 2135 compatible = "qcom,fastrpc"; 2136 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2137 label = "sdsp"; 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 2141 compute-cb@1 { 2142 compatible = "qcom,fastrpc-compute-cb"; 2143 reg = <1>; 2144 iommus = <&apps_smmu 0x0541 0x0>; 2145 }; 2146 2147 compute-cb@2 { 2148 compatible = "qcom,fastrpc-compute-cb"; 2149 reg = <2>; 2150 iommus = <&apps_smmu 0x0542 0x0>; 2151 }; 2152 2153 compute-cb@3 { 2154 compatible = "qcom,fastrpc-compute-cb"; 2155 reg = <3>; 2156 iommus = <&apps_smmu 0x0543 0x0>; 2157 /* note: shared-cb = <4> in downstream */ 2158 }; 2159 }; 2160 }; 2161 }; 2162 2163 wsa2macro: codec@31e0000 { 2164 compatible = "qcom,sm8450-lpass-wsa-macro"; 2165 reg = <0 0x031e0000 0 0x1000>; 2166 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2167 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2168 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2169 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2170 <&vamacro>; 2171 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2172 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2173 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2174 assigned-clock-rates = <19200000>, <19200000>; 2175 2176 #clock-cells = <0>; 2177 clock-output-names = "wsa2-mclk"; 2178 pinctrl-names = "default"; 2179 pinctrl-0 = <&wsa2_swr_active>; 2180 #sound-dai-cells = <1>; 2181 }; 2182 2183 swr4: soundwire@31f0000 { 2184 compatible = "qcom,soundwire-v1.7.0"; 2185 reg = <0 0x031f0000 0 0x2000>; 2186 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2187 clocks = <&wsa2macro>; 2188 clock-names = "iface"; 2189 label = "WSA2"; 2190 2191 qcom,din-ports = <2>; 2192 qcom,dout-ports = <6>; 2193 2194 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2195 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2196 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2197 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2198 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2199 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2200 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2201 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2202 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2203 2204 #address-cells = <2>; 2205 #size-cells = <0>; 2206 #sound-dai-cells = <1>; 2207 status = "disabled"; 2208 }; 2209 2210 rxmacro: codec@3200000 { 2211 compatible = "qcom,sm8450-lpass-rx-macro"; 2212 reg = <0 0x03200000 0 0x1000>; 2213 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2214 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2215 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2216 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2217 <&vamacro>; 2218 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2219 2220 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2221 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2222 assigned-clock-rates = <19200000>, <19200000>; 2223 2224 #clock-cells = <0>; 2225 clock-output-names = "mclk"; 2226 pinctrl-names = "default"; 2227 pinctrl-0 = <&rx_swr_active>; 2228 #sound-dai-cells = <1>; 2229 }; 2230 2231 swr1: soundwire@3210000 { 2232 compatible = "qcom,soundwire-v1.7.0"; 2233 reg = <0 0x03210000 0 0x2000>; 2234 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2235 clocks = <&rxmacro>; 2236 clock-names = "iface"; 2237 label = "RX"; 2238 qcom,din-ports = <0>; 2239 qcom,dout-ports = <5>; 2240 2241 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2242 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2243 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2244 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2245 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2246 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2247 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2248 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2249 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2250 2251 #address-cells = <2>; 2252 #size-cells = <0>; 2253 #sound-dai-cells = <1>; 2254 status = "disabled"; 2255 }; 2256 2257 txmacro: codec@3220000 { 2258 compatible = "qcom,sm8450-lpass-tx-macro"; 2259 reg = <0 0x03220000 0 0x1000>; 2260 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2261 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2262 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2263 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2264 <&vamacro>; 2265 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2266 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2267 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2268 assigned-clock-rates = <19200000>, <19200000>; 2269 2270 #clock-cells = <0>; 2271 clock-output-names = "mclk"; 2272 pinctrl-names = "default"; 2273 pinctrl-0 = <&tx_swr_active>; 2274 #sound-dai-cells = <1>; 2275 }; 2276 2277 wsamacro: codec@3240000 { 2278 compatible = "qcom,sm8450-lpass-wsa-macro"; 2279 reg = <0 0x03240000 0 0x1000>; 2280 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2281 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2282 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2283 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2284 <&vamacro>; 2285 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2286 2287 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2288 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2289 assigned-clock-rates = <19200000>, <19200000>; 2290 2291 #clock-cells = <0>; 2292 clock-output-names = "mclk"; 2293 pinctrl-names = "default"; 2294 pinctrl-0 = <&wsa_swr_active>; 2295 #sound-dai-cells = <1>; 2296 }; 2297 2298 swr0: soundwire@3250000 { 2299 compatible = "qcom,soundwire-v1.7.0"; 2300 reg = <0 0x03250000 0 0x2000>; 2301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&wsamacro>; 2303 clock-names = "iface"; 2304 label = "WSA"; 2305 2306 qcom,din-ports = <2>; 2307 qcom,dout-ports = <6>; 2308 2309 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2310 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2311 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2312 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2313 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2314 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2315 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2316 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2317 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2318 2319 #address-cells = <2>; 2320 #size-cells = <0>; 2321 #sound-dai-cells = <1>; 2322 status = "disabled"; 2323 }; 2324 2325 swr2: soundwire@33b0000 { 2326 compatible = "qcom,soundwire-v1.7.0"; 2327 reg = <0 0x033b0000 0 0x2000>; 2328 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2329 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2330 interrupt-names = "core", "wakeup"; 2331 2332 clocks = <&txmacro>; 2333 clock-names = "iface"; 2334 label = "TX"; 2335 2336 qcom,din-ports = <4>; 2337 qcom,dout-ports = <0>; 2338 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2339 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2340 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2341 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2342 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2343 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2344 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2345 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2346 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2347 2348 #address-cells = <2>; 2349 #size-cells = <0>; 2350 #sound-dai-cells = <1>; 2351 status = "disabled"; 2352 }; 2353 2354 vamacro: codec@33f0000 { 2355 compatible = "qcom,sm8450-lpass-va-macro"; 2356 reg = <0 0x033f0000 0 0x1000>; 2357 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2358 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2359 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2360 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2361 clock-names = "mclk", "macro", "dcodec", "npl"; 2362 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2363 assigned-clock-rates = <19200000>; 2364 2365 #clock-cells = <0>; 2366 clock-output-names = "fsgen"; 2367 #sound-dai-cells = <1>; 2368 status = "disabled"; 2369 }; 2370 2371 remoteproc_adsp: remoteproc@30000000 { 2372 compatible = "qcom,sm8450-adsp-pas"; 2373 reg = <0 0x30000000 0 0x100>; 2374 2375 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2376 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2377 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2378 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2379 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2380 interrupt-names = "wdog", "fatal", "ready", 2381 "handover", "stop-ack"; 2382 2383 clocks = <&rpmhcc RPMH_CXO_CLK>; 2384 clock-names = "xo"; 2385 2386 power-domains = <&rpmhpd RPMHPD_LCX>, 2387 <&rpmhpd RPMHPD_LMX>; 2388 power-domain-names = "lcx", "lmx"; 2389 2390 memory-region = <&adsp_mem>; 2391 2392 qcom,qmp = <&aoss_qmp>; 2393 2394 qcom,smem-states = <&smp2p_adsp_out 0>; 2395 qcom,smem-state-names = "stop"; 2396 2397 status = "disabled"; 2398 2399 remoteproc_adsp_glink: glink-edge { 2400 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2401 IPCC_MPROC_SIGNAL_GLINK_QMP 2402 IRQ_TYPE_EDGE_RISING>; 2403 mboxes = <&ipcc IPCC_CLIENT_LPASS 2404 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2405 2406 label = "lpass"; 2407 qcom,remote-pid = <2>; 2408 2409 gpr { 2410 compatible = "qcom,gpr"; 2411 qcom,glink-channels = "adsp_apps"; 2412 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2413 qcom,intents = <512 20>; 2414 #address-cells = <1>; 2415 #size-cells = <0>; 2416 2417 q6apm: service@1 { 2418 compatible = "qcom,q6apm"; 2419 reg = <GPR_APM_MODULE_IID>; 2420 #sound-dai-cells = <0>; 2421 qcom,protection-domain = "avs/audio", 2422 "msm/adsp/audio_pd"; 2423 2424 q6apmdai: dais { 2425 compatible = "qcom,q6apm-dais"; 2426 iommus = <&apps_smmu 0x1801 0x0>; 2427 }; 2428 2429 q6apmbedai: bedais { 2430 compatible = "qcom,q6apm-lpass-dais"; 2431 #sound-dai-cells = <1>; 2432 }; 2433 }; 2434 2435 q6prm: service@2 { 2436 compatible = "qcom,q6prm"; 2437 reg = <GPR_PRM_MODULE_IID>; 2438 qcom,protection-domain = "avs/audio", 2439 "msm/adsp/audio_pd"; 2440 2441 q6prmcc: clock-controller { 2442 compatible = "qcom,q6prm-lpass-clocks"; 2443 #clock-cells = <2>; 2444 }; 2445 }; 2446 }; 2447 2448 fastrpc { 2449 compatible = "qcom,fastrpc"; 2450 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2451 label = "adsp"; 2452 #address-cells = <1>; 2453 #size-cells = <0>; 2454 2455 compute-cb@3 { 2456 compatible = "qcom,fastrpc-compute-cb"; 2457 reg = <3>; 2458 iommus = <&apps_smmu 0x1803 0x0>; 2459 }; 2460 2461 compute-cb@4 { 2462 compatible = "qcom,fastrpc-compute-cb"; 2463 reg = <4>; 2464 iommus = <&apps_smmu 0x1804 0x0>; 2465 }; 2466 2467 compute-cb@5 { 2468 compatible = "qcom,fastrpc-compute-cb"; 2469 reg = <5>; 2470 iommus = <&apps_smmu 0x1805 0x0>; 2471 }; 2472 }; 2473 }; 2474 }; 2475 2476 remoteproc_cdsp: remoteproc@32300000 { 2477 compatible = "qcom,sm8450-cdsp-pas"; 2478 reg = <0 0x32300000 0 0x1400000>; 2479 2480 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2481 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2482 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2483 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2484 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2485 interrupt-names = "wdog", "fatal", "ready", 2486 "handover", "stop-ack"; 2487 2488 clocks = <&rpmhcc RPMH_CXO_CLK>; 2489 clock-names = "xo"; 2490 2491 power-domains = <&rpmhpd RPMHPD_CX>, 2492 <&rpmhpd RPMHPD_MXC>; 2493 power-domain-names = "cx", "mxc"; 2494 2495 memory-region = <&cdsp_mem>; 2496 2497 qcom,qmp = <&aoss_qmp>; 2498 2499 qcom,smem-states = <&smp2p_cdsp_out 0>; 2500 qcom,smem-state-names = "stop"; 2501 2502 status = "disabled"; 2503 2504 glink-edge { 2505 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2506 IPCC_MPROC_SIGNAL_GLINK_QMP 2507 IRQ_TYPE_EDGE_RISING>; 2508 mboxes = <&ipcc IPCC_CLIENT_CDSP 2509 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2510 2511 label = "cdsp"; 2512 qcom,remote-pid = <5>; 2513 2514 fastrpc { 2515 compatible = "qcom,fastrpc"; 2516 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2517 label = "cdsp"; 2518 #address-cells = <1>; 2519 #size-cells = <0>; 2520 2521 compute-cb@1 { 2522 compatible = "qcom,fastrpc-compute-cb"; 2523 reg = <1>; 2524 iommus = <&apps_smmu 0x2161 0x0400>, 2525 <&apps_smmu 0x1021 0x1420>; 2526 }; 2527 2528 compute-cb@2 { 2529 compatible = "qcom,fastrpc-compute-cb"; 2530 reg = <2>; 2531 iommus = <&apps_smmu 0x2162 0x0400>, 2532 <&apps_smmu 0x1022 0x1420>; 2533 }; 2534 2535 compute-cb@3 { 2536 compatible = "qcom,fastrpc-compute-cb"; 2537 reg = <3>; 2538 iommus = <&apps_smmu 0x2163 0x0400>, 2539 <&apps_smmu 0x1023 0x1420>; 2540 }; 2541 2542 compute-cb@4 { 2543 compatible = "qcom,fastrpc-compute-cb"; 2544 reg = <4>; 2545 iommus = <&apps_smmu 0x2164 0x0400>, 2546 <&apps_smmu 0x1024 0x1420>; 2547 }; 2548 2549 compute-cb@5 { 2550 compatible = "qcom,fastrpc-compute-cb"; 2551 reg = <5>; 2552 iommus = <&apps_smmu 0x2165 0x0400>, 2553 <&apps_smmu 0x1025 0x1420>; 2554 }; 2555 2556 compute-cb@6 { 2557 compatible = "qcom,fastrpc-compute-cb"; 2558 reg = <6>; 2559 iommus = <&apps_smmu 0x2166 0x0400>, 2560 <&apps_smmu 0x1026 0x1420>; 2561 }; 2562 2563 compute-cb@7 { 2564 compatible = "qcom,fastrpc-compute-cb"; 2565 reg = <7>; 2566 iommus = <&apps_smmu 0x2167 0x0400>, 2567 <&apps_smmu 0x1027 0x1420>; 2568 }; 2569 2570 compute-cb@8 { 2571 compatible = "qcom,fastrpc-compute-cb"; 2572 reg = <8>; 2573 iommus = <&apps_smmu 0x2168 0x0400>, 2574 <&apps_smmu 0x1028 0x1420>; 2575 }; 2576 2577 /* note: secure cb9 in downstream */ 2578 }; 2579 }; 2580 }; 2581 2582 remoteproc_mpss: remoteproc@4080000 { 2583 compatible = "qcom,sm8450-mpss-pas"; 2584 reg = <0x0 0x04080000 0x0 0x4040>; 2585 2586 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2587 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2588 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2589 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2590 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2591 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2592 interrupt-names = "wdog", "fatal", "ready", "handover", 2593 "stop-ack", "shutdown-ack"; 2594 2595 clocks = <&rpmhcc RPMH_CXO_CLK>; 2596 clock-names = "xo"; 2597 2598 power-domains = <&rpmhpd RPMHPD_CX>, 2599 <&rpmhpd RPMHPD_MSS>; 2600 power-domain-names = "cx", "mss"; 2601 2602 memory-region = <&mpss_mem>; 2603 2604 qcom,qmp = <&aoss_qmp>; 2605 2606 qcom,smem-states = <&smp2p_modem_out 0>; 2607 qcom,smem-state-names = "stop"; 2608 2609 status = "disabled"; 2610 2611 glink-edge { 2612 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2613 IPCC_MPROC_SIGNAL_GLINK_QMP 2614 IRQ_TYPE_EDGE_RISING>; 2615 mboxes = <&ipcc IPCC_CLIENT_MPSS 2616 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2617 label = "modem"; 2618 qcom,remote-pid = <1>; 2619 }; 2620 }; 2621 2622 videocc: clock-controller@aaf0000 { 2623 compatible = "qcom,sm8450-videocc"; 2624 reg = <0 0x0aaf0000 0 0x10000>; 2625 clocks = <&rpmhcc RPMH_CXO_CLK>, 2626 <&gcc GCC_VIDEO_AHB_CLK>; 2627 power-domains = <&rpmhpd RPMHPD_MMCX>; 2628 required-opps = <&rpmhpd_opp_low_svs>; 2629 #clock-cells = <1>; 2630 #reset-cells = <1>; 2631 #power-domain-cells = <1>; 2632 }; 2633 2634 cci0: cci@ac15000 { 2635 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2636 reg = <0 0x0ac15000 0 0x1000>; 2637 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2638 power-domains = <&camcc TITAN_TOP_GDSC>; 2639 2640 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2641 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2642 <&camcc CAM_CC_CPAS_AHB_CLK>, 2643 <&camcc CAM_CC_CCI_0_CLK>, 2644 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2645 clock-names = "camnoc_axi", 2646 "slow_ahb_src", 2647 "cpas_ahb", 2648 "cci", 2649 "cci_src"; 2650 pinctrl-0 = <&cci0_default &cci1_default>; 2651 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2652 pinctrl-names = "default", "sleep"; 2653 2654 status = "disabled"; 2655 #address-cells = <1>; 2656 #size-cells = <0>; 2657 2658 cci0_i2c0: i2c-bus@0 { 2659 reg = <0>; 2660 clock-frequency = <1000000>; 2661 #address-cells = <1>; 2662 #size-cells = <0>; 2663 }; 2664 2665 cci0_i2c1: i2c-bus@1 { 2666 reg = <1>; 2667 clock-frequency = <1000000>; 2668 #address-cells = <1>; 2669 #size-cells = <0>; 2670 }; 2671 }; 2672 2673 cci1: cci@ac16000 { 2674 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2675 reg = <0 0x0ac16000 0 0x1000>; 2676 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2677 power-domains = <&camcc TITAN_TOP_GDSC>; 2678 2679 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2680 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2681 <&camcc CAM_CC_CPAS_AHB_CLK>, 2682 <&camcc CAM_CC_CCI_1_CLK>, 2683 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2684 clock-names = "camnoc_axi", 2685 "slow_ahb_src", 2686 "cpas_ahb", 2687 "cci", 2688 "cci_src"; 2689 pinctrl-0 = <&cci2_default &cci3_default>; 2690 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2691 pinctrl-names = "default", "sleep"; 2692 2693 status = "disabled"; 2694 #address-cells = <1>; 2695 #size-cells = <0>; 2696 2697 cci1_i2c0: i2c-bus@0 { 2698 reg = <0>; 2699 clock-frequency = <1000000>; 2700 #address-cells = <1>; 2701 #size-cells = <0>; 2702 }; 2703 2704 cci1_i2c1: i2c-bus@1 { 2705 reg = <1>; 2706 clock-frequency = <1000000>; 2707 #address-cells = <1>; 2708 #size-cells = <0>; 2709 }; 2710 }; 2711 2712 camcc: clock-controller@ade0000 { 2713 compatible = "qcom,sm8450-camcc"; 2714 reg = <0 0x0ade0000 0 0x20000>; 2715 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2716 <&rpmhcc RPMH_CXO_CLK>, 2717 <&rpmhcc RPMH_CXO_CLK_A>, 2718 <&sleep_clk>; 2719 power-domains = <&rpmhpd RPMHPD_MMCX>; 2720 required-opps = <&rpmhpd_opp_low_svs>; 2721 #clock-cells = <1>; 2722 #reset-cells = <1>; 2723 #power-domain-cells = <1>; 2724 status = "disabled"; 2725 }; 2726 2727 mdss: display-subsystem@ae00000 { 2728 compatible = "qcom,sm8450-mdss"; 2729 reg = <0 0x0ae00000 0 0x1000>; 2730 reg-names = "mdss"; 2731 2732 /* same path used twice */ 2733 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2734 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2735 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2736 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2737 interconnect-names = "mdp0-mem", 2738 "mdp1-mem", 2739 "cpu-cfg"; 2740 2741 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2742 2743 power-domains = <&dispcc MDSS_GDSC>; 2744 2745 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2746 <&gcc GCC_DISP_HF_AXI_CLK>, 2747 <&gcc GCC_DISP_SF_AXI_CLK>, 2748 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2749 2750 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2751 interrupt-controller; 2752 #interrupt-cells = <1>; 2753 2754 iommus = <&apps_smmu 0x2800 0x402>; 2755 2756 #address-cells = <2>; 2757 #size-cells = <2>; 2758 ranges; 2759 2760 status = "disabled"; 2761 2762 mdss_mdp: display-controller@ae01000 { 2763 compatible = "qcom,sm8450-dpu"; 2764 reg = <0 0x0ae01000 0 0x8f000>, 2765 <0 0x0aeb0000 0 0x2008>; 2766 reg-names = "mdp", "vbif"; 2767 2768 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2769 <&gcc GCC_DISP_SF_AXI_CLK>, 2770 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2771 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2772 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2773 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2774 clock-names = "bus", 2775 "nrt_bus", 2776 "iface", 2777 "lut", 2778 "core", 2779 "vsync"; 2780 2781 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2782 assigned-clock-rates = <19200000>; 2783 2784 operating-points-v2 = <&mdp_opp_table>; 2785 power-domains = <&rpmhpd RPMHPD_MMCX>; 2786 2787 interrupt-parent = <&mdss>; 2788 interrupts = <0>; 2789 2790 ports { 2791 #address-cells = <1>; 2792 #size-cells = <0>; 2793 2794 port@0 { 2795 reg = <0>; 2796 dpu_intf1_out: endpoint { 2797 remote-endpoint = <&mdss_dsi0_in>; 2798 }; 2799 }; 2800 2801 port@1 { 2802 reg = <1>; 2803 dpu_intf2_out: endpoint { 2804 remote-endpoint = <&mdss_dsi1_in>; 2805 }; 2806 }; 2807 2808 port@2 { 2809 reg = <2>; 2810 dpu_intf0_out: endpoint { 2811 remote-endpoint = <&mdss_dp0_in>; 2812 }; 2813 }; 2814 }; 2815 2816 mdp_opp_table: opp-table { 2817 compatible = "operating-points-v2"; 2818 2819 opp-172000000 { 2820 opp-hz = /bits/ 64 <172000000>; 2821 required-opps = <&rpmhpd_opp_low_svs_d1>; 2822 }; 2823 2824 opp-200000000 { 2825 opp-hz = /bits/ 64 <200000000>; 2826 required-opps = <&rpmhpd_opp_low_svs>; 2827 }; 2828 2829 opp-325000000 { 2830 opp-hz = /bits/ 64 <325000000>; 2831 required-opps = <&rpmhpd_opp_svs>; 2832 }; 2833 2834 opp-375000000 { 2835 opp-hz = /bits/ 64 <375000000>; 2836 required-opps = <&rpmhpd_opp_svs_l1>; 2837 }; 2838 2839 opp-500000000 { 2840 opp-hz = /bits/ 64 <500000000>; 2841 required-opps = <&rpmhpd_opp_nom>; 2842 }; 2843 }; 2844 }; 2845 2846 mdss_dp0: displayport-controller@ae90000 { 2847 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 2848 reg = <0 0xae90000 0 0x200>, 2849 <0 0xae90200 0 0x200>, 2850 <0 0xae90400 0 0xc00>, 2851 <0 0xae91000 0 0x400>, 2852 <0 0xae91400 0 0x400>; 2853 interrupt-parent = <&mdss>; 2854 interrupts = <12>; 2855 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2856 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2857 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2858 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2859 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2860 clock-names = "core_iface", 2861 "core_aux", 2862 "ctrl_link", 2863 "ctrl_link_iface", 2864 "stream_pixel"; 2865 2866 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2867 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2868 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2869 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2870 2871 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2872 phy-names = "dp"; 2873 2874 #sound-dai-cells = <0>; 2875 2876 operating-points-v2 = <&dp_opp_table>; 2877 power-domains = <&rpmhpd RPMHPD_MMCX>; 2878 2879 status = "disabled"; 2880 2881 ports { 2882 #address-cells = <1>; 2883 #size-cells = <0>; 2884 2885 port@0 { 2886 reg = <0>; 2887 mdss_dp0_in: endpoint { 2888 remote-endpoint = <&dpu_intf0_out>; 2889 }; 2890 }; 2891 }; 2892 2893 dp_opp_table: opp-table { 2894 compatible = "operating-points-v2"; 2895 2896 opp-160000000 { 2897 opp-hz = /bits/ 64 <160000000>; 2898 required-opps = <&rpmhpd_opp_low_svs>; 2899 }; 2900 2901 opp-270000000 { 2902 opp-hz = /bits/ 64 <270000000>; 2903 required-opps = <&rpmhpd_opp_svs>; 2904 }; 2905 2906 opp-540000000 { 2907 opp-hz = /bits/ 64 <540000000>; 2908 required-opps = <&rpmhpd_opp_svs_l1>; 2909 }; 2910 2911 opp-810000000 { 2912 opp-hz = /bits/ 64 <810000000>; 2913 required-opps = <&rpmhpd_opp_nom>; 2914 }; 2915 }; 2916 }; 2917 2918 mdss_dsi0: dsi@ae94000 { 2919 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2920 reg = <0 0x0ae94000 0 0x400>; 2921 reg-names = "dsi_ctrl"; 2922 2923 interrupt-parent = <&mdss>; 2924 interrupts = <4>; 2925 2926 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2927 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2928 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2929 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2930 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2931 <&gcc GCC_DISP_HF_AXI_CLK>; 2932 clock-names = "byte", 2933 "byte_intf", 2934 "pixel", 2935 "core", 2936 "iface", 2937 "bus"; 2938 2939 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2940 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2941 2942 operating-points-v2 = <&mdss_dsi_opp_table>; 2943 power-domains = <&rpmhpd RPMHPD_MMCX>; 2944 2945 phys = <&mdss_dsi0_phy>; 2946 phy-names = "dsi"; 2947 2948 #address-cells = <1>; 2949 #size-cells = <0>; 2950 2951 status = "disabled"; 2952 2953 ports { 2954 #address-cells = <1>; 2955 #size-cells = <0>; 2956 2957 port@0 { 2958 reg = <0>; 2959 mdss_dsi0_in: endpoint { 2960 remote-endpoint = <&dpu_intf1_out>; 2961 }; 2962 }; 2963 2964 port@1 { 2965 reg = <1>; 2966 mdss_dsi0_out: endpoint { 2967 }; 2968 }; 2969 }; 2970 2971 mdss_dsi_opp_table: opp-table { 2972 compatible = "operating-points-v2"; 2973 2974 opp-187500000 { 2975 opp-hz = /bits/ 64 <187500000>; 2976 required-opps = <&rpmhpd_opp_low_svs>; 2977 }; 2978 2979 opp-300000000 { 2980 opp-hz = /bits/ 64 <300000000>; 2981 required-opps = <&rpmhpd_opp_svs>; 2982 }; 2983 2984 opp-358000000 { 2985 opp-hz = /bits/ 64 <358000000>; 2986 required-opps = <&rpmhpd_opp_svs_l1>; 2987 }; 2988 }; 2989 }; 2990 2991 mdss_dsi0_phy: phy@ae94400 { 2992 compatible = "qcom,sm8450-dsi-phy-5nm"; 2993 reg = <0 0x0ae94400 0 0x200>, 2994 <0 0x0ae94600 0 0x280>, 2995 <0 0x0ae94900 0 0x260>; 2996 reg-names = "dsi_phy", 2997 "dsi_phy_lane", 2998 "dsi_pll"; 2999 3000 #clock-cells = <1>; 3001 #phy-cells = <0>; 3002 3003 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3004 <&rpmhcc RPMH_CXO_CLK>; 3005 clock-names = "iface", "ref"; 3006 3007 status = "disabled"; 3008 }; 3009 3010 mdss_dsi1: dsi@ae96000 { 3011 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3012 reg = <0 0x0ae96000 0 0x400>; 3013 reg-names = "dsi_ctrl"; 3014 3015 interrupt-parent = <&mdss>; 3016 interrupts = <5>; 3017 3018 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3019 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3020 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3021 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3022 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3023 <&gcc GCC_DISP_HF_AXI_CLK>; 3024 clock-names = "byte", 3025 "byte_intf", 3026 "pixel", 3027 "core", 3028 "iface", 3029 "bus"; 3030 3031 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3032 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3033 3034 operating-points-v2 = <&mdss_dsi_opp_table>; 3035 power-domains = <&rpmhpd RPMHPD_MMCX>; 3036 3037 phys = <&mdss_dsi1_phy>; 3038 phy-names = "dsi"; 3039 3040 #address-cells = <1>; 3041 #size-cells = <0>; 3042 3043 status = "disabled"; 3044 3045 ports { 3046 #address-cells = <1>; 3047 #size-cells = <0>; 3048 3049 port@0 { 3050 reg = <0>; 3051 mdss_dsi1_in: endpoint { 3052 remote-endpoint = <&dpu_intf2_out>; 3053 }; 3054 }; 3055 3056 port@1 { 3057 reg = <1>; 3058 mdss_dsi1_out: endpoint { 3059 }; 3060 }; 3061 }; 3062 }; 3063 3064 mdss_dsi1_phy: phy@ae96400 { 3065 compatible = "qcom,sm8450-dsi-phy-5nm"; 3066 reg = <0 0x0ae96400 0 0x200>, 3067 <0 0x0ae96600 0 0x280>, 3068 <0 0x0ae96900 0 0x260>; 3069 reg-names = "dsi_phy", 3070 "dsi_phy_lane", 3071 "dsi_pll"; 3072 3073 #clock-cells = <1>; 3074 #phy-cells = <0>; 3075 3076 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3077 <&rpmhcc RPMH_CXO_CLK>; 3078 clock-names = "iface", "ref"; 3079 3080 status = "disabled"; 3081 }; 3082 }; 3083 3084 dispcc: clock-controller@af00000 { 3085 compatible = "qcom,sm8450-dispcc"; 3086 reg = <0 0x0af00000 0 0x20000>; 3087 clocks = <&rpmhcc RPMH_CXO_CLK>, 3088 <&rpmhcc RPMH_CXO_CLK_A>, 3089 <&gcc GCC_DISP_AHB_CLK>, 3090 <&sleep_clk>, 3091 <&mdss_dsi0_phy 0>, 3092 <&mdss_dsi0_phy 1>, 3093 <&mdss_dsi1_phy 0>, 3094 <&mdss_dsi1_phy 1>, 3095 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3096 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3097 <0>, /* dp1 */ 3098 <0>, 3099 <0>, /* dp2 */ 3100 <0>, 3101 <0>, /* dp3 */ 3102 <0>; 3103 power-domains = <&rpmhpd RPMHPD_MMCX>; 3104 required-opps = <&rpmhpd_opp_low_svs>; 3105 #clock-cells = <1>; 3106 #reset-cells = <1>; 3107 #power-domain-cells = <1>; 3108 status = "disabled"; 3109 }; 3110 3111 pdc: interrupt-controller@b220000 { 3112 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3113 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3114 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3115 <94 609 31>, <125 63 1>, <126 716 12>; 3116 #interrupt-cells = <2>; 3117 interrupt-parent = <&intc>; 3118 interrupt-controller; 3119 }; 3120 3121 tsens0: thermal-sensor@c263000 { 3122 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3123 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3124 <0 0x0c222000 0 0x1000>; /* SROT */ 3125 #qcom,sensors = <16>; 3126 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3128 interrupt-names = "uplow", "critical"; 3129 #thermal-sensor-cells = <1>; 3130 }; 3131 3132 tsens1: thermal-sensor@c265000 { 3133 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3134 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3135 <0 0x0c223000 0 0x1000>; /* SROT */ 3136 #qcom,sensors = <16>; 3137 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3139 interrupt-names = "uplow", "critical"; 3140 #thermal-sensor-cells = <1>; 3141 }; 3142 3143 aoss_qmp: power-management@c300000 { 3144 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3145 reg = <0 0x0c300000 0 0x400>; 3146 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3147 IRQ_TYPE_EDGE_RISING>; 3148 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3149 3150 #clock-cells = <0>; 3151 }; 3152 3153 sram@c3f0000 { 3154 compatible = "qcom,rpmh-stats"; 3155 reg = <0 0x0c3f0000 0 0x400>; 3156 }; 3157 3158 spmi_bus: spmi@c400000 { 3159 compatible = "qcom,spmi-pmic-arb"; 3160 reg = <0 0x0c400000 0 0x00003000>, 3161 <0 0x0c500000 0 0x00400000>, 3162 <0 0x0c440000 0 0x00080000>, 3163 <0 0x0c4c0000 0 0x00010000>, 3164 <0 0x0c42d000 0 0x00010000>; 3165 reg-names = "core", 3166 "chnls", 3167 "obsrvr", 3168 "intr", 3169 "cnfg"; 3170 interrupt-names = "periph_irq"; 3171 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3172 qcom,ee = <0>; 3173 qcom,channel = <0>; 3174 interrupt-controller; 3175 #interrupt-cells = <4>; 3176 #address-cells = <2>; 3177 #size-cells = <0>; 3178 }; 3179 3180 ipcc: mailbox@ed18000 { 3181 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3182 reg = <0 0x0ed18000 0 0x1000>; 3183 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3184 interrupt-controller; 3185 #interrupt-cells = <3>; 3186 #mbox-cells = <2>; 3187 }; 3188 3189 tlmm: pinctrl@f100000 { 3190 compatible = "qcom,sm8450-tlmm"; 3191 reg = <0 0x0f100000 0 0x300000>; 3192 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3193 gpio-controller; 3194 #gpio-cells = <2>; 3195 interrupt-controller; 3196 #interrupt-cells = <2>; 3197 gpio-ranges = <&tlmm 0 0 211>; 3198 wakeup-parent = <&pdc>; 3199 3200 sdc2_default_state: sdc2-default-state { 3201 clk-pins { 3202 pins = "sdc2_clk"; 3203 drive-strength = <16>; 3204 bias-disable; 3205 }; 3206 3207 cmd-pins { 3208 pins = "sdc2_cmd"; 3209 drive-strength = <16>; 3210 bias-pull-up; 3211 }; 3212 3213 data-pins { 3214 pins = "sdc2_data"; 3215 drive-strength = <16>; 3216 bias-pull-up; 3217 }; 3218 }; 3219 3220 sdc2_sleep_state: sdc2-sleep-state { 3221 clk-pins { 3222 pins = "sdc2_clk"; 3223 drive-strength = <2>; 3224 bias-disable; 3225 }; 3226 3227 cmd-pins { 3228 pins = "sdc2_cmd"; 3229 drive-strength = <2>; 3230 bias-pull-up; 3231 }; 3232 3233 data-pins { 3234 pins = "sdc2_data"; 3235 drive-strength = <2>; 3236 bias-pull-up; 3237 }; 3238 }; 3239 3240 cci0_default: cci0-default-state { 3241 /* SDA, SCL */ 3242 pins = "gpio110", "gpio111"; 3243 function = "cci_i2c"; 3244 drive-strength = <2>; 3245 bias-pull-up; 3246 }; 3247 3248 cci0_sleep: cci0-sleep-state { 3249 /* SDA, SCL */ 3250 pins = "gpio110", "gpio111"; 3251 function = "cci_i2c"; 3252 drive-strength = <2>; 3253 bias-pull-down; 3254 }; 3255 3256 cci1_default: cci1-default-state { 3257 /* SDA, SCL */ 3258 pins = "gpio112", "gpio113"; 3259 function = "cci_i2c"; 3260 drive-strength = <2>; 3261 bias-pull-up; 3262 }; 3263 3264 cci1_sleep: cci1-sleep-state { 3265 /* SDA, SCL */ 3266 pins = "gpio112", "gpio113"; 3267 function = "cci_i2c"; 3268 drive-strength = <2>; 3269 bias-pull-down; 3270 }; 3271 3272 cci2_default: cci2-default-state { 3273 /* SDA, SCL */ 3274 pins = "gpio114", "gpio115"; 3275 function = "cci_i2c"; 3276 drive-strength = <2>; 3277 bias-pull-up; 3278 }; 3279 3280 cci2_sleep: cci2-sleep-state { 3281 /* SDA, SCL */ 3282 pins = "gpio114", "gpio115"; 3283 function = "cci_i2c"; 3284 drive-strength = <2>; 3285 bias-pull-down; 3286 }; 3287 3288 cci3_default: cci3-default-state { 3289 /* SDA, SCL */ 3290 pins = "gpio208", "gpio209"; 3291 function = "cci_i2c"; 3292 drive-strength = <2>; 3293 bias-pull-up; 3294 }; 3295 3296 cci3_sleep: cci3-sleep-state { 3297 /* SDA, SCL */ 3298 pins = "gpio208", "gpio209"; 3299 function = "cci_i2c"; 3300 drive-strength = <2>; 3301 bias-pull-down; 3302 }; 3303 3304 pcie0_default_state: pcie0-default-state { 3305 perst-pins { 3306 pins = "gpio94"; 3307 function = "gpio"; 3308 drive-strength = <2>; 3309 bias-pull-down; 3310 }; 3311 3312 clkreq-pins { 3313 pins = "gpio95"; 3314 function = "pcie0_clkreqn"; 3315 drive-strength = <2>; 3316 bias-pull-up; 3317 }; 3318 3319 wake-pins { 3320 pins = "gpio96"; 3321 function = "gpio"; 3322 drive-strength = <2>; 3323 bias-pull-up; 3324 }; 3325 }; 3326 3327 pcie1_default_state: pcie1-default-state { 3328 perst-pins { 3329 pins = "gpio97"; 3330 function = "gpio"; 3331 drive-strength = <2>; 3332 bias-pull-down; 3333 }; 3334 3335 clkreq-pins { 3336 pins = "gpio98"; 3337 function = "pcie1_clkreqn"; 3338 drive-strength = <2>; 3339 bias-pull-up; 3340 }; 3341 3342 wake-pins { 3343 pins = "gpio99"; 3344 function = "gpio"; 3345 drive-strength = <2>; 3346 bias-pull-up; 3347 }; 3348 }; 3349 3350 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3351 pins = "gpio0", "gpio1"; 3352 function = "qup0"; 3353 }; 3354 3355 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3356 pins = "gpio4", "gpio5"; 3357 function = "qup1"; 3358 }; 3359 3360 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3361 pins = "gpio8", "gpio9"; 3362 function = "qup2"; 3363 }; 3364 3365 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3366 pins = "gpio12", "gpio13"; 3367 function = "qup3"; 3368 }; 3369 3370 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3371 pins = "gpio16", "gpio17"; 3372 function = "qup4"; 3373 }; 3374 3375 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3376 pins = "gpio206", "gpio207"; 3377 function = "qup5"; 3378 }; 3379 3380 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3381 pins = "gpio20", "gpio21"; 3382 function = "qup6"; 3383 }; 3384 3385 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3386 pins = "gpio28", "gpio29"; 3387 function = "qup8"; 3388 }; 3389 3390 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3391 pins = "gpio32", "gpio33"; 3392 function = "qup9"; 3393 }; 3394 3395 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3396 pins = "gpio36", "gpio37"; 3397 function = "qup10"; 3398 }; 3399 3400 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3401 pins = "gpio40", "gpio41"; 3402 function = "qup11"; 3403 }; 3404 3405 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3406 pins = "gpio44", "gpio45"; 3407 function = "qup12"; 3408 }; 3409 3410 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3411 pins = "gpio48", "gpio49"; 3412 function = "qup13"; 3413 drive-strength = <2>; 3414 bias-pull-up; 3415 }; 3416 3417 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3418 pins = "gpio52", "gpio53"; 3419 function = "qup14"; 3420 drive-strength = <2>; 3421 bias-pull-up; 3422 }; 3423 3424 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3425 pins = "gpio56", "gpio57"; 3426 function = "qup15"; 3427 }; 3428 3429 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3430 pins = "gpio60", "gpio61"; 3431 function = "qup16"; 3432 }; 3433 3434 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3435 pins = "gpio64", "gpio65"; 3436 function = "qup17"; 3437 }; 3438 3439 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3440 pins = "gpio68", "gpio69"; 3441 function = "qup18"; 3442 }; 3443 3444 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3445 pins = "gpio72", "gpio73"; 3446 function = "qup19"; 3447 }; 3448 3449 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3450 pins = "gpio76", "gpio77"; 3451 function = "qup20"; 3452 }; 3453 3454 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3455 pins = "gpio80", "gpio81"; 3456 function = "qup21"; 3457 }; 3458 3459 qup_spi0_cs: qup-spi0-cs-state { 3460 pins = "gpio3"; 3461 function = "qup0"; 3462 }; 3463 3464 qup_spi0_data_clk: qup-spi0-data-clk-state { 3465 pins = "gpio0", "gpio1", "gpio2"; 3466 function = "qup0"; 3467 }; 3468 3469 qup_spi1_cs: qup-spi1-cs-state { 3470 pins = "gpio7"; 3471 function = "qup1"; 3472 }; 3473 3474 qup_spi1_data_clk: qup-spi1-data-clk-state { 3475 pins = "gpio4", "gpio5", "gpio6"; 3476 function = "qup1"; 3477 }; 3478 3479 qup_spi2_cs: qup-spi2-cs-state { 3480 pins = "gpio11"; 3481 function = "qup2"; 3482 }; 3483 3484 qup_spi2_data_clk: qup-spi2-data-clk-state { 3485 pins = "gpio8", "gpio9", "gpio10"; 3486 function = "qup2"; 3487 }; 3488 3489 qup_spi3_cs: qup-spi3-cs-state { 3490 pins = "gpio15"; 3491 function = "qup3"; 3492 }; 3493 3494 qup_spi3_data_clk: qup-spi3-data-clk-state { 3495 pins = "gpio12", "gpio13", "gpio14"; 3496 function = "qup3"; 3497 }; 3498 3499 qup_spi4_cs: qup-spi4-cs-state { 3500 pins = "gpio19"; 3501 function = "qup4"; 3502 drive-strength = <6>; 3503 bias-disable; 3504 }; 3505 3506 qup_spi4_data_clk: qup-spi4-data-clk-state { 3507 pins = "gpio16", "gpio17", "gpio18"; 3508 function = "qup4"; 3509 }; 3510 3511 qup_spi5_cs: qup-spi5-cs-state { 3512 pins = "gpio85"; 3513 function = "qup5"; 3514 }; 3515 3516 qup_spi5_data_clk: qup-spi5-data-clk-state { 3517 pins = "gpio206", "gpio207", "gpio84"; 3518 function = "qup5"; 3519 }; 3520 3521 qup_spi6_cs: qup-spi6-cs-state { 3522 pins = "gpio23"; 3523 function = "qup6"; 3524 }; 3525 3526 qup_spi6_data_clk: qup-spi6-data-clk-state { 3527 pins = "gpio20", "gpio21", "gpio22"; 3528 function = "qup6"; 3529 }; 3530 3531 qup_spi8_cs: qup-spi8-cs-state { 3532 pins = "gpio31"; 3533 function = "qup8"; 3534 }; 3535 3536 qup_spi8_data_clk: qup-spi8-data-clk-state { 3537 pins = "gpio28", "gpio29", "gpio30"; 3538 function = "qup8"; 3539 }; 3540 3541 qup_spi9_cs: qup-spi9-cs-state { 3542 pins = "gpio35"; 3543 function = "qup9"; 3544 }; 3545 3546 qup_spi9_data_clk: qup-spi9-data-clk-state { 3547 pins = "gpio32", "gpio33", "gpio34"; 3548 function = "qup9"; 3549 }; 3550 3551 qup_spi10_cs: qup-spi10-cs-state { 3552 pins = "gpio39"; 3553 function = "qup10"; 3554 }; 3555 3556 qup_spi10_data_clk: qup-spi10-data-clk-state { 3557 pins = "gpio36", "gpio37", "gpio38"; 3558 function = "qup10"; 3559 }; 3560 3561 qup_spi11_cs: qup-spi11-cs-state { 3562 pins = "gpio43"; 3563 function = "qup11"; 3564 }; 3565 3566 qup_spi11_data_clk: qup-spi11-data-clk-state { 3567 pins = "gpio40", "gpio41", "gpio42"; 3568 function = "qup11"; 3569 }; 3570 3571 qup_spi12_cs: qup-spi12-cs-state { 3572 pins = "gpio47"; 3573 function = "qup12"; 3574 }; 3575 3576 qup_spi12_data_clk: qup-spi12-data-clk-state { 3577 pins = "gpio44", "gpio45", "gpio46"; 3578 function = "qup12"; 3579 }; 3580 3581 qup_spi13_cs: qup-spi13-cs-state { 3582 pins = "gpio51"; 3583 function = "qup13"; 3584 }; 3585 3586 qup_spi13_data_clk: qup-spi13-data-clk-state { 3587 pins = "gpio48", "gpio49", "gpio50"; 3588 function = "qup13"; 3589 }; 3590 3591 qup_spi14_cs: qup-spi14-cs-state { 3592 pins = "gpio55"; 3593 function = "qup14"; 3594 }; 3595 3596 qup_spi14_data_clk: qup-spi14-data-clk-state { 3597 pins = "gpio52", "gpio53", "gpio54"; 3598 function = "qup14"; 3599 }; 3600 3601 qup_spi15_cs: qup-spi15-cs-state { 3602 pins = "gpio59"; 3603 function = "qup15"; 3604 }; 3605 3606 qup_spi15_data_clk: qup-spi15-data-clk-state { 3607 pins = "gpio56", "gpio57", "gpio58"; 3608 function = "qup15"; 3609 }; 3610 3611 qup_spi16_cs: qup-spi16-cs-state { 3612 pins = "gpio63"; 3613 function = "qup16"; 3614 }; 3615 3616 qup_spi16_data_clk: qup-spi16-data-clk-state { 3617 pins = "gpio60", "gpio61", "gpio62"; 3618 function = "qup16"; 3619 }; 3620 3621 qup_spi17_cs: qup-spi17-cs-state { 3622 pins = "gpio67"; 3623 function = "qup17"; 3624 }; 3625 3626 qup_spi17_data_clk: qup-spi17-data-clk-state { 3627 pins = "gpio64", "gpio65", "gpio66"; 3628 function = "qup17"; 3629 }; 3630 3631 qup_spi18_cs: qup-spi18-cs-state { 3632 pins = "gpio71"; 3633 function = "qup18"; 3634 drive-strength = <6>; 3635 bias-disable; 3636 }; 3637 3638 qup_spi18_data_clk: qup-spi18-data-clk-state { 3639 pins = "gpio68", "gpio69", "gpio70"; 3640 function = "qup18"; 3641 drive-strength = <6>; 3642 bias-disable; 3643 }; 3644 3645 qup_spi19_cs: qup-spi19-cs-state { 3646 pins = "gpio75"; 3647 function = "qup19"; 3648 drive-strength = <6>; 3649 bias-disable; 3650 }; 3651 3652 qup_spi19_data_clk: qup-spi19-data-clk-state { 3653 pins = "gpio72", "gpio73", "gpio74"; 3654 function = "qup19"; 3655 drive-strength = <6>; 3656 bias-disable; 3657 }; 3658 3659 qup_spi20_cs: qup-spi20-cs-state { 3660 pins = "gpio79"; 3661 function = "qup20"; 3662 }; 3663 3664 qup_spi20_data_clk: qup-spi20-data-clk-state { 3665 pins = "gpio76", "gpio77", "gpio78"; 3666 function = "qup20"; 3667 }; 3668 3669 qup_spi21_cs: qup-spi21-cs-state { 3670 pins = "gpio83"; 3671 function = "qup21"; 3672 }; 3673 3674 qup_spi21_data_clk: qup-spi21-data-clk-state { 3675 pins = "gpio80", "gpio81", "gpio82"; 3676 function = "qup21"; 3677 }; 3678 3679 qup_uart7_rx: qup-uart7-rx-state { 3680 pins = "gpio26"; 3681 function = "qup7"; 3682 drive-strength = <2>; 3683 bias-disable; 3684 }; 3685 3686 qup_uart7_tx: qup-uart7-tx-state { 3687 pins = "gpio27"; 3688 function = "qup7"; 3689 drive-strength = <2>; 3690 bias-disable; 3691 }; 3692 3693 qup_uart20_default: qup-uart20-default-state { 3694 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3695 function = "qup20"; 3696 }; 3697 }; 3698 3699 lpass_tlmm: pinctrl@3440000 { 3700 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3701 reg = <0 0x03440000 0x0 0x20000>, 3702 <0 0x034d0000 0x0 0x10000>; 3703 gpio-controller; 3704 #gpio-cells = <2>; 3705 gpio-ranges = <&lpass_tlmm 0 0 23>; 3706 3707 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3708 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3709 clock-names = "core", "audio"; 3710 3711 tx_swr_active: tx-swr-active-state { 3712 clk-pins { 3713 pins = "gpio0"; 3714 function = "swr_tx_clk"; 3715 drive-strength = <2>; 3716 slew-rate = <1>; 3717 bias-disable; 3718 }; 3719 3720 data-pins { 3721 pins = "gpio1", "gpio2", "gpio14"; 3722 function = "swr_tx_data"; 3723 drive-strength = <2>; 3724 slew-rate = <1>; 3725 bias-bus-hold; 3726 }; 3727 }; 3728 3729 rx_swr_active: rx-swr-active-state { 3730 clk-pins { 3731 pins = "gpio3"; 3732 function = "swr_rx_clk"; 3733 drive-strength = <2>; 3734 slew-rate = <1>; 3735 bias-disable; 3736 }; 3737 3738 data-pins { 3739 pins = "gpio4", "gpio5"; 3740 function = "swr_rx_data"; 3741 drive-strength = <2>; 3742 slew-rate = <1>; 3743 bias-bus-hold; 3744 }; 3745 }; 3746 3747 dmic01_default: dmic01-default-state { 3748 clk-pins { 3749 pins = "gpio6"; 3750 function = "dmic1_clk"; 3751 drive-strength = <8>; 3752 output-high; 3753 }; 3754 3755 data-pins { 3756 pins = "gpio7"; 3757 function = "dmic1_data"; 3758 drive-strength = <8>; 3759 }; 3760 }; 3761 3762 dmic02_default: dmic02-default-state { 3763 clk-pins { 3764 pins = "gpio8"; 3765 function = "dmic2_clk"; 3766 drive-strength = <8>; 3767 output-high; 3768 }; 3769 3770 data-pins { 3771 pins = "gpio9"; 3772 function = "dmic2_data"; 3773 drive-strength = <8>; 3774 }; 3775 }; 3776 3777 wsa_swr_active: wsa-swr-active-state { 3778 clk-pins { 3779 pins = "gpio10"; 3780 function = "wsa_swr_clk"; 3781 drive-strength = <2>; 3782 slew-rate = <1>; 3783 bias-disable; 3784 }; 3785 3786 data-pins { 3787 pins = "gpio11"; 3788 function = "wsa_swr_data"; 3789 drive-strength = <2>; 3790 slew-rate = <1>; 3791 bias-bus-hold; 3792 }; 3793 }; 3794 3795 wsa2_swr_active: wsa2-swr-active-state { 3796 clk-pins { 3797 pins = "gpio15"; 3798 function = "wsa2_swr_clk"; 3799 drive-strength = <2>; 3800 slew-rate = <1>; 3801 bias-disable; 3802 }; 3803 3804 data-pins { 3805 pins = "gpio16"; 3806 function = "wsa2_swr_data"; 3807 drive-strength = <2>; 3808 slew-rate = <1>; 3809 bias-bus-hold; 3810 }; 3811 }; 3812 }; 3813 3814 sram@146aa000 { 3815 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3816 reg = <0 0x146aa000 0 0x1000>; 3817 ranges = <0 0 0x146aa000 0x1000>; 3818 3819 #address-cells = <1>; 3820 #size-cells = <1>; 3821 3822 pil-reloc@94c { 3823 compatible = "qcom,pil-reloc-info"; 3824 reg = <0x94c 0xc8>; 3825 }; 3826 }; 3827 3828 apps_smmu: iommu@15000000 { 3829 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3830 reg = <0 0x15000000 0 0x100000>; 3831 #iommu-cells = <2>; 3832 #global-interrupts = <1>; 3833 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3930 }; 3931 3932 intc: interrupt-controller@17100000 { 3933 compatible = "arm,gic-v3"; 3934 #interrupt-cells = <3>; 3935 interrupt-controller; 3936 #redistributor-regions = <1>; 3937 redistributor-stride = <0x0 0x40000>; 3938 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3939 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3940 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3941 #address-cells = <2>; 3942 #size-cells = <2>; 3943 ranges; 3944 3945 gic_its: msi-controller@17140000 { 3946 compatible = "arm,gic-v3-its"; 3947 reg = <0x0 0x17140000 0x0 0x20000>; 3948 msi-controller; 3949 #msi-cells = <1>; 3950 }; 3951 }; 3952 3953 timer@17420000 { 3954 compatible = "arm,armv7-timer-mem"; 3955 #address-cells = <1>; 3956 #size-cells = <1>; 3957 ranges = <0 0 0 0x20000000>; 3958 reg = <0x0 0x17420000 0x0 0x1000>; 3959 clock-frequency = <19200000>; 3960 3961 frame@17421000 { 3962 frame-number = <0>; 3963 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3965 reg = <0x17421000 0x1000>, 3966 <0x17422000 0x1000>; 3967 }; 3968 3969 frame@17423000 { 3970 frame-number = <1>; 3971 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3972 reg = <0x17423000 0x1000>; 3973 status = "disabled"; 3974 }; 3975 3976 frame@17425000 { 3977 frame-number = <2>; 3978 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3979 reg = <0x17425000 0x1000>; 3980 status = "disabled"; 3981 }; 3982 3983 frame@17427000 { 3984 frame-number = <3>; 3985 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3986 reg = <0x17427000 0x1000>; 3987 status = "disabled"; 3988 }; 3989 3990 frame@17429000 { 3991 frame-number = <4>; 3992 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3993 reg = <0x17429000 0x1000>; 3994 status = "disabled"; 3995 }; 3996 3997 frame@1742b000 { 3998 frame-number = <5>; 3999 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4000 reg = <0x1742b000 0x1000>; 4001 status = "disabled"; 4002 }; 4003 4004 frame@1742d000 { 4005 frame-number = <6>; 4006 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4007 reg = <0x1742d000 0x1000>; 4008 status = "disabled"; 4009 }; 4010 }; 4011 4012 apps_rsc: rsc@17a00000 { 4013 label = "apps_rsc"; 4014 compatible = "qcom,rpmh-rsc"; 4015 reg = <0x0 0x17a00000 0x0 0x10000>, 4016 <0x0 0x17a10000 0x0 0x10000>, 4017 <0x0 0x17a20000 0x0 0x10000>, 4018 <0x0 0x17a30000 0x0 0x10000>; 4019 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4020 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4023 qcom,tcs-offset = <0xd00>; 4024 qcom,drv-id = <2>; 4025 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4026 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4027 power-domains = <&CLUSTER_PD>; 4028 4029 apps_bcm_voter: bcm-voter { 4030 compatible = "qcom,bcm-voter"; 4031 }; 4032 4033 rpmhcc: clock-controller { 4034 compatible = "qcom,sm8450-rpmh-clk"; 4035 #clock-cells = <1>; 4036 clock-names = "xo"; 4037 clocks = <&xo_board>; 4038 }; 4039 4040 rpmhpd: power-controller { 4041 compatible = "qcom,sm8450-rpmhpd"; 4042 #power-domain-cells = <1>; 4043 operating-points-v2 = <&rpmhpd_opp_table>; 4044 4045 rpmhpd_opp_table: opp-table { 4046 compatible = "operating-points-v2"; 4047 4048 rpmhpd_opp_ret: opp1 { 4049 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4050 }; 4051 4052 rpmhpd_opp_min_svs: opp2 { 4053 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4054 }; 4055 4056 rpmhpd_opp_low_svs_d1: opp3 { 4057 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4058 }; 4059 4060 rpmhpd_opp_low_svs: opp4 { 4061 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4062 }; 4063 4064 rpmhpd_opp_low_svs_l1: opp5 { 4065 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4066 }; 4067 4068 rpmhpd_opp_svs: opp6 { 4069 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4070 }; 4071 4072 rpmhpd_opp_svs_l0: opp7 { 4073 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4074 }; 4075 4076 rpmhpd_opp_svs_l1: opp8 { 4077 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4078 }; 4079 4080 rpmhpd_opp_svs_l2: opp9 { 4081 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4082 }; 4083 4084 rpmhpd_opp_nom: opp10 { 4085 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4086 }; 4087 4088 rpmhpd_opp_nom_l1: opp11 { 4089 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4090 }; 4091 4092 rpmhpd_opp_nom_l2: opp12 { 4093 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4094 }; 4095 4096 rpmhpd_opp_turbo: opp13 { 4097 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4098 }; 4099 4100 rpmhpd_opp_turbo_l1: opp14 { 4101 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4102 }; 4103 }; 4104 }; 4105 }; 4106 4107 cpufreq_hw: cpufreq@17d91000 { 4108 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4109 reg = <0 0x17d91000 0 0x1000>, 4110 <0 0x17d92000 0 0x1000>, 4111 <0 0x17d93000 0 0x1000>; 4112 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4113 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4114 clock-names = "xo", "alternate"; 4115 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4118 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4119 #freq-domain-cells = <1>; 4120 #clock-cells = <1>; 4121 }; 4122 4123 gem_noc: interconnect@19100000 { 4124 compatible = "qcom,sm8450-gem-noc"; 4125 reg = <0 0x19100000 0 0xbb800>; 4126 #interconnect-cells = <2>; 4127 qcom,bcm-voters = <&apps_bcm_voter>; 4128 }; 4129 4130 system-cache-controller@19200000 { 4131 compatible = "qcom,sm8450-llcc"; 4132 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4133 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4134 <0 0x19a00000 0 0x80000>; 4135 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4136 "llcc3_base", "llcc_broadcast_base"; 4137 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4138 }; 4139 4140 ufs_mem_hc: ufshc@1d84000 { 4141 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4142 "jedec,ufs-2.0"; 4143 reg = <0 0x01d84000 0 0x3000>; 4144 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4145 phys = <&ufs_mem_phy_lanes>; 4146 phy-names = "ufsphy"; 4147 lanes-per-direction = <2>; 4148 #reset-cells = <1>; 4149 resets = <&gcc GCC_UFS_PHY_BCR>; 4150 reset-names = "rst"; 4151 4152 power-domains = <&gcc UFS_PHY_GDSC>; 4153 4154 iommus = <&apps_smmu 0xe0 0x0>; 4155 dma-coherent; 4156 4157 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4159 interconnect-names = "ufs-ddr", "cpu-ufs"; 4160 clock-names = 4161 "core_clk", 4162 "bus_aggr_clk", 4163 "iface_clk", 4164 "core_clk_unipro", 4165 "ref_clk", 4166 "tx_lane0_sync_clk", 4167 "rx_lane0_sync_clk", 4168 "rx_lane1_sync_clk"; 4169 clocks = 4170 <&gcc GCC_UFS_PHY_AXI_CLK>, 4171 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4172 <&gcc GCC_UFS_PHY_AHB_CLK>, 4173 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4174 <&rpmhcc RPMH_CXO_CLK>, 4175 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4176 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4177 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4178 freq-table-hz = 4179 <75000000 300000000>, 4180 <0 0>, 4181 <0 0>, 4182 <75000000 300000000>, 4183 <75000000 300000000>, 4184 <0 0>, 4185 <0 0>, 4186 <0 0>; 4187 qcom,ice = <&ice>; 4188 4189 status = "disabled"; 4190 }; 4191 4192 ufs_mem_phy: phy@1d87000 { 4193 compatible = "qcom,sm8450-qmp-ufs-phy"; 4194 reg = <0 0x01d87000 0 0x1c4>; 4195 #address-cells = <2>; 4196 #size-cells = <2>; 4197 ranges; 4198 clock-names = "ref", "ref_aux", "qref"; 4199 clocks = <&rpmhcc RPMH_CXO_CLK>, 4200 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4201 <&gcc GCC_UFS_0_CLKREF_EN>; 4202 4203 resets = <&ufs_mem_hc 0>; 4204 reset-names = "ufsphy"; 4205 status = "disabled"; 4206 4207 ufs_mem_phy_lanes: phy@1d87400 { 4208 reg = <0 0x01d87400 0 0x188>, 4209 <0 0x01d87600 0 0x200>, 4210 <0 0x01d87c00 0 0x200>, 4211 <0 0x01d87800 0 0x188>, 4212 <0 0x01d87a00 0 0x200>; 4213 #clock-cells = <1>; 4214 #phy-cells = <0>; 4215 }; 4216 }; 4217 4218 ice: crypto@1d88000 { 4219 compatible = "qcom,sm8450-inline-crypto-engine", 4220 "qcom,inline-crypto-engine"; 4221 reg = <0 0x01d88000 0 0x8000>; 4222 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4223 }; 4224 4225 cryptobam: dma-controller@1dc4000 { 4226 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4227 reg = <0 0x01dc4000 0 0x28000>; 4228 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4229 #dma-cells = <1>; 4230 qcom,ee = <0>; 4231 qcom,controlled-remotely; 4232 iommus = <&apps_smmu 0x584 0x11>, 4233 <&apps_smmu 0x588 0x0>, 4234 <&apps_smmu 0x598 0x5>, 4235 <&apps_smmu 0x59a 0x0>, 4236 <&apps_smmu 0x59f 0x0>; 4237 }; 4238 4239 crypto: crypto@1dfa000 { 4240 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4241 reg = <0 0x01dfa000 0 0x6000>; 4242 dmas = <&cryptobam 4>, <&cryptobam 5>; 4243 dma-names = "rx", "tx"; 4244 iommus = <&apps_smmu 0x584 0x11>, 4245 <&apps_smmu 0x588 0x0>, 4246 <&apps_smmu 0x598 0x5>, 4247 <&apps_smmu 0x59a 0x0>, 4248 <&apps_smmu 0x59f 0x0>; 4249 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4250 interconnect-names = "memory"; 4251 }; 4252 4253 sdhc_2: mmc@8804000 { 4254 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4255 reg = <0 0x08804000 0 0x1000>; 4256 4257 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4259 interrupt-names = "hc_irq", "pwr_irq"; 4260 4261 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4262 <&gcc GCC_SDCC2_APPS_CLK>, 4263 <&rpmhcc RPMH_CXO_CLK>; 4264 clock-names = "iface", "core", "xo"; 4265 resets = <&gcc GCC_SDCC2_BCR>; 4266 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4267 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4268 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4269 iommus = <&apps_smmu 0x4a0 0x0>; 4270 power-domains = <&rpmhpd RPMHPD_CX>; 4271 operating-points-v2 = <&sdhc2_opp_table>; 4272 bus-width = <4>; 4273 dma-coherent; 4274 4275 /* Forbid SDR104/SDR50 - broken hw! */ 4276 sdhci-caps-mask = <0x3 0x0>; 4277 4278 status = "disabled"; 4279 4280 sdhc2_opp_table: opp-table { 4281 compatible = "operating-points-v2"; 4282 4283 opp-100000000 { 4284 opp-hz = /bits/ 64 <100000000>; 4285 required-opps = <&rpmhpd_opp_low_svs>; 4286 }; 4287 4288 opp-202000000 { 4289 opp-hz = /bits/ 64 <202000000>; 4290 required-opps = <&rpmhpd_opp_svs_l1>; 4291 }; 4292 }; 4293 }; 4294 4295 usb_1: usb@a6f8800 { 4296 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4297 reg = <0 0x0a6f8800 0 0x400>; 4298 status = "disabled"; 4299 #address-cells = <2>; 4300 #size-cells = <2>; 4301 ranges; 4302 4303 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4304 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4305 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4306 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4307 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4308 <&gcc GCC_USB3_0_CLKREF_EN>; 4309 clock-names = "cfg_noc", 4310 "core", 4311 "iface", 4312 "sleep", 4313 "mock_utmi", 4314 "xo"; 4315 4316 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4317 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4318 assigned-clock-rates = <19200000>, <200000000>; 4319 4320 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4321 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4322 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4323 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4324 interrupt-names = "hs_phy_irq", 4325 "ss_phy_irq", 4326 "dm_hs_phy_irq", 4327 "dp_hs_phy_irq"; 4328 4329 power-domains = <&gcc USB30_PRIM_GDSC>; 4330 4331 resets = <&gcc GCC_USB30_PRIM_BCR>; 4332 4333 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4334 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4335 interconnect-names = "usb-ddr", "apps-usb"; 4336 4337 usb_1_dwc3: usb@a600000 { 4338 compatible = "snps,dwc3"; 4339 reg = <0 0x0a600000 0 0xcd00>; 4340 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4341 iommus = <&apps_smmu 0x0 0x0>; 4342 snps,dis_u2_susphy_quirk; 4343 snps,dis_enblslpm_quirk; 4344 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4345 phy-names = "usb2-phy", "usb3-phy"; 4346 4347 ports { 4348 #address-cells = <1>; 4349 #size-cells = <0>; 4350 4351 port@0 { 4352 reg = <0>; 4353 4354 usb_1_dwc3_hs: endpoint { 4355 }; 4356 }; 4357 4358 port@1 { 4359 reg = <1>; 4360 4361 usb_1_dwc3_ss: endpoint { 4362 }; 4363 }; 4364 }; 4365 }; 4366 }; 4367 4368 nsp_noc: interconnect@320c0000 { 4369 compatible = "qcom,sm8450-nsp-noc"; 4370 reg = <0 0x320c0000 0 0x10000>; 4371 #interconnect-cells = <2>; 4372 qcom,bcm-voters = <&apps_bcm_voter>; 4373 }; 4374 4375 lpass_ag_noc: interconnect@3c40000 { 4376 compatible = "qcom,sm8450-lpass-ag-noc"; 4377 reg = <0 0x03c40000 0 0x17200>; 4378 #interconnect-cells = <2>; 4379 qcom,bcm-voters = <&apps_bcm_voter>; 4380 }; 4381 }; 4382 4383 sound: sound { 4384 }; 4385 4386 thermal-zones { 4387 aoss0-thermal { 4388 polling-delay-passive = <0>; 4389 polling-delay = <0>; 4390 thermal-sensors = <&tsens0 0>; 4391 4392 trips { 4393 thermal-engine-config { 4394 temperature = <125000>; 4395 hysteresis = <1000>; 4396 type = "passive"; 4397 }; 4398 4399 reset-mon-cfg { 4400 temperature = <115000>; 4401 hysteresis = <5000>; 4402 type = "passive"; 4403 }; 4404 }; 4405 }; 4406 4407 cpuss0-thermal { 4408 polling-delay-passive = <0>; 4409 polling-delay = <0>; 4410 thermal-sensors = <&tsens0 1>; 4411 4412 trips { 4413 thermal-engine-config { 4414 temperature = <125000>; 4415 hysteresis = <1000>; 4416 type = "passive"; 4417 }; 4418 4419 reset-mon-cfg { 4420 temperature = <115000>; 4421 hysteresis = <5000>; 4422 type = "passive"; 4423 }; 4424 }; 4425 }; 4426 4427 cpuss1-thermal { 4428 polling-delay-passive = <0>; 4429 polling-delay = <0>; 4430 thermal-sensors = <&tsens0 2>; 4431 4432 trips { 4433 thermal-engine-config { 4434 temperature = <125000>; 4435 hysteresis = <1000>; 4436 type = "passive"; 4437 }; 4438 4439 reset-mon-cfg { 4440 temperature = <115000>; 4441 hysteresis = <5000>; 4442 type = "passive"; 4443 }; 4444 }; 4445 }; 4446 4447 cpuss3-thermal { 4448 polling-delay-passive = <0>; 4449 polling-delay = <0>; 4450 thermal-sensors = <&tsens0 3>; 4451 4452 trips { 4453 thermal-engine-config { 4454 temperature = <125000>; 4455 hysteresis = <1000>; 4456 type = "passive"; 4457 }; 4458 4459 reset-mon-cfg { 4460 temperature = <115000>; 4461 hysteresis = <5000>; 4462 type = "passive"; 4463 }; 4464 }; 4465 }; 4466 4467 cpuss4-thermal { 4468 polling-delay-passive = <0>; 4469 polling-delay = <0>; 4470 thermal-sensors = <&tsens0 4>; 4471 4472 trips { 4473 thermal-engine-config { 4474 temperature = <125000>; 4475 hysteresis = <1000>; 4476 type = "passive"; 4477 }; 4478 4479 reset-mon-cfg { 4480 temperature = <115000>; 4481 hysteresis = <5000>; 4482 type = "passive"; 4483 }; 4484 }; 4485 }; 4486 4487 cpu4-top-thermal { 4488 polling-delay-passive = <0>; 4489 polling-delay = <0>; 4490 thermal-sensors = <&tsens0 5>; 4491 4492 trips { 4493 cpu4_top_alert0: trip-point0 { 4494 temperature = <90000>; 4495 hysteresis = <2000>; 4496 type = "passive"; 4497 }; 4498 4499 cpu4_top_alert1: trip-point1 { 4500 temperature = <95000>; 4501 hysteresis = <2000>; 4502 type = "passive"; 4503 }; 4504 4505 cpu4_top_crit: cpu-crit { 4506 temperature = <110000>; 4507 hysteresis = <1000>; 4508 type = "critical"; 4509 }; 4510 }; 4511 }; 4512 4513 cpu4-bottom-thermal { 4514 polling-delay-passive = <0>; 4515 polling-delay = <0>; 4516 thermal-sensors = <&tsens0 6>; 4517 4518 trips { 4519 cpu4_bottom_alert0: trip-point0 { 4520 temperature = <90000>; 4521 hysteresis = <2000>; 4522 type = "passive"; 4523 }; 4524 4525 cpu4_bottom_alert1: trip-point1 { 4526 temperature = <95000>; 4527 hysteresis = <2000>; 4528 type = "passive"; 4529 }; 4530 4531 cpu4_bottom_crit: cpu-crit { 4532 temperature = <110000>; 4533 hysteresis = <1000>; 4534 type = "critical"; 4535 }; 4536 }; 4537 }; 4538 4539 cpu5-top-thermal { 4540 polling-delay-passive = <0>; 4541 polling-delay = <0>; 4542 thermal-sensors = <&tsens0 7>; 4543 4544 trips { 4545 cpu5_top_alert0: trip-point0 { 4546 temperature = <90000>; 4547 hysteresis = <2000>; 4548 type = "passive"; 4549 }; 4550 4551 cpu5_top_alert1: trip-point1 { 4552 temperature = <95000>; 4553 hysteresis = <2000>; 4554 type = "passive"; 4555 }; 4556 4557 cpu5_top_crit: cpu-crit { 4558 temperature = <110000>; 4559 hysteresis = <1000>; 4560 type = "critical"; 4561 }; 4562 }; 4563 }; 4564 4565 cpu5-bottom-thermal { 4566 polling-delay-passive = <0>; 4567 polling-delay = <0>; 4568 thermal-sensors = <&tsens0 8>; 4569 4570 trips { 4571 cpu5_bottom_alert0: trip-point0 { 4572 temperature = <90000>; 4573 hysteresis = <2000>; 4574 type = "passive"; 4575 }; 4576 4577 cpu5_bottom_alert1: trip-point1 { 4578 temperature = <95000>; 4579 hysteresis = <2000>; 4580 type = "passive"; 4581 }; 4582 4583 cpu5_bottom_crit: cpu-crit { 4584 temperature = <110000>; 4585 hysteresis = <1000>; 4586 type = "critical"; 4587 }; 4588 }; 4589 }; 4590 4591 cpu6-top-thermal { 4592 polling-delay-passive = <0>; 4593 polling-delay = <0>; 4594 thermal-sensors = <&tsens0 9>; 4595 4596 trips { 4597 cpu6_top_alert0: trip-point0 { 4598 temperature = <90000>; 4599 hysteresis = <2000>; 4600 type = "passive"; 4601 }; 4602 4603 cpu6_top_alert1: trip-point1 { 4604 temperature = <95000>; 4605 hysteresis = <2000>; 4606 type = "passive"; 4607 }; 4608 4609 cpu6_top_crit: cpu-crit { 4610 temperature = <110000>; 4611 hysteresis = <1000>; 4612 type = "critical"; 4613 }; 4614 }; 4615 }; 4616 4617 cpu6-bottom-thermal { 4618 polling-delay-passive = <0>; 4619 polling-delay = <0>; 4620 thermal-sensors = <&tsens0 10>; 4621 4622 trips { 4623 cpu6_bottom_alert0: trip-point0 { 4624 temperature = <90000>; 4625 hysteresis = <2000>; 4626 type = "passive"; 4627 }; 4628 4629 cpu6_bottom_alert1: trip-point1 { 4630 temperature = <95000>; 4631 hysteresis = <2000>; 4632 type = "passive"; 4633 }; 4634 4635 cpu6_bottom_crit: cpu-crit { 4636 temperature = <110000>; 4637 hysteresis = <1000>; 4638 type = "critical"; 4639 }; 4640 }; 4641 }; 4642 4643 cpu7-top-thermal { 4644 polling-delay-passive = <0>; 4645 polling-delay = <0>; 4646 thermal-sensors = <&tsens0 11>; 4647 4648 trips { 4649 cpu7_top_alert0: trip-point0 { 4650 temperature = <90000>; 4651 hysteresis = <2000>; 4652 type = "passive"; 4653 }; 4654 4655 cpu7_top_alert1: trip-point1 { 4656 temperature = <95000>; 4657 hysteresis = <2000>; 4658 type = "passive"; 4659 }; 4660 4661 cpu7_top_crit: cpu-crit { 4662 temperature = <110000>; 4663 hysteresis = <1000>; 4664 type = "critical"; 4665 }; 4666 }; 4667 }; 4668 4669 cpu7-middle-thermal { 4670 polling-delay-passive = <0>; 4671 polling-delay = <0>; 4672 thermal-sensors = <&tsens0 12>; 4673 4674 trips { 4675 cpu7_middle_alert0: trip-point0 { 4676 temperature = <90000>; 4677 hysteresis = <2000>; 4678 type = "passive"; 4679 }; 4680 4681 cpu7_middle_alert1: trip-point1 { 4682 temperature = <95000>; 4683 hysteresis = <2000>; 4684 type = "passive"; 4685 }; 4686 4687 cpu7_middle_crit: cpu-crit { 4688 temperature = <110000>; 4689 hysteresis = <1000>; 4690 type = "critical"; 4691 }; 4692 }; 4693 }; 4694 4695 cpu7-bottom-thermal { 4696 polling-delay-passive = <0>; 4697 polling-delay = <0>; 4698 thermal-sensors = <&tsens0 13>; 4699 4700 trips { 4701 cpu7_bottom_alert0: trip-point0 { 4702 temperature = <90000>; 4703 hysteresis = <2000>; 4704 type = "passive"; 4705 }; 4706 4707 cpu7_bottom_alert1: trip-point1 { 4708 temperature = <95000>; 4709 hysteresis = <2000>; 4710 type = "passive"; 4711 }; 4712 4713 cpu7_bottom_crit: cpu-crit { 4714 temperature = <110000>; 4715 hysteresis = <1000>; 4716 type = "critical"; 4717 }; 4718 }; 4719 }; 4720 4721 gpu-top-thermal { 4722 polling-delay-passive = <10>; 4723 polling-delay = <0>; 4724 thermal-sensors = <&tsens0 14>; 4725 4726 trips { 4727 thermal-engine-config { 4728 temperature = <125000>; 4729 hysteresis = <1000>; 4730 type = "passive"; 4731 }; 4732 4733 thermal-hal-config { 4734 temperature = <125000>; 4735 hysteresis = <1000>; 4736 type = "passive"; 4737 }; 4738 4739 reset-mon-cfg { 4740 temperature = <115000>; 4741 hysteresis = <5000>; 4742 type = "passive"; 4743 }; 4744 4745 gpu0_tj_cfg: tj-cfg { 4746 temperature = <95000>; 4747 hysteresis = <5000>; 4748 type = "passive"; 4749 }; 4750 }; 4751 }; 4752 4753 gpu-bottom-thermal { 4754 polling-delay-passive = <10>; 4755 polling-delay = <0>; 4756 thermal-sensors = <&tsens0 15>; 4757 4758 trips { 4759 thermal-engine-config { 4760 temperature = <125000>; 4761 hysteresis = <1000>; 4762 type = "passive"; 4763 }; 4764 4765 thermal-hal-config { 4766 temperature = <125000>; 4767 hysteresis = <1000>; 4768 type = "passive"; 4769 }; 4770 4771 reset-mon-cfg { 4772 temperature = <115000>; 4773 hysteresis = <5000>; 4774 type = "passive"; 4775 }; 4776 4777 gpu1_tj_cfg: tj-cfg { 4778 temperature = <95000>; 4779 hysteresis = <5000>; 4780 type = "passive"; 4781 }; 4782 }; 4783 }; 4784 4785 aoss1-thermal { 4786 polling-delay-passive = <0>; 4787 polling-delay = <0>; 4788 thermal-sensors = <&tsens1 0>; 4789 4790 trips { 4791 thermal-engine-config { 4792 temperature = <125000>; 4793 hysteresis = <1000>; 4794 type = "passive"; 4795 }; 4796 4797 reset-mon-cfg { 4798 temperature = <115000>; 4799 hysteresis = <5000>; 4800 type = "passive"; 4801 }; 4802 }; 4803 }; 4804 4805 cpu0-thermal { 4806 polling-delay-passive = <0>; 4807 polling-delay = <0>; 4808 thermal-sensors = <&tsens1 1>; 4809 4810 trips { 4811 cpu0_alert0: trip-point0 { 4812 temperature = <90000>; 4813 hysteresis = <2000>; 4814 type = "passive"; 4815 }; 4816 4817 cpu0_alert1: trip-point1 { 4818 temperature = <95000>; 4819 hysteresis = <2000>; 4820 type = "passive"; 4821 }; 4822 4823 cpu0_crit: cpu-crit { 4824 temperature = <110000>; 4825 hysteresis = <1000>; 4826 type = "critical"; 4827 }; 4828 }; 4829 }; 4830 4831 cpu1-thermal { 4832 polling-delay-passive = <0>; 4833 polling-delay = <0>; 4834 thermal-sensors = <&tsens1 2>; 4835 4836 trips { 4837 cpu1_alert0: trip-point0 { 4838 temperature = <90000>; 4839 hysteresis = <2000>; 4840 type = "passive"; 4841 }; 4842 4843 cpu1_alert1: trip-point1 { 4844 temperature = <95000>; 4845 hysteresis = <2000>; 4846 type = "passive"; 4847 }; 4848 4849 cpu1_crit: cpu-crit { 4850 temperature = <110000>; 4851 hysteresis = <1000>; 4852 type = "critical"; 4853 }; 4854 }; 4855 }; 4856 4857 cpu2-thermal { 4858 polling-delay-passive = <0>; 4859 polling-delay = <0>; 4860 thermal-sensors = <&tsens1 3>; 4861 4862 trips { 4863 cpu2_alert0: trip-point0 { 4864 temperature = <90000>; 4865 hysteresis = <2000>; 4866 type = "passive"; 4867 }; 4868 4869 cpu2_alert1: trip-point1 { 4870 temperature = <95000>; 4871 hysteresis = <2000>; 4872 type = "passive"; 4873 }; 4874 4875 cpu2_crit: cpu-crit { 4876 temperature = <110000>; 4877 hysteresis = <1000>; 4878 type = "critical"; 4879 }; 4880 }; 4881 }; 4882 4883 cpu3-thermal { 4884 polling-delay-passive = <0>; 4885 polling-delay = <0>; 4886 thermal-sensors = <&tsens1 4>; 4887 4888 trips { 4889 cpu3_alert0: trip-point0 { 4890 temperature = <90000>; 4891 hysteresis = <2000>; 4892 type = "passive"; 4893 }; 4894 4895 cpu3_alert1: trip-point1 { 4896 temperature = <95000>; 4897 hysteresis = <2000>; 4898 type = "passive"; 4899 }; 4900 4901 cpu3_crit: cpu-crit { 4902 temperature = <110000>; 4903 hysteresis = <1000>; 4904 type = "critical"; 4905 }; 4906 }; 4907 }; 4908 4909 cdsp0-thermal { 4910 polling-delay-passive = <10>; 4911 polling-delay = <0>; 4912 thermal-sensors = <&tsens1 5>; 4913 4914 trips { 4915 thermal-engine-config { 4916 temperature = <125000>; 4917 hysteresis = <1000>; 4918 type = "passive"; 4919 }; 4920 4921 thermal-hal-config { 4922 temperature = <125000>; 4923 hysteresis = <1000>; 4924 type = "passive"; 4925 }; 4926 4927 reset-mon-cfg { 4928 temperature = <115000>; 4929 hysteresis = <5000>; 4930 type = "passive"; 4931 }; 4932 4933 cdsp_0_config: junction-config { 4934 temperature = <95000>; 4935 hysteresis = <5000>; 4936 type = "passive"; 4937 }; 4938 }; 4939 }; 4940 4941 cdsp1-thermal { 4942 polling-delay-passive = <10>; 4943 polling-delay = <0>; 4944 thermal-sensors = <&tsens1 6>; 4945 4946 trips { 4947 thermal-engine-config { 4948 temperature = <125000>; 4949 hysteresis = <1000>; 4950 type = "passive"; 4951 }; 4952 4953 thermal-hal-config { 4954 temperature = <125000>; 4955 hysteresis = <1000>; 4956 type = "passive"; 4957 }; 4958 4959 reset-mon-cfg { 4960 temperature = <115000>; 4961 hysteresis = <5000>; 4962 type = "passive"; 4963 }; 4964 4965 cdsp_1_config: junction-config { 4966 temperature = <95000>; 4967 hysteresis = <5000>; 4968 type = "passive"; 4969 }; 4970 }; 4971 }; 4972 4973 cdsp2-thermal { 4974 polling-delay-passive = <10>; 4975 polling-delay = <0>; 4976 thermal-sensors = <&tsens1 7>; 4977 4978 trips { 4979 thermal-engine-config { 4980 temperature = <125000>; 4981 hysteresis = <1000>; 4982 type = "passive"; 4983 }; 4984 4985 thermal-hal-config { 4986 temperature = <125000>; 4987 hysteresis = <1000>; 4988 type = "passive"; 4989 }; 4990 4991 reset-mon-cfg { 4992 temperature = <115000>; 4993 hysteresis = <5000>; 4994 type = "passive"; 4995 }; 4996 4997 cdsp_2_config: junction-config { 4998 temperature = <95000>; 4999 hysteresis = <5000>; 5000 type = "passive"; 5001 }; 5002 }; 5003 }; 5004 5005 video-thermal { 5006 polling-delay-passive = <0>; 5007 polling-delay = <0>; 5008 thermal-sensors = <&tsens1 8>; 5009 5010 trips { 5011 thermal-engine-config { 5012 temperature = <125000>; 5013 hysteresis = <1000>; 5014 type = "passive"; 5015 }; 5016 5017 reset-mon-cfg { 5018 temperature = <115000>; 5019 hysteresis = <5000>; 5020 type = "passive"; 5021 }; 5022 }; 5023 }; 5024 5025 mem-thermal { 5026 polling-delay-passive = <10>; 5027 polling-delay = <0>; 5028 thermal-sensors = <&tsens1 9>; 5029 5030 trips { 5031 thermal-engine-config { 5032 temperature = <125000>; 5033 hysteresis = <1000>; 5034 type = "passive"; 5035 }; 5036 5037 ddr_config0: ddr0-config { 5038 temperature = <90000>; 5039 hysteresis = <5000>; 5040 type = "passive"; 5041 }; 5042 5043 reset-mon-cfg { 5044 temperature = <115000>; 5045 hysteresis = <5000>; 5046 type = "passive"; 5047 }; 5048 }; 5049 }; 5050 5051 modem0-thermal { 5052 polling-delay-passive = <0>; 5053 polling-delay = <0>; 5054 thermal-sensors = <&tsens1 10>; 5055 5056 trips { 5057 thermal-engine-config { 5058 temperature = <125000>; 5059 hysteresis = <1000>; 5060 type = "passive"; 5061 }; 5062 5063 mdmss0_config0: mdmss0-config0 { 5064 temperature = <102000>; 5065 hysteresis = <3000>; 5066 type = "passive"; 5067 }; 5068 5069 mdmss0_config1: mdmss0-config1 { 5070 temperature = <105000>; 5071 hysteresis = <3000>; 5072 type = "passive"; 5073 }; 5074 5075 reset-mon-cfg { 5076 temperature = <115000>; 5077 hysteresis = <5000>; 5078 type = "passive"; 5079 }; 5080 }; 5081 }; 5082 5083 modem1-thermal { 5084 polling-delay-passive = <0>; 5085 polling-delay = <0>; 5086 thermal-sensors = <&tsens1 11>; 5087 5088 trips { 5089 thermal-engine-config { 5090 temperature = <125000>; 5091 hysteresis = <1000>; 5092 type = "passive"; 5093 }; 5094 5095 mdmss1_config0: mdmss1-config0 { 5096 temperature = <102000>; 5097 hysteresis = <3000>; 5098 type = "passive"; 5099 }; 5100 5101 mdmss1_config1: mdmss1-config1 { 5102 temperature = <105000>; 5103 hysteresis = <3000>; 5104 type = "passive"; 5105 }; 5106 5107 reset-mon-cfg { 5108 temperature = <115000>; 5109 hysteresis = <5000>; 5110 type = "passive"; 5111 }; 5112 }; 5113 }; 5114 5115 modem2-thermal { 5116 polling-delay-passive = <0>; 5117 polling-delay = <0>; 5118 thermal-sensors = <&tsens1 12>; 5119 5120 trips { 5121 thermal-engine-config { 5122 temperature = <125000>; 5123 hysteresis = <1000>; 5124 type = "passive"; 5125 }; 5126 5127 mdmss2_config0: mdmss2-config0 { 5128 temperature = <102000>; 5129 hysteresis = <3000>; 5130 type = "passive"; 5131 }; 5132 5133 mdmss2_config1: mdmss2-config1 { 5134 temperature = <105000>; 5135 hysteresis = <3000>; 5136 type = "passive"; 5137 }; 5138 5139 reset-mon-cfg { 5140 temperature = <115000>; 5141 hysteresis = <5000>; 5142 type = "passive"; 5143 }; 5144 }; 5145 }; 5146 5147 modem3-thermal { 5148 polling-delay-passive = <0>; 5149 polling-delay = <0>; 5150 thermal-sensors = <&tsens1 13>; 5151 5152 trips { 5153 thermal-engine-config { 5154 temperature = <125000>; 5155 hysteresis = <1000>; 5156 type = "passive"; 5157 }; 5158 5159 mdmss3_config0: mdmss3-config0 { 5160 temperature = <102000>; 5161 hysteresis = <3000>; 5162 type = "passive"; 5163 }; 5164 5165 mdmss3_config1: mdmss3-config1 { 5166 temperature = <105000>; 5167 hysteresis = <3000>; 5168 type = "passive"; 5169 }; 5170 5171 reset-mon-cfg { 5172 temperature = <115000>; 5173 hysteresis = <5000>; 5174 type = "passive"; 5175 }; 5176 }; 5177 }; 5178 5179 camera0-thermal { 5180 polling-delay-passive = <0>; 5181 polling-delay = <0>; 5182 thermal-sensors = <&tsens1 14>; 5183 5184 trips { 5185 thermal-engine-config { 5186 temperature = <125000>; 5187 hysteresis = <1000>; 5188 type = "passive"; 5189 }; 5190 5191 reset-mon-cfg { 5192 temperature = <115000>; 5193 hysteresis = <5000>; 5194 type = "passive"; 5195 }; 5196 }; 5197 }; 5198 5199 camera1-thermal { 5200 polling-delay-passive = <0>; 5201 polling-delay = <0>; 5202 thermal-sensors = <&tsens1 15>; 5203 5204 trips { 5205 thermal-engine-config { 5206 temperature = <125000>; 5207 hysteresis = <1000>; 5208 type = "passive"; 5209 }; 5210 5211 reset-mon-cfg { 5212 temperature = <115000>; 5213 hysteresis = <5000>; 5214 type = "passive"; 5215 }; 5216 }; 5217 }; 5218 }; 5219 5220 timer { 5221 compatible = "arm,armv8-timer"; 5222 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5223 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5224 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5225 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5226 clock-frequency = <19200000>; 5227 }; 5228}; 5229