xref: /openbmc/qemu/hw/usb/hcd-ehci.h (revision 1c83f366)
1 /*
2  * QEMU USB EHCI Emulation
3  *
4  * This library is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU Lesser General Public
6  * License as published by the Free Software Foundation; either
7  * version 2.1 of the License, or (at your option) any later version.
8  *
9  * This library is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12  * Lesser General Public License for more details.
13  *
14  * You should have received a copy of the GNU Lesser General Public License
15  * along with this program; if not, see <http://www.gnu.org/licenses/>.
16  */
17 
18 #ifndef HW_USB_HCD_EHCI_H
19 #define HW_USB_HCD_EHCI_H
20 
21 #include "qemu/timer.h"
22 #include "hw/usb.h"
23 #include "sysemu/dma.h"
24 #include "hw/pci/pci_device.h"
25 #include "hw/sysbus.h"
26 
27 #ifndef EHCI_DEBUG
28 #define EHCI_DEBUG   0
29 #endif
30 
31 #if EHCI_DEBUG
32 #define DPRINTF printf
33 #else
34 #define DPRINTF(...)
35 #endif
36 
37 #define MMIO_SIZE        0x1000
38 #define CAPA_SIZE        0x10
39 
40 #define EHCI_PORTS       6        /* Max. Number of downstream ports */
41 
42 typedef struct EHCIPacket EHCIPacket;
43 typedef struct EHCIQueue EHCIQueue;
44 typedef struct EHCIState EHCIState;
45 
46 /*  EHCI spec version 1.0 Section 3.3
47  */
48 typedef struct EHCIitd {
49     uint32_t next;
50 
51     uint32_t transact[8];
52 #define ITD_XACT_ACTIVE          (1 << 31)
53 #define ITD_XACT_DBERROR         (1 << 30)
54 #define ITD_XACT_BABBLE          (1 << 29)
55 #define ITD_XACT_XACTERR         (1 << 28)
56 #define ITD_XACT_LENGTH_MASK     0x0fff0000
57 #define ITD_XACT_LENGTH_SH       16
58 #define ITD_XACT_IOC             (1 << 15)
59 #define ITD_XACT_PGSEL_MASK      0x00007000
60 #define ITD_XACT_PGSEL_SH        12
61 #define ITD_XACT_OFFSET_MASK     0x00000fff
62 
63     uint32_t bufptr[7];
64 #define ITD_BUFPTR_MASK          0xfffff000
65 #define ITD_BUFPTR_SH            12
66 #define ITD_BUFPTR_EP_MASK       0x00000f00
67 #define ITD_BUFPTR_EP_SH         8
68 #define ITD_BUFPTR_DEVADDR_MASK  0x0000007f
69 #define ITD_BUFPTR_DEVADDR_SH    0
70 #define ITD_BUFPTR_DIRECTION     (1 << 11)
71 #define ITD_BUFPTR_MAXPKT_MASK   0x000007ff
72 #define ITD_BUFPTR_MAXPKT_SH     0
73 #define ITD_BUFPTR_MULT_MASK     0x00000003
74 #define ITD_BUFPTR_MULT_SH       0
75 } EHCIitd;
76 
77 /*  EHCI spec version 1.0 Section 3.4
78  */
79 typedef struct EHCIsitd {
80     uint32_t next;                  /* Standard next link pointer */
81     uint32_t epchar;
82 #define SITD_EPCHAR_IO              (1 << 31)
83 #define SITD_EPCHAR_PORTNUM_MASK    0x7f000000
84 #define SITD_EPCHAR_PORTNUM_SH      24
85 #define SITD_EPCHAR_HUBADD_MASK     0x007f0000
86 #define SITD_EPCHAR_HUBADDR_SH      16
87 #define SITD_EPCHAR_EPNUM_MASK      0x00000f00
88 #define SITD_EPCHAR_EPNUM_SH        8
89 #define SITD_EPCHAR_DEVADDR_MASK    0x0000007f
90 
91     uint32_t uframe;
92 #define SITD_UFRAME_CMASK_MASK      0x0000ff00
93 #define SITD_UFRAME_CMASK_SH        8
94 #define SITD_UFRAME_SMASK_MASK      0x000000ff
95 
96     uint32_t results;
97 #define SITD_RESULTS_IOC              (1 << 31)
98 #define SITD_RESULTS_PGSEL            (1 << 30)
99 #define SITD_RESULTS_TBYTES_MASK      0x03ff0000
100 #define SITD_RESULTS_TYBYTES_SH       16
101 #define SITD_RESULTS_CPROGMASK_MASK   0x0000ff00
102 #define SITD_RESULTS_CPROGMASK_SH     8
103 #define SITD_RESULTS_ACTIVE           (1 << 7)
104 #define SITD_RESULTS_ERR              (1 << 6)
105 #define SITD_RESULTS_DBERR            (1 << 5)
106 #define SITD_RESULTS_BABBLE           (1 << 4)
107 #define SITD_RESULTS_XACTERR          (1 << 3)
108 #define SITD_RESULTS_MISSEDUF         (1 << 2)
109 #define SITD_RESULTS_SPLITXSTATE      (1 << 1)
110 
111     uint32_t bufptr[2];
112 #define SITD_BUFPTR_MASK              0xfffff000
113 #define SITD_BUFPTR_CURROFF_MASK      0x00000fff
114 #define SITD_BUFPTR_TPOS_MASK         0x00000018
115 #define SITD_BUFPTR_TPOS_SH           3
116 #define SITD_BUFPTR_TCNT_MASK         0x00000007
117 
118     uint32_t backptr;                 /* Standard next link pointer */
119 } EHCIsitd;
120 
121 /*  EHCI spec version 1.0 Section 3.5
122  */
123 typedef struct EHCIqtd {
124     uint32_t next;                    /* Standard next link pointer */
125     uint32_t altnext;                 /* Standard next link pointer */
126     uint32_t token;
127 #define QTD_TOKEN_DTOGGLE             (1 << 31)
128 #define QTD_TOKEN_TBYTES_MASK         0x7fff0000
129 #define QTD_TOKEN_TBYTES_SH           16
130 #define QTD_TOKEN_IOC                 (1 << 15)
131 #define QTD_TOKEN_CPAGE_MASK          0x00007000
132 #define QTD_TOKEN_CPAGE_SH            12
133 #define QTD_TOKEN_CERR_MASK           0x00000c00
134 #define QTD_TOKEN_CERR_SH             10
135 #define QTD_TOKEN_PID_MASK            0x00000300
136 #define QTD_TOKEN_PID_SH              8
137 #define QTD_TOKEN_ACTIVE              (1 << 7)
138 #define QTD_TOKEN_HALT                (1 << 6)
139 #define QTD_TOKEN_DBERR               (1 << 5)
140 #define QTD_TOKEN_BABBLE              (1 << 4)
141 #define QTD_TOKEN_XACTERR             (1 << 3)
142 #define QTD_TOKEN_MISSEDUF            (1 << 2)
143 #define QTD_TOKEN_SPLITXSTATE         (1 << 1)
144 #define QTD_TOKEN_PING                (1 << 0)
145 
146     uint32_t bufptr[5];               /* Standard buffer pointer */
147 #define QTD_BUFPTR_MASK               0xfffff000
148 #define QTD_BUFPTR_SH                 12
149 } EHCIqtd;
150 
151 /*  EHCI spec version 1.0 Section 3.6
152  */
153 typedef struct EHCIqh {
154     uint32_t next;                    /* Standard next link pointer */
155 
156     /* endpoint characteristics */
157     uint32_t epchar;
158 #define QH_EPCHAR_RL_MASK             0xf0000000
159 #define QH_EPCHAR_RL_SH               28
160 #define QH_EPCHAR_C                   (1 << 27)
161 #define QH_EPCHAR_MPLEN_MASK          0x07FF0000
162 #define QH_EPCHAR_MPLEN_SH            16
163 #define QH_EPCHAR_H                   (1 << 15)
164 #define QH_EPCHAR_DTC                 (1 << 14)
165 #define QH_EPCHAR_EPS_MASK            0x00003000
166 #define QH_EPCHAR_EPS_SH              12
167 #define EHCI_QH_EPS_FULL              0
168 #define EHCI_QH_EPS_LOW               1
169 #define EHCI_QH_EPS_HIGH              2
170 #define EHCI_QH_EPS_RESERVED          3
171 
172 #define QH_EPCHAR_EP_MASK             0x00000f00
173 #define QH_EPCHAR_EP_SH               8
174 #define QH_EPCHAR_I                   (1 << 7)
175 #define QH_EPCHAR_DEVADDR_MASK        0x0000007f
176 #define QH_EPCHAR_DEVADDR_SH          0
177 
178     /* endpoint capabilities */
179     uint32_t epcap;
180 #define QH_EPCAP_MULT_MASK            0xc0000000
181 #define QH_EPCAP_MULT_SH              30
182 #define QH_EPCAP_PORTNUM_MASK         0x3f800000
183 #define QH_EPCAP_PORTNUM_SH           23
184 #define QH_EPCAP_HUBADDR_MASK         0x007f0000
185 #define QH_EPCAP_HUBADDR_SH           16
186 #define QH_EPCAP_CMASK_MASK           0x0000ff00
187 #define QH_EPCAP_CMASK_SH             8
188 #define QH_EPCAP_SMASK_MASK           0x000000ff
189 #define QH_EPCAP_SMASK_SH             0
190 
191     uint32_t current_qtd;             /* Standard next link pointer */
192     uint32_t next_qtd;                /* Standard next link pointer */
193     uint32_t altnext_qtd;
194 #define QH_ALTNEXT_NAKCNT_MASK        0x0000001e
195 #define QH_ALTNEXT_NAKCNT_SH          1
196 
197     uint32_t token;                   /* Same as QTD token */
198     uint32_t bufptr[5];               /* Standard buffer pointer */
199 #define BUFPTR_CPROGMASK_MASK         0x000000ff
200 #define BUFPTR_FRAMETAG_MASK          0x0000001f
201 #define BUFPTR_SBYTES_MASK            0x00000fe0
202 #define BUFPTR_SBYTES_SH              5
203 } EHCIqh;
204 
205 /*  EHCI spec version 1.0 Section 3.7
206  */
207 typedef struct EHCIfstn {
208     uint32_t next;                    /* Standard next link pointer */
209     uint32_t backptr;                 /* Standard next link pointer */
210 } EHCIfstn;
211 
212 enum async_state {
213     EHCI_ASYNC_NONE = 0,
214     EHCI_ASYNC_INITIALIZED,
215     EHCI_ASYNC_INFLIGHT,
216     EHCI_ASYNC_FINISHED,
217 };
218 
219 struct EHCIPacket {
220     EHCIQueue *queue;
221     QTAILQ_ENTRY(EHCIPacket) next;
222 
223     EHCIqtd qtd;           /* copy of current QTD (being worked on) */
224     uint32_t qtdaddr;      /* address QTD read from                 */
225 
226     USBPacket packet;
227     QEMUSGList sgl;
228     int pid;
229     enum async_state async;
230 };
231 
232 struct EHCIQueue {
233     EHCIState *ehci;
234     QTAILQ_ENTRY(EHCIQueue) next;
235     uint32_t seen;
236     uint64_t ts;
237     int async;
238     int transact_ctr;
239 
240     /* cached data from guest - needs to be flushed
241      * when guest removes an entry (doorbell, handshake sequence)
242      */
243     EHCIqh qh;             /* copy of current QH (being worked on) */
244     uint32_t qhaddr;       /* address QH read from                 */
245     uint32_t qtdaddr;      /* address QTD read from                */
246     int last_pid;          /* pid of last packet executed          */
247     USBDevice *dev;
248     QTAILQ_HEAD(, EHCIPacket) packets;
249 };
250 
251 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
252 
253 struct EHCIState {
254     USBBus bus;
255     DeviceState *device;
256     qemu_irq irq;
257     MemoryRegion mem;
258     AddressSpace *as;
259     MemoryRegion mem_caps;
260     MemoryRegion mem_opreg;
261     MemoryRegion mem_ports;
262     int companion_count;
263     bool companion_enable;
264     uint16_t capsbase;
265     uint16_t opregbase;
266     uint16_t portscbase;
267     uint16_t portnr;
268 
269     /* properties */
270     uint32_t maxframes;
271 
272     /*
273      *  EHCI spec version 1.0 Section 2.3
274      *  Host Controller Operational Registers
275      */
276     uint8_t caps[CAPA_SIZE];
277     union {
278         uint32_t opreg[0x44/sizeof(uint32_t)];
279         struct {
280             uint32_t usbcmd;
281             uint32_t usbsts;
282             uint32_t usbintr;
283             uint32_t frindex;
284             uint32_t ctrldssegment;
285             uint32_t periodiclistbase;
286             uint32_t asynclistaddr;
287             uint32_t notused[9];
288             uint32_t configflag;
289         };
290     };
291     uint32_t portsc[EHCI_PORTS];
292 
293     /*
294      *  Internal states, shadow registers, etc
295      */
296     QEMUTimer *frame_timer;
297     QEMUBH *async_bh;
298     bool working;
299     uint32_t astate;         /* Current state in asynchronous schedule */
300     uint32_t pstate;         /* Current state in periodic schedule     */
301     USBPort ports[EHCI_PORTS];
302     USBPort *companion_ports[EHCI_PORTS];
303     uint32_t usbsts_pending;
304     uint32_t usbsts_frindex;
305     EHCIQueueHead aqueues;
306     EHCIQueueHead pqueues;
307 
308     /* which address to look at next */
309     uint32_t a_fetch_addr;
310     uint32_t p_fetch_addr;
311 
312     USBPacket ipacket;
313     QEMUSGList isgl;
314 
315     uint64_t last_run_ns;
316     uint32_t async_stepdown;
317     uint32_t periodic_sched_active;
318     bool int_req_by_async;
319     VMChangeStateEntry *vmstate;
320 };
321 
322 extern const VMStateDescription vmstate_ehci;
323 
324 void usb_ehci_init(EHCIState *s, DeviceState *dev);
325 void usb_ehci_finalize(EHCIState *s);
326 void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp);
327 void usb_ehci_unrealize(EHCIState *s, DeviceState *dev);
328 void ehci_reset(void *opaque);
329 
330 #define TYPE_PCI_EHCI "pci-ehci-usb"
331 OBJECT_DECLARE_SIMPLE_TYPE(EHCIPCIState, PCI_EHCI)
332 
333 struct EHCIPCIState {
334     /*< private >*/
335     PCIDevice pcidev;
336     /*< public >*/
337 
338     EHCIState ehci;
339 };
340 
341 
342 #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
343 #define TYPE_PLATFORM_EHCI "platform-ehci-usb"
344 #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
345 #define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
346 #define TYPE_NPCM7XX_EHCI "npcm7xx-ehci-usb"
347 #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
348 #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
349 #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
350 
351 OBJECT_DECLARE_TYPE(EHCISysBusState, SysBusEHCIClass, SYS_BUS_EHCI)
352 
353 struct EHCISysBusState {
354     /*< private >*/
355     SysBusDevice parent_obj;
356     /*< public >*/
357 
358     EHCIState ehci;
359 };
360 
361 struct SysBusEHCIClass {
362     /*< private >*/
363     SysBusDeviceClass parent_class;
364     /*< public >*/
365 
366     uint16_t capsbase;
367     uint16_t opregbase;
368     uint16_t portscbase;
369     uint16_t portnr;
370 };
371 
372 OBJECT_DECLARE_SIMPLE_TYPE(FUSBH200EHCIState, FUSBH200_EHCI)
373 
374 struct FUSBH200EHCIState {
375     /*< private >*/
376     EHCISysBusState parent_obj;
377     /*< public >*/
378 
379     MemoryRegion mem_vendor;
380 };
381 
382 #endif
383