1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define EDSA_HLEN 8 22 #define MV88E6XXX_N_FID 4096 23 #define MV88E6XXX_N_SID 64 24 25 #define MV88E6XXX_FID_STANDALONE 0 26 #define MV88E6XXX_FID_BRIDGED 1 27 28 /* PVT limits for 4-bit port and 5-bit switch */ 29 #define MV88E6XXX_MAX_PVT_SWITCHES 32 30 #define MV88E6XXX_MAX_PVT_PORTS 16 31 #define MV88E6XXX_MAX_PVT_ENTRIES \ 32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 33 34 #define MV88E6XXX_MAX_GPIO 16 35 36 enum mv88e6xxx_egress_mode { 37 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 38 MV88E6XXX_EGRESS_MODE_UNTAGGED, 39 MV88E6XXX_EGRESS_MODE_TAGGED, 40 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 41 }; 42 43 enum mv88e6xxx_egress_direction { 44 MV88E6XXX_EGRESS_DIR_INGRESS, 45 MV88E6XXX_EGRESS_DIR_EGRESS, 46 }; 47 48 enum mv88e6xxx_frame_mode { 49 MV88E6XXX_FRAME_MODE_NORMAL, 50 MV88E6XXX_FRAME_MODE_DSA, 51 MV88E6XXX_FRAME_MODE_PROVIDER, 52 MV88E6XXX_FRAME_MODE_ETHERTYPE, 53 }; 54 55 /* List of supported models */ 56 enum mv88e6xxx_model { 57 MV88E6020, 58 MV88E6071, 59 MV88E6085, 60 MV88E6095, 61 MV88E6097, 62 MV88E6123, 63 MV88E6131, 64 MV88E6141, 65 MV88E6161, 66 MV88E6165, 67 MV88E6171, 68 MV88E6172, 69 MV88E6175, 70 MV88E6176, 71 MV88E6185, 72 MV88E6190, 73 MV88E6190X, 74 MV88E6191, 75 MV88E6191X, 76 MV88E6193X, 77 MV88E6220, 78 MV88E6240, 79 MV88E6250, 80 MV88E6290, 81 MV88E6320, 82 MV88E6321, 83 MV88E6341, 84 MV88E6350, 85 MV88E6351, 86 MV88E6352, 87 MV88E6361, 88 MV88E6390, 89 MV88E6390X, 90 MV88E6393X, 91 }; 92 93 enum mv88e6xxx_family { 94 MV88E6XXX_FAMILY_NONE, 95 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 96 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 97 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 98 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 99 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 100 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */ 101 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 102 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 103 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 104 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 105 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 106 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */ 107 }; 108 109 /** 110 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 111 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 112 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 113 * egressing FORWARD frames with an EDSA 114 * tag is reserved for future use, but 115 * empirical data shows that this mode 116 * is supported. 117 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 118 */ 119 enum mv88e6xxx_edsa_support { 120 MV88E6XXX_EDSA_UNSUPPORTED = 0, 121 MV88E6XXX_EDSA_UNDOCUMENTED, 122 MV88E6XXX_EDSA_SUPPORTED, 123 }; 124 125 struct mv88e6xxx_ops; 126 127 struct mv88e6xxx_info { 128 enum mv88e6xxx_family family; 129 u16 prod_num; 130 const char *name; 131 unsigned int num_databases; 132 unsigned int num_macs; 133 unsigned int num_ports; 134 unsigned int num_internal_phys; 135 unsigned int num_gpio; 136 unsigned int max_vid; 137 unsigned int max_sid; 138 unsigned int port_base_addr; 139 unsigned int phy_base_addr; 140 unsigned int global1_addr; 141 unsigned int global2_addr; 142 unsigned int age_time_coeff; 143 unsigned int g1_irqs; 144 unsigned int g2_irqs; 145 bool pvt; 146 147 /* Mark certain ports as invalid. This is required for example for the 148 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 149 * ports 2-4 are not routet to pins. 150 */ 151 unsigned int invalid_port_mask; 152 /* Multi-chip Addressing Mode. 153 * Some chips respond to only 2 registers of its own SMI device address 154 * when it is non-zero, and use indirect access to internal registers. 155 */ 156 bool multi_chip; 157 /* Dual-chip Addressing Mode 158 * Some chips respond to only half of the 32 SMI addresses, 159 * allowing two to coexist on the same SMI interface. 160 */ 161 bool dual_chip; 162 163 enum mv88e6xxx_edsa_support edsa_support; 164 165 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 166 * operation. 0 means that the ATU Move operation is not supported. 167 */ 168 u8 atu_move_port_mask; 169 const struct mv88e6xxx_ops *ops; 170 171 /* Supports PTP */ 172 bool ptp_support; 173 174 /* Internal PHY start index. 0 means that internal PHYs range starts at 175 * port 0, 1 means internal PHYs range starts at port 1, etc 176 */ 177 unsigned int internal_phys_offset; 178 }; 179 180 struct mv88e6xxx_atu_entry { 181 u8 state; 182 bool trunk; 183 u16 portvec; 184 u8 mac[ETH_ALEN]; 185 }; 186 187 struct mv88e6xxx_vtu_entry { 188 u16 vid; 189 u16 fid; 190 u8 sid; 191 bool valid; 192 bool policy; 193 u8 member[DSA_MAX_PORTS]; 194 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 195 }; 196 197 struct mv88e6xxx_stu_entry { 198 u8 sid; 199 bool valid; 200 u8 state[DSA_MAX_PORTS]; 201 }; 202 203 struct mv88e6xxx_bus_ops; 204 struct mv88e6xxx_irq_ops; 205 struct mv88e6xxx_gpio_ops; 206 struct mv88e6xxx_avb_ops; 207 struct mv88e6xxx_ptp_ops; 208 struct mv88e6xxx_pcs_ops; 209 struct mv88e6xxx_cc_coeffs; 210 211 struct mv88e6xxx_irq { 212 u16 masked; 213 struct irq_chip chip; 214 struct irq_domain *domain; 215 int nirqs; 216 }; 217 218 /* state flags for mv88e6xxx_port_hwtstamp::state */ 219 enum { 220 MV88E6XXX_HWTSTAMP_ENABLED, 221 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 222 }; 223 224 struct mv88e6xxx_port_hwtstamp { 225 /* Port index */ 226 int port_id; 227 228 /* Timestamping state */ 229 unsigned long state; 230 231 /* Resources for receive timestamping */ 232 struct sk_buff_head rx_queue; 233 struct sk_buff_head rx_queue2; 234 235 /* Resources for transmit timestamping */ 236 unsigned long tx_tstamp_start; 237 struct sk_buff *tx_skb; 238 u16 tx_seq_id; 239 240 /* Current timestamp configuration */ 241 struct hwtstamp_config tstamp_config; 242 }; 243 244 enum mv88e6xxx_policy_mapping { 245 MV88E6XXX_POLICY_MAPPING_DA, 246 MV88E6XXX_POLICY_MAPPING_SA, 247 MV88E6XXX_POLICY_MAPPING_VTU, 248 MV88E6XXX_POLICY_MAPPING_ETYPE, 249 MV88E6XXX_POLICY_MAPPING_PPPOE, 250 MV88E6XXX_POLICY_MAPPING_VBAS, 251 MV88E6XXX_POLICY_MAPPING_OPT82, 252 MV88E6XXX_POLICY_MAPPING_UDP, 253 }; 254 255 enum mv88e6xxx_policy_action { 256 MV88E6XXX_POLICY_ACTION_NORMAL, 257 MV88E6XXX_POLICY_ACTION_MIRROR, 258 MV88E6XXX_POLICY_ACTION_TRAP, 259 MV88E6XXX_POLICY_ACTION_DISCARD, 260 }; 261 262 struct mv88e6xxx_policy { 263 enum mv88e6xxx_policy_mapping mapping; 264 enum mv88e6xxx_policy_action action; 265 struct ethtool_rx_flow_spec fs; 266 u8 addr[ETH_ALEN]; 267 int port; 268 u16 vid; 269 }; 270 271 struct mv88e6xxx_vlan { 272 u16 vid; 273 bool valid; 274 }; 275 276 struct mv88e6xxx_port { 277 struct mv88e6xxx_chip *chip; 278 int port; 279 struct mv88e6xxx_vlan bridge_pvid; 280 u64 serdes_stats[2]; 281 u64 atu_member_violation; 282 u64 atu_miss_violation; 283 u64 atu_full_violation; 284 u64 vtu_member_violation; 285 u64 vtu_miss_violation; 286 phy_interface_t interface; 287 u8 cmode; 288 bool mirror_ingress; 289 bool mirror_egress; 290 struct devlink_region *region; 291 void *pcs_private; 292 293 /* MacAuth Bypass control flag */ 294 bool mab; 295 }; 296 297 enum mv88e6xxx_region_id { 298 MV88E6XXX_REGION_GLOBAL1 = 0, 299 MV88E6XXX_REGION_GLOBAL2, 300 MV88E6XXX_REGION_ATU, 301 MV88E6XXX_REGION_VTU, 302 MV88E6XXX_REGION_STU, 303 MV88E6XXX_REGION_PVT, 304 305 _MV88E6XXX_REGION_MAX, 306 }; 307 308 struct mv88e6xxx_region_priv { 309 enum mv88e6xxx_region_id id; 310 }; 311 312 struct mv88e6xxx_mst { 313 struct list_head node; 314 315 refcount_t refcnt; 316 struct net_device *br; 317 u16 msti; 318 319 struct mv88e6xxx_stu_entry stu; 320 }; 321 322 struct mv88e6xxx_chip { 323 const struct mv88e6xxx_info *info; 324 325 /* Currently configured tagging protocol */ 326 enum dsa_tag_protocol tag_protocol; 327 328 /* The dsa_switch this private structure is related to */ 329 struct dsa_switch *ds; 330 331 /* The device this structure is associated to */ 332 struct device *dev; 333 334 /* This mutex protects the access to the switch registers */ 335 struct mutex reg_lock; 336 337 /* The MII bus and the address on the bus that is used to 338 * communication with the switch 339 */ 340 const struct mv88e6xxx_bus_ops *smi_ops; 341 struct mii_bus *bus; 342 int sw_addr; 343 344 /* Handles automatic disabling and re-enabling of the PHY 345 * polling unit. 346 */ 347 const struct mv88e6xxx_bus_ops *phy_ops; 348 struct mutex ppu_mutex; 349 int ppu_disabled; 350 struct work_struct ppu_work; 351 struct timer_list ppu_timer; 352 353 /* This mutex serialises access to the statistics unit. 354 * Hold this mutex over snapshot + dump sequences. 355 */ 356 struct mutex stats_mutex; 357 358 /* A switch may have a GPIO line tied to its reset pin. Parse 359 * this from the device tree, and use it before performing 360 * switch soft reset. 361 */ 362 struct gpio_desc *reset; 363 364 /* set to size of eeprom if supported by the switch */ 365 u32 eeprom_len; 366 367 /* List of mdio busses */ 368 struct list_head mdios; 369 370 /* Policy Control List IDs and rules */ 371 struct idr policies; 372 373 /* There can be two interrupt controllers, which are chained 374 * off a GPIO as interrupt source 375 */ 376 struct mv88e6xxx_irq g1_irq; 377 struct mv88e6xxx_irq g2_irq; 378 int irq; 379 char irq_name[64]; 380 int device_irq; 381 char device_irq_name[64]; 382 int watchdog_irq; 383 char watchdog_irq_name[64]; 384 385 int atu_prob_irq; 386 char atu_prob_irq_name[64]; 387 int vtu_prob_irq; 388 char vtu_prob_irq_name[64]; 389 struct kthread_worker *kworker; 390 struct kthread_delayed_work irq_poll_work; 391 392 /* GPIO resources */ 393 u8 gpio_data[2]; 394 395 /* This cyclecounter abstracts the switch PTP time. 396 * reg_lock must be held for any operation that read()s. 397 */ 398 struct cyclecounter tstamp_cc; 399 struct timecounter tstamp_tc; 400 struct delayed_work overflow_work; 401 const struct mv88e6xxx_cc_coeffs *cc_coeffs; 402 403 struct ptp_clock *ptp_clock; 404 struct ptp_clock_info ptp_clock_info; 405 struct delayed_work tai_event_work; 406 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 407 u16 trig_config; 408 u16 evcap_config; 409 u16 enable_count; 410 411 /* Current ingress and egress monitor ports */ 412 int egress_dest_port; 413 int ingress_dest_port; 414 415 /* Per-port timestamping resources. */ 416 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 417 418 /* Array of port structures. */ 419 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 420 421 /* devlink regions */ 422 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 423 424 /* Bridge MST to SID mappings */ 425 struct list_head msts; 426 }; 427 428 struct mv88e6xxx_bus_ops { 429 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 430 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 431 int (*init)(struct mv88e6xxx_chip *chip); 432 }; 433 434 struct mv88e6xxx_mdio_bus { 435 struct mii_bus *bus; 436 struct mv88e6xxx_chip *chip; 437 struct list_head list; 438 bool external; 439 }; 440 441 struct mv88e6xxx_ops { 442 /* Switch Setup Errata, called early in the switch setup to 443 * allow any errata actions to be performed 444 */ 445 int (*setup_errata)(struct mv88e6xxx_chip *chip); 446 447 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 448 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 449 450 /* Ingress Rate Limit unit (IRL) operations */ 451 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 452 453 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 454 struct ethtool_eeprom *eeprom, u8 *data); 455 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 456 struct ethtool_eeprom *eeprom, u8 *data); 457 458 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 459 460 int (*phy_read)(struct mv88e6xxx_chip *chip, 461 struct mii_bus *bus, 462 int addr, int reg, u16 *val); 463 int (*phy_write)(struct mv88e6xxx_chip *chip, 464 struct mii_bus *bus, 465 int addr, int reg, u16 val); 466 467 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 468 struct mii_bus *bus, 469 int addr, int devad, int reg, u16 *val); 470 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 471 struct mii_bus *bus, 472 int addr, int devad, int reg, u16 val); 473 474 /* Priority Override Table operations */ 475 int (*pot_clear)(struct mv88e6xxx_chip *chip); 476 477 /* PHY Polling Unit (PPU) operations */ 478 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 479 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 480 481 /* Additional handlers to run before and after hard reset, to make sure 482 * that the switch and EEPROM are in a good state. 483 */ 484 int (*hardware_reset_pre)(struct mv88e6xxx_chip *chip); 485 int (*hardware_reset_post)(struct mv88e6xxx_chip *chip); 486 487 /* Switch Software Reset */ 488 int (*reset)(struct mv88e6xxx_chip *chip); 489 490 /* RGMII Receive/Transmit Timing Control 491 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 492 */ 493 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 494 phy_interface_t mode); 495 496 #define LINK_FORCED_DOWN 0 497 #define LINK_FORCED_UP 1 498 #define LINK_UNFORCED -2 499 500 /* Port's MAC link state 501 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 502 * or LINK_UNFORCED for normal link detection. 503 */ 504 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 505 506 /* Synchronise the port link state with that of the SERDES 507 */ 508 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 509 510 #define PAUSE_ON 1 511 #define PAUSE_OFF 0 512 513 /* Enable/disable sending Pause */ 514 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 515 int pause); 516 517 #define SPEED_UNFORCED -2 518 #define DUPLEX_UNFORCED -2 519 520 /* Port's MAC speed (in Mbps) and MAC duplex mode 521 * 522 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 523 * Use SPEED_UNFORCED for normal detection. 524 * 525 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 526 * or DUPLEX_UNFORCED for normal duplex detection. 527 */ 528 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 529 int speed, int duplex); 530 531 /* What interface mode should be used for maximum speed? */ 532 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip, 533 int port); 534 535 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 536 537 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 538 enum mv88e6xxx_policy_mapping mapping, 539 enum mv88e6xxx_policy_action action); 540 541 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 542 enum mv88e6xxx_frame_mode mode); 543 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 544 bool unicast); 545 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 546 bool multicast); 547 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 548 u16 etype); 549 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 550 size_t size); 551 552 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 553 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 554 u8 out); 555 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 556 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 557 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 558 559 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 560 * Some chips allow this to be configured on specific ports. 561 */ 562 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 563 phy_interface_t mode); 564 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 565 566 /* Some devices have a per port register indicating what is 567 * the upstream port this port should forward to. 568 */ 569 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 570 int upstream_port); 571 572 /* Snapshot the statistics for a port. The statistics can then 573 * be read back a leisure but still with a consistent view. 574 */ 575 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 576 577 /* Set the histogram mode for statistics, when the control registers 578 * are separated out of the STATS_OP register. 579 */ 580 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 581 582 /* Return the number of strings describing statistics */ 583 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 584 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 585 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 586 uint64_t *data); 587 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 588 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 589 enum mv88e6xxx_egress_direction direction, 590 int port); 591 592 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 593 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 594 595 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 596 597 const struct mv88e6xxx_irq_ops *watchdog_ops; 598 599 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 600 601 /* SERDES lane mapping */ 602 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 603 604 /* SERDES interrupt handling */ 605 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 606 int port); 607 608 /* Statistics from the SERDES interface */ 609 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 610 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 611 uint8_t *data); 612 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 613 uint64_t *data); 614 615 /* SERDES registers for ethtool */ 616 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 617 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 618 void *_p); 619 620 /* SERDES SGMII/Fiber Output Amplitude */ 621 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 622 int val); 623 624 /* Address Translation Unit operations */ 625 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 626 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 627 628 /* VLAN Translation Unit operations */ 629 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 630 struct mv88e6xxx_vtu_entry *entry); 631 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 632 struct mv88e6xxx_vtu_entry *entry); 633 634 /* Spanning Tree Unit operations */ 635 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 636 struct mv88e6xxx_stu_entry *entry); 637 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 638 struct mv88e6xxx_stu_entry *entry); 639 640 /* GPIO operations */ 641 const struct mv88e6xxx_gpio_ops *gpio_ops; 642 643 /* Interface to the AVB/PTP registers */ 644 const struct mv88e6xxx_avb_ops *avb_ops; 645 646 /* Remote Management Unit operations */ 647 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 648 649 /* Precision Time Protocol operations */ 650 const struct mv88e6xxx_ptp_ops *ptp_ops; 651 652 /* Phylink */ 653 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 654 struct phylink_config *config); 655 656 const struct mv88e6xxx_pcs_ops *pcs_ops; 657 658 /* Max Frame Size */ 659 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 660 }; 661 662 struct mv88e6xxx_irq_ops { 663 /* Action to be performed when the interrupt happens */ 664 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 665 /* Setup the hardware to generate the interrupt */ 666 int (*irq_setup)(struct mv88e6xxx_chip *chip); 667 /* Reset the hardware to stop generating the interrupt */ 668 void (*irq_free)(struct mv88e6xxx_chip *chip); 669 }; 670 671 struct mv88e6xxx_gpio_ops { 672 /* Get/set data on GPIO pin */ 673 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 674 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 675 int value); 676 677 /* get/set GPIO direction */ 678 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 679 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 680 bool input); 681 682 /* get/set GPIO pin control */ 683 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 684 int *func); 685 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 686 int func); 687 }; 688 689 struct mv88e6xxx_avb_ops { 690 /* Access port-scoped Precision Time Protocol registers */ 691 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 692 u16 *data, int len); 693 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 694 u16 data); 695 696 /* Access global Precision Time Protocol registers */ 697 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 698 int len); 699 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 700 701 /* Access global Time Application Interface registers */ 702 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 703 int len); 704 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 705 }; 706 707 struct mv88e6xxx_ptp_ops { 708 u64 (*clock_read)(const struct cyclecounter *cc); 709 int (*ptp_enable)(struct ptp_clock_info *ptp, 710 struct ptp_clock_request *rq, int on); 711 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 712 enum ptp_pin_function func, unsigned int chan); 713 void (*event_work)(struct work_struct *ugly); 714 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 715 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 716 int (*global_enable)(struct mv88e6xxx_chip *chip); 717 int (*global_disable)(struct mv88e6xxx_chip *chip); 718 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 719 int n_ext_ts; 720 int arr0_sts_reg; 721 int arr1_sts_reg; 722 int dep_sts_reg; 723 u32 rx_filters; 724 }; 725 726 struct mv88e6xxx_pcs_ops { 727 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port); 728 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port); 729 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port, 730 phy_interface_t mode); 731 732 }; 733 734 #define STATS_TYPE_PORT BIT(0) 735 #define STATS_TYPE_BANK0 BIT(1) 736 #define STATS_TYPE_BANK1 BIT(2) 737 738 struct mv88e6xxx_hw_stat { 739 char string[ETH_GSTRING_LEN]; 740 size_t size; 741 int reg; 742 int type; 743 }; 744 mv88e6xxx_has_stu(struct mv88e6xxx_chip * chip)745 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 746 { 747 return chip->info->max_sid > 0 && 748 chip->info->ops->stu_loadpurge && 749 chip->info->ops->stu_getnext; 750 } 751 mv88e6xxx_has_pvt(struct mv88e6xxx_chip * chip)752 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 753 { 754 return chip->info->pvt; 755 } 756 mv88e6xxx_has_lag(struct mv88e6xxx_chip * chip)757 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 758 { 759 return !!chip->info->global2_addr; 760 } 761 mv88e6xxx_num_databases(struct mv88e6xxx_chip * chip)762 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 763 { 764 return chip->info->num_databases; 765 } 766 mv88e6xxx_num_macs(struct mv88e6xxx_chip * chip)767 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 768 { 769 return chip->info->num_macs; 770 } 771 mv88e6xxx_num_ports(struct mv88e6xxx_chip * chip)772 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 773 { 774 return chip->info->num_ports; 775 } 776 mv88e6xxx_max_vid(struct mv88e6xxx_chip * chip)777 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 778 { 779 return chip->info->max_vid; 780 } 781 mv88e6xxx_max_sid(struct mv88e6xxx_chip * chip)782 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 783 { 784 return chip->info->max_sid; 785 } 786 mv88e6xxx_port_mask(struct mv88e6xxx_chip * chip)787 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 788 { 789 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 790 } 791 mv88e6xxx_num_gpio(struct mv88e6xxx_chip * chip)792 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 793 { 794 return chip->info->num_gpio; 795 } 796 mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip * chip,int port)797 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 798 { 799 return (chip->info->invalid_port_mask & BIT(port)) != 0; 800 } 801 mv88e6xxx_port_set_mab(struct mv88e6xxx_chip * chip,int port,bool mab)802 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 803 int port, bool mab) 804 { 805 chip->ports[port].mab = mab; 806 } 807 808 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 809 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 810 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 811 u16 mask, u16 val); 812 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 813 int bit, int val); 814 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 815 mv88e6xxx_reg_lock(struct mv88e6xxx_chip * chip)816 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 817 { 818 mutex_lock(&chip->reg_lock); 819 } 820 mv88e6xxx_reg_unlock(struct mv88e6xxx_chip * chip)821 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 822 { 823 mutex_unlock(&chip->reg_lock); 824 } 825 826 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 827 int (*cb)(struct mv88e6xxx_chip *chip, 828 const struct mv88e6xxx_vtu_entry *entry, 829 void *priv), 830 void *priv); 831 832 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 833 834 #endif /* _MV88E6XXX_CHIP_H */ 835