xref: /openbmc/qemu/hw/arm/pxa2xx.c (revision 607ef570)
1 /*
2  * Intel XScale PXA255/270 processor support.
3  *
4  * Copyright (c) 2006 Openedhand Ltd.
5  * Written by Andrzej Zaborowski <balrog@zabor.org>
6  *
7  * This code is licensed under the GPL.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qemu/error-report.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "exec/address-spaces.h"
15 #include "cpu.h"
16 #include "hw/sysbus.h"
17 #include "migration/vmstate.h"
18 #include "hw/arm/pxa.h"
19 #include "sysemu/sysemu.h"
20 #include "hw/char/serial.h"
21 #include "hw/i2c/i2c.h"
22 #include "hw/irq.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/qdev-properties-system.h"
25 #include "hw/ssi/ssi.h"
26 #include "hw/sd/sd.h"
27 #include "chardev/char-fe.h"
28 #include "sysemu/blockdev.h"
29 #include "sysemu/qtest.h"
30 #include "sysemu/rtc.h"
31 #include "qemu/cutils.h"
32 #include "qemu/log.h"
33 #include "qom/object.h"
34 #include "target/arm/cpregs.h"
35 
36 static struct {
37     hwaddr io_base;
38     int irqn;
39 } pxa255_serial[] = {
40     { 0x40100000, PXA2XX_PIC_FFUART },
41     { 0x40200000, PXA2XX_PIC_BTUART },
42     { 0x40700000, PXA2XX_PIC_STUART },
43     { 0x41600000, PXA25X_PIC_HWUART },
44     { 0, 0 }
45 }, pxa270_serial[] = {
46     { 0x40100000, PXA2XX_PIC_FFUART },
47     { 0x40200000, PXA2XX_PIC_BTUART },
48     { 0x40700000, PXA2XX_PIC_STUART },
49     { 0, 0 }
50 };
51 
52 typedef struct PXASSPDef {
53     hwaddr io_base;
54     int irqn;
55 } PXASSPDef;
56 
57 #if 0
58 static PXASSPDef pxa250_ssp[] = {
59     { 0x41000000, PXA2XX_PIC_SSP },
60     { 0, 0 }
61 };
62 #endif
63 
64 static PXASSPDef pxa255_ssp[] = {
65     { 0x41000000, PXA2XX_PIC_SSP },
66     { 0x41400000, PXA25X_PIC_NSSP },
67     { 0, 0 }
68 };
69 
70 #if 0
71 static PXASSPDef pxa26x_ssp[] = {
72     { 0x41000000, PXA2XX_PIC_SSP },
73     { 0x41400000, PXA25X_PIC_NSSP },
74     { 0x41500000, PXA26X_PIC_ASSP },
75     { 0, 0 }
76 };
77 #endif
78 
79 static PXASSPDef pxa27x_ssp[] = {
80     { 0x41000000, PXA2XX_PIC_SSP },
81     { 0x41700000, PXA27X_PIC_SSP2 },
82     { 0x41900000, PXA2XX_PIC_SSP3 },
83     { 0, 0 }
84 };
85 
86 #define PMCR	0x00	/* Power Manager Control register */
87 #define PSSR	0x04	/* Power Manager Sleep Status register */
88 #define PSPR	0x08	/* Power Manager Scratch-Pad register */
89 #define PWER	0x0c	/* Power Manager Wake-Up Enable register */
90 #define PRER	0x10	/* Power Manager Rising-Edge Detect Enable register */
91 #define PFER	0x14	/* Power Manager Falling-Edge Detect Enable register */
92 #define PEDR	0x18	/* Power Manager Edge-Detect Status register */
93 #define PCFR	0x1c	/* Power Manager General Configuration register */
94 #define PGSR0	0x20	/* Power Manager GPIO Sleep-State register 0 */
95 #define PGSR1	0x24	/* Power Manager GPIO Sleep-State register 1 */
96 #define PGSR2	0x28	/* Power Manager GPIO Sleep-State register 2 */
97 #define PGSR3	0x2c	/* Power Manager GPIO Sleep-State register 3 */
98 #define RCSR	0x30	/* Reset Controller Status register */
99 #define PSLR	0x34	/* Power Manager Sleep Configuration register */
100 #define PTSR	0x38	/* Power Manager Standby Configuration register */
101 #define PVCR	0x40	/* Power Manager Voltage Change Control register */
102 #define PUCR	0x4c	/* Power Manager USIM Card Control/Status register */
103 #define PKWR	0x50	/* Power Manager Keyboard Wake-Up Enable register */
104 #define PKSR	0x54	/* Power Manager Keyboard Level-Detect Status */
105 #define PCMD0	0x80	/* Power Manager I2C Command register File 0 */
106 #define PCMD31	0xfc	/* Power Manager I2C Command register File 31 */
107 
pxa2xx_pm_read(void * opaque,hwaddr addr,unsigned size)108 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
109                                unsigned size)
110 {
111     PXA2xxState *s = (PXA2xxState *) opaque;
112 
113     switch (addr) {
114     case PMCR ... PCMD31:
115         if (addr & 3)
116             goto fail;
117 
118         return s->pm_regs[addr >> 2];
119     default:
120     fail:
121         qemu_log_mask(LOG_GUEST_ERROR,
122                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
123                       __func__, addr);
124         break;
125     }
126     return 0;
127 }
128 
pxa2xx_pm_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)129 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
130                             uint64_t value, unsigned size)
131 {
132     PXA2xxState *s = (PXA2xxState *) opaque;
133 
134     switch (addr) {
135     case PMCR:
136         /* Clear the write-one-to-clear bits... */
137         s->pm_regs[addr >> 2] &= ~(value & 0x2a);
138         /* ...and set the plain r/w bits */
139         s->pm_regs[addr >> 2] &= ~0x15;
140         s->pm_regs[addr >> 2] |= value & 0x15;
141         break;
142 
143     case PSSR:	/* Read-clean registers */
144     case RCSR:
145     case PKSR:
146         s->pm_regs[addr >> 2] &= ~value;
147         break;
148 
149     default:	/* Read-write registers */
150         if (!(addr & 3)) {
151             s->pm_regs[addr >> 2] = value;
152             break;
153         }
154         qemu_log_mask(LOG_GUEST_ERROR,
155                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
156                       __func__, addr);
157         break;
158     }
159 }
160 
161 static const MemoryRegionOps pxa2xx_pm_ops = {
162     .read = pxa2xx_pm_read,
163     .write = pxa2xx_pm_write,
164     .endianness = DEVICE_NATIVE_ENDIAN,
165 };
166 
167 static const VMStateDescription vmstate_pxa2xx_pm = {
168     .name = "pxa2xx_pm",
169     .version_id = 0,
170     .minimum_version_id = 0,
171     .fields = (const VMStateField[]) {
172         VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
173         VMSTATE_END_OF_LIST()
174     }
175 };
176 
177 #define CCCR	0x00	/* Core Clock Configuration register */
178 #define CKEN	0x04	/* Clock Enable register */
179 #define OSCC	0x08	/* Oscillator Configuration register */
180 #define CCSR	0x0c	/* Core Clock Status register */
181 
pxa2xx_cm_read(void * opaque,hwaddr addr,unsigned size)182 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
183                                unsigned size)
184 {
185     PXA2xxState *s = (PXA2xxState *) opaque;
186 
187     switch (addr) {
188     case CCCR:
189     case CKEN:
190     case OSCC:
191         return s->cm_regs[addr >> 2];
192 
193     case CCSR:
194         return s->cm_regs[CCCR >> 2] | (3 << 28);
195 
196     default:
197         qemu_log_mask(LOG_GUEST_ERROR,
198                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
199                       __func__, addr);
200         break;
201     }
202     return 0;
203 }
204 
pxa2xx_cm_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)205 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
206                             uint64_t value, unsigned size)
207 {
208     PXA2xxState *s = (PXA2xxState *) opaque;
209 
210     switch (addr) {
211     case CCCR:
212     case CKEN:
213         s->cm_regs[addr >> 2] = value;
214         break;
215 
216     case OSCC:
217         s->cm_regs[addr >> 2] &= ~0x6c;
218         s->cm_regs[addr >> 2] |= value & 0x6e;
219         if ((value >> 1) & 1)			/* OON */
220             s->cm_regs[addr >> 2] |= 1 << 0;	/* Oscillator is now stable */
221         break;
222 
223     default:
224         qemu_log_mask(LOG_GUEST_ERROR,
225                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
226                       __func__, addr);
227         break;
228     }
229 }
230 
231 static const MemoryRegionOps pxa2xx_cm_ops = {
232     .read = pxa2xx_cm_read,
233     .write = pxa2xx_cm_write,
234     .endianness = DEVICE_NATIVE_ENDIAN,
235 };
236 
237 static const VMStateDescription vmstate_pxa2xx_cm = {
238     .name = "pxa2xx_cm",
239     .version_id = 0,
240     .minimum_version_id = 0,
241     .fields = (const VMStateField[]) {
242         VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
243         VMSTATE_UINT32(clkcfg, PXA2xxState),
244         VMSTATE_UINT32(pmnc, PXA2xxState),
245         VMSTATE_END_OF_LIST()
246     }
247 };
248 
pxa2xx_clkcfg_read(CPUARMState * env,const ARMCPRegInfo * ri)249 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
250 {
251     PXA2xxState *s = (PXA2xxState *)ri->opaque;
252     return s->clkcfg;
253 }
254 
pxa2xx_clkcfg_write(CPUARMState * env,const ARMCPRegInfo * ri,uint64_t value)255 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
256                                 uint64_t value)
257 {
258     PXA2xxState *s = (PXA2xxState *)ri->opaque;
259     s->clkcfg = value & 0xf;
260     if (value & 2) {
261         printf("%s: CPU frequency change attempt\n", __func__);
262     }
263 }
264 
pxa2xx_pwrmode_write(CPUARMState * env,const ARMCPRegInfo * ri,uint64_t value)265 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
266                                  uint64_t value)
267 {
268     PXA2xxState *s = (PXA2xxState *)ri->opaque;
269     static const char *pwrmode[8] = {
270         "Normal", "Idle", "Deep-idle", "Standby",
271         "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
272     };
273 
274     if (value & 8) {
275         printf("%s: CPU voltage change attempt\n", __func__);
276     }
277     switch (value & 7) {
278     case 0:
279         /* Do nothing */
280         break;
281 
282     case 1:
283         /* Idle */
284         if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
285             cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
286             break;
287         }
288         /* Fall through.  */
289 
290     case 2:
291         /* Deep-Idle */
292         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
293         s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
294         goto message;
295 
296     case 3:
297         s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
298         s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
299         s->cpu->env.cp15.sctlr_ns = 0;
300         s->cpu->env.cp15.cpacr_el1 = 0;
301         s->cpu->env.cp15.ttbr0_el[1] = 0;
302         s->cpu->env.cp15.dacr_ns = 0;
303         s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
304         s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
305 
306         /*
307          * The scratch-pad register is almost universally used
308          * for storing the return address on suspend.  For the
309          * lack of a resuming bootloader, perform a jump
310          * directly to that address.
311          */
312         memset(s->cpu->env.regs, 0, 4 * 15);
313         s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
314 
315 #if 0
316         buffer = 0xe59ff000; /* ldr     pc, [pc, #0] */
317         cpu_physical_memory_write(0, &buffer, 4);
318         buffer = s->pm_regs[PSPR >> 2];
319         cpu_physical_memory_write(8, &buffer, 4);
320 #endif
321 
322         /* Suspend */
323         cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
324 
325         goto message;
326 
327     default:
328     message:
329         printf("%s: machine entered %s mode\n", __func__,
330                pwrmode[value & 7]);
331     }
332 }
333 
pxa2xx_cppmnc_read(CPUARMState * env,const ARMCPRegInfo * ri)334 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
335 {
336     PXA2xxState *s = (PXA2xxState *)ri->opaque;
337     return s->pmnc;
338 }
339 
pxa2xx_cppmnc_write(CPUARMState * env,const ARMCPRegInfo * ri,uint64_t value)340 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
341                                 uint64_t value)
342 {
343     PXA2xxState *s = (PXA2xxState *)ri->opaque;
344     s->pmnc = value;
345 }
346 
pxa2xx_cpccnt_read(CPUARMState * env,const ARMCPRegInfo * ri)347 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
348 {
349     PXA2xxState *s = (PXA2xxState *)ri->opaque;
350     if (s->pmnc & 1) {
351         return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
352     } else {
353         return 0;
354     }
355 }
356 
357 static const ARMCPRegInfo pxa_cp_reginfo[] = {
358     /* cp14 crm==1: perf registers */
359     { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
360       .access = PL1_RW, .type = ARM_CP_IO,
361       .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
362     { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
363       .access = PL1_RW, .type = ARM_CP_IO,
364       .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
365     { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
366       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
367     { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
368       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
369     { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
370       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
371     /* cp14 crm==2: performance count registers */
372     { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
373       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
374     { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
375       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
376     { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
377       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
378     { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
379       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
380     /* cp14 crn==6: CLKCFG */
381     { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
382       .access = PL1_RW, .type = ARM_CP_IO,
383       .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
384     /* cp14 crn==7: PWRMODE */
385     { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
386       .access = PL1_RW, .type = ARM_CP_IO,
387       .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
388 };
389 
pxa2xx_setup_cp14(PXA2xxState * s)390 static void pxa2xx_setup_cp14(PXA2xxState *s)
391 {
392     define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
393 }
394 
395 #define MDCNFG		0x00	/* SDRAM Configuration register */
396 #define MDREFR		0x04	/* SDRAM Refresh Control register */
397 #define MSC0		0x08	/* Static Memory Control register 0 */
398 #define MSC1		0x0c	/* Static Memory Control register 1 */
399 #define MSC2		0x10	/* Static Memory Control register 2 */
400 #define MECR		0x14	/* Expansion Memory Bus Config register */
401 #define SXCNFG		0x1c	/* Synchronous Static Memory Config register */
402 #define MCMEM0		0x28	/* PC Card Memory Socket 0 Timing register */
403 #define MCMEM1		0x2c	/* PC Card Memory Socket 1 Timing register */
404 #define MCATT0		0x30	/* PC Card Attribute Socket 0 register */
405 #define MCATT1		0x34	/* PC Card Attribute Socket 1 register */
406 #define MCIO0		0x38	/* PC Card I/O Socket 0 Timing register */
407 #define MCIO1		0x3c	/* PC Card I/O Socket 1 Timing register */
408 #define MDMRS		0x40	/* SDRAM Mode Register Set Config register */
409 #define BOOT_DEF	0x44	/* Boot-time Default Configuration register */
410 #define ARB_CNTL	0x48	/* Arbiter Control register */
411 #define BSCNTR0		0x4c	/* Memory Buffer Strength Control register 0 */
412 #define BSCNTR1		0x50	/* Memory Buffer Strength Control register 1 */
413 #define LCDBSCNTR	0x54	/* LCD Buffer Strength Control register */
414 #define MDMRSLP		0x58	/* Low Power SDRAM Mode Set Config register */
415 #define BSCNTR2		0x5c	/* Memory Buffer Strength Control register 2 */
416 #define BSCNTR3		0x60	/* Memory Buffer Strength Control register 3 */
417 #define SA1110		0x64	/* SA-1110 Memory Compatibility register */
418 
pxa2xx_mm_read(void * opaque,hwaddr addr,unsigned size)419 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
420                                unsigned size)
421 {
422     PXA2xxState *s = (PXA2xxState *) opaque;
423 
424     switch (addr) {
425     case MDCNFG ... SA1110:
426         if ((addr & 3) == 0)
427             return s->mm_regs[addr >> 2];
428         /* fall through */
429     default:
430         qemu_log_mask(LOG_GUEST_ERROR,
431                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
432                       __func__, addr);
433         break;
434     }
435     return 0;
436 }
437 
pxa2xx_mm_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)438 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
439                             uint64_t value, unsigned size)
440 {
441     PXA2xxState *s = (PXA2xxState *) opaque;
442 
443     switch (addr) {
444     case MDCNFG ... SA1110:
445         if ((addr & 3) == 0) {
446             s->mm_regs[addr >> 2] = value;
447             break;
448         }
449         /* fallthrough */
450     default:
451         qemu_log_mask(LOG_GUEST_ERROR,
452                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
453                       __func__, addr);
454         break;
455     }
456 }
457 
458 static const MemoryRegionOps pxa2xx_mm_ops = {
459     .read = pxa2xx_mm_read,
460     .write = pxa2xx_mm_write,
461     .endianness = DEVICE_NATIVE_ENDIAN,
462 };
463 
464 static const VMStateDescription vmstate_pxa2xx_mm = {
465     .name = "pxa2xx_mm",
466     .version_id = 0,
467     .minimum_version_id = 0,
468     .fields = (const VMStateField[]) {
469         VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
470         VMSTATE_END_OF_LIST()
471     }
472 };
473 
474 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
475 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxSSPState, PXA2XX_SSP)
476 
477 /* Synchronous Serial Ports */
478 struct PXA2xxSSPState {
479     /*< private >*/
480     SysBusDevice parent_obj;
481     /*< public >*/
482 
483     MemoryRegion iomem;
484     qemu_irq irq;
485     uint32_t enable;
486     SSIBus *bus;
487 
488     uint32_t sscr[2];
489     uint32_t sspsp;
490     uint32_t ssto;
491     uint32_t ssitr;
492     uint32_t sssr;
493     uint8_t sstsa;
494     uint8_t ssrsa;
495     uint8_t ssacd;
496 
497     uint32_t rx_fifo[16];
498     uint32_t rx_level;
499     uint32_t rx_start;
500 };
501 
pxa2xx_ssp_vmstate_validate(void * opaque,int version_id)502 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id)
503 {
504     PXA2xxSSPState *s = opaque;
505 
506     return s->rx_start < sizeof(s->rx_fifo);
507 }
508 
509 static const VMStateDescription vmstate_pxa2xx_ssp = {
510     .name = "pxa2xx-ssp",
511     .version_id = 1,
512     .minimum_version_id = 1,
513     .fields = (const VMStateField[]) {
514         VMSTATE_UINT32(enable, PXA2xxSSPState),
515         VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2),
516         VMSTATE_UINT32(sspsp, PXA2xxSSPState),
517         VMSTATE_UINT32(ssto, PXA2xxSSPState),
518         VMSTATE_UINT32(ssitr, PXA2xxSSPState),
519         VMSTATE_UINT32(sssr, PXA2xxSSPState),
520         VMSTATE_UINT8(sstsa, PXA2xxSSPState),
521         VMSTATE_UINT8(ssrsa, PXA2xxSSPState),
522         VMSTATE_UINT8(ssacd, PXA2xxSSPState),
523         VMSTATE_UINT32(rx_level, PXA2xxSSPState),
524         VMSTATE_UINT32(rx_start, PXA2xxSSPState),
525         VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate),
526         VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16),
527         VMSTATE_END_OF_LIST()
528     }
529 };
530 
531 #define SSCR0	0x00	/* SSP Control register 0 */
532 #define SSCR1	0x04	/* SSP Control register 1 */
533 #define SSSR	0x08	/* SSP Status register */
534 #define SSITR	0x0c	/* SSP Interrupt Test register */
535 #define SSDR	0x10	/* SSP Data register */
536 #define SSTO	0x28	/* SSP Time-Out register */
537 #define SSPSP	0x2c	/* SSP Programmable Serial Protocol register */
538 #define SSTSA	0x30	/* SSP TX Time Slot Active register */
539 #define SSRSA	0x34	/* SSP RX Time Slot Active register */
540 #define SSTSS	0x38	/* SSP Time Slot Status register */
541 #define SSACD	0x3c	/* SSP Audio Clock Divider register */
542 
543 /* Bitfields for above registers */
544 #define SSCR0_SPI(x)	(((x) & 0x30) == 0x00)
545 #define SSCR0_SSP(x)	(((x) & 0x30) == 0x10)
546 #define SSCR0_UWIRE(x)	(((x) & 0x30) == 0x20)
547 #define SSCR0_PSP(x)	(((x) & 0x30) == 0x30)
548 #define SSCR0_SSE	(1 << 7)
549 #define SSCR0_RIM	(1 << 22)
550 #define SSCR0_TIM	(1 << 23)
551 #define SSCR0_MOD       (1U << 31)
552 #define SSCR0_DSS(x)	(((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
553 #define SSCR1_RIE	(1 << 0)
554 #define SSCR1_TIE	(1 << 1)
555 #define SSCR1_LBM	(1 << 2)
556 #define SSCR1_MWDS	(1 << 5)
557 #define SSCR1_TFT(x)	((((x) >> 6) & 0xf) + 1)
558 #define SSCR1_RFT(x)	((((x) >> 10) & 0xf) + 1)
559 #define SSCR1_EFWR	(1 << 14)
560 #define SSCR1_PINTE	(1 << 18)
561 #define SSCR1_TINTE	(1 << 19)
562 #define SSCR1_RSRE	(1 << 20)
563 #define SSCR1_TSRE	(1 << 21)
564 #define SSCR1_EBCEI	(1 << 29)
565 #define SSITR_INT	(7 << 5)
566 #define SSSR_TNF	(1 << 2)
567 #define SSSR_RNE	(1 << 3)
568 #define SSSR_TFS	(1 << 5)
569 #define SSSR_RFS	(1 << 6)
570 #define SSSR_ROR	(1 << 7)
571 #define SSSR_PINT	(1 << 18)
572 #define SSSR_TINT	(1 << 19)
573 #define SSSR_EOC	(1 << 20)
574 #define SSSR_TUR	(1 << 21)
575 #define SSSR_BCE	(1 << 23)
576 #define SSSR_RW		0x00bc0080
577 
pxa2xx_ssp_int_update(PXA2xxSSPState * s)578 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
579 {
580     int level = 0;
581 
582     level |= s->ssitr & SSITR_INT;
583     level |= (s->sssr & SSSR_BCE)  &&  (s->sscr[1] & SSCR1_EBCEI);
584     level |= (s->sssr & SSSR_TUR)  && !(s->sscr[0] & SSCR0_TIM);
585     level |= (s->sssr & SSSR_EOC)  &&  (s->sssr & (SSSR_TINT | SSSR_PINT));
586     level |= (s->sssr & SSSR_TINT) &&  (s->sscr[1] & SSCR1_TINTE);
587     level |= (s->sssr & SSSR_PINT) &&  (s->sscr[1] & SSCR1_PINTE);
588     level |= (s->sssr & SSSR_ROR)  && !(s->sscr[0] & SSCR0_RIM);
589     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
590     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
591     qemu_set_irq(s->irq, !!level);
592 }
593 
pxa2xx_ssp_fifo_update(PXA2xxSSPState * s)594 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
595 {
596     s->sssr &= ~(0xf << 12);	/* Clear RFL */
597     s->sssr &= ~(0xf << 8);	/* Clear TFL */
598     s->sssr &= ~SSSR_TFS;
599     s->sssr &= ~SSSR_TNF;
600     if (s->enable) {
601         s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
602         if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
603             s->sssr |= SSSR_RFS;
604         else
605             s->sssr &= ~SSSR_RFS;
606         if (s->rx_level)
607             s->sssr |= SSSR_RNE;
608         else
609             s->sssr &= ~SSSR_RNE;
610         /* TX FIFO is never filled, so it is always in underrun
611            condition if SSP is enabled */
612         s->sssr |= SSSR_TFS;
613         s->sssr |= SSSR_TNF;
614     }
615 
616     pxa2xx_ssp_int_update(s);
617 }
618 
pxa2xx_ssp_read(void * opaque,hwaddr addr,unsigned size)619 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
620                                 unsigned size)
621 {
622     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
623     uint32_t retval;
624 
625     switch (addr) {
626     case SSCR0:
627         return s->sscr[0];
628     case SSCR1:
629         return s->sscr[1];
630     case SSPSP:
631         return s->sspsp;
632     case SSTO:
633         return s->ssto;
634     case SSITR:
635         return s->ssitr;
636     case SSSR:
637         return s->sssr | s->ssitr;
638     case SSDR:
639         if (!s->enable)
640             return 0xffffffff;
641         if (s->rx_level < 1) {
642             printf("%s: SSP Rx Underrun\n", __func__);
643             return 0xffffffff;
644         }
645         s->rx_level --;
646         retval = s->rx_fifo[s->rx_start ++];
647         s->rx_start &= 0xf;
648         pxa2xx_ssp_fifo_update(s);
649         return retval;
650     case SSTSA:
651         return s->sstsa;
652     case SSRSA:
653         return s->ssrsa;
654     case SSTSS:
655         return 0;
656     case SSACD:
657         return s->ssacd;
658     default:
659         qemu_log_mask(LOG_GUEST_ERROR,
660                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
661                       __func__, addr);
662         break;
663     }
664     return 0;
665 }
666 
pxa2xx_ssp_write(void * opaque,hwaddr addr,uint64_t value64,unsigned size)667 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
668                              uint64_t value64, unsigned size)
669 {
670     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
671     uint32_t value = value64;
672 
673     switch (addr) {
674     case SSCR0:
675         s->sscr[0] = value & 0xc7ffffff;
676         s->enable = value & SSCR0_SSE;
677         if (value & SSCR0_MOD)
678             printf("%s: Attempt to use network mode\n", __func__);
679         if (s->enable && SSCR0_DSS(value) < 4)
680             printf("%s: Wrong data size: %u bits\n", __func__,
681                             SSCR0_DSS(value));
682         if (!(value & SSCR0_SSE)) {
683             s->sssr = 0;
684             s->ssitr = 0;
685             s->rx_level = 0;
686         }
687         pxa2xx_ssp_fifo_update(s);
688         break;
689 
690     case SSCR1:
691         s->sscr[1] = value;
692         if (value & (SSCR1_LBM | SSCR1_EFWR))
693             printf("%s: Attempt to use SSP test mode\n", __func__);
694         pxa2xx_ssp_fifo_update(s);
695         break;
696 
697     case SSPSP:
698         s->sspsp = value;
699         break;
700 
701     case SSTO:
702         s->ssto = value;
703         break;
704 
705     case SSITR:
706         s->ssitr = value & SSITR_INT;
707         pxa2xx_ssp_int_update(s);
708         break;
709 
710     case SSSR:
711         s->sssr &= ~(value & SSSR_RW);
712         pxa2xx_ssp_int_update(s);
713         break;
714 
715     case SSDR:
716         if (SSCR0_UWIRE(s->sscr[0])) {
717             if (s->sscr[1] & SSCR1_MWDS)
718                 value &= 0xffff;
719             else
720                 value &= 0xff;
721         } else
722             /* Note how 32bits overflow does no harm here */
723             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
724 
725         /* Data goes from here to the Tx FIFO and is shifted out from
726          * there directly to the slave, no need to buffer it.
727          */
728         if (s->enable) {
729             uint32_t readval;
730             readval = ssi_transfer(s->bus, value);
731             if (s->rx_level < 0x10) {
732                 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
733             } else {
734                 s->sssr |= SSSR_ROR;
735             }
736         }
737         pxa2xx_ssp_fifo_update(s);
738         break;
739 
740     case SSTSA:
741         s->sstsa = value;
742         break;
743 
744     case SSRSA:
745         s->ssrsa = value;
746         break;
747 
748     case SSACD:
749         s->ssacd = value;
750         break;
751 
752     default:
753         qemu_log_mask(LOG_GUEST_ERROR,
754                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
755                       __func__, addr);
756         break;
757     }
758 }
759 
760 static const MemoryRegionOps pxa2xx_ssp_ops = {
761     .read = pxa2xx_ssp_read,
762     .write = pxa2xx_ssp_write,
763     .endianness = DEVICE_NATIVE_ENDIAN,
764 };
765 
pxa2xx_ssp_reset(DeviceState * d)766 static void pxa2xx_ssp_reset(DeviceState *d)
767 {
768     PXA2xxSSPState *s = PXA2XX_SSP(d);
769 
770     s->enable = 0;
771     s->sscr[0] = s->sscr[1] = 0;
772     s->sspsp = 0;
773     s->ssto = 0;
774     s->ssitr = 0;
775     s->sssr = 0;
776     s->sstsa = 0;
777     s->ssrsa = 0;
778     s->ssacd = 0;
779     s->rx_start = s->rx_level = 0;
780 }
781 
pxa2xx_ssp_init(Object * obj)782 static void pxa2xx_ssp_init(Object *obj)
783 {
784     DeviceState *dev = DEVICE(obj);
785     PXA2xxSSPState *s = PXA2XX_SSP(obj);
786     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
787     sysbus_init_irq(sbd, &s->irq);
788 
789     memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
790                           "pxa2xx-ssp", 0x1000);
791     sysbus_init_mmio(sbd, &s->iomem);
792 
793     s->bus = ssi_create_bus(dev, "ssi");
794 }
795 
796 /* Real-Time Clock */
797 #define RCNR		0x00	/* RTC Counter register */
798 #define RTAR		0x04	/* RTC Alarm register */
799 #define RTSR		0x08	/* RTC Status register */
800 #define RTTR		0x0c	/* RTC Timer Trim register */
801 #define RDCR		0x10	/* RTC Day Counter register */
802 #define RYCR		0x14	/* RTC Year Counter register */
803 #define RDAR1		0x18	/* RTC Wristwatch Day Alarm register 1 */
804 #define RYAR1		0x1c	/* RTC Wristwatch Year Alarm register 1 */
805 #define RDAR2		0x20	/* RTC Wristwatch Day Alarm register 2 */
806 #define RYAR2		0x24	/* RTC Wristwatch Year Alarm register 2 */
807 #define SWCR		0x28	/* RTC Stopwatch Counter register */
808 #define SWAR1		0x2c	/* RTC Stopwatch Alarm register 1 */
809 #define SWAR2		0x30	/* RTC Stopwatch Alarm register 2 */
810 #define RTCPICR		0x34	/* RTC Periodic Interrupt Counter register */
811 #define PIAR		0x38	/* RTC Periodic Interrupt Alarm register */
812 
813 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
814 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxRTCState, PXA2XX_RTC)
815 
816 struct PXA2xxRTCState {
817     /*< private >*/
818     SysBusDevice parent_obj;
819     /*< public >*/
820 
821     MemoryRegion iomem;
822     uint32_t rttr;
823     uint32_t rtsr;
824     uint32_t rtar;
825     uint32_t rdar1;
826     uint32_t rdar2;
827     uint32_t ryar1;
828     uint32_t ryar2;
829     uint32_t swar1;
830     uint32_t swar2;
831     uint32_t piar;
832     uint32_t last_rcnr;
833     uint32_t last_rdcr;
834     uint32_t last_rycr;
835     uint32_t last_swcr;
836     uint32_t last_rtcpicr;
837     int64_t last_hz;
838     int64_t last_sw;
839     int64_t last_pi;
840     QEMUTimer *rtc_hz;
841     QEMUTimer *rtc_rdal1;
842     QEMUTimer *rtc_rdal2;
843     QEMUTimer *rtc_swal1;
844     QEMUTimer *rtc_swal2;
845     QEMUTimer *rtc_pi;
846     qemu_irq rtc_irq;
847 };
848 
pxa2xx_rtc_int_update(PXA2xxRTCState * s)849 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
850 {
851     qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
852 }
853 
pxa2xx_rtc_hzupdate(PXA2xxRTCState * s)854 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
855 {
856     int64_t rt = qemu_clock_get_ms(rtc_clock);
857     s->last_rcnr += ((rt - s->last_hz) << 15) /
858             (1000 * ((s->rttr & 0xffff) + 1));
859     s->last_rdcr += ((rt - s->last_hz) << 15) /
860             (1000 * ((s->rttr & 0xffff) + 1));
861     s->last_hz = rt;
862 }
863 
pxa2xx_rtc_swupdate(PXA2xxRTCState * s)864 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
865 {
866     int64_t rt = qemu_clock_get_ms(rtc_clock);
867     if (s->rtsr & (1 << 12))
868         s->last_swcr += (rt - s->last_sw) / 10;
869     s->last_sw = rt;
870 }
871 
pxa2xx_rtc_piupdate(PXA2xxRTCState * s)872 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
873 {
874     int64_t rt = qemu_clock_get_ms(rtc_clock);
875     if (s->rtsr & (1 << 15))
876         s->last_swcr += rt - s->last_pi;
877     s->last_pi = rt;
878 }
879 
pxa2xx_rtc_alarm_update(PXA2xxRTCState * s,uint32_t rtsr)880 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
881                 uint32_t rtsr)
882 {
883     if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
884         timer_mod(s->rtc_hz, s->last_hz +
885                 (((s->rtar - s->last_rcnr) * 1000 *
886                   ((s->rttr & 0xffff) + 1)) >> 15));
887     else
888         timer_del(s->rtc_hz);
889 
890     if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
891         timer_mod(s->rtc_rdal1, s->last_hz +
892                 (((s->rdar1 - s->last_rdcr) * 1000 *
893                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
894     else
895         timer_del(s->rtc_rdal1);
896 
897     if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
898         timer_mod(s->rtc_rdal2, s->last_hz +
899                 (((s->rdar2 - s->last_rdcr) * 1000 *
900                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
901     else
902         timer_del(s->rtc_rdal2);
903 
904     if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
905         timer_mod(s->rtc_swal1, s->last_sw +
906                         (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
907     else
908         timer_del(s->rtc_swal1);
909 
910     if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
911         timer_mod(s->rtc_swal2, s->last_sw +
912                         (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
913     else
914         timer_del(s->rtc_swal2);
915 
916     if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
917         timer_mod(s->rtc_pi, s->last_pi +
918                         (s->piar & 0xffff) - s->last_rtcpicr);
919     else
920         timer_del(s->rtc_pi);
921 }
922 
pxa2xx_rtc_hz_tick(void * opaque)923 static inline void pxa2xx_rtc_hz_tick(void *opaque)
924 {
925     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
926     s->rtsr |= (1 << 0);
927     pxa2xx_rtc_alarm_update(s, s->rtsr);
928     pxa2xx_rtc_int_update(s);
929 }
930 
pxa2xx_rtc_rdal1_tick(void * opaque)931 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
932 {
933     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
934     s->rtsr |= (1 << 4);
935     pxa2xx_rtc_alarm_update(s, s->rtsr);
936     pxa2xx_rtc_int_update(s);
937 }
938 
pxa2xx_rtc_rdal2_tick(void * opaque)939 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
940 {
941     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
942     s->rtsr |= (1 << 6);
943     pxa2xx_rtc_alarm_update(s, s->rtsr);
944     pxa2xx_rtc_int_update(s);
945 }
946 
pxa2xx_rtc_swal1_tick(void * opaque)947 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
948 {
949     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
950     s->rtsr |= (1 << 8);
951     pxa2xx_rtc_alarm_update(s, s->rtsr);
952     pxa2xx_rtc_int_update(s);
953 }
954 
pxa2xx_rtc_swal2_tick(void * opaque)955 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
956 {
957     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
958     s->rtsr |= (1 << 10);
959     pxa2xx_rtc_alarm_update(s, s->rtsr);
960     pxa2xx_rtc_int_update(s);
961 }
962 
pxa2xx_rtc_pi_tick(void * opaque)963 static inline void pxa2xx_rtc_pi_tick(void *opaque)
964 {
965     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
966     s->rtsr |= (1 << 13);
967     pxa2xx_rtc_piupdate(s);
968     s->last_rtcpicr = 0;
969     pxa2xx_rtc_alarm_update(s, s->rtsr);
970     pxa2xx_rtc_int_update(s);
971 }
972 
pxa2xx_rtc_read(void * opaque,hwaddr addr,unsigned size)973 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
974                                 unsigned size)
975 {
976     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
977 
978     switch (addr) {
979     case RTTR:
980         return s->rttr;
981     case RTSR:
982         return s->rtsr;
983     case RTAR:
984         return s->rtar;
985     case RDAR1:
986         return s->rdar1;
987     case RDAR2:
988         return s->rdar2;
989     case RYAR1:
990         return s->ryar1;
991     case RYAR2:
992         return s->ryar2;
993     case SWAR1:
994         return s->swar1;
995     case SWAR2:
996         return s->swar2;
997     case PIAR:
998         return s->piar;
999     case RCNR:
1000         return s->last_rcnr +
1001             ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
1002             (1000 * ((s->rttr & 0xffff) + 1));
1003     case RDCR:
1004         return s->last_rdcr +
1005             ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
1006             (1000 * ((s->rttr & 0xffff) + 1));
1007     case RYCR:
1008         return s->last_rycr;
1009     case SWCR:
1010         if (s->rtsr & (1 << 12))
1011             return s->last_swcr +
1012                 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
1013         else
1014             return s->last_swcr;
1015     default:
1016         qemu_log_mask(LOG_GUEST_ERROR,
1017                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
1018                       __func__, addr);
1019         break;
1020     }
1021     return 0;
1022 }
1023 
pxa2xx_rtc_write(void * opaque,hwaddr addr,uint64_t value64,unsigned size)1024 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1025                              uint64_t value64, unsigned size)
1026 {
1027     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1028     uint32_t value = value64;
1029 
1030     switch (addr) {
1031     case RTTR:
1032         if (!(s->rttr & (1U << 31))) {
1033             pxa2xx_rtc_hzupdate(s);
1034             s->rttr = value;
1035             pxa2xx_rtc_alarm_update(s, s->rtsr);
1036         }
1037         break;
1038 
1039     case RTSR:
1040         if ((s->rtsr ^ value) & (1 << 15))
1041             pxa2xx_rtc_piupdate(s);
1042 
1043         if ((s->rtsr ^ value) & (1 << 12))
1044             pxa2xx_rtc_swupdate(s);
1045 
1046         if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1047             pxa2xx_rtc_alarm_update(s, value);
1048 
1049         s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1050         pxa2xx_rtc_int_update(s);
1051         break;
1052 
1053     case RTAR:
1054         s->rtar = value;
1055         pxa2xx_rtc_alarm_update(s, s->rtsr);
1056         break;
1057 
1058     case RDAR1:
1059         s->rdar1 = value;
1060         pxa2xx_rtc_alarm_update(s, s->rtsr);
1061         break;
1062 
1063     case RDAR2:
1064         s->rdar2 = value;
1065         pxa2xx_rtc_alarm_update(s, s->rtsr);
1066         break;
1067 
1068     case RYAR1:
1069         s->ryar1 = value;
1070         pxa2xx_rtc_alarm_update(s, s->rtsr);
1071         break;
1072 
1073     case RYAR2:
1074         s->ryar2 = value;
1075         pxa2xx_rtc_alarm_update(s, s->rtsr);
1076         break;
1077 
1078     case SWAR1:
1079         pxa2xx_rtc_swupdate(s);
1080         s->swar1 = value;
1081         s->last_swcr = 0;
1082         pxa2xx_rtc_alarm_update(s, s->rtsr);
1083         break;
1084 
1085     case SWAR2:
1086         s->swar2 = value;
1087         pxa2xx_rtc_alarm_update(s, s->rtsr);
1088         break;
1089 
1090     case PIAR:
1091         s->piar = value;
1092         pxa2xx_rtc_alarm_update(s, s->rtsr);
1093         break;
1094 
1095     case RCNR:
1096         pxa2xx_rtc_hzupdate(s);
1097         s->last_rcnr = value;
1098         pxa2xx_rtc_alarm_update(s, s->rtsr);
1099         break;
1100 
1101     case RDCR:
1102         pxa2xx_rtc_hzupdate(s);
1103         s->last_rdcr = value;
1104         pxa2xx_rtc_alarm_update(s, s->rtsr);
1105         break;
1106 
1107     case RYCR:
1108         s->last_rycr = value;
1109         break;
1110 
1111     case SWCR:
1112         pxa2xx_rtc_swupdate(s);
1113         s->last_swcr = value;
1114         pxa2xx_rtc_alarm_update(s, s->rtsr);
1115         break;
1116 
1117     case RTCPICR:
1118         pxa2xx_rtc_piupdate(s);
1119         s->last_rtcpicr = value & 0xffff;
1120         pxa2xx_rtc_alarm_update(s, s->rtsr);
1121         break;
1122 
1123     default:
1124         qemu_log_mask(LOG_GUEST_ERROR,
1125                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
1126                       __func__, addr);
1127     }
1128 }
1129 
1130 static const MemoryRegionOps pxa2xx_rtc_ops = {
1131     .read = pxa2xx_rtc_read,
1132     .write = pxa2xx_rtc_write,
1133     .endianness = DEVICE_NATIVE_ENDIAN,
1134 };
1135 
pxa2xx_rtc_init(Object * obj)1136 static void pxa2xx_rtc_init(Object *obj)
1137 {
1138     PXA2xxRTCState *s = PXA2XX_RTC(obj);
1139     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1140     struct tm tm;
1141     int wom;
1142 
1143     s->rttr = 0x7fff;
1144     s->rtsr = 0;
1145 
1146     qemu_get_timedate(&tm, 0);
1147     wom = ((tm.tm_mday - 1) / 7) + 1;
1148 
1149     s->last_rcnr = (uint32_t) mktimegm(&tm);
1150     s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1151             (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1152     s->last_rycr = ((tm.tm_year + 1900) << 9) |
1153             ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1154     s->last_swcr = (tm.tm_hour << 19) |
1155             (tm.tm_min << 13) | (tm.tm_sec << 7);
1156     s->last_rtcpicr = 0;
1157     s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1158 
1159     sysbus_init_irq(dev, &s->rtc_irq);
1160 
1161     memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s,
1162                           "pxa2xx-rtc", 0x10000);
1163     sysbus_init_mmio(dev, &s->iomem);
1164 }
1165 
pxa2xx_rtc_realize(DeviceState * dev,Error ** errp)1166 static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp)
1167 {
1168     PXA2xxRTCState *s = PXA2XX_RTC(dev);
1169     s->rtc_hz    = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick,    s);
1170     s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1171     s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1172     s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1173     s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1174     s->rtc_pi    = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick,    s);
1175 }
1176 
pxa2xx_rtc_pre_save(void * opaque)1177 static int pxa2xx_rtc_pre_save(void *opaque)
1178 {
1179     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1180 
1181     pxa2xx_rtc_hzupdate(s);
1182     pxa2xx_rtc_piupdate(s);
1183     pxa2xx_rtc_swupdate(s);
1184 
1185     return 0;
1186 }
1187 
pxa2xx_rtc_post_load(void * opaque,int version_id)1188 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1189 {
1190     PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1191 
1192     pxa2xx_rtc_alarm_update(s, s->rtsr);
1193 
1194     return 0;
1195 }
1196 
1197 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1198     .name = "pxa2xx_rtc",
1199     .version_id = 0,
1200     .minimum_version_id = 0,
1201     .pre_save = pxa2xx_rtc_pre_save,
1202     .post_load = pxa2xx_rtc_post_load,
1203     .fields = (const VMStateField[]) {
1204         VMSTATE_UINT32(rttr, PXA2xxRTCState),
1205         VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1206         VMSTATE_UINT32(rtar, PXA2xxRTCState),
1207         VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1208         VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1209         VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1210         VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1211         VMSTATE_UINT32(swar1, PXA2xxRTCState),
1212         VMSTATE_UINT32(swar2, PXA2xxRTCState),
1213         VMSTATE_UINT32(piar, PXA2xxRTCState),
1214         VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1215         VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1216         VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1217         VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1218         VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1219         VMSTATE_INT64(last_hz, PXA2xxRTCState),
1220         VMSTATE_INT64(last_sw, PXA2xxRTCState),
1221         VMSTATE_INT64(last_pi, PXA2xxRTCState),
1222         VMSTATE_END_OF_LIST(),
1223     },
1224 };
1225 
pxa2xx_rtc_sysbus_class_init(ObjectClass * klass,void * data)1226 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1227 {
1228     DeviceClass *dc = DEVICE_CLASS(klass);
1229 
1230     dc->desc = "PXA2xx RTC Controller";
1231     dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1232     dc->realize = pxa2xx_rtc_realize;
1233 }
1234 
1235 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1236     .name          = TYPE_PXA2XX_RTC,
1237     .parent        = TYPE_SYS_BUS_DEVICE,
1238     .instance_size = sizeof(PXA2xxRTCState),
1239     .instance_init = pxa2xx_rtc_init,
1240     .class_init    = pxa2xx_rtc_sysbus_class_init,
1241 };
1242 
1243 /* I2C Interface */
1244 
1245 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1246 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CSlaveState, PXA2XX_I2C_SLAVE)
1247 
1248 struct PXA2xxI2CSlaveState {
1249     I2CSlave parent_obj;
1250 
1251     PXA2xxI2CState *host;
1252 };
1253 
1254 struct PXA2xxI2CState {
1255     /*< private >*/
1256     SysBusDevice parent_obj;
1257     /*< public >*/
1258 
1259     MemoryRegion iomem;
1260     PXA2xxI2CSlaveState *slave;
1261     I2CBus *bus;
1262     qemu_irq irq;
1263     uint32_t offset;
1264     uint32_t region_size;
1265 
1266     uint16_t control;
1267     uint16_t status;
1268     uint8_t ibmr;
1269     uint8_t data;
1270 };
1271 
1272 #define IBMR	0x80	/* I2C Bus Monitor register */
1273 #define IDBR	0x88	/* I2C Data Buffer register */
1274 #define ICR	0x90	/* I2C Control register */
1275 #define ISR	0x98	/* I2C Status register */
1276 #define ISAR	0xa0	/* I2C Slave Address register */
1277 
pxa2xx_i2c_update(PXA2xxI2CState * s)1278 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1279 {
1280     uint16_t level = 0;
1281     level |= s->status & s->control & (1 << 10);		/* BED */
1282     level |= (s->status & (1 << 7)) && (s->control & (1 << 9));	/* IRF */
1283     level |= (s->status & (1 << 6)) && (s->control & (1 << 8));	/* ITE */
1284     level |= s->status & (1 << 9);				/* SAD */
1285     qemu_set_irq(s->irq, !!level);
1286 }
1287 
1288 /* These are only stubs now.  */
pxa2xx_i2c_event(I2CSlave * i2c,enum i2c_event event)1289 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1290 {
1291     PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1292     PXA2xxI2CState *s = slave->host;
1293 
1294     switch (event) {
1295     case I2C_START_SEND:
1296         s->status |= (1 << 9);				/* set SAD */
1297         s->status &= ~(1 << 0);				/* clear RWM */
1298         break;
1299     case I2C_START_RECV:
1300         s->status |= (1 << 9);				/* set SAD */
1301         s->status |= 1 << 0;				/* set RWM */
1302         break;
1303     case I2C_FINISH:
1304         s->status |= (1 << 4);				/* set SSD */
1305         break;
1306     case I2C_NACK:
1307         s->status |= 1 << 1;				/* set ACKNAK */
1308         break;
1309     default:
1310         return -1;
1311     }
1312     pxa2xx_i2c_update(s);
1313 
1314     return 0;
1315 }
1316 
pxa2xx_i2c_rx(I2CSlave * i2c)1317 static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c)
1318 {
1319     PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1320     PXA2xxI2CState *s = slave->host;
1321 
1322     if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1323         return 0;
1324     }
1325 
1326     if (s->status & (1 << 0)) {			/* RWM */
1327         s->status |= 1 << 6;			/* set ITE */
1328     }
1329     pxa2xx_i2c_update(s);
1330 
1331     return s->data;
1332 }
1333 
pxa2xx_i2c_tx(I2CSlave * i2c,uint8_t data)1334 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1335 {
1336     PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1337     PXA2xxI2CState *s = slave->host;
1338 
1339     if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1340         return 1;
1341     }
1342 
1343     if (!(s->status & (1 << 0))) {		/* RWM */
1344         s->status |= 1 << 7;			/* set IRF */
1345         s->data = data;
1346     }
1347     pxa2xx_i2c_update(s);
1348 
1349     return 1;
1350 }
1351 
pxa2xx_i2c_read(void * opaque,hwaddr addr,unsigned size)1352 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1353                                 unsigned size)
1354 {
1355     PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1356     I2CSlave *slave;
1357 
1358     addr -= s->offset;
1359     switch (addr) {
1360     case ICR:
1361         return s->control;
1362     case ISR:
1363         return s->status | (i2c_bus_busy(s->bus) << 2);
1364     case ISAR:
1365         slave = I2C_SLAVE(s->slave);
1366         return slave->address;
1367     case IDBR:
1368         return s->data;
1369     case IBMR:
1370         if (s->status & (1 << 2))
1371             s->ibmr ^= 3;	/* Fake SCL and SDA pin changes */
1372         else
1373             s->ibmr = 0;
1374         return s->ibmr;
1375     default:
1376         qemu_log_mask(LOG_GUEST_ERROR,
1377                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
1378                       __func__, addr);
1379         break;
1380     }
1381     return 0;
1382 }
1383 
pxa2xx_i2c_write(void * opaque,hwaddr addr,uint64_t value64,unsigned size)1384 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1385                              uint64_t value64, unsigned size)
1386 {
1387     PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1388     uint32_t value = value64;
1389     int ack;
1390 
1391     addr -= s->offset;
1392     switch (addr) {
1393     case ICR:
1394         s->control = value & 0xfff7;
1395         if ((value & (1 << 3)) && (value & (1 << 6))) {	/* TB and IUE */
1396             /* TODO: slave mode */
1397             if (value & (1 << 0)) {			/* START condition */
1398                 if (s->data & 1)
1399                     s->status |= 1 << 0;		/* set RWM */
1400                 else
1401                     s->status &= ~(1 << 0);		/* clear RWM */
1402                 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1403             } else {
1404                 if (s->status & (1 << 0)) {		/* RWM */
1405                     s->data = i2c_recv(s->bus);
1406                     if (value & (1 << 2))		/* ACKNAK */
1407                         i2c_nack(s->bus);
1408                     ack = 1;
1409                 } else
1410                     ack = !i2c_send(s->bus, s->data);
1411             }
1412 
1413             if (value & (1 << 1))			/* STOP condition */
1414                 i2c_end_transfer(s->bus);
1415 
1416             if (ack) {
1417                 if (value & (1 << 0))			/* START condition */
1418                     s->status |= 1 << 6;		/* set ITE */
1419                 else
1420                     if (s->status & (1 << 0))		/* RWM */
1421                         s->status |= 1 << 7;		/* set IRF */
1422                     else
1423                         s->status |= 1 << 6;		/* set ITE */
1424                 s->status &= ~(1 << 1);			/* clear ACKNAK */
1425             } else {
1426                 s->status |= 1 << 6;			/* set ITE */
1427                 s->status |= 1 << 10;			/* set BED */
1428                 s->status |= 1 << 1;			/* set ACKNAK */
1429             }
1430         }
1431         if (!(value & (1 << 3)) && (value & (1 << 6)))	/* !TB and IUE */
1432             if (value & (1 << 4))			/* MA */
1433                 i2c_end_transfer(s->bus);
1434         pxa2xx_i2c_update(s);
1435         break;
1436 
1437     case ISR:
1438         s->status &= ~(value & 0x07f0);
1439         pxa2xx_i2c_update(s);
1440         break;
1441 
1442     case ISAR:
1443         i2c_slave_set_address(I2C_SLAVE(s->slave), value & 0x7f);
1444         break;
1445 
1446     case IDBR:
1447         s->data = value & 0xff;
1448         break;
1449 
1450     default:
1451         qemu_log_mask(LOG_GUEST_ERROR,
1452                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
1453                       __func__, addr);
1454     }
1455 }
1456 
1457 static const MemoryRegionOps pxa2xx_i2c_ops = {
1458     .read = pxa2xx_i2c_read,
1459     .write = pxa2xx_i2c_write,
1460     .endianness = DEVICE_NATIVE_ENDIAN,
1461 };
1462 
1463 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1464     .name = "pxa2xx_i2c_slave",
1465     .version_id = 1,
1466     .minimum_version_id = 1,
1467     .fields = (const VMStateField[]) {
1468         VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1469         VMSTATE_END_OF_LIST()
1470     }
1471 };
1472 
1473 static const VMStateDescription vmstate_pxa2xx_i2c = {
1474     .name = "pxa2xx_i2c",
1475     .version_id = 1,
1476     .minimum_version_id = 1,
1477     .fields = (const VMStateField[]) {
1478         VMSTATE_UINT16(control, PXA2xxI2CState),
1479         VMSTATE_UINT16(status, PXA2xxI2CState),
1480         VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1481         VMSTATE_UINT8(data, PXA2xxI2CState),
1482         VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1483                                vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1484         VMSTATE_END_OF_LIST()
1485     }
1486 };
1487 
pxa2xx_i2c_slave_class_init(ObjectClass * klass,void * data)1488 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1489 {
1490     I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1491 
1492     k->event = pxa2xx_i2c_event;
1493     k->recv = pxa2xx_i2c_rx;
1494     k->send = pxa2xx_i2c_tx;
1495 }
1496 
1497 static const TypeInfo pxa2xx_i2c_slave_info = {
1498     .name          = TYPE_PXA2XX_I2C_SLAVE,
1499     .parent        = TYPE_I2C_SLAVE,
1500     .instance_size = sizeof(PXA2xxI2CSlaveState),
1501     .class_init    = pxa2xx_i2c_slave_class_init,
1502 };
1503 
pxa2xx_i2c_init(hwaddr base,qemu_irq irq,uint32_t region_size)1504 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1505                 qemu_irq irq, uint32_t region_size)
1506 {
1507     DeviceState *dev;
1508     SysBusDevice *i2c_dev;
1509     PXA2xxI2CState *s;
1510     I2CBus *i2cbus;
1511 
1512     dev = qdev_new(TYPE_PXA2XX_I2C);
1513     qdev_prop_set_uint32(dev, "size", region_size + 1);
1514     qdev_prop_set_uint32(dev, "offset", base & region_size);
1515 
1516     /* FIXME: Should the slave device really be on a separate bus?  */
1517     i2cbus = i2c_init_bus(dev, "dummy");
1518 
1519     i2c_dev = SYS_BUS_DEVICE(dev);
1520     sysbus_realize_and_unref(i2c_dev, &error_fatal);
1521     sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1522     sysbus_connect_irq(i2c_dev, 0, irq);
1523 
1524     s = PXA2XX_I2C(i2c_dev);
1525     s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus,
1526                                                         TYPE_PXA2XX_I2C_SLAVE,
1527                                                         0));
1528     s->slave->host = s;
1529 
1530     return s;
1531 }
1532 
pxa2xx_i2c_initfn(Object * obj)1533 static void pxa2xx_i2c_initfn(Object *obj)
1534 {
1535     DeviceState *dev = DEVICE(obj);
1536     PXA2xxI2CState *s = PXA2XX_I2C(obj);
1537     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1538 
1539     s->bus = i2c_init_bus(dev, NULL);
1540 
1541     memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s,
1542                           "pxa2xx-i2c", s->region_size);
1543     sysbus_init_mmio(sbd, &s->iomem);
1544     sysbus_init_irq(sbd, &s->irq);
1545 }
1546 
pxa2xx_i2c_bus(PXA2xxI2CState * s)1547 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1548 {
1549     return s->bus;
1550 }
1551 
1552 static Property pxa2xx_i2c_properties[] = {
1553     DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1554     DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1555     DEFINE_PROP_END_OF_LIST(),
1556 };
1557 
pxa2xx_i2c_class_init(ObjectClass * klass,void * data)1558 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1559 {
1560     DeviceClass *dc = DEVICE_CLASS(klass);
1561 
1562     dc->desc = "PXA2xx I2C Bus Controller";
1563     dc->vmsd = &vmstate_pxa2xx_i2c;
1564     device_class_set_props(dc, pxa2xx_i2c_properties);
1565 }
1566 
1567 static const TypeInfo pxa2xx_i2c_info = {
1568     .name          = TYPE_PXA2XX_I2C,
1569     .parent        = TYPE_SYS_BUS_DEVICE,
1570     .instance_size = sizeof(PXA2xxI2CState),
1571     .instance_init = pxa2xx_i2c_initfn,
1572     .class_init    = pxa2xx_i2c_class_init,
1573 };
1574 
1575 /* PXA Inter-IC Sound Controller */
pxa2xx_i2s_reset(PXA2xxI2SState * i2s)1576 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1577 {
1578     i2s->rx_len = 0;
1579     i2s->tx_len = 0;
1580     i2s->fifo_len = 0;
1581     i2s->clk = 0x1a;
1582     i2s->control[0] = 0x00;
1583     i2s->control[1] = 0x00;
1584     i2s->status = 0x00;
1585     i2s->mask = 0x00;
1586 }
1587 
1588 #define SACR_TFTH(val)	((val >> 8) & 0xf)
1589 #define SACR_RFTH(val)	((val >> 12) & 0xf)
1590 #define SACR_DREC(val)	(val & (1 << 3))
1591 #define SACR_DPRL(val)	(val & (1 << 4))
1592 
pxa2xx_i2s_update(PXA2xxI2SState * i2s)1593 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1594 {
1595     int rfs, tfs;
1596     rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1597             !SACR_DREC(i2s->control[1]);
1598     tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1599             i2s->enable && !SACR_DPRL(i2s->control[1]);
1600 
1601     qemu_set_irq(i2s->rx_dma, rfs);
1602     qemu_set_irq(i2s->tx_dma, tfs);
1603 
1604     i2s->status &= 0xe0;
1605     if (i2s->fifo_len < 16 || !i2s->enable)
1606         i2s->status |= 1 << 0;			/* TNF */
1607     if (i2s->rx_len)
1608         i2s->status |= 1 << 1;			/* RNE */
1609     if (i2s->enable)
1610         i2s->status |= 1 << 2;			/* BSY */
1611     if (tfs)
1612         i2s->status |= 1 << 3;			/* TFS */
1613     if (rfs)
1614         i2s->status |= 1 << 4;			/* RFS */
1615     if (!(i2s->tx_len && i2s->enable))
1616         i2s->status |= i2s->fifo_len << 8;	/* TFL */
1617     i2s->status |= MAX(i2s->rx_len, 0xf) << 12;	/* RFL */
1618 
1619     qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1620 }
1621 
1622 #define SACR0	0x00	/* Serial Audio Global Control register */
1623 #define SACR1	0x04	/* Serial Audio I2S/MSB-Justified Control register */
1624 #define SASR0	0x0c	/* Serial Audio Interface and FIFO Status register */
1625 #define SAIMR	0x14	/* Serial Audio Interrupt Mask register */
1626 #define SAICR	0x18	/* Serial Audio Interrupt Clear register */
1627 #define SADIV	0x60	/* Serial Audio Clock Divider register */
1628 #define SADR	0x80	/* Serial Audio Data register */
1629 
pxa2xx_i2s_read(void * opaque,hwaddr addr,unsigned size)1630 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1631                                 unsigned size)
1632 {
1633     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1634 
1635     switch (addr) {
1636     case SACR0:
1637         return s->control[0];
1638     case SACR1:
1639         return s->control[1];
1640     case SASR0:
1641         return s->status;
1642     case SAIMR:
1643         return s->mask;
1644     case SAICR:
1645         return 0;
1646     case SADIV:
1647         return s->clk;
1648     case SADR:
1649         if (s->rx_len > 0) {
1650             s->rx_len --;
1651             pxa2xx_i2s_update(s);
1652             return s->codec_in(s->opaque);
1653         }
1654         return 0;
1655     default:
1656         qemu_log_mask(LOG_GUEST_ERROR,
1657                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
1658                       __func__, addr);
1659         break;
1660     }
1661     return 0;
1662 }
1663 
pxa2xx_i2s_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)1664 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1665                              uint64_t value, unsigned size)
1666 {
1667     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1668     uint32_t *sample;
1669 
1670     switch (addr) {
1671     case SACR0:
1672         if (value & (1 << 3))				/* RST */
1673             pxa2xx_i2s_reset(s);
1674         s->control[0] = value & 0xff3d;
1675         if (!s->enable && (value & 1) && s->tx_len) {	/* ENB */
1676             for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1677                 s->codec_out(s->opaque, *sample);
1678             s->status &= ~(1 << 7);			/* I2SOFF */
1679         }
1680         if (value & (1 << 4))				/* EFWR */
1681             printf("%s: Attempt to use special function\n", __func__);
1682         s->enable = (value & 9) == 1;			/* ENB && !RST*/
1683         pxa2xx_i2s_update(s);
1684         break;
1685     case SACR1:
1686         s->control[1] = value & 0x0039;
1687         if (value & (1 << 5))				/* ENLBF */
1688             printf("%s: Attempt to use loopback function\n", __func__);
1689         if (value & (1 << 4))				/* DPRL */
1690             s->fifo_len = 0;
1691         pxa2xx_i2s_update(s);
1692         break;
1693     case SAIMR:
1694         s->mask = value & 0x0078;
1695         pxa2xx_i2s_update(s);
1696         break;
1697     case SAICR:
1698         s->status &= ~(value & (3 << 5));
1699         pxa2xx_i2s_update(s);
1700         break;
1701     case SADIV:
1702         s->clk = value & 0x007f;
1703         break;
1704     case SADR:
1705         if (s->tx_len && s->enable) {
1706             s->tx_len --;
1707             pxa2xx_i2s_update(s);
1708             s->codec_out(s->opaque, value);
1709         } else if (s->fifo_len < 16) {
1710             s->fifo[s->fifo_len ++] = value;
1711             pxa2xx_i2s_update(s);
1712         }
1713         break;
1714     default:
1715         qemu_log_mask(LOG_GUEST_ERROR,
1716                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
1717                       __func__, addr);
1718     }
1719 }
1720 
1721 static const MemoryRegionOps pxa2xx_i2s_ops = {
1722     .read = pxa2xx_i2s_read,
1723     .write = pxa2xx_i2s_write,
1724     .endianness = DEVICE_NATIVE_ENDIAN,
1725 };
1726 
1727 static const VMStateDescription vmstate_pxa2xx_i2s = {
1728     .name = "pxa2xx_i2s",
1729     .version_id = 0,
1730     .minimum_version_id = 0,
1731     .fields = (const VMStateField[]) {
1732         VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1733         VMSTATE_UINT32(status, PXA2xxI2SState),
1734         VMSTATE_UINT32(mask, PXA2xxI2SState),
1735         VMSTATE_UINT32(clk, PXA2xxI2SState),
1736         VMSTATE_INT32(enable, PXA2xxI2SState),
1737         VMSTATE_INT32(rx_len, PXA2xxI2SState),
1738         VMSTATE_INT32(tx_len, PXA2xxI2SState),
1739         VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1740         VMSTATE_END_OF_LIST()
1741     }
1742 };
1743 
pxa2xx_i2s_data_req(void * opaque,int tx,int rx)1744 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1745 {
1746     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1747     uint32_t *sample;
1748 
1749     /* Signal FIFO errors */
1750     if (s->enable && s->tx_len)
1751         s->status |= 1 << 5;		/* TUR */
1752     if (s->enable && s->rx_len)
1753         s->status |= 1 << 6;		/* ROR */
1754 
1755     /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1756      * handle the cases where it makes a difference.  */
1757     s->tx_len = tx - s->fifo_len;
1758     s->rx_len = rx;
1759     /* Note that is s->codec_out wasn't set, we wouldn't get called.  */
1760     if (s->enable)
1761         for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1762             s->codec_out(s->opaque, *sample);
1763     pxa2xx_i2s_update(s);
1764 }
1765 
pxa2xx_i2s_init(MemoryRegion * sysmem,hwaddr base,qemu_irq irq,qemu_irq rx_dma,qemu_irq tx_dma)1766 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1767                 hwaddr base,
1768                 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1769 {
1770     PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1);
1771 
1772     s->irq = irq;
1773     s->rx_dma = rx_dma;
1774     s->tx_dma = tx_dma;
1775     s->data_req = pxa2xx_i2s_data_req;
1776 
1777     pxa2xx_i2s_reset(s);
1778 
1779     memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1780                           "pxa2xx-i2s", 0x100000);
1781     memory_region_add_subregion(sysmem, base, &s->iomem);
1782 
1783     vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1784 
1785     return s;
1786 }
1787 
1788 /* PXA Fast Infra-red Communications Port */
1789 struct PXA2xxFIrState {
1790     /*< private >*/
1791     SysBusDevice parent_obj;
1792     /*< public >*/
1793 
1794     MemoryRegion iomem;
1795     qemu_irq irq;
1796     qemu_irq rx_dma;
1797     qemu_irq tx_dma;
1798     uint32_t enable;
1799     CharBackend chr;
1800 
1801     uint8_t control[3];
1802     uint8_t status[2];
1803 
1804     uint32_t rx_len;
1805     uint32_t rx_start;
1806     uint8_t rx_fifo[64];
1807 };
1808 
pxa2xx_fir_reset(DeviceState * d)1809 static void pxa2xx_fir_reset(DeviceState *d)
1810 {
1811     PXA2xxFIrState *s = PXA2XX_FIR(d);
1812 
1813     s->control[0] = 0x00;
1814     s->control[1] = 0x00;
1815     s->control[2] = 0x00;
1816     s->status[0] = 0x00;
1817     s->status[1] = 0x00;
1818     s->enable = 0;
1819 }
1820 
pxa2xx_fir_update(PXA2xxFIrState * s)1821 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1822 {
1823     static const int tresh[4] = { 8, 16, 32, 0 };
1824     int intr = 0;
1825     if ((s->control[0] & (1 << 4)) &&			/* RXE */
1826                     s->rx_len >= tresh[s->control[2] & 3])	/* TRIG */
1827         s->status[0] |= 1 << 4;				/* RFS */
1828     else
1829         s->status[0] &= ~(1 << 4);			/* RFS */
1830     if (s->control[0] & (1 << 3))			/* TXE */
1831         s->status[0] |= 1 << 3;				/* TFS */
1832     else
1833         s->status[0] &= ~(1 << 3);			/* TFS */
1834     if (s->rx_len)
1835         s->status[1] |= 1 << 2;				/* RNE */
1836     else
1837         s->status[1] &= ~(1 << 2);			/* RNE */
1838     if (s->control[0] & (1 << 4))			/* RXE */
1839         s->status[1] |= 1 << 0;				/* RSY */
1840     else
1841         s->status[1] &= ~(1 << 0);			/* RSY */
1842 
1843     intr |= (s->control[0] & (1 << 5)) &&		/* RIE */
1844             (s->status[0] & (1 << 4));			/* RFS */
1845     intr |= (s->control[0] & (1 << 6)) &&		/* TIE */
1846             (s->status[0] & (1 << 3));			/* TFS */
1847     intr |= (s->control[2] & (1 << 4)) &&		/* TRAIL */
1848             (s->status[0] & (1 << 6));			/* EOC */
1849     intr |= (s->control[0] & (1 << 2)) &&		/* TUS */
1850             (s->status[0] & (1 << 1));			/* TUR */
1851     intr |= s->status[0] & 0x25;			/* FRE, RAB, EIF */
1852 
1853     qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1854     qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1855 
1856     qemu_set_irq(s->irq, intr && s->enable);
1857 }
1858 
1859 #define ICCR0	0x00	/* FICP Control register 0 */
1860 #define ICCR1	0x04	/* FICP Control register 1 */
1861 #define ICCR2	0x08	/* FICP Control register 2 */
1862 #define ICDR	0x0c	/* FICP Data register */
1863 #define ICSR0	0x14	/* FICP Status register 0 */
1864 #define ICSR1	0x18	/* FICP Status register 1 */
1865 #define ICFOR	0x1c	/* FICP FIFO Occupancy Status register */
1866 
pxa2xx_fir_read(void * opaque,hwaddr addr,unsigned size)1867 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1868                                 unsigned size)
1869 {
1870     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1871     uint8_t ret;
1872 
1873     switch (addr) {
1874     case ICCR0:
1875         return s->control[0];
1876     case ICCR1:
1877         return s->control[1];
1878     case ICCR2:
1879         return s->control[2];
1880     case ICDR:
1881         s->status[0] &= ~0x01;
1882         s->status[1] &= ~0x72;
1883         if (s->rx_len) {
1884             s->rx_len --;
1885             ret = s->rx_fifo[s->rx_start ++];
1886             s->rx_start &= 63;
1887             pxa2xx_fir_update(s);
1888             return ret;
1889         }
1890         printf("%s: Rx FIFO underrun.\n", __func__);
1891         break;
1892     case ICSR0:
1893         return s->status[0];
1894     case ICSR1:
1895         return s->status[1] | (1 << 3);			/* TNF */
1896     case ICFOR:
1897         return s->rx_len;
1898     default:
1899         qemu_log_mask(LOG_GUEST_ERROR,
1900                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
1901                       __func__, addr);
1902         break;
1903     }
1904     return 0;
1905 }
1906 
pxa2xx_fir_write(void * opaque,hwaddr addr,uint64_t value64,unsigned size)1907 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1908                              uint64_t value64, unsigned size)
1909 {
1910     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1911     uint32_t value = value64;
1912     uint8_t ch;
1913 
1914     switch (addr) {
1915     case ICCR0:
1916         s->control[0] = value;
1917         if (!(value & (1 << 4)))			/* RXE */
1918             s->rx_len = s->rx_start = 0;
1919         if (!(value & (1 << 3))) {                      /* TXE */
1920             /* Nop */
1921         }
1922         s->enable = value & 1;				/* ITR */
1923         if (!s->enable)
1924             s->status[0] = 0;
1925         pxa2xx_fir_update(s);
1926         break;
1927     case ICCR1:
1928         s->control[1] = value;
1929         break;
1930     case ICCR2:
1931         s->control[2] = value & 0x3f;
1932         pxa2xx_fir_update(s);
1933         break;
1934     case ICDR:
1935         if (s->control[2] & (1 << 2)) { /* TXP */
1936             ch = value;
1937         } else {
1938             ch = ~value;
1939         }
1940         if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */
1941             /* XXX this blocks entire thread. Rewrite to use
1942              * qemu_chr_fe_write and background I/O callbacks */
1943             qemu_chr_fe_write_all(&s->chr, &ch, 1);
1944         }
1945         break;
1946     case ICSR0:
1947         s->status[0] &= ~(value & 0x66);
1948         pxa2xx_fir_update(s);
1949         break;
1950     case ICFOR:
1951         break;
1952     default:
1953         qemu_log_mask(LOG_GUEST_ERROR,
1954                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
1955                       __func__, addr);
1956     }
1957 }
1958 
1959 static const MemoryRegionOps pxa2xx_fir_ops = {
1960     .read = pxa2xx_fir_read,
1961     .write = pxa2xx_fir_write,
1962     .endianness = DEVICE_NATIVE_ENDIAN,
1963 };
1964 
pxa2xx_fir_is_empty(void * opaque)1965 static int pxa2xx_fir_is_empty(void *opaque)
1966 {
1967     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1968     return (s->rx_len < 64);
1969 }
1970 
pxa2xx_fir_rx(void * opaque,const uint8_t * buf,int size)1971 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1972 {
1973     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1974     if (!(s->control[0] & (1 << 4)))			/* RXE */
1975         return;
1976 
1977     while (size --) {
1978         s->status[1] |= 1 << 4;				/* EOF */
1979         if (s->rx_len >= 64) {
1980             s->status[1] |= 1 << 6;			/* ROR */
1981             break;
1982         }
1983 
1984         if (s->control[2] & (1 << 3))			/* RXP */
1985             s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1986         else
1987             s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1988     }
1989 
1990     pxa2xx_fir_update(s);
1991 }
1992 
pxa2xx_fir_event(void * opaque,QEMUChrEvent event)1993 static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event)
1994 {
1995 }
1996 
pxa2xx_fir_instance_init(Object * obj)1997 static void pxa2xx_fir_instance_init(Object *obj)
1998 {
1999     PXA2xxFIrState *s = PXA2XX_FIR(obj);
2000     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2001 
2002     memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s,
2003                           "pxa2xx-fir", 0x1000);
2004     sysbus_init_mmio(sbd, &s->iomem);
2005     sysbus_init_irq(sbd, &s->irq);
2006     sysbus_init_irq(sbd, &s->rx_dma);
2007     sysbus_init_irq(sbd, &s->tx_dma);
2008 }
2009 
pxa2xx_fir_realize(DeviceState * dev,Error ** errp)2010 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
2011 {
2012     PXA2xxFIrState *s = PXA2XX_FIR(dev);
2013 
2014     qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
2015                              pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL,
2016                              true);
2017 }
2018 
pxa2xx_fir_vmstate_validate(void * opaque,int version_id)2019 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
2020 {
2021     PXA2xxFIrState *s = opaque;
2022 
2023     return s->rx_start < ARRAY_SIZE(s->rx_fifo);
2024 }
2025 
2026 static const VMStateDescription pxa2xx_fir_vmsd = {
2027     .name = "pxa2xx-fir",
2028     .version_id = 1,
2029     .minimum_version_id = 1,
2030     .fields = (const VMStateField[]) {
2031         VMSTATE_UINT32(enable, PXA2xxFIrState),
2032         VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3),
2033         VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2),
2034         VMSTATE_UINT32(rx_len, PXA2xxFIrState),
2035         VMSTATE_UINT32(rx_start, PXA2xxFIrState),
2036         VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate),
2037         VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64),
2038         VMSTATE_END_OF_LIST()
2039     }
2040 };
2041 
2042 static Property pxa2xx_fir_properties[] = {
2043     DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr),
2044     DEFINE_PROP_END_OF_LIST(),
2045 };
2046 
pxa2xx_fir_class_init(ObjectClass * klass,void * data)2047 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data)
2048 {
2049     DeviceClass *dc = DEVICE_CLASS(klass);
2050 
2051     dc->realize = pxa2xx_fir_realize;
2052     dc->vmsd = &pxa2xx_fir_vmsd;
2053     device_class_set_props(dc, pxa2xx_fir_properties);
2054     dc->reset = pxa2xx_fir_reset;
2055 }
2056 
2057 static const TypeInfo pxa2xx_fir_info = {
2058     .name = TYPE_PXA2XX_FIR,
2059     .parent = TYPE_SYS_BUS_DEVICE,
2060     .instance_size = sizeof(PXA2xxFIrState),
2061     .class_init = pxa2xx_fir_class_init,
2062     .instance_init = pxa2xx_fir_instance_init,
2063 };
2064 
pxa2xx_fir_init(MemoryRegion * sysmem,hwaddr base,qemu_irq irq,qemu_irq rx_dma,qemu_irq tx_dma,Chardev * chr)2065 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2066                                        hwaddr base,
2067                                        qemu_irq irq, qemu_irq rx_dma,
2068                                        qemu_irq tx_dma,
2069                                        Chardev *chr)
2070 {
2071     DeviceState *dev;
2072     SysBusDevice *sbd;
2073 
2074     dev = qdev_new(TYPE_PXA2XX_FIR);
2075     qdev_prop_set_chr(dev, "chardev", chr);
2076     sbd = SYS_BUS_DEVICE(dev);
2077     sysbus_realize_and_unref(sbd, &error_fatal);
2078     sysbus_mmio_map(sbd, 0, base);
2079     sysbus_connect_irq(sbd, 0, irq);
2080     sysbus_connect_irq(sbd, 1, rx_dma);
2081     sysbus_connect_irq(sbd, 2, tx_dma);
2082     return PXA2XX_FIR(dev);
2083 }
2084 
pxa2xx_reset(void * opaque,int line,int level)2085 static void pxa2xx_reset(void *opaque, int line, int level)
2086 {
2087     PXA2xxState *s = (PXA2xxState *) opaque;
2088 
2089     if (level && (s->pm_regs[PCFR >> 2] & 0x10)) {	/* GPR_EN */
2090         cpu_reset(CPU(s->cpu));
2091         /* TODO: reset peripherals */
2092     }
2093 }
2094 
2095 /* Initialise a PXA270 integrated chip (ARM based core).  */
pxa270_init(unsigned int sdram_size,const char * cpu_type)2096 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
2097 {
2098     MemoryRegion *address_space = get_system_memory();
2099     PXA2xxState *s;
2100     int i;
2101     DriveInfo *dinfo;
2102     s = g_new0(PXA2xxState, 1);
2103 
2104     if (strncmp(cpu_type, "pxa27", 5)) {
2105         error_report("Machine requires a PXA27x processor");
2106         exit(1);
2107     }
2108 
2109     s->cpu = ARM_CPU(cpu_create(cpu_type));
2110     s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2111 
2112     /* SDRAM & Internal Memory Storage */
2113     memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size,
2114                            &error_fatal);
2115     memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2116     memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000,
2117                            &error_fatal);
2118     memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2119                                 &s->internal);
2120 
2121     s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2122 
2123     s->dma = pxa27x_dma_init(0x40000000,
2124                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2125 
2126     sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2127                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2128                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2129                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2130                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2131                     qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2132                     NULL);
2133 
2134     s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2135 
2136     s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2137                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2138                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2139                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2140     dinfo = drive_get(IF_SD, 0, 0);
2141     if (dinfo) {
2142         DeviceState *carddev;
2143 
2144         /* Create and plug in the sd card */
2145         carddev = qdev_new(TYPE_SD_CARD);
2146         qdev_prop_set_drive_err(carddev, "drive",
2147                                 blk_by_legacy_dinfo(dinfo), &error_fatal);
2148         qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc),
2149                                                            "sd-bus"),
2150                                &error_fatal);
2151     } else if (!qtest_enabled()) {
2152         warn_report("missing SecureDigital device");
2153     }
2154 
2155     for (i = 0; pxa270_serial[i].io_base; i++) {
2156         if (serial_hd(i)) {
2157             serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2158                            qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2159                            14857000 / 16, serial_hd(i),
2160                            DEVICE_NATIVE_ENDIAN);
2161         } else {
2162             break;
2163         }
2164     }
2165     if (serial_hd(i))
2166         s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2167                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2168                         qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2169                         qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2170                         serial_hd(i));
2171 
2172     s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2173                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2174 
2175     s->cm_base = 0x41300000;
2176     s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
2177     s->clkcfg = 0x00000009;		/* Turbo mode active */
2178     memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2179     memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2180     vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2181 
2182     pxa2xx_setup_cp14(s);
2183 
2184     s->mm_base = 0x48000000;
2185     s->mm_regs[MDMRS >> 2] = 0x00020002;
2186     s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2187     s->mm_regs[MECR >> 2] = 0x00000001;	/* Two PC Card sockets */
2188     memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2189     memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2190     vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2191 
2192     s->pm_base = 0x40f00000;
2193     memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2194     memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2195     vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2196 
2197     for (i = 0; pxa27x_ssp[i].io_base; i ++);
2198     s->ssp = g_new0(SSIBus *, i);
2199     for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2200         DeviceState *dev;
2201         dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2202                         qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2203         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2204     }
2205 
2206     sysbus_create_simple("sysbus-ohci", 0x4c000000,
2207                          qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2208 
2209     s->pcmcia[0] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
2210                                                       0x20000000, NULL));
2211     s->pcmcia[1] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
2212                                                       0x30000000, NULL));
2213 
2214     sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2215                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2216 
2217     s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2218                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2219     s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2220                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2221 
2222     s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2223                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2224                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2225                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2226 
2227     s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2228                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2229 
2230     /* GPIO1 resets the processor */
2231     /* The handler can be overridden by board-specific code */
2232     qdev_connect_gpio_out(s->gpio, 1, s->reset);
2233     return s;
2234 }
2235 
2236 /* Initialise a PXA255 integrated chip (ARM based core).  */
pxa255_init(unsigned int sdram_size)2237 PXA2xxState *pxa255_init(unsigned int sdram_size)
2238 {
2239     MemoryRegion *address_space = get_system_memory();
2240     PXA2xxState *s;
2241     int i;
2242     DriveInfo *dinfo;
2243 
2244     s = g_new0(PXA2xxState, 1);
2245 
2246     s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255")));
2247     s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2248 
2249     /* SDRAM & Internal Memory Storage */
2250     memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size,
2251                            &error_fatal);
2252     memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2253     memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2254                            PXA2XX_INTERNAL_SIZE, &error_fatal);
2255     memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2256                                 &s->internal);
2257 
2258     s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2259 
2260     s->dma = pxa255_dma_init(0x40000000,
2261                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2262 
2263     sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2264                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2265                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2266                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2267                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2268                     NULL);
2269 
2270     s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2271 
2272     s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2273                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2274                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2275                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2276     dinfo = drive_get(IF_SD, 0, 0);
2277     if (dinfo) {
2278         DeviceState *carddev;
2279 
2280         /* Create and plug in the sd card */
2281         carddev = qdev_new(TYPE_SD_CARD);
2282         qdev_prop_set_drive_err(carddev, "drive",
2283                                 blk_by_legacy_dinfo(dinfo), &error_fatal);
2284         qdev_realize_and_unref(carddev, qdev_get_child_bus(DEVICE(s->mmc),
2285                                                            "sd-bus"),
2286                                &error_fatal);
2287     } else if (!qtest_enabled()) {
2288         warn_report("missing SecureDigital device");
2289     }
2290 
2291     for (i = 0; pxa255_serial[i].io_base; i++) {
2292         if (serial_hd(i)) {
2293             serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2294                            qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2295                            14745600 / 16, serial_hd(i),
2296                            DEVICE_NATIVE_ENDIAN);
2297         } else {
2298             break;
2299         }
2300     }
2301     if (serial_hd(i))
2302         s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2303                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2304                         qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2305                         qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2306                         serial_hd(i));
2307 
2308     s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2309                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2310 
2311     s->cm_base = 0x41300000;
2312     s->cm_regs[CCCR >> 2] = 0x00000121;         /* from datasheet */
2313     s->cm_regs[CKEN >> 2] = 0x00017def;         /* from datasheet */
2314 
2315     s->clkcfg = 0x00000009;		/* Turbo mode active */
2316     memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2317     memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2318     vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2319 
2320     pxa2xx_setup_cp14(s);
2321 
2322     s->mm_base = 0x48000000;
2323     s->mm_regs[MDMRS >> 2] = 0x00020002;
2324     s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2325     s->mm_regs[MECR >> 2] = 0x00000001;	/* Two PC Card sockets */
2326     memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2327     memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2328     vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2329 
2330     s->pm_base = 0x40f00000;
2331     memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2332     memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2333     vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2334 
2335     for (i = 0; pxa255_ssp[i].io_base; i ++);
2336     s->ssp = g_new0(SSIBus *, i);
2337     for (i = 0; pxa255_ssp[i].io_base; i ++) {
2338         DeviceState *dev;
2339         dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2340                         qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2341         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2342     }
2343 
2344     s->pcmcia[0] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
2345                                                       0x20000000, NULL));
2346     s->pcmcia[1] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
2347                                                       0x30000000, NULL));
2348 
2349     sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2350                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2351 
2352     s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2353                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2354     s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2355                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2356 
2357     s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2358                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2359                     qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2360                     qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2361 
2362     /* GPIO1 resets the processor */
2363     /* The handler can be overridden by board-specific code */
2364     qdev_connect_gpio_out(s->gpio, 1, s->reset);
2365     return s;
2366 }
2367 
pxa2xx_ssp_class_init(ObjectClass * klass,void * data)2368 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2369 {
2370     DeviceClass *dc = DEVICE_CLASS(klass);
2371 
2372     dc->reset = pxa2xx_ssp_reset;
2373     dc->vmsd = &vmstate_pxa2xx_ssp;
2374 }
2375 
2376 static const TypeInfo pxa2xx_ssp_info = {
2377     .name          = TYPE_PXA2XX_SSP,
2378     .parent        = TYPE_SYS_BUS_DEVICE,
2379     .instance_size = sizeof(PXA2xxSSPState),
2380     .instance_init = pxa2xx_ssp_init,
2381     .class_init    = pxa2xx_ssp_class_init,
2382 };
2383 
pxa2xx_register_types(void)2384 static void pxa2xx_register_types(void)
2385 {
2386     type_register_static(&pxa2xx_i2c_slave_info);
2387     type_register_static(&pxa2xx_ssp_info);
2388     type_register_static(&pxa2xx_i2c_info);
2389     type_register_static(&pxa2xx_rtc_sysbus_info);
2390     type_register_static(&pxa2xx_fir_info);
2391 }
2392 
2393 type_init(pxa2xx_register_types)
2394