xref: /openbmc/linux/drivers/tty/serial/8250/8250_pci.c (revision f35ce68d)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Probe module for 8250/16550-type PCI serial ports.
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *
7  *  Copyright (C) 2001 Russell King, All Rights Reserved.
8  */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 
23 #include <asm/byteorder.h>
24 #include <asm/io.h>
25 
26 #include "8250.h"
27 #include "8250_pcilib.h"
28 
29 /*
30  * init function returns:
31  *  > 0 - number of ports
32  *  = 0 - use board->num_ports
33  *  < 0 - error
34  */
35 struct pci_serial_quirk {
36 	u32	vendor;
37 	u32	device;
38 	u32	subvendor;
39 	u32	subdevice;
40 	int	(*probe)(struct pci_dev *dev);
41 	int	(*init)(struct pci_dev *dev);
42 	int	(*setup)(struct serial_private *,
43 			 const struct pciserial_board *,
44 			 struct uart_8250_port *, int);
45 	void	(*exit)(struct pci_dev *dev);
46 };
47 
48 struct f815xxa_data {
49 	spinlock_t lock;
50 	int idx;
51 };
52 
53 struct serial_private {
54 	struct pci_dev		*dev;
55 	unsigned int		nr;
56 	struct pci_serial_quirk	*quirk;
57 	const struct pciserial_board *board;
58 	int			line[];
59 };
60 
61 #define PCI_DEVICE_ID_HPE_PCI_SERIAL	0x37e
62 
63 static const struct pci_device_id pci_use_msi[] = {
64 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
65 			 0xA000, 0x1000) },
66 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
67 			 0xA000, 0x1000) },
68 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
69 			 0xA000, 0x1000) },
70 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
71 			 0xA000, 0x1000) },
72 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
73 			 PCI_ANY_ID, PCI_ANY_ID) },
74 	{ }
75 };
76 
77 static int pci_default_setup(struct serial_private*,
78 	  const struct pciserial_board*, struct uart_8250_port *, int);
79 
moan_device(const char * str,struct pci_dev * dev)80 static void moan_device(const char *str, struct pci_dev *dev)
81 {
82 	pci_err(dev, "%s\n"
83 	       "Please send the output of lspci -vv, this\n"
84 	       "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
85 	       "manufacturer and name of serial board or\n"
86 	       "modem board to <linux-serial@vger.kernel.org>.\n",
87 	       str, dev->vendor, dev->device,
88 	       dev->subsystem_vendor, dev->subsystem_device);
89 }
90 
91 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)92 setup_port(struct serial_private *priv, struct uart_8250_port *port,
93 	   u8 bar, unsigned int offset, int regshift)
94 {
95 	return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);
96 }
97 
98 /*
99  * ADDI-DATA GmbH communication cards <info@addi-data.com>
100  */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)101 static int addidata_apci7800_setup(struct serial_private *priv,
102 				const struct pciserial_board *board,
103 				struct uart_8250_port *port, int idx)
104 {
105 	unsigned int bar = 0, offset = board->first_offset;
106 	bar = FL_GET_BASE(board->flags);
107 
108 	if (idx < 2) {
109 		offset += idx * board->uart_offset;
110 	} else if ((idx >= 2) && (idx < 4)) {
111 		bar += 1;
112 		offset += ((idx - 2) * board->uart_offset);
113 	} else if ((idx >= 4) && (idx < 6)) {
114 		bar += 2;
115 		offset += ((idx - 4) * board->uart_offset);
116 	} else if (idx >= 6) {
117 		bar += 3;
118 		offset += ((idx - 6) * board->uart_offset);
119 	}
120 
121 	return setup_port(priv, port, bar, offset, board->reg_shift);
122 }
123 
124 /*
125  * AFAVLAB uses a different mixture of BARs and offsets
126  * Not that ugly ;) -- HW
127  */
128 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)129 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
130 	      struct uart_8250_port *port, int idx)
131 {
132 	unsigned int bar, offset = board->first_offset;
133 
134 	bar = FL_GET_BASE(board->flags);
135 	if (idx < 4)
136 		bar += idx;
137 	else {
138 		bar = 4;
139 		offset += (idx - 4) * board->uart_offset;
140 	}
141 
142 	return setup_port(priv, port, bar, offset, board->reg_shift);
143 }
144 
145 /*
146  * HP's Remote Management Console.  The Diva chip came in several
147  * different versions.  N-class, L2000 and A500 have two Diva chips, each
148  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
149  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
150  * one Diva chip, but it has been expanded to 5 UARTs.
151  */
pci_hp_diva_init(struct pci_dev * dev)152 static int pci_hp_diva_init(struct pci_dev *dev)
153 {
154 	int rc = 0;
155 
156 	switch (dev->subsystem_device) {
157 	case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
158 	case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
159 	case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
160 	case PCI_DEVICE_ID_HP_DIVA_EVEREST:
161 		rc = 3;
162 		break;
163 	case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
164 		rc = 2;
165 		break;
166 	case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
167 		rc = 4;
168 		break;
169 	case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
170 	case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
171 		rc = 1;
172 		break;
173 	}
174 
175 	return rc;
176 }
177 
178 /*
179  * HP's Diva chip puts the 4th/5th serial port further out, and
180  * some serial ports are supposed to be hidden on certain models.
181  */
182 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)183 pci_hp_diva_setup(struct serial_private *priv,
184 		const struct pciserial_board *board,
185 		struct uart_8250_port *port, int idx)
186 {
187 	unsigned int offset = board->first_offset;
188 	unsigned int bar = FL_GET_BASE(board->flags);
189 
190 	switch (priv->dev->subsystem_device) {
191 	case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
192 		if (idx == 3)
193 			idx++;
194 		break;
195 	case PCI_DEVICE_ID_HP_DIVA_EVEREST:
196 		if (idx > 0)
197 			idx++;
198 		if (idx > 2)
199 			idx++;
200 		break;
201 	}
202 	if (idx > 2)
203 		offset = 0x18;
204 
205 	offset += idx * board->uart_offset;
206 
207 	return setup_port(priv, port, bar, offset, board->reg_shift);
208 }
209 
210 /*
211  * Added for EKF Intel i960 serial boards
212  */
pci_inteli960ni_init(struct pci_dev * dev)213 static int pci_inteli960ni_init(struct pci_dev *dev)
214 {
215 	u32 oldval;
216 
217 	if (!(dev->subsystem_device & 0x1000))
218 		return -ENODEV;
219 
220 	/* is firmware started? */
221 	pci_read_config_dword(dev, 0x44, &oldval);
222 	if (oldval == 0x00001000L) { /* RESET value */
223 		pci_dbg(dev, "Local i960 firmware missing\n");
224 		return -ENODEV;
225 	}
226 	return 0;
227 }
228 
229 /*
230  * Some PCI serial cards using the PLX 9050 PCI interface chip require
231  * that the card interrupt be explicitly enabled or disabled.  This
232  * seems to be mainly needed on card using the PLX which also use I/O
233  * mapped memory.
234  */
pci_plx9050_init(struct pci_dev * dev)235 static int pci_plx9050_init(struct pci_dev *dev)
236 {
237 	u8 irq_config;
238 	void __iomem *p;
239 
240 	if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
241 		moan_device("no memory in bar 0", dev);
242 		return 0;
243 	}
244 
245 	irq_config = 0x41;
246 	if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
247 	    dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
248 		irq_config = 0x43;
249 
250 	if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
251 	    (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
252 		/*
253 		 * As the megawolf cards have the int pins active
254 		 * high, and have 2 UART chips, both ints must be
255 		 * enabled on the 9050. Also, the UARTS are set in
256 		 * 16450 mode by default, so we have to enable the
257 		 * 16C950 'enhanced' mode so that we can use the
258 		 * deep FIFOs
259 		 */
260 		irq_config = 0x5b;
261 	/*
262 	 * enable/disable interrupts
263 	 */
264 	p = ioremap(pci_resource_start(dev, 0), 0x80);
265 	if (p == NULL)
266 		return -ENOMEM;
267 	writel(irq_config, p + 0x4c);
268 
269 	/*
270 	 * Read the register back to ensure that it took effect.
271 	 */
272 	readl(p + 0x4c);
273 	iounmap(p);
274 
275 	return 0;
276 }
277 
pci_plx9050_exit(struct pci_dev * dev)278 static void pci_plx9050_exit(struct pci_dev *dev)
279 {
280 	u8 __iomem *p;
281 
282 	if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
283 		return;
284 
285 	/*
286 	 * disable interrupts
287 	 */
288 	p = ioremap(pci_resource_start(dev, 0), 0x80);
289 	if (p != NULL) {
290 		writel(0, p + 0x4c);
291 
292 		/*
293 		 * Read the register back to ensure that it took effect.
294 		 */
295 		readl(p + 0x4c);
296 		iounmap(p);
297 	}
298 }
299 
300 #define NI8420_INT_ENABLE_REG	0x38
301 #define NI8420_INT_ENABLE_BIT	0x2000
302 
pci_ni8420_exit(struct pci_dev * dev)303 static void pci_ni8420_exit(struct pci_dev *dev)
304 {
305 	void __iomem *p;
306 	unsigned int bar = 0;
307 
308 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
309 		moan_device("no memory in bar", dev);
310 		return;
311 	}
312 
313 	p = pci_ioremap_bar(dev, bar);
314 	if (p == NULL)
315 		return;
316 
317 	/* Disable the CPU Interrupt */
318 	writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
319 	       p + NI8420_INT_ENABLE_REG);
320 	iounmap(p);
321 }
322 
323 
324 /* MITE registers */
325 #define MITE_IOWBSR1	0xc4
326 #define MITE_IOWCR1	0xf4
327 #define MITE_LCIMR1	0x08
328 #define MITE_LCIMR2	0x10
329 
330 #define MITE_LCIMR2_CLR_CPU_IE	(1 << 30)
331 
pci_ni8430_exit(struct pci_dev * dev)332 static void pci_ni8430_exit(struct pci_dev *dev)
333 {
334 	void __iomem *p;
335 	unsigned int bar = 0;
336 
337 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
338 		moan_device("no memory in bar", dev);
339 		return;
340 	}
341 
342 	p = pci_ioremap_bar(dev, bar);
343 	if (p == NULL)
344 		return;
345 
346 	/* Disable the CPU Interrupt */
347 	writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
348 	iounmap(p);
349 }
350 
351 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
352 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)353 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
354 		struct uart_8250_port *port, int idx)
355 {
356 	unsigned int bar, offset = board->first_offset;
357 
358 	bar = 0;
359 
360 	if (idx < 4) {
361 		/* first four channels map to 0, 0x100, 0x200, 0x300 */
362 		offset += idx * board->uart_offset;
363 	} else if (idx < 8) {
364 		/* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
365 		offset += idx * board->uart_offset + 0xC00;
366 	} else /* we have only 8 ports on PMC-OCTALPRO */
367 		return 1;
368 
369 	return setup_port(priv, port, bar, offset, board->reg_shift);
370 }
371 
372 /*
373 * This does initialization for PMC OCTALPRO cards:
374 * maps the device memory, resets the UARTs (needed, bc
375 * if the module is removed and inserted again, the card
376 * is in the sleep mode) and enables global interrupt.
377 */
378 
379 /* global control register offset for SBS PMC-OctalPro */
380 #define OCT_REG_CR_OFF		0x500
381 
sbs_init(struct pci_dev * dev)382 static int sbs_init(struct pci_dev *dev)
383 {
384 	u8 __iomem *p;
385 
386 	p = pci_ioremap_bar(dev, 0);
387 
388 	if (p == NULL)
389 		return -ENOMEM;
390 	/* Set bit-4 Control Register (UART RESET) in to reset the uarts */
391 	writeb(0x10, p + OCT_REG_CR_OFF);
392 	udelay(50);
393 	writeb(0x0, p + OCT_REG_CR_OFF);
394 
395 	/* Set bit-2 (INTENABLE) of Control Register */
396 	writeb(0x4, p + OCT_REG_CR_OFF);
397 	iounmap(p);
398 
399 	return 0;
400 }
401 
402 /*
403  * Disables the global interrupt of PMC-OctalPro
404  */
405 
sbs_exit(struct pci_dev * dev)406 static void sbs_exit(struct pci_dev *dev)
407 {
408 	u8 __iomem *p;
409 
410 	p = pci_ioremap_bar(dev, 0);
411 	/* FIXME: What if resource_len < OCT_REG_CR_OFF */
412 	if (p != NULL)
413 		writeb(0, p + OCT_REG_CR_OFF);
414 	iounmap(p);
415 }
416 
417 /*
418  * SIIG serial cards have an PCI interface chip which also controls
419  * the UART clocking frequency. Each UART can be clocked independently
420  * (except cards equipped with 4 UARTs) and initial clocking settings
421  * are stored in the EEPROM chip. It can cause problems because this
422  * version of serial driver doesn't support differently clocked UART's
423  * on single PCI card. To prevent this, initialization functions set
424  * high frequency clocking for all UART's on given card. It is safe (I
425  * hope) because it doesn't touch EEPROM settings to prevent conflicts
426  * with other OSes (like M$ DOS).
427  *
428  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
429  *
430  * There is two family of SIIG serial cards with different PCI
431  * interface chip and different configuration methods:
432  *     - 10x cards have control registers in IO and/or memory space;
433  *     - 20x cards have control registers in standard PCI configuration space.
434  *
435  * Note: all 10x cards have PCI device ids 0x10..
436  *       all 20x cards have PCI device ids 0x20..
437  *
438  * There are also Quartet Serial cards which use Oxford Semiconductor
439  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
440  *
441  * Note: some SIIG cards are probed by the parport_serial object.
442  */
443 
444 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
445 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
446 
pci_siig10x_init(struct pci_dev * dev)447 static int pci_siig10x_init(struct pci_dev *dev)
448 {
449 	u16 data;
450 	void __iomem *p;
451 
452 	switch (dev->device & 0xfff8) {
453 	case PCI_DEVICE_ID_SIIG_1S_10x:	/* 1S */
454 		data = 0xffdf;
455 		break;
456 	case PCI_DEVICE_ID_SIIG_2S_10x:	/* 2S, 2S1P */
457 		data = 0xf7ff;
458 		break;
459 	default:			/* 1S1P, 4S */
460 		data = 0xfffb;
461 		break;
462 	}
463 
464 	p = ioremap(pci_resource_start(dev, 0), 0x80);
465 	if (p == NULL)
466 		return -ENOMEM;
467 
468 	writew(readw(p + 0x28) & data, p + 0x28);
469 	readw(p + 0x28);
470 	iounmap(p);
471 	return 0;
472 }
473 
474 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
475 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
476 
pci_siig20x_init(struct pci_dev * dev)477 static int pci_siig20x_init(struct pci_dev *dev)
478 {
479 	u8 data;
480 
481 	/* Change clock frequency for the first UART. */
482 	pci_read_config_byte(dev, 0x6f, &data);
483 	pci_write_config_byte(dev, 0x6f, data & 0xef);
484 
485 	/* If this card has 2 UART, we have to do the same with second UART. */
486 	if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
487 	    ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
488 		pci_read_config_byte(dev, 0x73, &data);
489 		pci_write_config_byte(dev, 0x73, data & 0xef);
490 	}
491 	return 0;
492 }
493 
pci_siig_init(struct pci_dev * dev)494 static int pci_siig_init(struct pci_dev *dev)
495 {
496 	unsigned int type = dev->device & 0xff00;
497 
498 	if (type == 0x1000)
499 		return pci_siig10x_init(dev);
500 	if (type == 0x2000)
501 		return pci_siig20x_init(dev);
502 
503 	moan_device("Unknown SIIG card", dev);
504 	return -ENODEV;
505 }
506 
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)507 static int pci_siig_setup(struct serial_private *priv,
508 			  const struct pciserial_board *board,
509 			  struct uart_8250_port *port, int idx)
510 {
511 	unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
512 
513 	if (idx > 3) {
514 		bar = 4;
515 		offset = (idx - 4) * 8;
516 	}
517 
518 	return setup_port(priv, port, bar, offset, 0);
519 }
520 
521 /*
522  * Timedia has an explosion of boards, and to avoid the PCI table from
523  * growing *huge*, we use this function to collapse some 70 entries
524  * in the PCI table into one, for sanity's and compactness's sake.
525  */
526 static const unsigned short timedia_single_port[] = {
527 	0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
528 };
529 
530 static const unsigned short timedia_dual_port[] = {
531 	0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
532 	0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
533 	0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
534 	0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
535 	0xD079, 0
536 };
537 
538 static const unsigned short timedia_quad_port[] = {
539 	0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
540 	0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
541 	0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
542 	0xB157, 0
543 };
544 
545 static const unsigned short timedia_eight_port[] = {
546 	0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
547 	0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
548 };
549 
550 static const struct timedia_struct {
551 	int num;
552 	const unsigned short *ids;
553 } timedia_data[] = {
554 	{ 1, timedia_single_port },
555 	{ 2, timedia_dual_port },
556 	{ 4, timedia_quad_port },
557 	{ 8, timedia_eight_port }
558 };
559 
560 /*
561  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
562  * listing them individually, this driver merely grabs them all with
563  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
564  * and should be left free to be claimed by parport_serial instead.
565  */
pci_timedia_probe(struct pci_dev * dev)566 static int pci_timedia_probe(struct pci_dev *dev)
567 {
568 	/*
569 	 * Check the third digit of the subdevice ID
570 	 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
571 	 */
572 	if ((dev->subsystem_device & 0x00f0) >= 0x70) {
573 		pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
574 			 dev->subsystem_device);
575 		return -ENODEV;
576 	}
577 
578 	return 0;
579 }
580 
pci_timedia_init(struct pci_dev * dev)581 static int pci_timedia_init(struct pci_dev *dev)
582 {
583 	const unsigned short *ids;
584 	int i, j;
585 
586 	for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
587 		ids = timedia_data[i].ids;
588 		for (j = 0; ids[j]; j++)
589 			if (dev->subsystem_device == ids[j])
590 				return timedia_data[i].num;
591 	}
592 	return 0;
593 }
594 
595 /*
596  * Timedia/SUNIX uses a mixture of BARs and offsets
597  * Ugh, this is ugly as all hell --- TYT
598  */
599 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)600 pci_timedia_setup(struct serial_private *priv,
601 		  const struct pciserial_board *board,
602 		  struct uart_8250_port *port, int idx)
603 {
604 	unsigned int bar = 0, offset = board->first_offset;
605 
606 	switch (idx) {
607 	case 0:
608 		bar = 0;
609 		break;
610 	case 1:
611 		offset = board->uart_offset;
612 		bar = 0;
613 		break;
614 	case 2:
615 		bar = 1;
616 		break;
617 	case 3:
618 		offset = board->uart_offset;
619 		fallthrough;
620 	case 4: /* BAR 2 */
621 	case 5: /* BAR 3 */
622 	case 6: /* BAR 4 */
623 	case 7: /* BAR 5 */
624 		bar = idx - 2;
625 	}
626 
627 	return setup_port(priv, port, bar, offset, board->reg_shift);
628 }
629 
630 /*
631  * Some Titan cards are also a little weird
632  */
633 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)634 titan_400l_800l_setup(struct serial_private *priv,
635 		      const struct pciserial_board *board,
636 		      struct uart_8250_port *port, int idx)
637 {
638 	unsigned int bar, offset = board->first_offset;
639 
640 	switch (idx) {
641 	case 0:
642 		bar = 1;
643 		break;
644 	case 1:
645 		bar = 2;
646 		break;
647 	default:
648 		bar = 4;
649 		offset = (idx - 2) * board->uart_offset;
650 	}
651 
652 	return setup_port(priv, port, bar, offset, board->reg_shift);
653 }
654 
pci_xircom_init(struct pci_dev * dev)655 static int pci_xircom_init(struct pci_dev *dev)
656 {
657 	msleep(100);
658 	return 0;
659 }
660 
pci_ni8420_init(struct pci_dev * dev)661 static int pci_ni8420_init(struct pci_dev *dev)
662 {
663 	void __iomem *p;
664 	unsigned int bar = 0;
665 
666 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
667 		moan_device("no memory in bar", dev);
668 		return 0;
669 	}
670 
671 	p = pci_ioremap_bar(dev, bar);
672 	if (p == NULL)
673 		return -ENOMEM;
674 
675 	/* Enable CPU Interrupt */
676 	writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
677 	       p + NI8420_INT_ENABLE_REG);
678 
679 	iounmap(p);
680 	return 0;
681 }
682 
683 #define MITE_IOWBSR1_WSIZE	0xa
684 #define MITE_IOWBSR1_WIN_OFFSET	0x800
685 #define MITE_IOWBSR1_WENAB	(1 << 7)
686 #define MITE_LCIMR1_IO_IE_0	(1 << 24)
687 #define MITE_LCIMR2_SET_CPU_IE	(1 << 31)
688 #define MITE_IOWCR1_RAMSEL_MASK	0xfffffffe
689 
pci_ni8430_init(struct pci_dev * dev)690 static int pci_ni8430_init(struct pci_dev *dev)
691 {
692 	void __iomem *p;
693 	struct pci_bus_region region;
694 	u32 device_window;
695 	unsigned int bar = 0;
696 
697 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
698 		moan_device("no memory in bar", dev);
699 		return 0;
700 	}
701 
702 	p = pci_ioremap_bar(dev, bar);
703 	if (p == NULL)
704 		return -ENOMEM;
705 
706 	/*
707 	 * Set device window address and size in BAR0, while acknowledging that
708 	 * the resource structure may contain a translated address that differs
709 	 * from the address the device responds to.
710 	 */
711 	pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
712 	device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
713 			| MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
714 	writel(device_window, p + MITE_IOWBSR1);
715 
716 	/* Set window access to go to RAMSEL IO address space */
717 	writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
718 	       p + MITE_IOWCR1);
719 
720 	/* Enable IO Bus Interrupt 0 */
721 	writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
722 
723 	/* Enable CPU Interrupt */
724 	writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
725 
726 	iounmap(p);
727 	return 0;
728 }
729 
730 /* UART Port Control Register */
731 #define NI8430_PORTCON	0x0f
732 #define NI8430_PORTCON_TXVR_ENABLE	(1 << 3)
733 
734 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)735 pci_ni8430_setup(struct serial_private *priv,
736 		 const struct pciserial_board *board,
737 		 struct uart_8250_port *port, int idx)
738 {
739 	struct pci_dev *dev = priv->dev;
740 	void __iomem *p;
741 	unsigned int bar, offset = board->first_offset;
742 
743 	if (idx >= board->num_ports)
744 		return 1;
745 
746 	bar = FL_GET_BASE(board->flags);
747 	offset += idx * board->uart_offset;
748 
749 	p = pci_ioremap_bar(dev, bar);
750 	if (!p)
751 		return -ENOMEM;
752 
753 	/* enable the transceiver */
754 	writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
755 	       p + offset + NI8430_PORTCON);
756 
757 	iounmap(p);
758 
759 	return setup_port(priv, port, bar, offset, board->reg_shift);
760 }
761 
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)762 static int pci_netmos_9900_setup(struct serial_private *priv,
763 				const struct pciserial_board *board,
764 				struct uart_8250_port *port, int idx)
765 {
766 	unsigned int bar;
767 
768 	if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
769 	    (priv->dev->subsystem_device & 0xff00) == 0x3000) {
770 		/* netmos apparently orders BARs by datasheet layout, so serial
771 		 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
772 		 */
773 		bar = 3 * idx;
774 
775 		return setup_port(priv, port, bar, 0, board->reg_shift);
776 	}
777 
778 	return pci_default_setup(priv, board, port, idx);
779 }
780 
781 /* the 99xx series comes with a range of device IDs and a variety
782  * of capabilities:
783  *
784  * 9900 has varying capabilities and can cascade to sub-controllers
785  *   (cascading should be purely internal)
786  * 9904 is hardwired with 4 serial ports
787  * 9912 and 9922 are hardwired with 2 serial ports
788  */
pci_netmos_9900_numports(struct pci_dev * dev)789 static int pci_netmos_9900_numports(struct pci_dev *dev)
790 {
791 	unsigned int c = dev->class;
792 	unsigned int pi;
793 	unsigned short sub_serports;
794 
795 	pi = c & 0xff;
796 
797 	if (pi == 2)
798 		return 1;
799 
800 	if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
801 		/* two possibilities: 0x30ps encodes number of parallel and
802 		 * serial ports, or 0x1000 indicates *something*. This is not
803 		 * immediately obvious, since the 2s1p+4s configuration seems
804 		 * to offer all functionality on functions 0..2, while still
805 		 * advertising the same function 3 as the 4s+2s1p config.
806 		 */
807 		sub_serports = dev->subsystem_device & 0xf;
808 		if (sub_serports > 0)
809 			return sub_serports;
810 
811 		pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
812 		return 0;
813 	}
814 
815 	moan_device("unknown NetMos/Mostech program interface", dev);
816 	return 0;
817 }
818 
pci_netmos_init(struct pci_dev * dev)819 static int pci_netmos_init(struct pci_dev *dev)
820 {
821 	/* subdevice 0x00PS means <P> parallel, <S> serial */
822 	unsigned int num_serial = dev->subsystem_device & 0xf;
823 
824 	if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
825 		(dev->device == PCI_DEVICE_ID_NETMOS_9865))
826 		return 0;
827 
828 	if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
829 			dev->subsystem_device == 0x0299)
830 		return 0;
831 
832 	switch (dev->device) { /* FALLTHROUGH on all */
833 	case PCI_DEVICE_ID_NETMOS_9904:
834 	case PCI_DEVICE_ID_NETMOS_9912:
835 	case PCI_DEVICE_ID_NETMOS_9922:
836 	case PCI_DEVICE_ID_NETMOS_9900:
837 		num_serial = pci_netmos_9900_numports(dev);
838 		break;
839 
840 	default:
841 		break;
842 	}
843 
844 	if (num_serial == 0) {
845 		moan_device("unknown NetMos/Mostech device", dev);
846 		return -ENODEV;
847 	}
848 
849 	return num_serial;
850 }
851 
852 /*
853  * These chips are available with optionally one parallel port and up to
854  * two serial ports. Unfortunately they all have the same product id.
855  *
856  * Basic configuration is done over a region of 32 I/O ports. The base
857  * ioport is called INTA or INTC, depending on docs/other drivers.
858  *
859  * The region of the 32 I/O ports is configured in POSIO0R...
860  */
861 
862 /* registers */
863 #define ITE_887x_MISCR		0x9c
864 #define ITE_887x_INTCBAR	0x78
865 #define ITE_887x_UARTBAR	0x7c
866 #define ITE_887x_PS0BAR		0x10
867 #define ITE_887x_POSIO0		0x60
868 
869 /* I/O space size */
870 #define ITE_887x_IOSIZE		32
871 /* I/O space size (bits 26-24; 8 bytes = 011b) */
872 #define ITE_887x_POSIO_IOSIZE_8		(3 << 24)
873 /* I/O space size (bits 26-24; 32 bytes = 101b) */
874 #define ITE_887x_POSIO_IOSIZE_32	(5 << 24)
875 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
876 #define ITE_887x_POSIO_SPEED		(3 << 29)
877 /* enable IO_Space bit */
878 #define ITE_887x_POSIO_ENABLE		(1 << 31)
879 
880 /* inta_addr are the configuration addresses of the ITE */
881 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)882 static int pci_ite887x_init(struct pci_dev *dev)
883 {
884 	int ret, i, type;
885 	struct resource *iobase = NULL;
886 	u32 miscr, uartbar, ioport;
887 
888 	/* search for the base-ioport */
889 	for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
890 		iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
891 								"ite887x");
892 		if (iobase != NULL) {
893 			/* write POSIO0R - speed | size | ioport */
894 			pci_write_config_dword(dev, ITE_887x_POSIO0,
895 				ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
896 				ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
897 			/* write INTCBAR - ioport */
898 			pci_write_config_dword(dev, ITE_887x_INTCBAR,
899 								inta_addr[i]);
900 			ret = inb(inta_addr[i]);
901 			if (ret != 0xff) {
902 				/* ioport connected */
903 				break;
904 			}
905 			release_region(iobase->start, ITE_887x_IOSIZE);
906 		}
907 	}
908 
909 	if (i == ARRAY_SIZE(inta_addr)) {
910 		pci_err(dev, "could not find iobase\n");
911 		return -ENODEV;
912 	}
913 
914 	/* start of undocumented type checking (see parport_pc.c) */
915 	type = inb(iobase->start + 0x18) & 0x0f;
916 
917 	switch (type) {
918 	case 0x2:	/* ITE8871 (1P) */
919 	case 0xa:	/* ITE8875 (1P) */
920 		ret = 0;
921 		break;
922 	case 0xe:	/* ITE8872 (2S1P) */
923 		ret = 2;
924 		break;
925 	case 0x6:	/* ITE8873 (1S) */
926 		ret = 1;
927 		break;
928 	case 0x8:	/* ITE8874 (2S) */
929 		ret = 2;
930 		break;
931 	default:
932 		moan_device("Unknown ITE887x", dev);
933 		ret = -ENODEV;
934 	}
935 
936 	/* configure all serial ports */
937 	for (i = 0; i < ret; i++) {
938 		/* read the I/O port from the device */
939 		pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
940 								&ioport);
941 		ioport &= 0x0000FF00;	/* the actual base address */
942 		pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
943 			ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
944 			ITE_887x_POSIO_IOSIZE_8 | ioport);
945 
946 		/* write the ioport to the UARTBAR */
947 		pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
948 		uartbar &= ~(0xffff << (16 * i));	/* clear half the reg */
949 		uartbar |= (ioport << (16 * i));	/* set the ioport */
950 		pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
951 
952 		/* get current config */
953 		pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
954 		/* disable interrupts (UARTx_Routing[3:0]) */
955 		miscr &= ~(0xf << (12 - 4 * i));
956 		/* activate the UART (UARTx_En) */
957 		miscr |= 1 << (23 - i);
958 		/* write new config with activated UART */
959 		pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
960 	}
961 
962 	if (ret <= 0) {
963 		/* the device has no UARTs if we get here */
964 		release_region(iobase->start, ITE_887x_IOSIZE);
965 	}
966 
967 	return ret;
968 }
969 
pci_ite887x_exit(struct pci_dev * dev)970 static void pci_ite887x_exit(struct pci_dev *dev)
971 {
972 	u32 ioport;
973 	/* the ioport is bit 0-15 in POSIO0R */
974 	pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
975 	ioport &= 0xffff;
976 	release_region(ioport, ITE_887x_IOSIZE);
977 }
978 
979 /*
980  * Oxford Semiconductor Inc.
981  * Check if an OxSemi device is part of the Tornado range of devices.
982  */
983 #define PCI_VENDOR_ID_ENDRUN			0x7401
984 #define PCI_DEVICE_ID_ENDRUN_1588	0xe100
985 
pci_oxsemi_tornado_p(struct pci_dev * dev)986 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
987 {
988 	/* OxSemi Tornado devices are all 0xCxxx */
989 	if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
990 	    (dev->device & 0xf000) != 0xc000)
991 		return false;
992 
993 	/* EndRun devices are all 0xExxx */
994 	if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
995 	    (dev->device & 0xf000) != 0xe000)
996 		return false;
997 
998 	return true;
999 }
1000 
1001 /*
1002  * Determine the number of ports available on a Tornado device.
1003  */
pci_oxsemi_tornado_init(struct pci_dev * dev)1004 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1005 {
1006 	u8 __iomem *p;
1007 	unsigned long deviceID;
1008 	unsigned int  number_uarts = 0;
1009 
1010 	if (!pci_oxsemi_tornado_p(dev))
1011 		return 0;
1012 
1013 	p = pci_iomap(dev, 0, 5);
1014 	if (p == NULL)
1015 		return -ENOMEM;
1016 
1017 	deviceID = ioread32(p);
1018 	/* Tornado device */
1019 	if (deviceID == 0x07000200) {
1020 		number_uarts = ioread8(p + 4);
1021 		pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1022 			number_uarts,
1023 			dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1024 			"EndRun" : "Oxford");
1025 	}
1026 	pci_iounmap(dev, p);
1027 	return number_uarts;
1028 }
1029 
1030 /* Tornado-specific constants for the TCR and CPR registers; see below.  */
1031 #define OXSEMI_TORNADO_TCR_MASK	0xf
1032 #define OXSEMI_TORNADO_CPR_MASK	0x1ff
1033 #define OXSEMI_TORNADO_CPR_MIN	0x008
1034 #define OXSEMI_TORNADO_CPR_DEF	0x10f
1035 
1036 /*
1037  * Determine the oversampling rate, the clock prescaler, and the clock
1038  * divisor for the requested baud rate.  The clock rate is 62.5 MHz,
1039  * which is four times the baud base, and the prescaler increments in
1040  * steps of 1/8.  Therefore to make calculations on integers we need
1041  * to use a scaled clock rate, which is the baud base multiplied by 32
1042  * (or our assumed UART clock rate multiplied by 2).
1043  *
1044  * The allowed oversampling rates are from 4 up to 16 inclusive (values
1045  * from 0 to 3 inclusive map to 16).  Likewise the clock prescaler allows
1046  * values between 1.000 and 63.875 inclusive (operation for values from
1047  * 0.000 to 0.875 has not been specified).  The clock divisor is the usual
1048  * unsigned 16-bit integer.
1049  *
1050  * For the most accurate baud rate we use a table of predetermined
1051  * oversampling rates and clock prescalers that records all possible
1052  * products of the two parameters in the range from 4 up to 255 inclusive,
1053  * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1054  * by 8.  The table is sorted by the decreasing value of the oversampling
1055  * rate and ties are resolved by sorting by the decreasing value of the
1056  * product.  This way preference is given to higher oversampling rates.
1057  *
1058  * We iterate over the table and choose the product of an oversampling
1059  * rate and a clock prescaler that gives the lowest integer division
1060  * result deviation, or if an exact integer divider is found we stop
1061  * looking for it right away.  We do some fixup if the resulting clock
1062  * divisor required would be out of its unsigned 16-bit integer range.
1063  *
1064  * Finally we abuse the supposed fractional part returned to encode the
1065  * 4-bit value of the oversampling rate and the 9-bit value of the clock
1066  * prescaler which will end up in the TCR and CPR/CPR2 registers.
1067  */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1068 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1069 						   unsigned int baud,
1070 						   unsigned int *frac)
1071 {
1072 	static u8 p[][2] = {
1073 		{ 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1074 		{ 16, 10, }, { 16,  9, }, { 16,  8, }, { 15, 17, },
1075 		{ 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1076 		{ 15, 12, }, { 15, 11, }, { 15, 10, }, { 15,  9, },
1077 		{ 15,  8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1078 		{ 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1079 		{ 14,  9, }, { 14,  8, }, { 13, 19, }, { 13, 18, },
1080 		{ 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1081 		{ 13, 10, }, { 13,  9, }, { 13,  8, }, { 12, 19, },
1082 		{ 12, 18, }, { 12, 17, }, { 12, 11, }, { 12,  9, },
1083 		{ 12,  8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1084 		{ 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1085 		{ 11, 11, }, { 11, 10, }, { 11,  9, }, { 11,  8, },
1086 		{ 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1087 		{ 10, 17, }, { 10, 10, }, { 10,  9, }, { 10,  8, },
1088 		{  9, 27, }, {  9, 23, }, {  9, 21, }, {  9, 19, },
1089 		{  9, 18, }, {  9, 17, }, {  9,  9, }, {  9,  8, },
1090 		{  8, 31, }, {  8, 29, }, {  8, 23, }, {  8, 19, },
1091 		{  8, 17, }, {  8,  8, }, {  7, 35, }, {  7, 31, },
1092 		{  7, 29, }, {  7, 25, }, {  7, 23, }, {  7, 21, },
1093 		{  7, 19, }, {  7, 17, }, {  7, 15, }, {  7, 14, },
1094 		{  7, 13, }, {  7, 12, }, {  7, 11, }, {  7, 10, },
1095 		{  7,  9, }, {  7,  8, }, {  6, 41, }, {  6, 37, },
1096 		{  6, 31, }, {  6, 29, }, {  6, 23, }, {  6, 19, },
1097 		{  6, 17, }, {  6, 13, }, {  6, 11, }, {  6, 10, },
1098 		{  6,  9, }, {  6,  8, }, {  5, 67, }, {  5, 47, },
1099 		{  5, 43, }, {  5, 41, }, {  5, 37, }, {  5, 31, },
1100 		{  5, 29, }, {  5, 25, }, {  5, 23, }, {  5, 19, },
1101 		{  5, 17, }, {  5, 15, }, {  5, 13, }, {  5, 11, },
1102 		{  5, 10, }, {  5,  9, }, {  5,  8, }, {  4, 61, },
1103 		{  4, 59, }, {  4, 53, }, {  4, 47, }, {  4, 43, },
1104 		{  4, 41, }, {  4, 37, }, {  4, 31, }, {  4, 29, },
1105 		{  4, 23, }, {  4, 19, }, {  4, 17, }, {  4, 13, },
1106 		{  4,  9, }, {  4,  8, },
1107 	};
1108 	/* Scale the quotient for comparison to get the fractional part.  */
1109 	const unsigned int quot_scale = 65536;
1110 	unsigned int sclk = port->uartclk * 2;
1111 	unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1112 	unsigned int best_squot;
1113 	unsigned int squot;
1114 	unsigned int quot;
1115 	u16 cpr;
1116 	u8 tcr;
1117 	int i;
1118 
1119 	/* Old custom speed handling.  */
1120 	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1121 		unsigned int cust_div = port->custom_divisor;
1122 
1123 		quot = cust_div & UART_DIV_MAX;
1124 		tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1125 		cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1126 		if (cpr < OXSEMI_TORNADO_CPR_MIN)
1127 			cpr = OXSEMI_TORNADO_CPR_DEF;
1128 	} else {
1129 		best_squot = quot_scale;
1130 		for (i = 0; i < ARRAY_SIZE(p); i++) {
1131 			unsigned int spre;
1132 			unsigned int srem;
1133 			u8 cp;
1134 			u8 tc;
1135 
1136 			tc = p[i][0];
1137 			cp = p[i][1];
1138 			spre = tc * cp;
1139 
1140 			srem = sdiv % spre;
1141 			if (srem > spre / 2)
1142 				srem = spre - srem;
1143 			squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1144 
1145 			if (srem == 0) {
1146 				tcr = tc;
1147 				cpr = cp;
1148 				quot = sdiv / spre;
1149 				break;
1150 			} else if (squot < best_squot) {
1151 				best_squot = squot;
1152 				tcr = tc;
1153 				cpr = cp;
1154 				quot = DIV_ROUND_CLOSEST(sdiv, spre);
1155 			}
1156 		}
1157 		while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1158 		       quot % 2 == 0) {
1159 			quot >>= 1;
1160 			tcr <<= 1;
1161 		}
1162 		while (quot > UART_DIV_MAX) {
1163 			if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1164 				quot >>= 1;
1165 				tcr <<= 1;
1166 			} else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1167 				quot >>= 1;
1168 				cpr <<= 1;
1169 			} else {
1170 				quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1171 				cpr = OXSEMI_TORNADO_CPR_MASK;
1172 			}
1173 		}
1174 	}
1175 
1176 	*frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1177 	return quot;
1178 }
1179 
1180 /*
1181  * Set the oversampling rate in the transmitter clock cycle register (TCR),
1182  * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1183  * the clock divisor in the divisor latch (DLL and DLM).  Note that for
1184  * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1185  * has to be written first, followed by CPR2, which occupies the location
1186  * of CKS used with earlier UART designs.
1187  */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1188 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1189 					   unsigned int baud,
1190 					   unsigned int quot,
1191 					   unsigned int quot_frac)
1192 {
1193 	struct uart_8250_port *up = up_to_u8250p(port);
1194 	u8 cpr2 = quot_frac >> 16;
1195 	u8 cpr = quot_frac >> 8;
1196 	u8 tcr = quot_frac;
1197 
1198 	serial_icr_write(up, UART_TCR, tcr);
1199 	serial_icr_write(up, UART_CPR, cpr);
1200 	serial_icr_write(up, UART_CKS, cpr2);
1201 	serial8250_do_set_divisor(port, baud, quot, 0);
1202 }
1203 
1204 /*
1205  * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1206  * generator prescaler (CPR and CPR2).  Otherwise no prescaler would be used.
1207  */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1208 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1209 					 unsigned int mctrl)
1210 {
1211 	struct uart_8250_port *up = up_to_u8250p(port);
1212 
1213 	up->mcr |= UART_MCR_CLKSEL;
1214 	serial8250_do_set_mctrl(port, mctrl);
1215 }
1216 
1217 /*
1218  * We require EFR features for clock programming, so set UPF_FULL_PROBE
1219  * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1220  */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1221 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1222 				    const struct pciserial_board *board,
1223 				    struct uart_8250_port *up, int idx)
1224 {
1225 	struct pci_dev *dev = priv->dev;
1226 
1227 	if (pci_oxsemi_tornado_p(dev)) {
1228 		up->port.flags |= UPF_FULL_PROBE;
1229 		up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1230 		up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1231 		up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1232 	}
1233 
1234 	return pci_default_setup(priv, board, up, idx);
1235 }
1236 
1237 #define QPCR_TEST_FOR1		0x3F
1238 #define QPCR_TEST_GET1		0x00
1239 #define QPCR_TEST_FOR2		0x40
1240 #define QPCR_TEST_GET2		0x40
1241 #define QPCR_TEST_FOR3		0x80
1242 #define QPCR_TEST_GET3		0x40
1243 #define QPCR_TEST_FOR4		0xC0
1244 #define QPCR_TEST_GET4		0x80
1245 
1246 #define QOPR_CLOCK_X1		0x0000
1247 #define QOPR_CLOCK_X2		0x0001
1248 #define QOPR_CLOCK_X4		0x0002
1249 #define QOPR_CLOCK_X8		0x0003
1250 #define QOPR_CLOCK_RATE_MASK	0x0003
1251 
1252 /* Quatech devices have their own extra interface features */
1253 static struct pci_device_id quatech_cards[] = {
1254 	{ PCI_DEVICE_DATA(QUATECH, QSC100,   1) },
1255 	{ PCI_DEVICE_DATA(QUATECH, DSC100,   1) },
1256 	{ PCI_DEVICE_DATA(QUATECH, DSC100E,  0) },
1257 	{ PCI_DEVICE_DATA(QUATECH, DSC200,   1) },
1258 	{ PCI_DEVICE_DATA(QUATECH, DSC200E,  0) },
1259 	{ PCI_DEVICE_DATA(QUATECH, ESC100D,  1) },
1260 	{ PCI_DEVICE_DATA(QUATECH, ESC100M,  1) },
1261 	{ PCI_DEVICE_DATA(QUATECH, QSCP100,  1) },
1262 	{ PCI_DEVICE_DATA(QUATECH, DSCP100,  1) },
1263 	{ PCI_DEVICE_DATA(QUATECH, QSCP200,  1) },
1264 	{ PCI_DEVICE_DATA(QUATECH, DSCP200,  1) },
1265 	{ PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1266 	{ PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1267 	{ PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1268 	{ PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1269 	{ PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1270 	{ PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1271 	{ PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1272 	{ PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1273 	{ 0, }
1274 };
1275 
pci_quatech_rqopr(struct uart_8250_port * port)1276 static int pci_quatech_rqopr(struct uart_8250_port *port)
1277 {
1278 	unsigned long base = port->port.iobase;
1279 	u8 LCR, val;
1280 
1281 	LCR = inb(base + UART_LCR);
1282 	outb(0xBF, base + UART_LCR);
1283 	val = inb(base + UART_SCR);
1284 	outb(LCR, base + UART_LCR);
1285 	return val;
1286 }
1287 
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1288 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1289 {
1290 	unsigned long base = port->port.iobase;
1291 	u8 LCR;
1292 
1293 	LCR = inb(base + UART_LCR);
1294 	outb(0xBF, base + UART_LCR);
1295 	inb(base + UART_SCR);
1296 	outb(qopr, base + UART_SCR);
1297 	outb(LCR, base + UART_LCR);
1298 }
1299 
pci_quatech_rqmcr(struct uart_8250_port * port)1300 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1301 {
1302 	unsigned long base = port->port.iobase;
1303 	u8 LCR, val, qmcr;
1304 
1305 	LCR = inb(base + UART_LCR);
1306 	outb(0xBF, base + UART_LCR);
1307 	val = inb(base + UART_SCR);
1308 	outb(val | 0x10, base + UART_SCR);
1309 	qmcr = inb(base + UART_MCR);
1310 	outb(val, base + UART_SCR);
1311 	outb(LCR, base + UART_LCR);
1312 
1313 	return qmcr;
1314 }
1315 
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1316 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1317 {
1318 	unsigned long base = port->port.iobase;
1319 	u8 LCR, val;
1320 
1321 	LCR = inb(base + UART_LCR);
1322 	outb(0xBF, base + UART_LCR);
1323 	val = inb(base + UART_SCR);
1324 	outb(val | 0x10, base + UART_SCR);
1325 	outb(qmcr, base + UART_MCR);
1326 	outb(val, base + UART_SCR);
1327 	outb(LCR, base + UART_LCR);
1328 }
1329 
pci_quatech_has_qmcr(struct uart_8250_port * port)1330 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1331 {
1332 	unsigned long base = port->port.iobase;
1333 	u8 LCR, val;
1334 
1335 	LCR = inb(base + UART_LCR);
1336 	outb(0xBF, base + UART_LCR);
1337 	val = inb(base + UART_SCR);
1338 	if (val & 0x20) {
1339 		outb(0x80, UART_LCR);
1340 		if (!(inb(UART_SCR) & 0x20)) {
1341 			outb(LCR, base + UART_LCR);
1342 			return 1;
1343 		}
1344 	}
1345 	return 0;
1346 }
1347 
pci_quatech_test(struct uart_8250_port * port)1348 static int pci_quatech_test(struct uart_8250_port *port)
1349 {
1350 	u8 reg, qopr;
1351 
1352 	qopr = pci_quatech_rqopr(port);
1353 	pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1354 	reg = pci_quatech_rqopr(port) & 0xC0;
1355 	if (reg != QPCR_TEST_GET1)
1356 		return -EINVAL;
1357 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1358 	reg = pci_quatech_rqopr(port) & 0xC0;
1359 	if (reg != QPCR_TEST_GET2)
1360 		return -EINVAL;
1361 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1362 	reg = pci_quatech_rqopr(port) & 0xC0;
1363 	if (reg != QPCR_TEST_GET3)
1364 		return -EINVAL;
1365 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1366 	reg = pci_quatech_rqopr(port) & 0xC0;
1367 	if (reg != QPCR_TEST_GET4)
1368 		return -EINVAL;
1369 
1370 	pci_quatech_wqopr(port, qopr);
1371 	return 0;
1372 }
1373 
pci_quatech_clock(struct uart_8250_port * port)1374 static int pci_quatech_clock(struct uart_8250_port *port)
1375 {
1376 	u8 qopr, reg, set;
1377 	unsigned long clock;
1378 
1379 	if (pci_quatech_test(port) < 0)
1380 		return 1843200;
1381 
1382 	qopr = pci_quatech_rqopr(port);
1383 
1384 	pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1385 	reg = pci_quatech_rqopr(port);
1386 	if (reg & QOPR_CLOCK_X8) {
1387 		clock = 1843200;
1388 		goto out;
1389 	}
1390 	pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1391 	reg = pci_quatech_rqopr(port);
1392 	if (!(reg & QOPR_CLOCK_X8)) {
1393 		clock = 1843200;
1394 		goto out;
1395 	}
1396 	reg &= QOPR_CLOCK_X8;
1397 	if (reg == QOPR_CLOCK_X2) {
1398 		clock =  3685400;
1399 		set = QOPR_CLOCK_X2;
1400 	} else if (reg == QOPR_CLOCK_X4) {
1401 		clock = 7372800;
1402 		set = QOPR_CLOCK_X4;
1403 	} else if (reg == QOPR_CLOCK_X8) {
1404 		clock = 14745600;
1405 		set = QOPR_CLOCK_X8;
1406 	} else {
1407 		clock = 1843200;
1408 		set = QOPR_CLOCK_X1;
1409 	}
1410 	qopr &= ~QOPR_CLOCK_RATE_MASK;
1411 	qopr |= set;
1412 
1413 out:
1414 	pci_quatech_wqopr(port, qopr);
1415 	return clock;
1416 }
1417 
pci_quatech_rs422(struct uart_8250_port * port)1418 static int pci_quatech_rs422(struct uart_8250_port *port)
1419 {
1420 	u8 qmcr;
1421 	int rs422 = 0;
1422 
1423 	if (!pci_quatech_has_qmcr(port))
1424 		return 0;
1425 	qmcr = pci_quatech_rqmcr(port);
1426 	pci_quatech_wqmcr(port, 0xFF);
1427 	if (pci_quatech_rqmcr(port))
1428 		rs422 = 1;
1429 	pci_quatech_wqmcr(port, qmcr);
1430 	return rs422;
1431 }
1432 
pci_quatech_init(struct pci_dev * dev)1433 static int pci_quatech_init(struct pci_dev *dev)
1434 {
1435 	const struct pci_device_id *match;
1436 	bool amcc = false;
1437 
1438 	match = pci_match_id(quatech_cards, dev);
1439 	if (match)
1440 		amcc = match->driver_data;
1441 	else
1442 		pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1443 
1444 	if (amcc) {
1445 		unsigned long base = pci_resource_start(dev, 0);
1446 		if (base) {
1447 			u32 tmp;
1448 
1449 			outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1450 			tmp = inl(base + 0x3c);
1451 			outl(tmp | 0x01000000, base + 0x3c);
1452 			outl(tmp & ~0x01000000, base + 0x3c);
1453 		}
1454 	}
1455 	return 0;
1456 }
1457 
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1458 static int pci_quatech_setup(struct serial_private *priv,
1459 		  const struct pciserial_board *board,
1460 		  struct uart_8250_port *port, int idx)
1461 {
1462 	/* Needed by pci_quatech calls below */
1463 	port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1464 	/* Set up the clocking */
1465 	port->port.uartclk = pci_quatech_clock(port);
1466 	/* For now just warn about RS422 */
1467 	if (pci_quatech_rs422(port))
1468 		pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1469 	return pci_default_setup(priv, board, port, idx);
1470 }
1471 
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1472 static int pci_default_setup(struct serial_private *priv,
1473 		  const struct pciserial_board *board,
1474 		  struct uart_8250_port *port, int idx)
1475 {
1476 	unsigned int bar, offset = board->first_offset, maxnr;
1477 
1478 	bar = FL_GET_BASE(board->flags);
1479 	if (board->flags & FL_BASE_BARS)
1480 		bar += idx;
1481 	else
1482 		offset += idx * board->uart_offset;
1483 
1484 	maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1485 		(board->reg_shift + 3);
1486 
1487 	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1488 		return 1;
1489 
1490 	return setup_port(priv, port, bar, offset, board->reg_shift);
1491 }
1492 
1493 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1494 ce4100_serial_setup(struct serial_private *priv,
1495 		  const struct pciserial_board *board,
1496 		  struct uart_8250_port *port, int idx)
1497 {
1498 	int ret;
1499 
1500 	ret = setup_port(priv, port, idx, 0, board->reg_shift);
1501 	port->port.iotype = UPIO_MEM32;
1502 	port->port.type = PORT_XSCALE;
1503 	port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1504 	port->port.regshift = 2;
1505 
1506 	return ret;
1507 }
1508 
1509 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1510 pci_omegapci_setup(struct serial_private *priv,
1511 		      const struct pciserial_board *board,
1512 		      struct uart_8250_port *port, int idx)
1513 {
1514 	return setup_port(priv, port, 2, idx * 8, 0);
1515 }
1516 
1517 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1518 pci_brcm_trumanage_setup(struct serial_private *priv,
1519 			 const struct pciserial_board *board,
1520 			 struct uart_8250_port *port, int idx)
1521 {
1522 	int ret = pci_default_setup(priv, board, port, idx);
1523 
1524 	port->port.type = PORT_BRCM_TRUMANAGE;
1525 	port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1526 	return ret;
1527 }
1528 
1529 /* RTS will control by MCR if this bit is 0 */
1530 #define FINTEK_RTS_CONTROL_BY_HW	BIT(4)
1531 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1532 #define FINTEK_RTS_INVERT		BIT(5)
1533 
1534 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1535 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1536 			       struct serial_rs485 *rs485)
1537 {
1538 	struct pci_dev *pci_dev = to_pci_dev(port->dev);
1539 	u8 setting;
1540 	u8 *index = (u8 *) port->private_data;
1541 
1542 	pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1543 
1544 	if (rs485->flags & SER_RS485_ENABLED) {
1545 		/* Enable RTS H/W control mode */
1546 		setting |= FINTEK_RTS_CONTROL_BY_HW;
1547 
1548 		if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1549 			/* RTS driving high on TX */
1550 			setting &= ~FINTEK_RTS_INVERT;
1551 		} else {
1552 			/* RTS driving low on TX */
1553 			setting |= FINTEK_RTS_INVERT;
1554 		}
1555 	} else {
1556 		/* Disable RTS H/W control mode */
1557 		setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1558 	}
1559 
1560 	pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1561 
1562 	return 0;
1563 }
1564 
1565 static const struct serial_rs485 pci_fintek_rs485_supported = {
1566 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1567 	/* F81504/508/512 does not support RTS delay before or after send */
1568 };
1569 
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1570 static int pci_fintek_setup(struct serial_private *priv,
1571 			    const struct pciserial_board *board,
1572 			    struct uart_8250_port *port, int idx)
1573 {
1574 	struct pci_dev *pdev = priv->dev;
1575 	u8 *data;
1576 	u8 config_base;
1577 	u16 iobase;
1578 
1579 	config_base = 0x40 + 0x08 * idx;
1580 
1581 	/* Get the io address from configuration space */
1582 	pci_read_config_word(pdev, config_base + 4, &iobase);
1583 
1584 	pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1585 
1586 	port->port.iotype = UPIO_PORT;
1587 	port->port.iobase = iobase;
1588 	port->port.rs485_config = pci_fintek_rs485_config;
1589 	port->port.rs485_supported = pci_fintek_rs485_supported;
1590 
1591 	data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1592 	if (!data)
1593 		return -ENOMEM;
1594 
1595 	/* preserve index in PCI configuration space */
1596 	*data = idx;
1597 	port->port.private_data = data;
1598 
1599 	return 0;
1600 }
1601 
pci_fintek_init(struct pci_dev * dev)1602 static int pci_fintek_init(struct pci_dev *dev)
1603 {
1604 	unsigned long iobase;
1605 	u32 max_port, i;
1606 	resource_size_t bar_data[3];
1607 	u8 config_base;
1608 	struct serial_private *priv = pci_get_drvdata(dev);
1609 
1610 	if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1611 			!(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1612 			!(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1613 		return -ENODEV;
1614 
1615 	switch (dev->device) {
1616 	case 0x1104: /* 4 ports */
1617 	case 0x1108: /* 8 ports */
1618 		max_port = dev->device & 0xff;
1619 		break;
1620 	case 0x1112: /* 12 ports */
1621 		max_port = 12;
1622 		break;
1623 	default:
1624 		return -EINVAL;
1625 	}
1626 
1627 	/* Get the io address dispatch from the BIOS */
1628 	bar_data[0] = pci_resource_start(dev, 5);
1629 	bar_data[1] = pci_resource_start(dev, 4);
1630 	bar_data[2] = pci_resource_start(dev, 3);
1631 
1632 	for (i = 0; i < max_port; ++i) {
1633 		/* UART0 configuration offset start from 0x40 */
1634 		config_base = 0x40 + 0x08 * i;
1635 
1636 		/* Calculate Real IO Port */
1637 		iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1638 
1639 		/* Enable UART I/O port */
1640 		pci_write_config_byte(dev, config_base + 0x00, 0x01);
1641 
1642 		/* Select 128-byte FIFO and 8x FIFO threshold */
1643 		pci_write_config_byte(dev, config_base + 0x01, 0x33);
1644 
1645 		/* LSB UART */
1646 		pci_write_config_byte(dev, config_base + 0x04,
1647 				(u8)(iobase & 0xff));
1648 
1649 		/* MSB UART */
1650 		pci_write_config_byte(dev, config_base + 0x05,
1651 				(u8)((iobase & 0xff00) >> 8));
1652 
1653 		pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1654 
1655 		if (!priv) {
1656 			/* First init without port data
1657 			 * force init to RS232 Mode
1658 			 */
1659 			pci_write_config_byte(dev, config_base + 0x07, 0x01);
1660 		}
1661 	}
1662 
1663 	return max_port;
1664 }
1665 
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1666 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1667 {
1668 	struct f815xxa_data *data = p->private_data;
1669 	unsigned long flags;
1670 
1671 	spin_lock_irqsave(&data->lock, flags);
1672 	writeb(value, p->membase + offset);
1673 	readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1674 	spin_unlock_irqrestore(&data->lock, flags);
1675 }
1676 
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1677 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1678 			    const struct pciserial_board *board,
1679 			    struct uart_8250_port *port, int idx)
1680 {
1681 	struct pci_dev *pdev = priv->dev;
1682 	struct f815xxa_data *data;
1683 
1684 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1685 	if (!data)
1686 		return -ENOMEM;
1687 
1688 	data->idx = idx;
1689 	spin_lock_init(&data->lock);
1690 
1691 	port->port.private_data = data;
1692 	port->port.iotype = UPIO_MEM;
1693 	port->port.flags |= UPF_IOREMAP;
1694 	port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1695 	port->port.serial_out = f815xxa_mem_serial_out;
1696 
1697 	return 0;
1698 }
1699 
pci_fintek_f815xxa_init(struct pci_dev * dev)1700 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1701 {
1702 	u32 max_port, i;
1703 	int config_base;
1704 
1705 	if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1706 		return -ENODEV;
1707 
1708 	switch (dev->device) {
1709 	case 0x1204: /* 4 ports */
1710 	case 0x1208: /* 8 ports */
1711 		max_port = dev->device & 0xff;
1712 		break;
1713 	case 0x1212: /* 12 ports */
1714 		max_port = 12;
1715 		break;
1716 	default:
1717 		return -EINVAL;
1718 	}
1719 
1720 	/* Set to mmio decode */
1721 	pci_write_config_byte(dev, 0x209, 0x40);
1722 
1723 	for (i = 0; i < max_port; ++i) {
1724 		/* UART0 configuration offset start from 0x2A0 */
1725 		config_base = 0x2A0 + 0x08 * i;
1726 
1727 		/* Select 128-byte FIFO and 8x FIFO threshold */
1728 		pci_write_config_byte(dev, config_base + 0x01, 0x33);
1729 
1730 		/* Enable UART I/O port */
1731 		pci_write_config_byte(dev, config_base + 0, 0x01);
1732 	}
1733 
1734 	return max_port;
1735 }
1736 
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1737 static int skip_tx_en_setup(struct serial_private *priv,
1738 			const struct pciserial_board *board,
1739 			struct uart_8250_port *port, int idx)
1740 {
1741 	port->port.quirks |= UPQ_NO_TXEN_TEST;
1742 	pci_dbg(priv->dev,
1743 		"serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1744 		priv->dev->vendor, priv->dev->device,
1745 		priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1746 
1747 	return pci_default_setup(priv, board, port, idx);
1748 }
1749 
kt_handle_break(struct uart_port * p)1750 static void kt_handle_break(struct uart_port *p)
1751 {
1752 	struct uart_8250_port *up = up_to_u8250p(p);
1753 	/*
1754 	 * On receipt of a BI, serial device in Intel ME (Intel
1755 	 * management engine) needs to have its fifos cleared for sane
1756 	 * SOL (Serial Over Lan) output.
1757 	 */
1758 	serial8250_clear_and_reinit_fifos(up);
1759 }
1760 
kt_serial_in(struct uart_port * p,int offset)1761 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1762 {
1763 	struct uart_8250_port *up = up_to_u8250p(p);
1764 	unsigned int val;
1765 
1766 	/*
1767 	 * When the Intel ME (management engine) gets reset its serial
1768 	 * port registers could return 0 momentarily.  Functions like
1769 	 * serial8250_console_write, read and save the IER, perform
1770 	 * some operation and then restore it.  In order to avoid
1771 	 * setting IER register inadvertently to 0, if the value read
1772 	 * is 0, double check with ier value in uart_8250_port and use
1773 	 * that instead.  up->ier should be the same value as what is
1774 	 * currently configured.
1775 	 */
1776 	val = inb(p->iobase + offset);
1777 	if (offset == UART_IER) {
1778 		if (val == 0)
1779 			val = up->ier;
1780 	}
1781 	return val;
1782 }
1783 
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1784 static int kt_serial_setup(struct serial_private *priv,
1785 			   const struct pciserial_board *board,
1786 			   struct uart_8250_port *port, int idx)
1787 {
1788 	port->port.flags |= UPF_BUG_THRE;
1789 	port->port.serial_in = kt_serial_in;
1790 	port->port.handle_break = kt_handle_break;
1791 	return skip_tx_en_setup(priv, board, port, idx);
1792 }
1793 
pci_eg20t_init(struct pci_dev * dev)1794 static int pci_eg20t_init(struct pci_dev *dev)
1795 {
1796 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1797 	return -ENODEV;
1798 #else
1799 	return 0;
1800 #endif
1801 }
1802 
1803 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1804 pci_wch_ch353_setup(struct serial_private *priv,
1805 		    const struct pciserial_board *board,
1806 		    struct uart_8250_port *port, int idx)
1807 {
1808 	port->port.flags |= UPF_FIXED_TYPE;
1809 	port->port.type = PORT_16550A;
1810 	return pci_default_setup(priv, board, port, idx);
1811 }
1812 
1813 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1814 pci_wch_ch355_setup(struct serial_private *priv,
1815 		const struct pciserial_board *board,
1816 		struct uart_8250_port *port, int idx)
1817 {
1818 	port->port.flags |= UPF_FIXED_TYPE;
1819 	port->port.type = PORT_16550A;
1820 	return pci_default_setup(priv, board, port, idx);
1821 }
1822 
1823 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1824 pci_wch_ch38x_setup(struct serial_private *priv,
1825 		    const struct pciserial_board *board,
1826 		    struct uart_8250_port *port, int idx)
1827 {
1828 	port->port.flags |= UPF_FIXED_TYPE;
1829 	port->port.type = PORT_16850;
1830 	return pci_default_setup(priv, board, port, idx);
1831 }
1832 
1833 
1834 #define CH384_XINT_ENABLE_REG   0xEB
1835 #define CH384_XINT_ENABLE_BIT   0x02
1836 
pci_wch_ch38x_init(struct pci_dev * dev)1837 static int pci_wch_ch38x_init(struct pci_dev *dev)
1838 {
1839 	int max_port;
1840 	unsigned long iobase;
1841 
1842 
1843 	switch (dev->device) {
1844 	case 0x3853: /* 8 ports */
1845 		max_port = 8;
1846 		break;
1847 	default:
1848 		return -EINVAL;
1849 	}
1850 
1851 	iobase = pci_resource_start(dev, 0);
1852 	outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1853 
1854 	return max_port;
1855 }
1856 
pci_wch_ch38x_exit(struct pci_dev * dev)1857 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1858 {
1859 	unsigned long iobase;
1860 
1861 	iobase = pci_resource_start(dev, 0);
1862 	outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1863 }
1864 
1865 
1866 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1867 pci_sunix_setup(struct serial_private *priv,
1868 		const struct pciserial_board *board,
1869 		struct uart_8250_port *port, int idx)
1870 {
1871 	int bar;
1872 	int offset;
1873 
1874 	port->port.flags |= UPF_FIXED_TYPE;
1875 	port->port.type = PORT_SUNIX;
1876 
1877 	if (idx < 4) {
1878 		bar = 0;
1879 		offset = idx * board->uart_offset;
1880 	} else {
1881 		bar = 1;
1882 		idx -= 4;
1883 		idx = div_s64_rem(idx, 4, &offset);
1884 		offset = idx * 64 + offset * board->uart_offset;
1885 	}
1886 
1887 	return setup_port(priv, port, bar, offset, 0);
1888 }
1889 
1890 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1891 pci_moxa_setup(struct serial_private *priv,
1892 		const struct pciserial_board *board,
1893 		struct uart_8250_port *port, int idx)
1894 {
1895 	unsigned int bar = FL_GET_BASE(board->flags);
1896 	int offset;
1897 
1898 	if (board->num_ports == 4 && idx == 3)
1899 		offset = 7 * board->uart_offset;
1900 	else
1901 		offset = idx * board->uart_offset;
1902 
1903 	return setup_port(priv, port, bar, offset, 0);
1904 }
1905 
1906 #define PCI_VENDOR_ID_SBSMODULARIO	0x124B
1907 #define PCI_SUBVENDOR_ID_SBSMODULARIO	0x124B
1908 #define PCI_DEVICE_ID_OCTPRO		0x0001
1909 #define PCI_SUBDEVICE_ID_OCTPRO232	0x0108
1910 #define PCI_SUBDEVICE_ID_OCTPRO422	0x0208
1911 #define PCI_SUBDEVICE_ID_POCTAL232	0x0308
1912 #define PCI_SUBDEVICE_ID_POCTAL422	0x0408
1913 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00	0x2500
1914 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30	0x2530
1915 #define PCI_VENDOR_ID_ADVANTECH		0x13fe
1916 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1917 #define PCI_DEVICE_ID_ADVANTECH_PCI1600	0x1600
1918 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611	0x1611
1919 #define PCI_DEVICE_ID_ADVANTECH_PCI3620	0x3620
1920 #define PCI_DEVICE_ID_ADVANTECH_PCI3618	0x3618
1921 #define PCI_DEVICE_ID_ADVANTECH_PCIf618	0xf618
1922 #define PCI_DEVICE_ID_TITAN_200I	0x8028
1923 #define PCI_DEVICE_ID_TITAN_400I	0x8048
1924 #define PCI_DEVICE_ID_TITAN_800I	0x8088
1925 #define PCI_DEVICE_ID_TITAN_800EH	0xA007
1926 #define PCI_DEVICE_ID_TITAN_800EHB	0xA008
1927 #define PCI_DEVICE_ID_TITAN_400EH	0xA009
1928 #define PCI_DEVICE_ID_TITAN_100E	0xA010
1929 #define PCI_DEVICE_ID_TITAN_200E	0xA012
1930 #define PCI_DEVICE_ID_TITAN_400E	0xA013
1931 #define PCI_DEVICE_ID_TITAN_800E	0xA014
1932 #define PCI_DEVICE_ID_TITAN_200EI	0xA016
1933 #define PCI_DEVICE_ID_TITAN_200EISI	0xA017
1934 #define PCI_DEVICE_ID_TITAN_200V3	0xA306
1935 #define PCI_DEVICE_ID_TITAN_400V3	0xA310
1936 #define PCI_DEVICE_ID_TITAN_410V3	0xA312
1937 #define PCI_DEVICE_ID_TITAN_800V3	0xA314
1938 #define PCI_DEVICE_ID_TITAN_800V3B	0xA315
1939 #define PCI_DEVICE_ID_OXSEMI_16PCI958	0x9538
1940 #define PCIE_DEVICE_ID_NEO_2_OX_IBM	0x00F6
1941 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA	0xc001
1942 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1943 #define PCI_VENDOR_ID_WCH		0x4348
1944 #define PCI_DEVICE_ID_WCH_CH352_2S	0x3253
1945 #define PCI_DEVICE_ID_WCH_CH353_4S	0x3453
1946 #define PCI_DEVICE_ID_WCH_CH353_2S1PF	0x5046
1947 #define PCI_DEVICE_ID_WCH_CH353_1S1P	0x5053
1948 #define PCI_DEVICE_ID_WCH_CH353_2S1P	0x7053
1949 #define PCI_DEVICE_ID_WCH_CH355_4S	0x7173
1950 #define PCI_VENDOR_ID_AGESTAR		0x5372
1951 #define PCI_DEVICE_ID_AGESTAR_9375	0x6872
1952 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1953 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1954 
1955 #define PCIE_VENDOR_ID_WCH		0x1c00
1956 #define PCIE_DEVICE_ID_WCH_CH382_2S1P	0x3250
1957 #define PCIE_DEVICE_ID_WCH_CH384_4S	0x3470
1958 #define PCIE_DEVICE_ID_WCH_CH384_8S	0x3853
1959 #define PCIE_DEVICE_ID_WCH_CH382_2S	0x3253
1960 
1961 #define	PCI_DEVICE_ID_MOXA_CP102E	0x1024
1962 #define	PCI_DEVICE_ID_MOXA_CP102EL	0x1025
1963 #define	PCI_DEVICE_ID_MOXA_CP104EL_A	0x1045
1964 #define	PCI_DEVICE_ID_MOXA_CP114EL	0x1144
1965 #define	PCI_DEVICE_ID_MOXA_CP116E_A_A	0x1160
1966 #define	PCI_DEVICE_ID_MOXA_CP116E_A_B	0x1161
1967 #define	PCI_DEVICE_ID_MOXA_CP118EL_A	0x1182
1968 #define	PCI_DEVICE_ID_MOXA_CP118E_A_I	0x1183
1969 #define	PCI_DEVICE_ID_MOXA_CP132EL	0x1322
1970 #define	PCI_DEVICE_ID_MOXA_CP134EL_A	0x1342
1971 #define	PCI_DEVICE_ID_MOXA_CP138E_A	0x1381
1972 #define	PCI_DEVICE_ID_MOXA_CP168EL_A	0x1683
1973 
1974 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1975 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584	0x1584
1976 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588	0x1588
1977 
1978 /*
1979  * Master list of serial port init/setup/exit quirks.
1980  * This does not describe the general nature of the port.
1981  * (ie, baud base, number and location of ports, etc)
1982  *
1983  * This list is ordered alphabetically by vendor then device.
1984  * Specific entries must come before more generic entries.
1985  */
1986 static struct pci_serial_quirk pci_serial_quirks[] = {
1987 	/*
1988 	* ADDI-DATA GmbH communication cards <info@addi-data.com>
1989 	*/
1990 	{
1991 		.vendor         = PCI_VENDOR_ID_AMCC,
1992 		.device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1993 		.subvendor      = PCI_ANY_ID,
1994 		.subdevice      = PCI_ANY_ID,
1995 		.setup          = addidata_apci7800_setup,
1996 	},
1997 	/*
1998 	 * AFAVLAB cards - these may be called via parport_serial
1999 	 *  It is not clear whether this applies to all products.
2000 	 */
2001 	{
2002 		.vendor		= PCI_VENDOR_ID_AFAVLAB,
2003 		.device		= PCI_ANY_ID,
2004 		.subvendor	= PCI_ANY_ID,
2005 		.subdevice	= PCI_ANY_ID,
2006 		.setup		= afavlab_setup,
2007 	},
2008 	/*
2009 	 * HP Diva
2010 	 */
2011 	{
2012 		.vendor		= PCI_VENDOR_ID_HP,
2013 		.device		= PCI_DEVICE_ID_HP_DIVA,
2014 		.subvendor	= PCI_ANY_ID,
2015 		.subdevice	= PCI_ANY_ID,
2016 		.init		= pci_hp_diva_init,
2017 		.setup		= pci_hp_diva_setup,
2018 	},
2019 	/*
2020 	 * HPE PCI serial device
2021 	 */
2022 	{
2023 		.vendor         = PCI_VENDOR_ID_HP_3PAR,
2024 		.device         = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2025 		.subvendor      = PCI_ANY_ID,
2026 		.subdevice      = PCI_ANY_ID,
2027 		.setup		= pci_hp_diva_setup,
2028 	},
2029 	/*
2030 	 * Intel
2031 	 */
2032 	{
2033 		.vendor		= PCI_VENDOR_ID_INTEL,
2034 		.device		= PCI_DEVICE_ID_INTEL_80960_RP,
2035 		.subvendor	= 0xe4bf,
2036 		.subdevice	= PCI_ANY_ID,
2037 		.init		= pci_inteli960ni_init,
2038 		.setup		= pci_default_setup,
2039 	},
2040 	{
2041 		.vendor		= PCI_VENDOR_ID_INTEL,
2042 		.device		= PCI_DEVICE_ID_INTEL_8257X_SOL,
2043 		.subvendor	= PCI_ANY_ID,
2044 		.subdevice	= PCI_ANY_ID,
2045 		.setup		= skip_tx_en_setup,
2046 	},
2047 	{
2048 		.vendor		= PCI_VENDOR_ID_INTEL,
2049 		.device		= PCI_DEVICE_ID_INTEL_82573L_SOL,
2050 		.subvendor	= PCI_ANY_ID,
2051 		.subdevice	= PCI_ANY_ID,
2052 		.setup		= skip_tx_en_setup,
2053 	},
2054 	{
2055 		.vendor		= PCI_VENDOR_ID_INTEL,
2056 		.device		= PCI_DEVICE_ID_INTEL_82573E_SOL,
2057 		.subvendor	= PCI_ANY_ID,
2058 		.subdevice	= PCI_ANY_ID,
2059 		.setup		= skip_tx_en_setup,
2060 	},
2061 	{
2062 		.vendor		= PCI_VENDOR_ID_INTEL,
2063 		.device		= PCI_DEVICE_ID_INTEL_CE4100_UART,
2064 		.subvendor	= PCI_ANY_ID,
2065 		.subdevice	= PCI_ANY_ID,
2066 		.setup		= ce4100_serial_setup,
2067 	},
2068 	{
2069 		.vendor		= PCI_VENDOR_ID_INTEL,
2070 		.device		= PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2071 		.subvendor	= PCI_ANY_ID,
2072 		.subdevice	= PCI_ANY_ID,
2073 		.setup		= kt_serial_setup,
2074 	},
2075 	/*
2076 	 * ITE
2077 	 */
2078 	{
2079 		.vendor		= PCI_VENDOR_ID_ITE,
2080 		.device		= PCI_DEVICE_ID_ITE_8872,
2081 		.subvendor	= PCI_ANY_ID,
2082 		.subdevice	= PCI_ANY_ID,
2083 		.init		= pci_ite887x_init,
2084 		.setup		= pci_default_setup,
2085 		.exit		= pci_ite887x_exit,
2086 	},
2087 	/*
2088 	 * National Instruments
2089 	 */
2090 	{
2091 		.vendor		= PCI_VENDOR_ID_NI,
2092 		.device		= PCI_DEVICE_ID_NI_PCI23216,
2093 		.subvendor	= PCI_ANY_ID,
2094 		.subdevice	= PCI_ANY_ID,
2095 		.init		= pci_ni8420_init,
2096 		.setup		= pci_default_setup,
2097 		.exit		= pci_ni8420_exit,
2098 	},
2099 	{
2100 		.vendor		= PCI_VENDOR_ID_NI,
2101 		.device		= PCI_DEVICE_ID_NI_PCI2328,
2102 		.subvendor	= PCI_ANY_ID,
2103 		.subdevice	= PCI_ANY_ID,
2104 		.init		= pci_ni8420_init,
2105 		.setup		= pci_default_setup,
2106 		.exit		= pci_ni8420_exit,
2107 	},
2108 	{
2109 		.vendor		= PCI_VENDOR_ID_NI,
2110 		.device		= PCI_DEVICE_ID_NI_PCI2324,
2111 		.subvendor	= PCI_ANY_ID,
2112 		.subdevice	= PCI_ANY_ID,
2113 		.init		= pci_ni8420_init,
2114 		.setup		= pci_default_setup,
2115 		.exit		= pci_ni8420_exit,
2116 	},
2117 	{
2118 		.vendor		= PCI_VENDOR_ID_NI,
2119 		.device		= PCI_DEVICE_ID_NI_PCI2322,
2120 		.subvendor	= PCI_ANY_ID,
2121 		.subdevice	= PCI_ANY_ID,
2122 		.init		= pci_ni8420_init,
2123 		.setup		= pci_default_setup,
2124 		.exit		= pci_ni8420_exit,
2125 	},
2126 	{
2127 		.vendor		= PCI_VENDOR_ID_NI,
2128 		.device		= PCI_DEVICE_ID_NI_PCI2324I,
2129 		.subvendor	= PCI_ANY_ID,
2130 		.subdevice	= PCI_ANY_ID,
2131 		.init		= pci_ni8420_init,
2132 		.setup		= pci_default_setup,
2133 		.exit		= pci_ni8420_exit,
2134 	},
2135 	{
2136 		.vendor		= PCI_VENDOR_ID_NI,
2137 		.device		= PCI_DEVICE_ID_NI_PCI2322I,
2138 		.subvendor	= PCI_ANY_ID,
2139 		.subdevice	= PCI_ANY_ID,
2140 		.init		= pci_ni8420_init,
2141 		.setup		= pci_default_setup,
2142 		.exit		= pci_ni8420_exit,
2143 	},
2144 	{
2145 		.vendor		= PCI_VENDOR_ID_NI,
2146 		.device		= PCI_DEVICE_ID_NI_PXI8420_23216,
2147 		.subvendor	= PCI_ANY_ID,
2148 		.subdevice	= PCI_ANY_ID,
2149 		.init		= pci_ni8420_init,
2150 		.setup		= pci_default_setup,
2151 		.exit		= pci_ni8420_exit,
2152 	},
2153 	{
2154 		.vendor		= PCI_VENDOR_ID_NI,
2155 		.device		= PCI_DEVICE_ID_NI_PXI8420_2328,
2156 		.subvendor	= PCI_ANY_ID,
2157 		.subdevice	= PCI_ANY_ID,
2158 		.init		= pci_ni8420_init,
2159 		.setup		= pci_default_setup,
2160 		.exit		= pci_ni8420_exit,
2161 	},
2162 	{
2163 		.vendor		= PCI_VENDOR_ID_NI,
2164 		.device		= PCI_DEVICE_ID_NI_PXI8420_2324,
2165 		.subvendor	= PCI_ANY_ID,
2166 		.subdevice	= PCI_ANY_ID,
2167 		.init		= pci_ni8420_init,
2168 		.setup		= pci_default_setup,
2169 		.exit		= pci_ni8420_exit,
2170 	},
2171 	{
2172 		.vendor		= PCI_VENDOR_ID_NI,
2173 		.device		= PCI_DEVICE_ID_NI_PXI8420_2322,
2174 		.subvendor	= PCI_ANY_ID,
2175 		.subdevice	= PCI_ANY_ID,
2176 		.init		= pci_ni8420_init,
2177 		.setup		= pci_default_setup,
2178 		.exit		= pci_ni8420_exit,
2179 	},
2180 	{
2181 		.vendor		= PCI_VENDOR_ID_NI,
2182 		.device		= PCI_DEVICE_ID_NI_PXI8422_2324,
2183 		.subvendor	= PCI_ANY_ID,
2184 		.subdevice	= PCI_ANY_ID,
2185 		.init		= pci_ni8420_init,
2186 		.setup		= pci_default_setup,
2187 		.exit		= pci_ni8420_exit,
2188 	},
2189 	{
2190 		.vendor		= PCI_VENDOR_ID_NI,
2191 		.device		= PCI_DEVICE_ID_NI_PXI8422_2322,
2192 		.subvendor	= PCI_ANY_ID,
2193 		.subdevice	= PCI_ANY_ID,
2194 		.init		= pci_ni8420_init,
2195 		.setup		= pci_default_setup,
2196 		.exit		= pci_ni8420_exit,
2197 	},
2198 	{
2199 		.vendor		= PCI_VENDOR_ID_NI,
2200 		.device		= PCI_ANY_ID,
2201 		.subvendor	= PCI_ANY_ID,
2202 		.subdevice	= PCI_ANY_ID,
2203 		.init		= pci_ni8430_init,
2204 		.setup		= pci_ni8430_setup,
2205 		.exit		= pci_ni8430_exit,
2206 	},
2207 	/* Quatech */
2208 	{
2209 		.vendor		= PCI_VENDOR_ID_QUATECH,
2210 		.device		= PCI_ANY_ID,
2211 		.subvendor	= PCI_ANY_ID,
2212 		.subdevice	= PCI_ANY_ID,
2213 		.init		= pci_quatech_init,
2214 		.setup		= pci_quatech_setup,
2215 	},
2216 	/*
2217 	 * Panacom
2218 	 */
2219 	{
2220 		.vendor		= PCI_VENDOR_ID_PANACOM,
2221 		.device		= PCI_DEVICE_ID_PANACOM_QUADMODEM,
2222 		.subvendor	= PCI_ANY_ID,
2223 		.subdevice	= PCI_ANY_ID,
2224 		.init		= pci_plx9050_init,
2225 		.setup		= pci_default_setup,
2226 		.exit		= pci_plx9050_exit,
2227 	},
2228 	{
2229 		.vendor		= PCI_VENDOR_ID_PANACOM,
2230 		.device		= PCI_DEVICE_ID_PANACOM_DUALMODEM,
2231 		.subvendor	= PCI_ANY_ID,
2232 		.subdevice	= PCI_ANY_ID,
2233 		.init		= pci_plx9050_init,
2234 		.setup		= pci_default_setup,
2235 		.exit		= pci_plx9050_exit,
2236 	},
2237 	/*
2238 	 * PLX
2239 	 */
2240 	{
2241 		.vendor		= PCI_VENDOR_ID_PLX,
2242 		.device		= PCI_DEVICE_ID_PLX_9050,
2243 		.subvendor	= PCI_SUBVENDOR_ID_EXSYS,
2244 		.subdevice	= PCI_SUBDEVICE_ID_EXSYS_4055,
2245 		.init		= pci_plx9050_init,
2246 		.setup		= pci_default_setup,
2247 		.exit		= pci_plx9050_exit,
2248 	},
2249 	{
2250 		.vendor		= PCI_VENDOR_ID_PLX,
2251 		.device		= PCI_DEVICE_ID_PLX_9050,
2252 		.subvendor	= PCI_SUBVENDOR_ID_KEYSPAN,
2253 		.subdevice	= PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2254 		.init		= pci_plx9050_init,
2255 		.setup		= pci_default_setup,
2256 		.exit		= pci_plx9050_exit,
2257 	},
2258 	{
2259 		.vendor		= PCI_VENDOR_ID_PLX,
2260 		.device		= PCI_DEVICE_ID_PLX_ROMULUS,
2261 		.subvendor	= PCI_VENDOR_ID_PLX,
2262 		.subdevice	= PCI_DEVICE_ID_PLX_ROMULUS,
2263 		.init		= pci_plx9050_init,
2264 		.setup		= pci_default_setup,
2265 		.exit		= pci_plx9050_exit,
2266 	},
2267 	/*
2268 	 * SBS Technologies, Inc., PMC-OCTALPRO 232
2269 	 */
2270 	{
2271 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2272 		.device		= PCI_DEVICE_ID_OCTPRO,
2273 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2274 		.subdevice	= PCI_SUBDEVICE_ID_OCTPRO232,
2275 		.init		= sbs_init,
2276 		.setup		= sbs_setup,
2277 		.exit		= sbs_exit,
2278 	},
2279 	/*
2280 	 * SBS Technologies, Inc., PMC-OCTALPRO 422
2281 	 */
2282 	{
2283 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2284 		.device		= PCI_DEVICE_ID_OCTPRO,
2285 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2286 		.subdevice	= PCI_SUBDEVICE_ID_OCTPRO422,
2287 		.init		= sbs_init,
2288 		.setup		= sbs_setup,
2289 		.exit		= sbs_exit,
2290 	},
2291 	/*
2292 	 * SBS Technologies, Inc., P-Octal 232
2293 	 */
2294 	{
2295 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2296 		.device		= PCI_DEVICE_ID_OCTPRO,
2297 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2298 		.subdevice	= PCI_SUBDEVICE_ID_POCTAL232,
2299 		.init		= sbs_init,
2300 		.setup		= sbs_setup,
2301 		.exit		= sbs_exit,
2302 	},
2303 	/*
2304 	 * SBS Technologies, Inc., P-Octal 422
2305 	 */
2306 	{
2307 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2308 		.device		= PCI_DEVICE_ID_OCTPRO,
2309 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2310 		.subdevice	= PCI_SUBDEVICE_ID_POCTAL422,
2311 		.init		= sbs_init,
2312 		.setup		= sbs_setup,
2313 		.exit		= sbs_exit,
2314 	},
2315 	/*
2316 	 * SIIG cards - these may be called via parport_serial
2317 	 */
2318 	{
2319 		.vendor		= PCI_VENDOR_ID_SIIG,
2320 		.device		= PCI_ANY_ID,
2321 		.subvendor	= PCI_ANY_ID,
2322 		.subdevice	= PCI_ANY_ID,
2323 		.init		= pci_siig_init,
2324 		.setup		= pci_siig_setup,
2325 	},
2326 	/*
2327 	 * Titan cards
2328 	 */
2329 	{
2330 		.vendor		= PCI_VENDOR_ID_TITAN,
2331 		.device		= PCI_DEVICE_ID_TITAN_400L,
2332 		.subvendor	= PCI_ANY_ID,
2333 		.subdevice	= PCI_ANY_ID,
2334 		.setup		= titan_400l_800l_setup,
2335 	},
2336 	{
2337 		.vendor		= PCI_VENDOR_ID_TITAN,
2338 		.device		= PCI_DEVICE_ID_TITAN_800L,
2339 		.subvendor	= PCI_ANY_ID,
2340 		.subdevice	= PCI_ANY_ID,
2341 		.setup		= titan_400l_800l_setup,
2342 	},
2343 	/*
2344 	 * Timedia cards
2345 	 */
2346 	{
2347 		.vendor		= PCI_VENDOR_ID_TIMEDIA,
2348 		.device		= PCI_DEVICE_ID_TIMEDIA_1889,
2349 		.subvendor	= PCI_VENDOR_ID_TIMEDIA,
2350 		.subdevice	= PCI_ANY_ID,
2351 		.probe		= pci_timedia_probe,
2352 		.init		= pci_timedia_init,
2353 		.setup		= pci_timedia_setup,
2354 	},
2355 	{
2356 		.vendor		= PCI_VENDOR_ID_TIMEDIA,
2357 		.device		= PCI_ANY_ID,
2358 		.subvendor	= PCI_ANY_ID,
2359 		.subdevice	= PCI_ANY_ID,
2360 		.setup		= pci_timedia_setup,
2361 	},
2362 	/*
2363 	 * Sunix PCI serial boards
2364 	 */
2365 	{
2366 		.vendor		= PCI_VENDOR_ID_SUNIX,
2367 		.device		= PCI_DEVICE_ID_SUNIX_1999,
2368 		.subvendor	= PCI_VENDOR_ID_SUNIX,
2369 		.subdevice	= PCI_ANY_ID,
2370 		.setup		= pci_sunix_setup,
2371 	},
2372 	/*
2373 	 * Xircom cards
2374 	 */
2375 	{
2376 		.vendor		= PCI_VENDOR_ID_XIRCOM,
2377 		.device		= PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2378 		.subvendor	= PCI_ANY_ID,
2379 		.subdevice	= PCI_ANY_ID,
2380 		.init		= pci_xircom_init,
2381 		.setup		= pci_default_setup,
2382 	},
2383 	/*
2384 	 * Netmos cards - these may be called via parport_serial
2385 	 */
2386 	{
2387 		.vendor		= PCI_VENDOR_ID_NETMOS,
2388 		.device		= PCI_ANY_ID,
2389 		.subvendor	= PCI_ANY_ID,
2390 		.subdevice	= PCI_ANY_ID,
2391 		.init		= pci_netmos_init,
2392 		.setup		= pci_netmos_9900_setup,
2393 	},
2394 	/*
2395 	 * EndRun Technologies
2396 	*/
2397 	{
2398 		.vendor		= PCI_VENDOR_ID_ENDRUN,
2399 		.device		= PCI_ANY_ID,
2400 		.subvendor	= PCI_ANY_ID,
2401 		.subdevice	= PCI_ANY_ID,
2402 		.init		= pci_oxsemi_tornado_init,
2403 		.setup		= pci_default_setup,
2404 	},
2405 	/*
2406 	 * For Oxford Semiconductor Tornado based devices
2407 	 */
2408 	{
2409 		.vendor		= PCI_VENDOR_ID_OXSEMI,
2410 		.device		= PCI_ANY_ID,
2411 		.subvendor	= PCI_ANY_ID,
2412 		.subdevice	= PCI_ANY_ID,
2413 		.init		= pci_oxsemi_tornado_init,
2414 		.setup		= pci_oxsemi_tornado_setup,
2415 	},
2416 	{
2417 		.vendor		= PCI_VENDOR_ID_MAINPINE,
2418 		.device		= PCI_ANY_ID,
2419 		.subvendor	= PCI_ANY_ID,
2420 		.subdevice	= PCI_ANY_ID,
2421 		.init		= pci_oxsemi_tornado_init,
2422 		.setup		= pci_oxsemi_tornado_setup,
2423 	},
2424 	{
2425 		.vendor		= PCI_VENDOR_ID_DIGI,
2426 		.device		= PCIE_DEVICE_ID_NEO_2_OX_IBM,
2427 		.subvendor		= PCI_SUBVENDOR_ID_IBM,
2428 		.subdevice		= PCI_ANY_ID,
2429 		.init			= pci_oxsemi_tornado_init,
2430 		.setup		= pci_oxsemi_tornado_setup,
2431 	},
2432 	/*
2433 	 * Brainboxes devices - all Oxsemi based
2434 	 */
2435 	{
2436 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2437 		.device		= 0x4027,
2438 		.subvendor	= PCI_ANY_ID,
2439 		.subdevice	= PCI_ANY_ID,
2440 		.init		= pci_oxsemi_tornado_init,
2441 		.setup		= pci_oxsemi_tornado_setup,
2442 	},
2443 	{
2444 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2445 		.device		= 0x4028,
2446 		.subvendor	= PCI_ANY_ID,
2447 		.subdevice	= PCI_ANY_ID,
2448 		.init		= pci_oxsemi_tornado_init,
2449 		.setup		= pci_oxsemi_tornado_setup,
2450 	},
2451 	{
2452 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2453 		.device		= 0x4029,
2454 		.subvendor	= PCI_ANY_ID,
2455 		.subdevice	= PCI_ANY_ID,
2456 		.init		= pci_oxsemi_tornado_init,
2457 		.setup		= pci_oxsemi_tornado_setup,
2458 	},
2459 	{
2460 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2461 		.device		= 0x4019,
2462 		.subvendor	= PCI_ANY_ID,
2463 		.subdevice	= PCI_ANY_ID,
2464 		.init		= pci_oxsemi_tornado_init,
2465 		.setup		= pci_oxsemi_tornado_setup,
2466 	},
2467 	{
2468 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2469 		.device		= 0x4016,
2470 		.subvendor	= PCI_ANY_ID,
2471 		.subdevice	= PCI_ANY_ID,
2472 		.init		= pci_oxsemi_tornado_init,
2473 		.setup		= pci_oxsemi_tornado_setup,
2474 	},
2475 	{
2476 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2477 		.device		= 0x4015,
2478 		.subvendor	= PCI_ANY_ID,
2479 		.subdevice	= PCI_ANY_ID,
2480 		.init		= pci_oxsemi_tornado_init,
2481 		.setup		= pci_oxsemi_tornado_setup,
2482 	},
2483 	{
2484 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2485 		.device		= 0x400A,
2486 		.subvendor	= PCI_ANY_ID,
2487 		.subdevice	= PCI_ANY_ID,
2488 		.init		= pci_oxsemi_tornado_init,
2489 		.setup		= pci_oxsemi_tornado_setup,
2490 	},
2491 	{
2492 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2493 		.device		= 0x400E,
2494 		.subvendor	= PCI_ANY_ID,
2495 		.subdevice	= PCI_ANY_ID,
2496 		.init		= pci_oxsemi_tornado_init,
2497 		.setup		= pci_oxsemi_tornado_setup,
2498 	},
2499 	{
2500 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2501 		.device		= 0x400C,
2502 		.subvendor	= PCI_ANY_ID,
2503 		.subdevice	= PCI_ANY_ID,
2504 		.init		= pci_oxsemi_tornado_init,
2505 		.setup		= pci_oxsemi_tornado_setup,
2506 	},
2507 	{
2508 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2509 		.device		= 0x400B,
2510 		.subvendor	= PCI_ANY_ID,
2511 		.subdevice	= PCI_ANY_ID,
2512 		.init		= pci_oxsemi_tornado_init,
2513 		.setup		= pci_oxsemi_tornado_setup,
2514 	},
2515 	{
2516 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2517 		.device		= 0x400F,
2518 		.subvendor	= PCI_ANY_ID,
2519 		.subdevice	= PCI_ANY_ID,
2520 		.init		= pci_oxsemi_tornado_init,
2521 		.setup		= pci_oxsemi_tornado_setup,
2522 	},
2523 	{
2524 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2525 		.device		= 0x4010,
2526 		.subvendor	= PCI_ANY_ID,
2527 		.subdevice	= PCI_ANY_ID,
2528 		.init		= pci_oxsemi_tornado_init,
2529 		.setup		= pci_oxsemi_tornado_setup,
2530 	},
2531 	{
2532 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2533 		.device		= 0x4011,
2534 		.subvendor	= PCI_ANY_ID,
2535 		.subdevice	= PCI_ANY_ID,
2536 		.init		= pci_oxsemi_tornado_init,
2537 		.setup		= pci_oxsemi_tornado_setup,
2538 	},
2539 	{
2540 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2541 		.device		= 0x401D,
2542 		.subvendor	= PCI_ANY_ID,
2543 		.subdevice	= PCI_ANY_ID,
2544 		.init		= pci_oxsemi_tornado_init,
2545 		.setup		= pci_oxsemi_tornado_setup,
2546 	},
2547 	{
2548 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2549 		.device		= 0x401E,
2550 		.subvendor	= PCI_ANY_ID,
2551 		.subdevice	= PCI_ANY_ID,
2552 		.init		= pci_oxsemi_tornado_init,
2553 		.setup		= pci_oxsemi_tornado_setup,
2554 	},
2555 	{
2556 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2557 		.device		= 0x4013,
2558 		.subvendor	= PCI_ANY_ID,
2559 		.subdevice	= PCI_ANY_ID,
2560 		.init		= pci_oxsemi_tornado_init,
2561 		.setup		= pci_oxsemi_tornado_setup,
2562 	},
2563 	{
2564 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2565 		.device		= 0x4017,
2566 		.subvendor	= PCI_ANY_ID,
2567 		.subdevice	= PCI_ANY_ID,
2568 		.init		= pci_oxsemi_tornado_init,
2569 		.setup		= pci_oxsemi_tornado_setup,
2570 	},
2571 	{
2572 		.vendor		= PCI_VENDOR_ID_INTASHIELD,
2573 		.device		= 0x4018,
2574 		.subvendor	= PCI_ANY_ID,
2575 		.subdevice	= PCI_ANY_ID,
2576 		.init		= pci_oxsemi_tornado_init,
2577 		.setup		= pci_oxsemi_tornado_setup,
2578 	},
2579 	{
2580 		.vendor         = PCI_VENDOR_ID_INTEL,
2581 		.device         = 0x8811,
2582 		.subvendor	= PCI_ANY_ID,
2583 		.subdevice	= PCI_ANY_ID,
2584 		.init		= pci_eg20t_init,
2585 		.setup		= pci_default_setup,
2586 	},
2587 	{
2588 		.vendor         = PCI_VENDOR_ID_INTEL,
2589 		.device         = 0x8812,
2590 		.subvendor	= PCI_ANY_ID,
2591 		.subdevice	= PCI_ANY_ID,
2592 		.init		= pci_eg20t_init,
2593 		.setup		= pci_default_setup,
2594 	},
2595 	{
2596 		.vendor         = PCI_VENDOR_ID_INTEL,
2597 		.device         = 0x8813,
2598 		.subvendor	= PCI_ANY_ID,
2599 		.subdevice	= PCI_ANY_ID,
2600 		.init		= pci_eg20t_init,
2601 		.setup		= pci_default_setup,
2602 	},
2603 	{
2604 		.vendor         = PCI_VENDOR_ID_INTEL,
2605 		.device         = 0x8814,
2606 		.subvendor	= PCI_ANY_ID,
2607 		.subdevice	= PCI_ANY_ID,
2608 		.init		= pci_eg20t_init,
2609 		.setup		= pci_default_setup,
2610 	},
2611 	{
2612 		.vendor         = 0x10DB,
2613 		.device         = 0x8027,
2614 		.subvendor	= PCI_ANY_ID,
2615 		.subdevice	= PCI_ANY_ID,
2616 		.init		= pci_eg20t_init,
2617 		.setup		= pci_default_setup,
2618 	},
2619 	{
2620 		.vendor         = 0x10DB,
2621 		.device         = 0x8028,
2622 		.subvendor	= PCI_ANY_ID,
2623 		.subdevice	= PCI_ANY_ID,
2624 		.init		= pci_eg20t_init,
2625 		.setup		= pci_default_setup,
2626 	},
2627 	{
2628 		.vendor         = 0x10DB,
2629 		.device         = 0x8029,
2630 		.subvendor	= PCI_ANY_ID,
2631 		.subdevice	= PCI_ANY_ID,
2632 		.init		= pci_eg20t_init,
2633 		.setup		= pci_default_setup,
2634 	},
2635 	{
2636 		.vendor         = 0x10DB,
2637 		.device         = 0x800C,
2638 		.subvendor	= PCI_ANY_ID,
2639 		.subdevice	= PCI_ANY_ID,
2640 		.init		= pci_eg20t_init,
2641 		.setup		= pci_default_setup,
2642 	},
2643 	{
2644 		.vendor         = 0x10DB,
2645 		.device         = 0x800D,
2646 		.subvendor	= PCI_ANY_ID,
2647 		.subdevice	= PCI_ANY_ID,
2648 		.init		= pci_eg20t_init,
2649 		.setup		= pci_default_setup,
2650 	},
2651 	/*
2652 	 * Cronyx Omega PCI (PLX-chip based)
2653 	 */
2654 	{
2655 		.vendor		= PCI_VENDOR_ID_PLX,
2656 		.device		= PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2657 		.subvendor	= PCI_ANY_ID,
2658 		.subdevice	= PCI_ANY_ID,
2659 		.setup		= pci_omegapci_setup,
2660 	},
2661 	/* WCH CH353 1S1P card (16550 clone) */
2662 	{
2663 		.vendor         = PCI_VENDOR_ID_WCH,
2664 		.device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2665 		.subvendor      = PCI_ANY_ID,
2666 		.subdevice      = PCI_ANY_ID,
2667 		.setup          = pci_wch_ch353_setup,
2668 	},
2669 	/* WCH CH353 2S1P card (16550 clone) */
2670 	{
2671 		.vendor         = PCI_VENDOR_ID_WCH,
2672 		.device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2673 		.subvendor      = PCI_ANY_ID,
2674 		.subdevice      = PCI_ANY_ID,
2675 		.setup          = pci_wch_ch353_setup,
2676 	},
2677 	/* WCH CH353 4S card (16550 clone) */
2678 	{
2679 		.vendor         = PCI_VENDOR_ID_WCH,
2680 		.device         = PCI_DEVICE_ID_WCH_CH353_4S,
2681 		.subvendor      = PCI_ANY_ID,
2682 		.subdevice      = PCI_ANY_ID,
2683 		.setup          = pci_wch_ch353_setup,
2684 	},
2685 	/* WCH CH353 2S1PF card (16550 clone) */
2686 	{
2687 		.vendor         = PCI_VENDOR_ID_WCH,
2688 		.device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2689 		.subvendor      = PCI_ANY_ID,
2690 		.subdevice      = PCI_ANY_ID,
2691 		.setup          = pci_wch_ch353_setup,
2692 	},
2693 	/* WCH CH352 2S card (16550 clone) */
2694 	{
2695 		.vendor		= PCI_VENDOR_ID_WCH,
2696 		.device		= PCI_DEVICE_ID_WCH_CH352_2S,
2697 		.subvendor	= PCI_ANY_ID,
2698 		.subdevice	= PCI_ANY_ID,
2699 		.setup		= pci_wch_ch353_setup,
2700 	},
2701 	/* WCH CH355 4S card (16550 clone) */
2702 	{
2703 		.vendor		= PCI_VENDOR_ID_WCH,
2704 		.device		= PCI_DEVICE_ID_WCH_CH355_4S,
2705 		.subvendor	= PCI_ANY_ID,
2706 		.subdevice	= PCI_ANY_ID,
2707 		.setup		= pci_wch_ch355_setup,
2708 	},
2709 	/* WCH CH382 2S card (16850 clone) */
2710 	{
2711 		.vendor         = PCIE_VENDOR_ID_WCH,
2712 		.device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2713 		.subvendor      = PCI_ANY_ID,
2714 		.subdevice      = PCI_ANY_ID,
2715 		.setup          = pci_wch_ch38x_setup,
2716 	},
2717 	/* WCH CH382 2S1P card (16850 clone) */
2718 	{
2719 		.vendor         = PCIE_VENDOR_ID_WCH,
2720 		.device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2721 		.subvendor      = PCI_ANY_ID,
2722 		.subdevice      = PCI_ANY_ID,
2723 		.setup          = pci_wch_ch38x_setup,
2724 	},
2725 	/* WCH CH384 4S card (16850 clone) */
2726 	{
2727 		.vendor         = PCIE_VENDOR_ID_WCH,
2728 		.device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2729 		.subvendor      = PCI_ANY_ID,
2730 		.subdevice      = PCI_ANY_ID,
2731 		.setup          = pci_wch_ch38x_setup,
2732 	},
2733 	/* WCH CH384 8S card (16850 clone) */
2734 	{
2735 		.vendor         = PCIE_VENDOR_ID_WCH,
2736 		.device         = PCIE_DEVICE_ID_WCH_CH384_8S,
2737 		.subvendor      = PCI_ANY_ID,
2738 		.subdevice      = PCI_ANY_ID,
2739 		.init           = pci_wch_ch38x_init,
2740 		.exit		= pci_wch_ch38x_exit,
2741 		.setup          = pci_wch_ch38x_setup,
2742 	},
2743 	/*
2744 	 * Broadcom TruManage (NetXtreme)
2745 	 */
2746 	{
2747 		.vendor		= PCI_VENDOR_ID_BROADCOM,
2748 		.device		= PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2749 		.subvendor	= PCI_ANY_ID,
2750 		.subdevice	= PCI_ANY_ID,
2751 		.setup		= pci_brcm_trumanage_setup,
2752 	},
2753 	{
2754 		.vendor		= 0x1c29,
2755 		.device		= 0x1104,
2756 		.subvendor	= PCI_ANY_ID,
2757 		.subdevice	= PCI_ANY_ID,
2758 		.setup		= pci_fintek_setup,
2759 		.init		= pci_fintek_init,
2760 	},
2761 	{
2762 		.vendor		= 0x1c29,
2763 		.device		= 0x1108,
2764 		.subvendor	= PCI_ANY_ID,
2765 		.subdevice	= PCI_ANY_ID,
2766 		.setup		= pci_fintek_setup,
2767 		.init		= pci_fintek_init,
2768 	},
2769 	{
2770 		.vendor		= 0x1c29,
2771 		.device		= 0x1112,
2772 		.subvendor	= PCI_ANY_ID,
2773 		.subdevice	= PCI_ANY_ID,
2774 		.setup		= pci_fintek_setup,
2775 		.init		= pci_fintek_init,
2776 	},
2777 	/*
2778 	 * MOXA
2779 	 */
2780 	{
2781 		.vendor		= PCI_VENDOR_ID_MOXA,
2782 		.device		= PCI_ANY_ID,
2783 		.subvendor	= PCI_ANY_ID,
2784 		.subdevice	= PCI_ANY_ID,
2785 		.setup		= pci_moxa_setup,
2786 	},
2787 	{
2788 		.vendor		= 0x1c29,
2789 		.device		= 0x1204,
2790 		.subvendor	= PCI_ANY_ID,
2791 		.subdevice	= PCI_ANY_ID,
2792 		.setup		= pci_fintek_f815xxa_setup,
2793 		.init		= pci_fintek_f815xxa_init,
2794 	},
2795 	{
2796 		.vendor		= 0x1c29,
2797 		.device		= 0x1208,
2798 		.subvendor	= PCI_ANY_ID,
2799 		.subdevice	= PCI_ANY_ID,
2800 		.setup		= pci_fintek_f815xxa_setup,
2801 		.init		= pci_fintek_f815xxa_init,
2802 	},
2803 	{
2804 		.vendor		= 0x1c29,
2805 		.device		= 0x1212,
2806 		.subvendor	= PCI_ANY_ID,
2807 		.subdevice	= PCI_ANY_ID,
2808 		.setup		= pci_fintek_f815xxa_setup,
2809 		.init		= pci_fintek_f815xxa_init,
2810 	},
2811 
2812 	/*
2813 	 * Default "match everything" terminator entry
2814 	 */
2815 	{
2816 		.vendor		= PCI_ANY_ID,
2817 		.device		= PCI_ANY_ID,
2818 		.subvendor	= PCI_ANY_ID,
2819 		.subdevice	= PCI_ANY_ID,
2820 		.setup		= pci_default_setup,
2821 	}
2822 };
2823 
quirk_id_matches(u32 quirk_id,u32 dev_id)2824 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2825 {
2826 	return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2827 }
2828 
find_quirk(struct pci_dev * dev)2829 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2830 {
2831 	struct pci_serial_quirk *quirk;
2832 
2833 	for (quirk = pci_serial_quirks; ; quirk++)
2834 		if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2835 		    quirk_id_matches(quirk->device, dev->device) &&
2836 		    quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2837 		    quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2838 			break;
2839 	return quirk;
2840 }
2841 
2842 /*
2843  * This is the configuration table for all of the PCI serial boards
2844  * which we support.  It is directly indexed by the pci_board_num_t enum
2845  * value, which is encoded in the pci_device_id PCI probe table's
2846  * driver_data member.
2847  *
2848  * The makeup of these names are:
2849  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2850  *
2851  *  bn		= PCI BAR number
2852  *  bt		= Index using PCI BARs
2853  *  n		= number of serial ports
2854  *  baud	= baud rate
2855  *  offsetinhex	= offset for each sequential port (in hex)
2856  *
2857  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2858  *
2859  * Please note: in theory if n = 1, _bt infix should make no difference.
2860  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2861  */
2862 enum pci_board_num_t {
2863 	pbn_default = 0,
2864 
2865 	pbn_b0_1_115200,
2866 	pbn_b0_2_115200,
2867 	pbn_b0_4_115200,
2868 	pbn_b0_5_115200,
2869 	pbn_b0_8_115200,
2870 
2871 	pbn_b0_1_921600,
2872 	pbn_b0_2_921600,
2873 	pbn_b0_4_921600,
2874 
2875 	pbn_b0_2_1130000,
2876 
2877 	pbn_b0_4_1152000,
2878 
2879 	pbn_b0_4_1250000,
2880 
2881 	pbn_b0_2_1843200,
2882 	pbn_b0_4_1843200,
2883 
2884 	pbn_b0_1_15625000,
2885 
2886 	pbn_b0_bt_1_115200,
2887 	pbn_b0_bt_2_115200,
2888 	pbn_b0_bt_4_115200,
2889 	pbn_b0_bt_8_115200,
2890 
2891 	pbn_b0_bt_1_460800,
2892 	pbn_b0_bt_2_460800,
2893 	pbn_b0_bt_4_460800,
2894 
2895 	pbn_b0_bt_1_921600,
2896 	pbn_b0_bt_2_921600,
2897 	pbn_b0_bt_4_921600,
2898 	pbn_b0_bt_8_921600,
2899 
2900 	pbn_b1_1_115200,
2901 	pbn_b1_2_115200,
2902 	pbn_b1_4_115200,
2903 	pbn_b1_8_115200,
2904 	pbn_b1_16_115200,
2905 
2906 	pbn_b1_1_921600,
2907 	pbn_b1_2_921600,
2908 	pbn_b1_4_921600,
2909 	pbn_b1_8_921600,
2910 
2911 	pbn_b1_2_1250000,
2912 
2913 	pbn_b1_bt_1_115200,
2914 	pbn_b1_bt_2_115200,
2915 	pbn_b1_bt_4_115200,
2916 
2917 	pbn_b1_bt_2_921600,
2918 
2919 	pbn_b1_1_1382400,
2920 	pbn_b1_2_1382400,
2921 	pbn_b1_4_1382400,
2922 	pbn_b1_8_1382400,
2923 
2924 	pbn_b2_1_115200,
2925 	pbn_b2_2_115200,
2926 	pbn_b2_4_115200,
2927 	pbn_b2_8_115200,
2928 
2929 	pbn_b2_1_460800,
2930 	pbn_b2_4_460800,
2931 	pbn_b2_8_460800,
2932 	pbn_b2_16_460800,
2933 
2934 	pbn_b2_1_921600,
2935 	pbn_b2_4_921600,
2936 	pbn_b2_8_921600,
2937 
2938 	pbn_b2_8_1152000,
2939 
2940 	pbn_b2_bt_1_115200,
2941 	pbn_b2_bt_2_115200,
2942 	pbn_b2_bt_4_115200,
2943 
2944 	pbn_b2_bt_2_921600,
2945 	pbn_b2_bt_4_921600,
2946 
2947 	pbn_b3_2_115200,
2948 	pbn_b3_4_115200,
2949 	pbn_b3_8_115200,
2950 
2951 	pbn_b4_bt_2_921600,
2952 	pbn_b4_bt_4_921600,
2953 	pbn_b4_bt_8_921600,
2954 
2955 	/*
2956 	 * Board-specific versions.
2957 	 */
2958 	pbn_panacom,
2959 	pbn_panacom2,
2960 	pbn_panacom4,
2961 	pbn_plx_romulus,
2962 	pbn_oxsemi,
2963 	pbn_oxsemi_1_15625000,
2964 	pbn_oxsemi_2_15625000,
2965 	pbn_oxsemi_4_15625000,
2966 	pbn_oxsemi_8_15625000,
2967 	pbn_intel_i960,
2968 	pbn_sgi_ioc3,
2969 	pbn_computone_4,
2970 	pbn_computone_6,
2971 	pbn_computone_8,
2972 	pbn_sbsxrsio,
2973 	pbn_pasemi_1682M,
2974 	pbn_ni8430_2,
2975 	pbn_ni8430_4,
2976 	pbn_ni8430_8,
2977 	pbn_ni8430_16,
2978 	pbn_ADDIDATA_PCIe_1_3906250,
2979 	pbn_ADDIDATA_PCIe_2_3906250,
2980 	pbn_ADDIDATA_PCIe_4_3906250,
2981 	pbn_ADDIDATA_PCIe_8_3906250,
2982 	pbn_ce4100_1_115200,
2983 	pbn_omegapci,
2984 	pbn_NETMOS9900_2s_115200,
2985 	pbn_brcm_trumanage,
2986 	pbn_fintek_4,
2987 	pbn_fintek_8,
2988 	pbn_fintek_12,
2989 	pbn_fintek_F81504A,
2990 	pbn_fintek_F81508A,
2991 	pbn_fintek_F81512A,
2992 	pbn_wch382_2,
2993 	pbn_wch384_4,
2994 	pbn_wch384_8,
2995 	pbn_sunix_pci_1s,
2996 	pbn_sunix_pci_2s,
2997 	pbn_sunix_pci_4s,
2998 	pbn_sunix_pci_8s,
2999 	pbn_sunix_pci_16s,
3000 	pbn_titan_1_4000000,
3001 	pbn_titan_2_4000000,
3002 	pbn_titan_4_4000000,
3003 	pbn_titan_8_4000000,
3004 	pbn_moxa8250_2p,
3005 	pbn_moxa8250_4p,
3006 	pbn_moxa8250_8p,
3007 };
3008 
3009 /*
3010  * uart_offset - the space between channels
3011  * reg_shift   - describes how the UART registers are mapped
3012  *               to PCI memory by the card.
3013  * For example IER register on SBS, Inc. PMC-OctPro is located at
3014  * offset 0x10 from the UART base, while UART_IER is defined as 1
3015  * in include/linux/serial_reg.h,
3016  * see first lines of serial_in() and serial_out() in 8250.c
3017 */
3018 
3019 static struct pciserial_board pci_boards[] = {
3020 	[pbn_default] = {
3021 		.flags		= FL_BASE0,
3022 		.num_ports	= 1,
3023 		.base_baud	= 115200,
3024 		.uart_offset	= 8,
3025 	},
3026 	[pbn_b0_1_115200] = {
3027 		.flags		= FL_BASE0,
3028 		.num_ports	= 1,
3029 		.base_baud	= 115200,
3030 		.uart_offset	= 8,
3031 	},
3032 	[pbn_b0_2_115200] = {
3033 		.flags		= FL_BASE0,
3034 		.num_ports	= 2,
3035 		.base_baud	= 115200,
3036 		.uart_offset	= 8,
3037 	},
3038 	[pbn_b0_4_115200] = {
3039 		.flags		= FL_BASE0,
3040 		.num_ports	= 4,
3041 		.base_baud	= 115200,
3042 		.uart_offset	= 8,
3043 	},
3044 	[pbn_b0_5_115200] = {
3045 		.flags		= FL_BASE0,
3046 		.num_ports	= 5,
3047 		.base_baud	= 115200,
3048 		.uart_offset	= 8,
3049 	},
3050 	[pbn_b0_8_115200] = {
3051 		.flags		= FL_BASE0,
3052 		.num_ports	= 8,
3053 		.base_baud	= 115200,
3054 		.uart_offset	= 8,
3055 	},
3056 	[pbn_b0_1_921600] = {
3057 		.flags		= FL_BASE0,
3058 		.num_ports	= 1,
3059 		.base_baud	= 921600,
3060 		.uart_offset	= 8,
3061 	},
3062 	[pbn_b0_2_921600] = {
3063 		.flags		= FL_BASE0,
3064 		.num_ports	= 2,
3065 		.base_baud	= 921600,
3066 		.uart_offset	= 8,
3067 	},
3068 	[pbn_b0_4_921600] = {
3069 		.flags		= FL_BASE0,
3070 		.num_ports	= 4,
3071 		.base_baud	= 921600,
3072 		.uart_offset	= 8,
3073 	},
3074 
3075 	[pbn_b0_2_1130000] = {
3076 		.flags          = FL_BASE0,
3077 		.num_ports      = 2,
3078 		.base_baud      = 1130000,
3079 		.uart_offset    = 8,
3080 	},
3081 
3082 	[pbn_b0_4_1152000] = {
3083 		.flags		= FL_BASE0,
3084 		.num_ports	= 4,
3085 		.base_baud	= 1152000,
3086 		.uart_offset	= 8,
3087 	},
3088 
3089 	[pbn_b0_4_1250000] = {
3090 		.flags		= FL_BASE0,
3091 		.num_ports	= 4,
3092 		.base_baud	= 1250000,
3093 		.uart_offset	= 8,
3094 	},
3095 
3096 	[pbn_b0_2_1843200] = {
3097 		.flags		= FL_BASE0,
3098 		.num_ports	= 2,
3099 		.base_baud	= 1843200,
3100 		.uart_offset	= 8,
3101 	},
3102 	[pbn_b0_4_1843200] = {
3103 		.flags		= FL_BASE0,
3104 		.num_ports	= 4,
3105 		.base_baud	= 1843200,
3106 		.uart_offset	= 8,
3107 	},
3108 
3109 	[pbn_b0_1_15625000] = {
3110 		.flags		= FL_BASE0,
3111 		.num_ports	= 1,
3112 		.base_baud	= 15625000,
3113 		.uart_offset	= 8,
3114 	},
3115 
3116 	[pbn_b0_bt_1_115200] = {
3117 		.flags		= FL_BASE0|FL_BASE_BARS,
3118 		.num_ports	= 1,
3119 		.base_baud	= 115200,
3120 		.uart_offset	= 8,
3121 	},
3122 	[pbn_b0_bt_2_115200] = {
3123 		.flags		= FL_BASE0|FL_BASE_BARS,
3124 		.num_ports	= 2,
3125 		.base_baud	= 115200,
3126 		.uart_offset	= 8,
3127 	},
3128 	[pbn_b0_bt_4_115200] = {
3129 		.flags		= FL_BASE0|FL_BASE_BARS,
3130 		.num_ports	= 4,
3131 		.base_baud	= 115200,
3132 		.uart_offset	= 8,
3133 	},
3134 	[pbn_b0_bt_8_115200] = {
3135 		.flags		= FL_BASE0|FL_BASE_BARS,
3136 		.num_ports	= 8,
3137 		.base_baud	= 115200,
3138 		.uart_offset	= 8,
3139 	},
3140 
3141 	[pbn_b0_bt_1_460800] = {
3142 		.flags		= FL_BASE0|FL_BASE_BARS,
3143 		.num_ports	= 1,
3144 		.base_baud	= 460800,
3145 		.uart_offset	= 8,
3146 	},
3147 	[pbn_b0_bt_2_460800] = {
3148 		.flags		= FL_BASE0|FL_BASE_BARS,
3149 		.num_ports	= 2,
3150 		.base_baud	= 460800,
3151 		.uart_offset	= 8,
3152 	},
3153 	[pbn_b0_bt_4_460800] = {
3154 		.flags		= FL_BASE0|FL_BASE_BARS,
3155 		.num_ports	= 4,
3156 		.base_baud	= 460800,
3157 		.uart_offset	= 8,
3158 	},
3159 
3160 	[pbn_b0_bt_1_921600] = {
3161 		.flags		= FL_BASE0|FL_BASE_BARS,
3162 		.num_ports	= 1,
3163 		.base_baud	= 921600,
3164 		.uart_offset	= 8,
3165 	},
3166 	[pbn_b0_bt_2_921600] = {
3167 		.flags		= FL_BASE0|FL_BASE_BARS,
3168 		.num_ports	= 2,
3169 		.base_baud	= 921600,
3170 		.uart_offset	= 8,
3171 	},
3172 	[pbn_b0_bt_4_921600] = {
3173 		.flags		= FL_BASE0|FL_BASE_BARS,
3174 		.num_ports	= 4,
3175 		.base_baud	= 921600,
3176 		.uart_offset	= 8,
3177 	},
3178 	[pbn_b0_bt_8_921600] = {
3179 		.flags		= FL_BASE0|FL_BASE_BARS,
3180 		.num_ports	= 8,
3181 		.base_baud	= 921600,
3182 		.uart_offset	= 8,
3183 	},
3184 
3185 	[pbn_b1_1_115200] = {
3186 		.flags		= FL_BASE1,
3187 		.num_ports	= 1,
3188 		.base_baud	= 115200,
3189 		.uart_offset	= 8,
3190 	},
3191 	[pbn_b1_2_115200] = {
3192 		.flags		= FL_BASE1,
3193 		.num_ports	= 2,
3194 		.base_baud	= 115200,
3195 		.uart_offset	= 8,
3196 	},
3197 	[pbn_b1_4_115200] = {
3198 		.flags		= FL_BASE1,
3199 		.num_ports	= 4,
3200 		.base_baud	= 115200,
3201 		.uart_offset	= 8,
3202 	},
3203 	[pbn_b1_8_115200] = {
3204 		.flags		= FL_BASE1,
3205 		.num_ports	= 8,
3206 		.base_baud	= 115200,
3207 		.uart_offset	= 8,
3208 	},
3209 	[pbn_b1_16_115200] = {
3210 		.flags		= FL_BASE1,
3211 		.num_ports	= 16,
3212 		.base_baud	= 115200,
3213 		.uart_offset	= 8,
3214 	},
3215 
3216 	[pbn_b1_1_921600] = {
3217 		.flags		= FL_BASE1,
3218 		.num_ports	= 1,
3219 		.base_baud	= 921600,
3220 		.uart_offset	= 8,
3221 	},
3222 	[pbn_b1_2_921600] = {
3223 		.flags		= FL_BASE1,
3224 		.num_ports	= 2,
3225 		.base_baud	= 921600,
3226 		.uart_offset	= 8,
3227 	},
3228 	[pbn_b1_4_921600] = {
3229 		.flags		= FL_BASE1,
3230 		.num_ports	= 4,
3231 		.base_baud	= 921600,
3232 		.uart_offset	= 8,
3233 	},
3234 	[pbn_b1_8_921600] = {
3235 		.flags		= FL_BASE1,
3236 		.num_ports	= 8,
3237 		.base_baud	= 921600,
3238 		.uart_offset	= 8,
3239 	},
3240 	[pbn_b1_2_1250000] = {
3241 		.flags		= FL_BASE1,
3242 		.num_ports	= 2,
3243 		.base_baud	= 1250000,
3244 		.uart_offset	= 8,
3245 	},
3246 
3247 	[pbn_b1_bt_1_115200] = {
3248 		.flags		= FL_BASE1|FL_BASE_BARS,
3249 		.num_ports	= 1,
3250 		.base_baud	= 115200,
3251 		.uart_offset	= 8,
3252 	},
3253 	[pbn_b1_bt_2_115200] = {
3254 		.flags		= FL_BASE1|FL_BASE_BARS,
3255 		.num_ports	= 2,
3256 		.base_baud	= 115200,
3257 		.uart_offset	= 8,
3258 	},
3259 	[pbn_b1_bt_4_115200] = {
3260 		.flags		= FL_BASE1|FL_BASE_BARS,
3261 		.num_ports	= 4,
3262 		.base_baud	= 115200,
3263 		.uart_offset	= 8,
3264 	},
3265 
3266 	[pbn_b1_bt_2_921600] = {
3267 		.flags		= FL_BASE1|FL_BASE_BARS,
3268 		.num_ports	= 2,
3269 		.base_baud	= 921600,
3270 		.uart_offset	= 8,
3271 	},
3272 
3273 	[pbn_b1_1_1382400] = {
3274 		.flags		= FL_BASE1,
3275 		.num_ports	= 1,
3276 		.base_baud	= 1382400,
3277 		.uart_offset	= 8,
3278 	},
3279 	[pbn_b1_2_1382400] = {
3280 		.flags		= FL_BASE1,
3281 		.num_ports	= 2,
3282 		.base_baud	= 1382400,
3283 		.uart_offset	= 8,
3284 	},
3285 	[pbn_b1_4_1382400] = {
3286 		.flags		= FL_BASE1,
3287 		.num_ports	= 4,
3288 		.base_baud	= 1382400,
3289 		.uart_offset	= 8,
3290 	},
3291 	[pbn_b1_8_1382400] = {
3292 		.flags		= FL_BASE1,
3293 		.num_ports	= 8,
3294 		.base_baud	= 1382400,
3295 		.uart_offset	= 8,
3296 	},
3297 
3298 	[pbn_b2_1_115200] = {
3299 		.flags		= FL_BASE2,
3300 		.num_ports	= 1,
3301 		.base_baud	= 115200,
3302 		.uart_offset	= 8,
3303 	},
3304 	[pbn_b2_2_115200] = {
3305 		.flags		= FL_BASE2,
3306 		.num_ports	= 2,
3307 		.base_baud	= 115200,
3308 		.uart_offset	= 8,
3309 	},
3310 	[pbn_b2_4_115200] = {
3311 		.flags          = FL_BASE2,
3312 		.num_ports      = 4,
3313 		.base_baud      = 115200,
3314 		.uart_offset    = 8,
3315 	},
3316 	[pbn_b2_8_115200] = {
3317 		.flags		= FL_BASE2,
3318 		.num_ports	= 8,
3319 		.base_baud	= 115200,
3320 		.uart_offset	= 8,
3321 	},
3322 
3323 	[pbn_b2_1_460800] = {
3324 		.flags		= FL_BASE2,
3325 		.num_ports	= 1,
3326 		.base_baud	= 460800,
3327 		.uart_offset	= 8,
3328 	},
3329 	[pbn_b2_4_460800] = {
3330 		.flags		= FL_BASE2,
3331 		.num_ports	= 4,
3332 		.base_baud	= 460800,
3333 		.uart_offset	= 8,
3334 	},
3335 	[pbn_b2_8_460800] = {
3336 		.flags		= FL_BASE2,
3337 		.num_ports	= 8,
3338 		.base_baud	= 460800,
3339 		.uart_offset	= 8,
3340 	},
3341 	[pbn_b2_16_460800] = {
3342 		.flags		= FL_BASE2,
3343 		.num_ports	= 16,
3344 		.base_baud	= 460800,
3345 		.uart_offset	= 8,
3346 	 },
3347 
3348 	[pbn_b2_1_921600] = {
3349 		.flags		= FL_BASE2,
3350 		.num_ports	= 1,
3351 		.base_baud	= 921600,
3352 		.uart_offset	= 8,
3353 	},
3354 	[pbn_b2_4_921600] = {
3355 		.flags		= FL_BASE2,
3356 		.num_ports	= 4,
3357 		.base_baud	= 921600,
3358 		.uart_offset	= 8,
3359 	},
3360 	[pbn_b2_8_921600] = {
3361 		.flags		= FL_BASE2,
3362 		.num_ports	= 8,
3363 		.base_baud	= 921600,
3364 		.uart_offset	= 8,
3365 	},
3366 
3367 	[pbn_b2_8_1152000] = {
3368 		.flags		= FL_BASE2,
3369 		.num_ports	= 8,
3370 		.base_baud	= 1152000,
3371 		.uart_offset	= 8,
3372 	},
3373 
3374 	[pbn_b2_bt_1_115200] = {
3375 		.flags		= FL_BASE2|FL_BASE_BARS,
3376 		.num_ports	= 1,
3377 		.base_baud	= 115200,
3378 		.uart_offset	= 8,
3379 	},
3380 	[pbn_b2_bt_2_115200] = {
3381 		.flags		= FL_BASE2|FL_BASE_BARS,
3382 		.num_ports	= 2,
3383 		.base_baud	= 115200,
3384 		.uart_offset	= 8,
3385 	},
3386 	[pbn_b2_bt_4_115200] = {
3387 		.flags		= FL_BASE2|FL_BASE_BARS,
3388 		.num_ports	= 4,
3389 		.base_baud	= 115200,
3390 		.uart_offset	= 8,
3391 	},
3392 
3393 	[pbn_b2_bt_2_921600] = {
3394 		.flags		= FL_BASE2|FL_BASE_BARS,
3395 		.num_ports	= 2,
3396 		.base_baud	= 921600,
3397 		.uart_offset	= 8,
3398 	},
3399 	[pbn_b2_bt_4_921600] = {
3400 		.flags		= FL_BASE2|FL_BASE_BARS,
3401 		.num_ports	= 4,
3402 		.base_baud	= 921600,
3403 		.uart_offset	= 8,
3404 	},
3405 
3406 	[pbn_b3_2_115200] = {
3407 		.flags		= FL_BASE3,
3408 		.num_ports	= 2,
3409 		.base_baud	= 115200,
3410 		.uart_offset	= 8,
3411 	},
3412 	[pbn_b3_4_115200] = {
3413 		.flags		= FL_BASE3,
3414 		.num_ports	= 4,
3415 		.base_baud	= 115200,
3416 		.uart_offset	= 8,
3417 	},
3418 	[pbn_b3_8_115200] = {
3419 		.flags		= FL_BASE3,
3420 		.num_ports	= 8,
3421 		.base_baud	= 115200,
3422 		.uart_offset	= 8,
3423 	},
3424 
3425 	[pbn_b4_bt_2_921600] = {
3426 		.flags		= FL_BASE4,
3427 		.num_ports	= 2,
3428 		.base_baud	= 921600,
3429 		.uart_offset	= 8,
3430 	},
3431 	[pbn_b4_bt_4_921600] = {
3432 		.flags		= FL_BASE4,
3433 		.num_ports	= 4,
3434 		.base_baud	= 921600,
3435 		.uart_offset	= 8,
3436 	},
3437 	[pbn_b4_bt_8_921600] = {
3438 		.flags		= FL_BASE4,
3439 		.num_ports	= 8,
3440 		.base_baud	= 921600,
3441 		.uart_offset	= 8,
3442 	},
3443 
3444 	/*
3445 	 * Entries following this are board-specific.
3446 	 */
3447 
3448 	/*
3449 	 * Panacom - IOMEM
3450 	 */
3451 	[pbn_panacom] = {
3452 		.flags		= FL_BASE2,
3453 		.num_ports	= 2,
3454 		.base_baud	= 921600,
3455 		.uart_offset	= 0x400,
3456 		.reg_shift	= 7,
3457 	},
3458 	[pbn_panacom2] = {
3459 		.flags		= FL_BASE2|FL_BASE_BARS,
3460 		.num_ports	= 2,
3461 		.base_baud	= 921600,
3462 		.uart_offset	= 0x400,
3463 		.reg_shift	= 7,
3464 	},
3465 	[pbn_panacom4] = {
3466 		.flags		= FL_BASE2|FL_BASE_BARS,
3467 		.num_ports	= 4,
3468 		.base_baud	= 921600,
3469 		.uart_offset	= 0x400,
3470 		.reg_shift	= 7,
3471 	},
3472 
3473 	/* I think this entry is broken - the first_offset looks wrong --rmk */
3474 	[pbn_plx_romulus] = {
3475 		.flags		= FL_BASE2,
3476 		.num_ports	= 4,
3477 		.base_baud	= 921600,
3478 		.uart_offset	= 8 << 2,
3479 		.reg_shift	= 2,
3480 		.first_offset	= 0x03,
3481 	},
3482 
3483 	/*
3484 	 * This board uses the size of PCI Base region 0 to
3485 	 * signal now many ports are available
3486 	 */
3487 	[pbn_oxsemi] = {
3488 		.flags		= FL_BASE0|FL_REGION_SZ_CAP,
3489 		.num_ports	= 32,
3490 		.base_baud	= 115200,
3491 		.uart_offset	= 8,
3492 	},
3493 	[pbn_oxsemi_1_15625000] = {
3494 		.flags		= FL_BASE0,
3495 		.num_ports	= 1,
3496 		.base_baud	= 15625000,
3497 		.uart_offset	= 0x200,
3498 		.first_offset	= 0x1000,
3499 	},
3500 	[pbn_oxsemi_2_15625000] = {
3501 		.flags		= FL_BASE0,
3502 		.num_ports	= 2,
3503 		.base_baud	= 15625000,
3504 		.uart_offset	= 0x200,
3505 		.first_offset	= 0x1000,
3506 	},
3507 	[pbn_oxsemi_4_15625000] = {
3508 		.flags		= FL_BASE0,
3509 		.num_ports	= 4,
3510 		.base_baud	= 15625000,
3511 		.uart_offset	= 0x200,
3512 		.first_offset	= 0x1000,
3513 	},
3514 	[pbn_oxsemi_8_15625000] = {
3515 		.flags		= FL_BASE0,
3516 		.num_ports	= 8,
3517 		.base_baud	= 15625000,
3518 		.uart_offset	= 0x200,
3519 		.first_offset	= 0x1000,
3520 	},
3521 
3522 
3523 	/*
3524 	 * EKF addition for i960 Boards form EKF with serial port.
3525 	 * Max 256 ports.
3526 	 */
3527 	[pbn_intel_i960] = {
3528 		.flags		= FL_BASE0,
3529 		.num_ports	= 32,
3530 		.base_baud	= 921600,
3531 		.uart_offset	= 8 << 2,
3532 		.reg_shift	= 2,
3533 		.first_offset	= 0x10000,
3534 	},
3535 	[pbn_sgi_ioc3] = {
3536 		.flags		= FL_BASE0|FL_NOIRQ,
3537 		.num_ports	= 1,
3538 		.base_baud	= 458333,
3539 		.uart_offset	= 8,
3540 		.reg_shift	= 0,
3541 		.first_offset	= 0x20178,
3542 	},
3543 
3544 	/*
3545 	 * Computone - uses IOMEM.
3546 	 */
3547 	[pbn_computone_4] = {
3548 		.flags		= FL_BASE0,
3549 		.num_ports	= 4,
3550 		.base_baud	= 921600,
3551 		.uart_offset	= 0x40,
3552 		.reg_shift	= 2,
3553 		.first_offset	= 0x200,
3554 	},
3555 	[pbn_computone_6] = {
3556 		.flags		= FL_BASE0,
3557 		.num_ports	= 6,
3558 		.base_baud	= 921600,
3559 		.uart_offset	= 0x40,
3560 		.reg_shift	= 2,
3561 		.first_offset	= 0x200,
3562 	},
3563 	[pbn_computone_8] = {
3564 		.flags		= FL_BASE0,
3565 		.num_ports	= 8,
3566 		.base_baud	= 921600,
3567 		.uart_offset	= 0x40,
3568 		.reg_shift	= 2,
3569 		.first_offset	= 0x200,
3570 	},
3571 	[pbn_sbsxrsio] = {
3572 		.flags		= FL_BASE0,
3573 		.num_ports	= 8,
3574 		.base_baud	= 460800,
3575 		.uart_offset	= 256,
3576 		.reg_shift	= 4,
3577 	},
3578 	/*
3579 	 * PA Semi PWRficient PA6T-1682M on-chip UART
3580 	 */
3581 	[pbn_pasemi_1682M] = {
3582 		.flags		= FL_BASE0,
3583 		.num_ports	= 1,
3584 		.base_baud	= 8333333,
3585 	},
3586 	/*
3587 	 * National Instruments 843x
3588 	 */
3589 	[pbn_ni8430_16] = {
3590 		.flags		= FL_BASE0,
3591 		.num_ports	= 16,
3592 		.base_baud	= 3686400,
3593 		.uart_offset	= 0x10,
3594 		.first_offset	= 0x800,
3595 	},
3596 	[pbn_ni8430_8] = {
3597 		.flags		= FL_BASE0,
3598 		.num_ports	= 8,
3599 		.base_baud	= 3686400,
3600 		.uart_offset	= 0x10,
3601 		.first_offset	= 0x800,
3602 	},
3603 	[pbn_ni8430_4] = {
3604 		.flags		= FL_BASE0,
3605 		.num_ports	= 4,
3606 		.base_baud	= 3686400,
3607 		.uart_offset	= 0x10,
3608 		.first_offset	= 0x800,
3609 	},
3610 	[pbn_ni8430_2] = {
3611 		.flags		= FL_BASE0,
3612 		.num_ports	= 2,
3613 		.base_baud	= 3686400,
3614 		.uart_offset	= 0x10,
3615 		.first_offset	= 0x800,
3616 	},
3617 	/*
3618 	 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3619 	 */
3620 	[pbn_ADDIDATA_PCIe_1_3906250] = {
3621 		.flags		= FL_BASE0,
3622 		.num_ports	= 1,
3623 		.base_baud	= 3906250,
3624 		.uart_offset	= 0x200,
3625 		.first_offset	= 0x1000,
3626 	},
3627 	[pbn_ADDIDATA_PCIe_2_3906250] = {
3628 		.flags		= FL_BASE0,
3629 		.num_ports	= 2,
3630 		.base_baud	= 3906250,
3631 		.uart_offset	= 0x200,
3632 		.first_offset	= 0x1000,
3633 	},
3634 	[pbn_ADDIDATA_PCIe_4_3906250] = {
3635 		.flags		= FL_BASE0,
3636 		.num_ports	= 4,
3637 		.base_baud	= 3906250,
3638 		.uart_offset	= 0x200,
3639 		.first_offset	= 0x1000,
3640 	},
3641 	[pbn_ADDIDATA_PCIe_8_3906250] = {
3642 		.flags		= FL_BASE0,
3643 		.num_ports	= 8,
3644 		.base_baud	= 3906250,
3645 		.uart_offset	= 0x200,
3646 		.first_offset	= 0x1000,
3647 	},
3648 	[pbn_ce4100_1_115200] = {
3649 		.flags		= FL_BASE_BARS,
3650 		.num_ports	= 2,
3651 		.base_baud	= 921600,
3652 		.reg_shift      = 2,
3653 	},
3654 	[pbn_omegapci] = {
3655 		.flags		= FL_BASE0,
3656 		.num_ports	= 8,
3657 		.base_baud	= 115200,
3658 		.uart_offset	= 0x200,
3659 	},
3660 	[pbn_NETMOS9900_2s_115200] = {
3661 		.flags		= FL_BASE0,
3662 		.num_ports	= 2,
3663 		.base_baud	= 115200,
3664 	},
3665 	[pbn_brcm_trumanage] = {
3666 		.flags		= FL_BASE0,
3667 		.num_ports	= 1,
3668 		.reg_shift	= 2,
3669 		.base_baud	= 115200,
3670 	},
3671 	[pbn_fintek_4] = {
3672 		.num_ports	= 4,
3673 		.uart_offset	= 8,
3674 		.base_baud	= 115200,
3675 		.first_offset	= 0x40,
3676 	},
3677 	[pbn_fintek_8] = {
3678 		.num_ports	= 8,
3679 		.uart_offset	= 8,
3680 		.base_baud	= 115200,
3681 		.first_offset	= 0x40,
3682 	},
3683 	[pbn_fintek_12] = {
3684 		.num_ports	= 12,
3685 		.uart_offset	= 8,
3686 		.base_baud	= 115200,
3687 		.first_offset	= 0x40,
3688 	},
3689 	[pbn_fintek_F81504A] = {
3690 		.num_ports	= 4,
3691 		.uart_offset	= 8,
3692 		.base_baud	= 115200,
3693 	},
3694 	[pbn_fintek_F81508A] = {
3695 		.num_ports	= 8,
3696 		.uart_offset	= 8,
3697 		.base_baud	= 115200,
3698 	},
3699 	[pbn_fintek_F81512A] = {
3700 		.num_ports	= 12,
3701 		.uart_offset	= 8,
3702 		.base_baud	= 115200,
3703 	},
3704 	[pbn_wch382_2] = {
3705 		.flags		= FL_BASE0,
3706 		.num_ports	= 2,
3707 		.base_baud	= 115200,
3708 		.uart_offset	= 8,
3709 		.first_offset	= 0xC0,
3710 	},
3711 	[pbn_wch384_4] = {
3712 		.flags		= FL_BASE0,
3713 		.num_ports	= 4,
3714 		.base_baud      = 115200,
3715 		.uart_offset    = 8,
3716 		.first_offset   = 0xC0,
3717 	},
3718 	[pbn_wch384_8] = {
3719 		.flags		= FL_BASE0,
3720 		.num_ports	= 8,
3721 		.base_baud      = 115200,
3722 		.uart_offset    = 8,
3723 		.first_offset   = 0x00,
3724 	},
3725 	[pbn_sunix_pci_1s] = {
3726 		.num_ports	= 1,
3727 		.base_baud      = 921600,
3728 		.uart_offset	= 0x8,
3729 	},
3730 	[pbn_sunix_pci_2s] = {
3731 		.num_ports	= 2,
3732 		.base_baud      = 921600,
3733 		.uart_offset	= 0x8,
3734 	},
3735 	[pbn_sunix_pci_4s] = {
3736 		.num_ports	= 4,
3737 		.base_baud      = 921600,
3738 		.uart_offset	= 0x8,
3739 	},
3740 	[pbn_sunix_pci_8s] = {
3741 		.num_ports	= 8,
3742 		.base_baud      = 921600,
3743 		.uart_offset	= 0x8,
3744 	},
3745 	[pbn_sunix_pci_16s] = {
3746 		.num_ports	= 16,
3747 		.base_baud      = 921600,
3748 		.uart_offset	= 0x8,
3749 	},
3750 	[pbn_titan_1_4000000] = {
3751 		.flags		= FL_BASE0,
3752 		.num_ports	= 1,
3753 		.base_baud	= 4000000,
3754 		.uart_offset	= 0x200,
3755 		.first_offset	= 0x1000,
3756 	},
3757 	[pbn_titan_2_4000000] = {
3758 		.flags		= FL_BASE0,
3759 		.num_ports	= 2,
3760 		.base_baud	= 4000000,
3761 		.uart_offset	= 0x200,
3762 		.first_offset	= 0x1000,
3763 	},
3764 	[pbn_titan_4_4000000] = {
3765 		.flags		= FL_BASE0,
3766 		.num_ports	= 4,
3767 		.base_baud	= 4000000,
3768 		.uart_offset	= 0x200,
3769 		.first_offset	= 0x1000,
3770 	},
3771 	[pbn_titan_8_4000000] = {
3772 		.flags		= FL_BASE0,
3773 		.num_ports	= 8,
3774 		.base_baud	= 4000000,
3775 		.uart_offset	= 0x200,
3776 		.first_offset	= 0x1000,
3777 	},
3778 	[pbn_moxa8250_2p] = {
3779 		.flags		= FL_BASE1,
3780 		.num_ports      = 2,
3781 		.base_baud      = 921600,
3782 		.uart_offset	= 0x200,
3783 	},
3784 	[pbn_moxa8250_4p] = {
3785 		.flags		= FL_BASE1,
3786 		.num_ports      = 4,
3787 		.base_baud      = 921600,
3788 		.uart_offset	= 0x200,
3789 	},
3790 	[pbn_moxa8250_8p] = {
3791 		.flags		= FL_BASE1,
3792 		.num_ports      = 8,
3793 		.base_baud      = 921600,
3794 		.uart_offset	= 0x200,
3795 	},
3796 };
3797 
3798 #define REPORT_CONFIG(option) \
3799 	(IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3800 #define REPORT_8250_CONFIG(option) \
3801 	(IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3802 	 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3803 
3804 static const struct pci_device_id blacklist[] = {
3805 	/* softmodems */
3806 	{ PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3807 	{ PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3808 	{ PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3809 
3810 	/* multi-io cards handled by parport_serial */
3811 	/* WCH CH353 2S1P */
3812 	{ PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3813 	/* WCH CH353 1S1P */
3814 	{ PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3815 	/* WCH CH382 2S1P */
3816 	{ PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3817 
3818 	/* Intel platforms with MID UART */
3819 	{ PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3820 	{ PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3821 	{ PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3822 	{ PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3823 	{ PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3824 	{ PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3825 
3826 	/* Intel platforms with DesignWare UART */
3827 	{ PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3828 	{ PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3829 	{ PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3830 	{ PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3831 	{ PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
3832 	{ PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
3833 	{ PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
3834 	{ PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
3835 	{ PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
3836 	{ PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
3837 	{ PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
3838 	{ PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
3839 	{ PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
3840 
3841 	/* Exar devices */
3842 	{ PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3843 	{ PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3844 
3845 	/* Pericom devices */
3846 	{ PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3847 	{ PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3848 
3849 	/* End of the black list */
3850 	{ }
3851 };
3852 
serial_pci_is_class_communication(struct pci_dev * dev)3853 static int serial_pci_is_class_communication(struct pci_dev *dev)
3854 {
3855 	/*
3856 	 * If it is not a communications device or the programming
3857 	 * interface is greater than 6, give up.
3858 	 */
3859 	if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3860 	     ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3861 	     ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3862 	    (dev->class & 0xff) > 6)
3863 		return -ENODEV;
3864 
3865 	return 0;
3866 }
3867 
3868 /*
3869  * Given a complete unknown PCI device, try to use some heuristics to
3870  * guess what the configuration might be, based on the pitiful PCI
3871  * serial specs.  Returns 0 on success, -ENODEV on failure.
3872  */
3873 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3874 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3875 {
3876 	int num_iomem, num_port, first_port = -1, i;
3877 	int rc;
3878 
3879 	rc = serial_pci_is_class_communication(dev);
3880 	if (rc)
3881 		return rc;
3882 
3883 	/*
3884 	 * Should we try to make guesses for multiport serial devices later?
3885 	 */
3886 	if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3887 		return -ENODEV;
3888 
3889 	num_iomem = num_port = 0;
3890 	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3891 		if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3892 			num_port++;
3893 			if (first_port == -1)
3894 				first_port = i;
3895 		}
3896 		if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3897 			num_iomem++;
3898 	}
3899 
3900 	/*
3901 	 * If there is 1 or 0 iomem regions, and exactly one port,
3902 	 * use it.  We guess the number of ports based on the IO
3903 	 * region size.
3904 	 */
3905 	if (num_iomem <= 1 && num_port == 1) {
3906 		board->flags = first_port;
3907 		board->num_ports = pci_resource_len(dev, first_port) / 8;
3908 		return 0;
3909 	}
3910 
3911 	/*
3912 	 * Now guess if we've got a board which indexes by BARs.
3913 	 * Each IO BAR should be 8 bytes, and they should follow
3914 	 * consecutively.
3915 	 */
3916 	first_port = -1;
3917 	num_port = 0;
3918 	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3919 		if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3920 		    pci_resource_len(dev, i) == 8 &&
3921 		    (first_port == -1 || (first_port + num_port) == i)) {
3922 			num_port++;
3923 			if (first_port == -1)
3924 				first_port = i;
3925 		}
3926 	}
3927 
3928 	if (num_port > 1) {
3929 		board->flags = first_port | FL_BASE_BARS;
3930 		board->num_ports = num_port;
3931 		return 0;
3932 	}
3933 
3934 	return -ENODEV;
3935 }
3936 
3937 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3938 serial_pci_matches(const struct pciserial_board *board,
3939 		   const struct pciserial_board *guessed)
3940 {
3941 	return
3942 	    board->num_ports == guessed->num_ports &&
3943 	    board->base_baud == guessed->base_baud &&
3944 	    board->uart_offset == guessed->uart_offset &&
3945 	    board->reg_shift == guessed->reg_shift &&
3946 	    board->first_offset == guessed->first_offset;
3947 }
3948 
3949 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3950 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3951 {
3952 	struct uart_8250_port uart;
3953 	struct serial_private *priv;
3954 	struct pci_serial_quirk *quirk;
3955 	int rc, nr_ports, i;
3956 
3957 	nr_ports = board->num_ports;
3958 
3959 	/*
3960 	 * Find an init and setup quirks.
3961 	 */
3962 	quirk = find_quirk(dev);
3963 
3964 	/*
3965 	 * Run the new-style initialization function.
3966 	 * The initialization function returns:
3967 	 *  <0  - error
3968 	 *   0  - use board->num_ports
3969 	 *  >0  - number of ports
3970 	 */
3971 	if (quirk->init) {
3972 		rc = quirk->init(dev);
3973 		if (rc < 0) {
3974 			priv = ERR_PTR(rc);
3975 			goto err_out;
3976 		}
3977 		if (rc)
3978 			nr_ports = rc;
3979 	}
3980 
3981 	priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
3982 	if (!priv) {
3983 		priv = ERR_PTR(-ENOMEM);
3984 		goto err_deinit;
3985 	}
3986 
3987 	priv->dev = dev;
3988 	priv->quirk = quirk;
3989 
3990 	memset(&uart, 0, sizeof(uart));
3991 	uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3992 	uart.port.uartclk = board->base_baud * 16;
3993 
3994 	if (board->flags & FL_NOIRQ) {
3995 		uart.port.irq = 0;
3996 	} else {
3997 		if (pci_match_id(pci_use_msi, dev)) {
3998 			pci_dbg(dev, "Using MSI(-X) interrupts\n");
3999 			pci_set_master(dev);
4000 			uart.port.flags &= ~UPF_SHARE_IRQ;
4001 			rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4002 		} else {
4003 			pci_dbg(dev, "Using legacy interrupts\n");
4004 			rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
4005 		}
4006 		if (rc < 0) {
4007 			kfree(priv);
4008 			priv = ERR_PTR(rc);
4009 			goto err_deinit;
4010 		}
4011 
4012 		uart.port.irq = pci_irq_vector(dev, 0);
4013 	}
4014 
4015 	uart.port.dev = &dev->dev;
4016 
4017 	for (i = 0; i < nr_ports; i++) {
4018 		if (quirk->setup(priv, board, &uart, i))
4019 			break;
4020 
4021 		pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4022 			uart.port.iobase, uart.port.irq, uart.port.iotype);
4023 
4024 		priv->line[i] = serial8250_register_8250_port(&uart);
4025 		if (priv->line[i] < 0) {
4026 			pci_err(dev,
4027 				"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4028 				uart.port.iobase, uart.port.irq,
4029 				uart.port.iotype, priv->line[i]);
4030 			break;
4031 		}
4032 	}
4033 	priv->nr = i;
4034 	priv->board = board;
4035 	return priv;
4036 
4037 err_deinit:
4038 	if (quirk->exit)
4039 		quirk->exit(dev);
4040 err_out:
4041 	return priv;
4042 }
4043 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4044 
pciserial_detach_ports(struct serial_private * priv)4045 static void pciserial_detach_ports(struct serial_private *priv)
4046 {
4047 	struct pci_serial_quirk *quirk;
4048 	int i;
4049 
4050 	for (i = 0; i < priv->nr; i++)
4051 		serial8250_unregister_port(priv->line[i]);
4052 
4053 	/*
4054 	 * Find the exit quirks.
4055 	 */
4056 	quirk = find_quirk(priv->dev);
4057 	if (quirk->exit)
4058 		quirk->exit(priv->dev);
4059 }
4060 
pciserial_remove_ports(struct serial_private * priv)4061 void pciserial_remove_ports(struct serial_private *priv)
4062 {
4063 	pciserial_detach_ports(priv);
4064 	kfree(priv);
4065 }
4066 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4067 
pciserial_suspend_ports(struct serial_private * priv)4068 void pciserial_suspend_ports(struct serial_private *priv)
4069 {
4070 	int i;
4071 
4072 	for (i = 0; i < priv->nr; i++)
4073 		if (priv->line[i] >= 0)
4074 			serial8250_suspend_port(priv->line[i]);
4075 
4076 	/*
4077 	 * Ensure that every init quirk is properly torn down
4078 	 */
4079 	if (priv->quirk->exit)
4080 		priv->quirk->exit(priv->dev);
4081 }
4082 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4083 
pciserial_resume_ports(struct serial_private * priv)4084 void pciserial_resume_ports(struct serial_private *priv)
4085 {
4086 	int i;
4087 
4088 	/*
4089 	 * Ensure that the board is correctly configured.
4090 	 */
4091 	if (priv->quirk->init)
4092 		priv->quirk->init(priv->dev);
4093 
4094 	for (i = 0; i < priv->nr; i++)
4095 		if (priv->line[i] >= 0)
4096 			serial8250_resume_port(priv->line[i]);
4097 }
4098 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4099 
4100 /*
4101  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4102  * to the arrangement of serial ports on a PCI card.
4103  */
4104 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4105 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4106 {
4107 	struct pci_serial_quirk *quirk;
4108 	struct serial_private *priv;
4109 	const struct pciserial_board *board;
4110 	const struct pci_device_id *exclude;
4111 	struct pciserial_board tmp;
4112 	int rc;
4113 
4114 	quirk = find_quirk(dev);
4115 	if (quirk->probe) {
4116 		rc = quirk->probe(dev);
4117 		if (rc)
4118 			return rc;
4119 	}
4120 
4121 	if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4122 		pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4123 		return -EINVAL;
4124 	}
4125 
4126 	board = &pci_boards[ent->driver_data];
4127 
4128 	exclude = pci_match_id(blacklist, dev);
4129 	if (exclude) {
4130 		if (exclude->driver_data)
4131 			pci_warn(dev, "ignoring port, enable %s to handle\n",
4132 				 (const char *)exclude->driver_data);
4133 		return -ENODEV;
4134 	}
4135 
4136 	rc = pcim_enable_device(dev);
4137 	pci_save_state(dev);
4138 	if (rc)
4139 		return rc;
4140 
4141 	if (ent->driver_data == pbn_default) {
4142 		/*
4143 		 * Use a copy of the pci_board entry for this;
4144 		 * avoid changing entries in the table.
4145 		 */
4146 		memcpy(&tmp, board, sizeof(struct pciserial_board));
4147 		board = &tmp;
4148 
4149 		/*
4150 		 * We matched one of our class entries.  Try to
4151 		 * determine the parameters of this board.
4152 		 */
4153 		rc = serial_pci_guess_board(dev, &tmp);
4154 		if (rc)
4155 			return rc;
4156 	} else {
4157 		/*
4158 		 * We matched an explicit entry.  If we are able to
4159 		 * detect this boards settings with our heuristic,
4160 		 * then we no longer need this entry.
4161 		 */
4162 		memcpy(&tmp, &pci_boards[pbn_default],
4163 		       sizeof(struct pciserial_board));
4164 		rc = serial_pci_guess_board(dev, &tmp);
4165 		if (rc == 0 && serial_pci_matches(board, &tmp))
4166 			moan_device("Redundant entry in serial pci_table.",
4167 				    dev);
4168 	}
4169 
4170 	priv = pciserial_init_ports(dev, board);
4171 	if (IS_ERR(priv))
4172 		return PTR_ERR(priv);
4173 
4174 	pci_set_drvdata(dev, priv);
4175 	return 0;
4176 }
4177 
pciserial_remove_one(struct pci_dev * dev)4178 static void pciserial_remove_one(struct pci_dev *dev)
4179 {
4180 	struct serial_private *priv = pci_get_drvdata(dev);
4181 
4182 	pciserial_remove_ports(priv);
4183 }
4184 
4185 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4186 static int pciserial_suspend_one(struct device *dev)
4187 {
4188 	struct serial_private *priv = dev_get_drvdata(dev);
4189 
4190 	if (priv)
4191 		pciserial_suspend_ports(priv);
4192 
4193 	return 0;
4194 }
4195 
pciserial_resume_one(struct device * dev)4196 static int pciserial_resume_one(struct device *dev)
4197 {
4198 	struct pci_dev *pdev = to_pci_dev(dev);
4199 	struct serial_private *priv = pci_get_drvdata(pdev);
4200 	int err;
4201 
4202 	if (priv) {
4203 		/*
4204 		 * The device may have been disabled.  Re-enable it.
4205 		 */
4206 		err = pci_enable_device(pdev);
4207 		/* FIXME: We cannot simply error out here */
4208 		if (err)
4209 			pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4210 		pciserial_resume_ports(priv);
4211 	}
4212 	return 0;
4213 }
4214 #endif
4215 
4216 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4217 			 pciserial_resume_one);
4218 
4219 static const struct pci_device_id serial_pci_tbl[] = {
4220 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4221 		PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4222 		pbn_b0_4_921600 },
4223 	/* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4224 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4225 		PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4226 		pbn_b2_8_921600 },
4227 	/* Advantech also use 0x3618 and 0xf618 */
4228 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4229 		PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4230 		pbn_b0_4_921600 },
4231 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4232 		PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4233 		pbn_b0_4_921600 },
4234 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4235 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4236 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4237 		pbn_b1_8_1382400 },
4238 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4239 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4240 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4241 		pbn_b1_4_1382400 },
4242 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4243 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4244 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4245 		pbn_b1_2_1382400 },
4246 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4247 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4248 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4249 		pbn_b1_8_1382400 },
4250 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4251 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4252 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4253 		pbn_b1_4_1382400 },
4254 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4255 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4256 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4257 		pbn_b1_2_1382400 },
4258 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4259 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4260 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4261 		pbn_b1_8_921600 },
4262 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4263 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4264 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4265 		pbn_b1_8_921600 },
4266 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4267 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4268 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4269 		pbn_b1_4_921600 },
4270 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4271 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4272 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4273 		pbn_b1_4_921600 },
4274 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4275 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4276 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4277 		pbn_b1_2_921600 },
4278 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4279 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4280 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4281 		pbn_b1_8_921600 },
4282 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4283 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4284 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4285 		pbn_b1_8_921600 },
4286 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4287 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4288 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4289 		pbn_b1_4_921600 },
4290 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4291 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4292 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4293 		pbn_b1_2_1250000 },
4294 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4295 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4296 		PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4297 		pbn_b0_2_1843200 },
4298 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4299 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4300 		PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4301 		pbn_b0_4_1843200 },
4302 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4303 		PCI_VENDOR_ID_AFAVLAB,
4304 		PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4305 		pbn_b0_4_1152000 },
4306 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4307 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308 		pbn_b2_bt_1_115200 },
4309 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4310 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 		pbn_b2_bt_2_115200 },
4312 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4313 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 		pbn_b2_bt_4_115200 },
4315 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4316 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4317 		pbn_b2_bt_2_115200 },
4318 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4319 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 		pbn_b2_bt_4_115200 },
4321 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4322 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 		pbn_b2_8_115200 },
4324 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4325 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4326 		pbn_b2_8_460800 },
4327 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4328 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4329 		pbn_b2_8_115200 },
4330 
4331 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4332 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 		pbn_b2_bt_2_115200 },
4334 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4335 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 		pbn_b2_bt_2_921600 },
4337 	/*
4338 	 * VScom SPCOM800, from sl@s.pl
4339 	 */
4340 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4341 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 		pbn_b2_8_921600 },
4343 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4344 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 		pbn_b2_4_921600 },
4346 	/* Unknown card - subdevice 0x1584 */
4347 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4348 		PCI_VENDOR_ID_PLX,
4349 		PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4350 		pbn_b2_4_115200 },
4351 	/* Unknown card - subdevice 0x1588 */
4352 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4353 		PCI_VENDOR_ID_PLX,
4354 		PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4355 		pbn_b2_8_115200 },
4356 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4357 		PCI_SUBVENDOR_ID_KEYSPAN,
4358 		PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4359 		pbn_panacom },
4360 	{	PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4361 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362 		pbn_panacom4 },
4363 	{	PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4364 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365 		pbn_panacom2 },
4366 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4367 		PCI_VENDOR_ID_ESDGMBH,
4368 		PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4369 		pbn_b2_4_115200 },
4370 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4371 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4372 		PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4373 		pbn_b2_4_460800 },
4374 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4375 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4376 		PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4377 		pbn_b2_8_460800 },
4378 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4379 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4380 		PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4381 		pbn_b2_16_460800 },
4382 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4383 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4384 		PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4385 		pbn_b2_16_460800 },
4386 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4387 		PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4388 		PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4389 		pbn_b2_4_460800 },
4390 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4391 		PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4392 		PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4393 		pbn_b2_8_460800 },
4394 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4395 		PCI_SUBVENDOR_ID_EXSYS,
4396 		PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4397 		pbn_b2_4_115200 },
4398 	/*
4399 	 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4400 	 * (Exoray@isys.ca)
4401 	 */
4402 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4403 		0x10b5, 0x106a, 0, 0,
4404 		pbn_plx_romulus },
4405 	/*
4406 	 * Quatech cards. These actually have configurable clocks but for
4407 	 * now we just use the default.
4408 	 *
4409 	 * 100 series are RS232, 200 series RS422,
4410 	 */
4411 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4412 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 		pbn_b1_4_115200 },
4414 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4415 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 		pbn_b1_2_115200 },
4417 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4418 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 		pbn_b2_2_115200 },
4420 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4421 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 		pbn_b1_2_115200 },
4423 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4424 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 		pbn_b2_2_115200 },
4426 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4427 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 		pbn_b1_4_115200 },
4429 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4430 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 		pbn_b1_8_115200 },
4432 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4433 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 		pbn_b1_8_115200 },
4435 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4436 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 		pbn_b1_4_115200 },
4438 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4439 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 		pbn_b1_2_115200 },
4441 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4442 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 		pbn_b1_4_115200 },
4444 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4445 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 		pbn_b1_2_115200 },
4447 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4448 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 		pbn_b2_4_115200 },
4450 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4451 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 		pbn_b2_2_115200 },
4453 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4454 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455 		pbn_b2_1_115200 },
4456 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4457 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 		pbn_b2_4_115200 },
4459 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4460 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 		pbn_b2_2_115200 },
4462 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4463 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 		pbn_b2_1_115200 },
4465 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4466 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 		pbn_b0_8_115200 },
4468 
4469 	{	PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4470 		PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4471 		0, 0,
4472 		pbn_b0_4_921600 },
4473 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4474 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4475 		0, 0,
4476 		pbn_b0_4_1152000 },
4477 	{	PCI_VENDOR_ID_OXSEMI, 0x9505,
4478 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 		pbn_b0_bt_2_921600 },
4480 
4481 		/*
4482 		 * The below card is a little controversial since it is the
4483 		 * subject of a PCI vendor/device ID clash.  (See
4484 		 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4485 		 * For now just used the hex ID 0x950a.
4486 		 */
4487 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4488 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4489 		0, 0, pbn_b0_2_115200 },
4490 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4491 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4492 		0, 0, pbn_b0_2_115200 },
4493 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4494 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 		pbn_b0_2_1130000 },
4496 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4497 		PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4498 		pbn_b0_1_921600 },
4499 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4500 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 		pbn_b0_4_115200 },
4502 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4503 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 		pbn_b0_bt_2_921600 },
4505 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4506 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 		pbn_b2_8_1152000 },
4508 
4509 	/*
4510 	 * Oxford Semiconductor Inc. Tornado PCI express device range.
4511 	 */
4512 	{	PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4513 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 		pbn_b0_1_15625000 },
4515 	{	PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4516 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 		pbn_b0_1_15625000 },
4518 	{	PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4519 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 		pbn_oxsemi_1_15625000 },
4521 	{	PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4522 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 		pbn_oxsemi_1_15625000 },
4524 	{	PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4525 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 		pbn_b0_1_15625000 },
4527 	{	PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4528 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 		pbn_b0_1_15625000 },
4530 	{	PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4531 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 		pbn_oxsemi_1_15625000 },
4533 	{	PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4534 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 		pbn_oxsemi_1_15625000 },
4536 	{	PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4537 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 		pbn_b0_1_15625000 },
4539 	{	PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4540 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 		pbn_b0_1_15625000 },
4542 	{	PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4543 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 		pbn_b0_1_15625000 },
4545 	{	PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4546 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 		pbn_b0_1_15625000 },
4548 	{	PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4549 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 		pbn_oxsemi_2_15625000 },
4551 	{	PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4552 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 		pbn_oxsemi_2_15625000 },
4554 	{	PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4555 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 		pbn_oxsemi_4_15625000 },
4557 	{	PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4558 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 		pbn_oxsemi_4_15625000 },
4560 	{	PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4561 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562 		pbn_oxsemi_8_15625000 },
4563 	{	PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4564 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 		pbn_oxsemi_8_15625000 },
4566 	{	PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4567 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 		pbn_oxsemi_1_15625000 },
4569 	{	PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4570 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 		pbn_oxsemi_1_15625000 },
4572 	{	PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4573 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 		pbn_oxsemi_1_15625000 },
4575 	{	PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4576 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 		pbn_oxsemi_1_15625000 },
4578 	{	PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4579 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 		pbn_oxsemi_1_15625000 },
4581 	{	PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4582 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 		pbn_oxsemi_1_15625000 },
4584 	{	PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4585 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 		pbn_oxsemi_1_15625000 },
4587 	{	PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4588 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 		pbn_oxsemi_1_15625000 },
4590 	{	PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4591 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 		pbn_oxsemi_1_15625000 },
4593 	{	PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4594 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 		pbn_oxsemi_1_15625000 },
4596 	{	PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4597 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 		pbn_oxsemi_1_15625000 },
4599 	{	PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4600 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 		pbn_oxsemi_1_15625000 },
4602 	{	PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4603 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 		pbn_oxsemi_1_15625000 },
4605 	{	PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4606 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 		pbn_oxsemi_1_15625000 },
4608 	{	PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4609 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 		pbn_oxsemi_1_15625000 },
4611 	{	PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4612 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 		pbn_oxsemi_1_15625000 },
4614 	{	PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4615 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 		pbn_oxsemi_1_15625000 },
4617 	{	PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4618 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 		pbn_oxsemi_1_15625000 },
4620 	{	PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4621 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 		pbn_oxsemi_1_15625000 },
4623 	{	PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4624 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 		pbn_oxsemi_1_15625000 },
4626 	{	PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4627 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 		pbn_oxsemi_1_15625000 },
4629 	{	PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4630 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 		pbn_oxsemi_1_15625000 },
4632 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4633 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 		pbn_oxsemi_1_15625000 },
4635 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4636 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 		pbn_oxsemi_1_15625000 },
4638 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4639 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 		pbn_oxsemi_1_15625000 },
4641 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4642 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 		pbn_oxsemi_1_15625000 },
4644 	/*
4645 	 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4646 	 */
4647 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 1 Port V.34 Super-G3 Fax */
4648 		PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4649 		pbn_oxsemi_1_15625000 },
4650 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 2 Port V.34 Super-G3 Fax */
4651 		PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4652 		pbn_oxsemi_2_15625000 },
4653 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 4 Port V.34 Super-G3 Fax */
4654 		PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4655 		pbn_oxsemi_4_15625000 },
4656 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 8 Port V.34 Super-G3 Fax */
4657 		PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4658 		pbn_oxsemi_8_15625000 },
4659 
4660 	/*
4661 	 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4662 	 */
4663 	{	PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4664 		PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4665 		pbn_oxsemi_2_15625000 },
4666 	/*
4667 	 * EndRun Technologies. PCI express device range.
4668 	 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4669 	 */
4670 	{	PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4671 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 		pbn_oxsemi_2_15625000 },
4673 
4674 	/*
4675 	 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4676 	 * from skokodyn@yahoo.com
4677 	 */
4678 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4679 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4680 		pbn_sbsxrsio },
4681 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4682 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4683 		pbn_sbsxrsio },
4684 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4685 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4686 		pbn_sbsxrsio },
4687 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4688 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4689 		pbn_sbsxrsio },
4690 
4691 	/*
4692 	 * Digitan DS560-558, from jimd@esoft.com
4693 	 */
4694 	{	PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4695 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 		pbn_b1_1_115200 },
4697 
4698 	/*
4699 	 * Titan Electronic cards
4700 	 *  The 400L and 800L have a custom setup quirk.
4701 	 */
4702 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4703 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 		pbn_b0_1_921600 },
4705 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4706 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 		pbn_b0_2_921600 },
4708 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4709 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 		pbn_b0_4_921600 },
4711 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4712 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 		pbn_b0_4_921600 },
4714 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4715 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 		pbn_b1_1_921600 },
4717 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4718 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 		pbn_b1_bt_2_921600 },
4720 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4721 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 		pbn_b0_bt_4_921600 },
4723 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4724 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 		pbn_b0_bt_8_921600 },
4726 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4727 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 		pbn_b4_bt_2_921600 },
4729 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4730 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 		pbn_b4_bt_4_921600 },
4732 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4733 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 		pbn_b4_bt_8_921600 },
4735 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4736 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 		pbn_b0_4_921600 },
4738 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4739 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 		pbn_b0_4_921600 },
4741 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4742 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 		pbn_b0_4_921600 },
4744 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4745 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 		pbn_titan_1_4000000 },
4747 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4748 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 		pbn_titan_2_4000000 },
4750 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4751 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 		pbn_titan_4_4000000 },
4753 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4754 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 		pbn_titan_8_4000000 },
4756 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4757 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 		pbn_titan_2_4000000 },
4759 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4760 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 		pbn_titan_2_4000000 },
4762 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4763 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 		pbn_b0_bt_2_921600 },
4765 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4766 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 		pbn_b0_4_921600 },
4768 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4769 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 		pbn_b0_4_921600 },
4771 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4772 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 		pbn_b0_4_921600 },
4774 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4775 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 		pbn_b0_4_921600 },
4777 
4778 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4779 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 		pbn_b2_1_460800 },
4781 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4782 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 		pbn_b2_1_460800 },
4784 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4785 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 		pbn_b2_1_460800 },
4787 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4788 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 		pbn_b2_bt_2_921600 },
4790 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4791 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 		pbn_b2_bt_2_921600 },
4793 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4794 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 		pbn_b2_bt_2_921600 },
4796 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4797 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 		pbn_b2_bt_4_921600 },
4799 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4800 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 		pbn_b2_bt_4_921600 },
4802 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4803 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 		pbn_b2_bt_4_921600 },
4805 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4806 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 		pbn_b0_1_921600 },
4808 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4809 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 		pbn_b0_1_921600 },
4811 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4812 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 		pbn_b0_1_921600 },
4814 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4815 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816 		pbn_b0_bt_2_921600 },
4817 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4818 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 		pbn_b0_bt_2_921600 },
4820 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4821 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 		pbn_b0_bt_2_921600 },
4823 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4824 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 		pbn_b0_bt_4_921600 },
4826 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4827 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828 		pbn_b0_bt_4_921600 },
4829 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4830 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831 		pbn_b0_bt_4_921600 },
4832 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4833 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834 		pbn_b0_bt_8_921600 },
4835 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4836 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837 		pbn_b0_bt_8_921600 },
4838 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4839 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 		pbn_b0_bt_8_921600 },
4841 
4842 	/*
4843 	 * Computone devices submitted by Doug McNash dmcnash@computone.com
4844 	 */
4845 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4846 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4847 		0, 0, pbn_computone_4 },
4848 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4849 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4850 		0, 0, pbn_computone_8 },
4851 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4852 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4853 		0, 0, pbn_computone_6 },
4854 
4855 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4856 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 		pbn_oxsemi },
4858 	{	PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4859 		PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4860 		pbn_b0_bt_1_921600 },
4861 
4862 	/*
4863 	 * Sunix PCI serial boards
4864 	 */
4865 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4866 		PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4867 		pbn_sunix_pci_1s },
4868 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4869 		PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4870 		pbn_sunix_pci_2s },
4871 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4872 		PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4873 		pbn_sunix_pci_4s },
4874 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4875 		PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4876 		pbn_sunix_pci_4s },
4877 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4878 		PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4879 		pbn_sunix_pci_8s },
4880 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4881 		PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4882 		pbn_sunix_pci_8s },
4883 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4884 		PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4885 		pbn_sunix_pci_16s },
4886 
4887 	/*
4888 	 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4889 	 */
4890 	{	PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4891 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 		pbn_b0_bt_8_115200 },
4893 	{	PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4894 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 		pbn_b0_bt_8_115200 },
4896 
4897 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4898 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 		pbn_b0_bt_2_115200 },
4900 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4901 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 		pbn_b0_bt_2_115200 },
4903 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4904 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 		pbn_b0_bt_2_115200 },
4906 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4907 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 		pbn_b0_bt_2_115200 },
4909 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4910 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 		pbn_b0_bt_2_115200 },
4912 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4913 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 		pbn_b0_bt_4_460800 },
4915 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4916 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 		pbn_b0_bt_4_460800 },
4918 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4919 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 		pbn_b0_bt_2_460800 },
4921 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4922 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 		pbn_b0_bt_2_460800 },
4924 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4925 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 		pbn_b0_bt_2_460800 },
4927 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4928 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 		pbn_b0_bt_1_115200 },
4930 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4931 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 		pbn_b0_bt_1_460800 },
4933 
4934 	/*
4935 	 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4936 	 * Cards are identified by their subsystem vendor IDs, which
4937 	 * (in hex) match the model number.
4938 	 *
4939 	 * Note that JC140x are RS422/485 cards which require ox950
4940 	 * ACR = 0x10, and as such are not currently fully supported.
4941 	 */
4942 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4943 		0x1204, 0x0004, 0, 0,
4944 		pbn_b0_4_921600 },
4945 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4946 		0x1208, 0x0004, 0, 0,
4947 		pbn_b0_4_921600 },
4948 /*	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4949 		0x1402, 0x0002, 0, 0,
4950 		pbn_b0_2_921600 }, */
4951 /*	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4952 		0x1404, 0x0004, 0, 0,
4953 		pbn_b0_4_921600 }, */
4954 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4955 		0x1208, 0x0004, 0, 0,
4956 		pbn_b0_4_921600 },
4957 
4958 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4959 		0x1204, 0x0004, 0, 0,
4960 		pbn_b0_4_921600 },
4961 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4962 		0x1208, 0x0004, 0, 0,
4963 		pbn_b0_4_921600 },
4964 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4965 		0x1208, 0x0004, 0, 0,
4966 		pbn_b0_4_921600 },
4967 	/*
4968 	 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4969 	 */
4970 	{	PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4971 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 		pbn_b1_1_1382400 },
4973 
4974 	/*
4975 	 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4976 	 */
4977 	{	PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4978 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979 		pbn_b1_1_1382400 },
4980 
4981 	/*
4982 	 * RAStel 2 port modem, gerg@moreton.com.au
4983 	 */
4984 	{	PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4985 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 		pbn_b2_bt_2_115200 },
4987 
4988 	/*
4989 	 * EKF addition for i960 Boards form EKF with serial port
4990 	 */
4991 	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4992 		0xE4BF, PCI_ANY_ID, 0, 0,
4993 		pbn_intel_i960 },
4994 
4995 	/*
4996 	 * Xircom Cardbus/Ethernet combos
4997 	 */
4998 	{	PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4999 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5000 		pbn_b0_1_115200 },
5001 	/*
5002 	 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5003 	 */
5004 	{	PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5005 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5006 		pbn_b0_1_115200 },
5007 
5008 	/*
5009 	 * Untested PCI modems, sent in from various folks...
5010 	 */
5011 
5012 	/*
5013 	 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5014 	 */
5015 	{	PCI_VENDOR_ID_ROCKWELL, 0x1004,
5016 		0x1048, 0x1500, 0, 0,
5017 		pbn_b1_1_115200 },
5018 
5019 	{	PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5020 		0xFF00, 0, 0, 0,
5021 		pbn_sgi_ioc3 },
5022 
5023 	/*
5024 	 * HP Diva card
5025 	 */
5026 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5027 		PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5028 		pbn_b1_1_115200 },
5029 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5030 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031 		pbn_b0_5_115200 },
5032 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5033 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5034 		pbn_b2_1_115200 },
5035 	/* HPE PCI serial device */
5036 	{	PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5037 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 		pbn_b1_1_115200 },
5039 
5040 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5041 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5042 		pbn_b3_2_115200 },
5043 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5044 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5045 		pbn_b3_4_115200 },
5046 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5047 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5048 		pbn_b3_8_115200 },
5049 	/*
5050 	 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5051 	 */
5052 	{	PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5053 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5054 		pbn_b0_1_115200 },
5055 	/*
5056 	 * ITE
5057 	 */
5058 	{	PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5059 		PCI_ANY_ID, PCI_ANY_ID,
5060 		0, 0,
5061 		pbn_b1_bt_1_115200 },
5062 
5063 	/*
5064 	 * IntaShield IS-100
5065 	 */
5066 	{	PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5067 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5068 		pbn_b2_1_115200 },
5069 	/*
5070 	 * IntaShield IS-200
5071 	 */
5072 	{	PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5073 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,	/* 135a.0811 */
5074 		pbn_b2_2_115200 },
5075 	/*
5076 	 * IntaShield IS-400
5077 	 */
5078 	{	PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5079 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5080 		pbn_b2_4_115200 },
5081 	/*
5082 	 * IntaShield IX-100
5083 	 */
5084 	{	PCI_VENDOR_ID_INTASHIELD, 0x4027,
5085 		PCI_ANY_ID, PCI_ANY_ID,
5086 		0, 0,
5087 		pbn_oxsemi_1_15625000 },
5088 	/*
5089 	 * IntaShield IX-200
5090 	 */
5091 	{	PCI_VENDOR_ID_INTASHIELD, 0x4028,
5092 		PCI_ANY_ID, PCI_ANY_ID,
5093 		0, 0,
5094 		pbn_oxsemi_2_15625000 },
5095 	/*
5096 	 * IntaShield IX-400
5097 	 */
5098 	{	PCI_VENDOR_ID_INTASHIELD, 0x4029,
5099 		PCI_ANY_ID, PCI_ANY_ID,
5100 		0, 0,
5101 		pbn_oxsemi_4_15625000 },
5102 	/* Brainboxes Devices */
5103 	/*
5104 	* Brainboxes UC-101
5105 	*/
5106 	{       PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5107 		PCI_ANY_ID, PCI_ANY_ID,
5108 		0, 0,
5109 		pbn_b2_2_115200 },
5110 	/*
5111 	 * Brainboxes UC-235/246
5112 	 */
5113 	{	PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5114 		PCI_ANY_ID, PCI_ANY_ID,
5115 		0, 0,
5116 		pbn_b2_1_115200 },
5117 	{	PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5118 		PCI_ANY_ID, PCI_ANY_ID,
5119 		0, 0,
5120 		pbn_b2_1_115200 },
5121 	/*
5122 	 * Brainboxes UC-253/UC-734
5123 	 */
5124 	{	PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5125 		PCI_ANY_ID, PCI_ANY_ID,
5126 		0, 0,
5127 		pbn_b2_2_115200 },
5128 	/*
5129 	 * Brainboxes UC-260/271/701/756
5130 	 */
5131 	{	PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5132 		PCI_ANY_ID, PCI_ANY_ID,
5133 		PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5134 		pbn_b2_4_115200 },
5135 	{	PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5136 		PCI_ANY_ID, PCI_ANY_ID,
5137 		PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5138 		pbn_b2_4_115200 },
5139 	/*
5140 	 * Brainboxes UC-268
5141 	 */
5142 	{       PCI_VENDOR_ID_INTASHIELD, 0x0841,
5143 		PCI_ANY_ID, PCI_ANY_ID,
5144 		0, 0,
5145 		pbn_b2_4_115200 },
5146 	/*
5147 	 * Brainboxes UC-275/279
5148 	 */
5149 	{	PCI_VENDOR_ID_INTASHIELD, 0x0881,
5150 		PCI_ANY_ID, PCI_ANY_ID,
5151 		0, 0,
5152 		pbn_b2_8_115200 },
5153 	/*
5154 	 * Brainboxes UC-302
5155 	 */
5156 	{	PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5157 		PCI_ANY_ID, PCI_ANY_ID,
5158 		0, 0,
5159 		pbn_b2_2_115200 },
5160 	{	PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5161 		PCI_ANY_ID, PCI_ANY_ID,
5162 		0, 0,
5163 		pbn_b2_2_115200 },
5164 	{	PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5165 		PCI_ANY_ID, PCI_ANY_ID,
5166 		0, 0,
5167 		pbn_b2_2_115200 },
5168 	/*
5169 	 * Brainboxes UC-310
5170 	 */
5171 	{       PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5172 		PCI_ANY_ID, PCI_ANY_ID,
5173 		0, 0,
5174 		pbn_b2_2_115200 },
5175 	/*
5176 	 * Brainboxes UC-313
5177 	 */
5178 	{       PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5179 		PCI_ANY_ID, PCI_ANY_ID,
5180 		0, 0,
5181 		pbn_b2_2_115200 },
5182 	{       PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5183 		PCI_ANY_ID, PCI_ANY_ID,
5184 		0, 0,
5185 		pbn_b2_2_115200 },
5186 	{       PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5187 		PCI_ANY_ID, PCI_ANY_ID,
5188 		0, 0,
5189 		pbn_b2_2_115200 },
5190 	/*
5191 	 * Brainboxes UC-320/324
5192 	 */
5193 	{	PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5194 		PCI_ANY_ID, PCI_ANY_ID,
5195 		0, 0,
5196 		pbn_b2_1_115200 },
5197 	/*
5198 	 * Brainboxes UC-346
5199 	 */
5200 	{	PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5201 		PCI_ANY_ID, PCI_ANY_ID,
5202 		0, 0,
5203 		pbn_b2_4_115200 },
5204 	{	PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5205 		PCI_ANY_ID, PCI_ANY_ID,
5206 		0, 0,
5207 		pbn_b2_4_115200 },
5208 	/*
5209 	 * Brainboxes UC-357
5210 	 */
5211 	{	PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5212 		PCI_ANY_ID, PCI_ANY_ID,
5213 		0, 0,
5214 		pbn_b2_2_115200 },
5215 	{	PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5216 		PCI_ANY_ID, PCI_ANY_ID,
5217 		0, 0,
5218 		pbn_b2_2_115200 },
5219 	{	PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5220 		PCI_ANY_ID, PCI_ANY_ID,
5221 		0, 0,
5222 		pbn_b2_2_115200 },
5223 	/*
5224 	 * Brainboxes UC-368
5225 	 */
5226 	{	PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5227 		PCI_ANY_ID, PCI_ANY_ID,
5228 		0, 0,
5229 		pbn_b2_4_115200 },
5230 	/*
5231 	 * Brainboxes UC-420
5232 	 */
5233 	{       PCI_VENDOR_ID_INTASHIELD, 0x0921,
5234 		PCI_ANY_ID, PCI_ANY_ID,
5235 		0, 0,
5236 		pbn_b2_4_115200 },
5237 	/*
5238 	 * Brainboxes UC-607
5239 	 */
5240 	{	PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5241 		PCI_ANY_ID, PCI_ANY_ID,
5242 		0, 0,
5243 		pbn_b2_2_115200 },
5244 	{	PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5245 		PCI_ANY_ID, PCI_ANY_ID,
5246 		0, 0,
5247 		pbn_b2_2_115200 },
5248 	{	PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5249 		PCI_ANY_ID, PCI_ANY_ID,
5250 		0, 0,
5251 		pbn_b2_2_115200 },
5252 	/*
5253 	 * Brainboxes UC-836
5254 	 */
5255 	{	PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5256 		PCI_ANY_ID, PCI_ANY_ID,
5257 		0, 0,
5258 		pbn_b2_4_115200 },
5259 	/*
5260 	 * Brainboxes UP-189
5261 	 */
5262 	{	PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5263 		PCI_ANY_ID, PCI_ANY_ID,
5264 		0, 0,
5265 		pbn_b2_2_115200 },
5266 	{	PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5267 		PCI_ANY_ID, PCI_ANY_ID,
5268 		0, 0,
5269 		pbn_b2_2_115200 },
5270 	{	PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5271 		PCI_ANY_ID, PCI_ANY_ID,
5272 		0, 0,
5273 		pbn_b2_2_115200 },
5274 	/*
5275 	 * Brainboxes UP-200
5276 	 */
5277 	{	PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5278 		PCI_ANY_ID, PCI_ANY_ID,
5279 		0, 0,
5280 		pbn_b2_2_115200 },
5281 	{	PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5282 		PCI_ANY_ID, PCI_ANY_ID,
5283 		0, 0,
5284 		pbn_b2_2_115200 },
5285 	{	PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5286 		PCI_ANY_ID, PCI_ANY_ID,
5287 		0, 0,
5288 		pbn_b2_2_115200 },
5289 	/*
5290 	 * Brainboxes UP-869
5291 	 */
5292 	{	PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5293 		PCI_ANY_ID, PCI_ANY_ID,
5294 		0, 0,
5295 		pbn_b2_2_115200 },
5296 	{	PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5297 		PCI_ANY_ID, PCI_ANY_ID,
5298 		0, 0,
5299 		pbn_b2_2_115200 },
5300 	{	PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5301 		PCI_ANY_ID, PCI_ANY_ID,
5302 		0, 0,
5303 		pbn_b2_2_115200 },
5304 	/*
5305 	 * Brainboxes UP-880
5306 	 */
5307 	{	PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5308 		PCI_ANY_ID, PCI_ANY_ID,
5309 		0, 0,
5310 		pbn_b2_2_115200 },
5311 	{	PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5312 		PCI_ANY_ID, PCI_ANY_ID,
5313 		0, 0,
5314 		pbn_b2_2_115200 },
5315 	{	PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5316 		PCI_ANY_ID, PCI_ANY_ID,
5317 		0, 0,
5318 		pbn_b2_2_115200 },
5319 	/*
5320 	 * Brainboxes PX-101
5321 	 */
5322 	{	PCI_VENDOR_ID_INTASHIELD, 0x4005,
5323 		PCI_ANY_ID, PCI_ANY_ID,
5324 		0, 0,
5325 		pbn_b0_2_115200 },
5326 	{	PCI_VENDOR_ID_INTASHIELD, 0x4019,
5327 		PCI_ANY_ID, PCI_ANY_ID,
5328 		0, 0,
5329 		pbn_oxsemi_2_15625000 },
5330 	/*
5331 	 * Brainboxes PX-235/246
5332 	 */
5333 	{	PCI_VENDOR_ID_INTASHIELD, 0x4004,
5334 		PCI_ANY_ID, PCI_ANY_ID,
5335 		0, 0,
5336 		pbn_b0_1_115200 },
5337 	{	PCI_VENDOR_ID_INTASHIELD, 0x4016,
5338 		PCI_ANY_ID, PCI_ANY_ID,
5339 		0, 0,
5340 		pbn_oxsemi_1_15625000 },
5341 	/*
5342 	 * Brainboxes PX-203/PX-257
5343 	 */
5344 	{	PCI_VENDOR_ID_INTASHIELD, 0x4006,
5345 		PCI_ANY_ID, PCI_ANY_ID,
5346 		0, 0,
5347 		pbn_b0_2_115200 },
5348 	{	PCI_VENDOR_ID_INTASHIELD, 0x4015,
5349 		PCI_ANY_ID, PCI_ANY_ID,
5350 		0, 0,
5351 		pbn_oxsemi_2_15625000 },
5352 	/*
5353 	 * Brainboxes PX-260/PX-701
5354 	 */
5355 	{	PCI_VENDOR_ID_INTASHIELD, 0x400A,
5356 		PCI_ANY_ID, PCI_ANY_ID,
5357 		0, 0,
5358 		pbn_oxsemi_4_15625000 },
5359 	/*
5360 	 * Brainboxes PX-275/279
5361 	 */
5362 	{	PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5363 		PCI_ANY_ID, PCI_ANY_ID,
5364 		0, 0,
5365 		pbn_b2_8_115200 },
5366 	/*
5367 	 * Brainboxes PX-310
5368 	 */
5369 	{	PCI_VENDOR_ID_INTASHIELD, 0x400E,
5370 		PCI_ANY_ID, PCI_ANY_ID,
5371 		0, 0,
5372 		pbn_oxsemi_2_15625000 },
5373 	/*
5374 	 * Brainboxes PX-313
5375 	 */
5376 	{	PCI_VENDOR_ID_INTASHIELD, 0x400C,
5377 		PCI_ANY_ID, PCI_ANY_ID,
5378 		0, 0,
5379 		pbn_oxsemi_2_15625000 },
5380 	/*
5381 	 * Brainboxes PX-320/324/PX-376/PX-387
5382 	 */
5383 	{	PCI_VENDOR_ID_INTASHIELD, 0x400B,
5384 		PCI_ANY_ID, PCI_ANY_ID,
5385 		0, 0,
5386 		pbn_oxsemi_1_15625000 },
5387 	/*
5388 	 * Brainboxes PX-335/346
5389 	 */
5390 	{	PCI_VENDOR_ID_INTASHIELD, 0x400F,
5391 		PCI_ANY_ID, PCI_ANY_ID,
5392 		0, 0,
5393 		pbn_oxsemi_4_15625000 },
5394 	/*
5395 	 * Brainboxes PX-368
5396 	 */
5397 	{       PCI_VENDOR_ID_INTASHIELD, 0x4010,
5398 		PCI_ANY_ID, PCI_ANY_ID,
5399 		0, 0,
5400 		pbn_oxsemi_4_15625000 },
5401 	/*
5402 	 * Brainboxes PX-420
5403 	 */
5404 	{	PCI_VENDOR_ID_INTASHIELD, 0x4000,
5405 		PCI_ANY_ID, PCI_ANY_ID,
5406 		0, 0,
5407 		pbn_b0_4_115200 },
5408 	{	PCI_VENDOR_ID_INTASHIELD, 0x4011,
5409 		PCI_ANY_ID, PCI_ANY_ID,
5410 		0, 0,
5411 		pbn_oxsemi_4_15625000 },
5412 	/*
5413 	 * Brainboxes PX-475
5414 	 */
5415 	{	PCI_VENDOR_ID_INTASHIELD, 0x401D,
5416 		PCI_ANY_ID, PCI_ANY_ID,
5417 		0, 0,
5418 		pbn_oxsemi_1_15625000 },
5419 	/*
5420 	 * Brainboxes PX-803/PX-857
5421 	 */
5422 	{	PCI_VENDOR_ID_INTASHIELD, 0x4009,
5423 		PCI_ANY_ID, PCI_ANY_ID,
5424 		0, 0,
5425 		pbn_b0_2_115200 },
5426 	{	PCI_VENDOR_ID_INTASHIELD, 0x4018,
5427 		PCI_ANY_ID, PCI_ANY_ID,
5428 		0, 0,
5429 		pbn_oxsemi_2_15625000 },
5430 	{	PCI_VENDOR_ID_INTASHIELD, 0x401E,
5431 		PCI_ANY_ID, PCI_ANY_ID,
5432 		0, 0,
5433 		pbn_oxsemi_2_15625000 },
5434 	/*
5435 	 * Brainboxes PX-820
5436 	 */
5437 	{	PCI_VENDOR_ID_INTASHIELD, 0x4002,
5438 		PCI_ANY_ID, PCI_ANY_ID,
5439 		0, 0,
5440 		pbn_b0_4_115200 },
5441 	{	PCI_VENDOR_ID_INTASHIELD, 0x4013,
5442 		PCI_ANY_ID, PCI_ANY_ID,
5443 		0, 0,
5444 		pbn_oxsemi_4_15625000 },
5445 	/*
5446 	 * Brainboxes PX-846
5447 	 */
5448 	{	PCI_VENDOR_ID_INTASHIELD, 0x4008,
5449 		PCI_ANY_ID, PCI_ANY_ID,
5450 		0, 0,
5451 		pbn_b0_1_115200 },
5452 	{	PCI_VENDOR_ID_INTASHIELD, 0x4017,
5453 		PCI_ANY_ID, PCI_ANY_ID,
5454 		0, 0,
5455 		pbn_oxsemi_1_15625000 },
5456 
5457 	/*
5458 	 * Perle PCI-RAS cards
5459 	 */
5460 	{       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5461 		PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5462 		0, 0, pbn_b2_4_921600 },
5463 	{       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5464 		PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5465 		0, 0, pbn_b2_8_921600 },
5466 
5467 	/*
5468 	 * Mainpine series cards: Fairly standard layout but fools
5469 	 * parts of the autodetect in some cases and uses otherwise
5470 	 * unmatched communications subclasses in the PCI Express case
5471 	 */
5472 
5473 	{	/* RockForceDUO */
5474 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5475 		PCI_VENDOR_ID_MAINPINE, 0x0200,
5476 		0, 0, pbn_b0_2_115200 },
5477 	{	/* RockForceQUATRO */
5478 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5479 		PCI_VENDOR_ID_MAINPINE, 0x0300,
5480 		0, 0, pbn_b0_4_115200 },
5481 	{	/* RockForceDUO+ */
5482 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5483 		PCI_VENDOR_ID_MAINPINE, 0x0400,
5484 		0, 0, pbn_b0_2_115200 },
5485 	{	/* RockForceQUATRO+ */
5486 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5487 		PCI_VENDOR_ID_MAINPINE, 0x0500,
5488 		0, 0, pbn_b0_4_115200 },
5489 	{	/* RockForce+ */
5490 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5491 		PCI_VENDOR_ID_MAINPINE, 0x0600,
5492 		0, 0, pbn_b0_2_115200 },
5493 	{	/* RockForce+ */
5494 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5495 		PCI_VENDOR_ID_MAINPINE, 0x0700,
5496 		0, 0, pbn_b0_4_115200 },
5497 	{	/* RockForceOCTO+ */
5498 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5499 		PCI_VENDOR_ID_MAINPINE, 0x0800,
5500 		0, 0, pbn_b0_8_115200 },
5501 	{	/* RockForceDUO+ */
5502 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5503 		PCI_VENDOR_ID_MAINPINE, 0x0C00,
5504 		0, 0, pbn_b0_2_115200 },
5505 	{	/* RockForceQUARTRO+ */
5506 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5507 		PCI_VENDOR_ID_MAINPINE, 0x0D00,
5508 		0, 0, pbn_b0_4_115200 },
5509 	{	/* RockForceOCTO+ */
5510 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5511 		PCI_VENDOR_ID_MAINPINE, 0x1D00,
5512 		0, 0, pbn_b0_8_115200 },
5513 	{	/* RockForceD1 */
5514 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5515 		PCI_VENDOR_ID_MAINPINE, 0x2000,
5516 		0, 0, pbn_b0_1_115200 },
5517 	{	/* RockForceF1 */
5518 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5519 		PCI_VENDOR_ID_MAINPINE, 0x2100,
5520 		0, 0, pbn_b0_1_115200 },
5521 	{	/* RockForceD2 */
5522 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5523 		PCI_VENDOR_ID_MAINPINE, 0x2200,
5524 		0, 0, pbn_b0_2_115200 },
5525 	{	/* RockForceF2 */
5526 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5527 		PCI_VENDOR_ID_MAINPINE, 0x2300,
5528 		0, 0, pbn_b0_2_115200 },
5529 	{	/* RockForceD4 */
5530 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5531 		PCI_VENDOR_ID_MAINPINE, 0x2400,
5532 		0, 0, pbn_b0_4_115200 },
5533 	{	/* RockForceF4 */
5534 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5535 		PCI_VENDOR_ID_MAINPINE, 0x2500,
5536 		0, 0, pbn_b0_4_115200 },
5537 	{	/* RockForceD8 */
5538 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5539 		PCI_VENDOR_ID_MAINPINE, 0x2600,
5540 		0, 0, pbn_b0_8_115200 },
5541 	{	/* RockForceF8 */
5542 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5543 		PCI_VENDOR_ID_MAINPINE, 0x2700,
5544 		0, 0, pbn_b0_8_115200 },
5545 	{	/* IQ Express D1 */
5546 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5547 		PCI_VENDOR_ID_MAINPINE, 0x3000,
5548 		0, 0, pbn_b0_1_115200 },
5549 	{	/* IQ Express F1 */
5550 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5551 		PCI_VENDOR_ID_MAINPINE, 0x3100,
5552 		0, 0, pbn_b0_1_115200 },
5553 	{	/* IQ Express D2 */
5554 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5555 		PCI_VENDOR_ID_MAINPINE, 0x3200,
5556 		0, 0, pbn_b0_2_115200 },
5557 	{	/* IQ Express F2 */
5558 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5559 		PCI_VENDOR_ID_MAINPINE, 0x3300,
5560 		0, 0, pbn_b0_2_115200 },
5561 	{	/* IQ Express D4 */
5562 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5563 		PCI_VENDOR_ID_MAINPINE, 0x3400,
5564 		0, 0, pbn_b0_4_115200 },
5565 	{	/* IQ Express F4 */
5566 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5567 		PCI_VENDOR_ID_MAINPINE, 0x3500,
5568 		0, 0, pbn_b0_4_115200 },
5569 	{	/* IQ Express D8 */
5570 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5571 		PCI_VENDOR_ID_MAINPINE, 0x3C00,
5572 		0, 0, pbn_b0_8_115200 },
5573 	{	/* IQ Express F8 */
5574 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5575 		PCI_VENDOR_ID_MAINPINE, 0x3D00,
5576 		0, 0, pbn_b0_8_115200 },
5577 
5578 
5579 	/*
5580 	 * PA Semi PA6T-1682M on-chip UART
5581 	 */
5582 	{	PCI_VENDOR_ID_PASEMI, 0xa004,
5583 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5584 		pbn_pasemi_1682M },
5585 
5586 	/*
5587 	 * National Instruments
5588 	 */
5589 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5590 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5591 		pbn_b1_16_115200 },
5592 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5593 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5594 		pbn_b1_8_115200 },
5595 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5596 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5597 		pbn_b1_bt_4_115200 },
5598 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5599 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5600 		pbn_b1_bt_2_115200 },
5601 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5602 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5603 		pbn_b1_bt_4_115200 },
5604 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5605 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5606 		pbn_b1_bt_2_115200 },
5607 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5608 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5609 		pbn_b1_16_115200 },
5610 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5611 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5612 		pbn_b1_8_115200 },
5613 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5614 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5615 		pbn_b1_bt_4_115200 },
5616 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5617 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5618 		pbn_b1_bt_2_115200 },
5619 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5620 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5621 		pbn_b1_bt_4_115200 },
5622 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5623 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5624 		pbn_b1_bt_2_115200 },
5625 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5626 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5627 		pbn_ni8430_2 },
5628 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5629 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5630 		pbn_ni8430_2 },
5631 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5632 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5633 		pbn_ni8430_4 },
5634 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5635 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5636 		pbn_ni8430_4 },
5637 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5638 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5639 		pbn_ni8430_8 },
5640 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5641 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5642 		pbn_ni8430_8 },
5643 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5644 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5645 		pbn_ni8430_16 },
5646 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5647 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5648 		pbn_ni8430_16 },
5649 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5650 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5651 		pbn_ni8430_2 },
5652 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5653 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5654 		pbn_ni8430_2 },
5655 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5656 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5657 		pbn_ni8430_4 },
5658 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5659 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5660 		pbn_ni8430_4 },
5661 
5662 	/*
5663 	 * MOXA
5664 	 */
5665 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5666 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5667 		pbn_moxa8250_2p },
5668 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5669 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5670 		pbn_moxa8250_2p },
5671 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5672 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5673 		pbn_moxa8250_4p },
5674 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5675 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5676 		pbn_moxa8250_4p },
5677 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5678 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5679 		pbn_moxa8250_8p },
5680 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5681 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5682 		pbn_moxa8250_8p },
5683 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5684 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5685 		pbn_moxa8250_8p },
5686 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5687 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5688 		pbn_moxa8250_8p },
5689 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5690 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5691 		pbn_moxa8250_2p },
5692 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5693 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5694 		pbn_moxa8250_4p },
5695 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5696 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5697 		pbn_moxa8250_8p },
5698 	{	PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5699 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5700 		pbn_moxa8250_8p },
5701 
5702 	/*
5703 	* ADDI-DATA GmbH communication cards <info@addi-data.com>
5704 	*/
5705 	{	PCI_VENDOR_ID_ADDIDATA,
5706 		PCI_DEVICE_ID_ADDIDATA_APCI7500,
5707 		PCI_ANY_ID,
5708 		PCI_ANY_ID,
5709 		0,
5710 		0,
5711 		pbn_b0_4_115200 },
5712 
5713 	{	PCI_VENDOR_ID_ADDIDATA,
5714 		PCI_DEVICE_ID_ADDIDATA_APCI7420,
5715 		PCI_ANY_ID,
5716 		PCI_ANY_ID,
5717 		0,
5718 		0,
5719 		pbn_b0_2_115200 },
5720 
5721 	{	PCI_VENDOR_ID_ADDIDATA,
5722 		PCI_DEVICE_ID_ADDIDATA_APCI7300,
5723 		PCI_ANY_ID,
5724 		PCI_ANY_ID,
5725 		0,
5726 		0,
5727 		pbn_b0_1_115200 },
5728 
5729 	{	PCI_VENDOR_ID_AMCC,
5730 		PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5731 		PCI_ANY_ID,
5732 		PCI_ANY_ID,
5733 		0,
5734 		0,
5735 		pbn_b1_8_115200 },
5736 
5737 	{	PCI_VENDOR_ID_ADDIDATA,
5738 		PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5739 		PCI_ANY_ID,
5740 		PCI_ANY_ID,
5741 		0,
5742 		0,
5743 		pbn_b0_4_115200 },
5744 
5745 	{	PCI_VENDOR_ID_ADDIDATA,
5746 		PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5747 		PCI_ANY_ID,
5748 		PCI_ANY_ID,
5749 		0,
5750 		0,
5751 		pbn_b0_2_115200 },
5752 
5753 	{	PCI_VENDOR_ID_ADDIDATA,
5754 		PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5755 		PCI_ANY_ID,
5756 		PCI_ANY_ID,
5757 		0,
5758 		0,
5759 		pbn_b0_1_115200 },
5760 
5761 	{	PCI_VENDOR_ID_ADDIDATA,
5762 		PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5763 		PCI_ANY_ID,
5764 		PCI_ANY_ID,
5765 		0,
5766 		0,
5767 		pbn_b0_4_115200 },
5768 
5769 	{	PCI_VENDOR_ID_ADDIDATA,
5770 		PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5771 		PCI_ANY_ID,
5772 		PCI_ANY_ID,
5773 		0,
5774 		0,
5775 		pbn_b0_2_115200 },
5776 
5777 	{	PCI_VENDOR_ID_ADDIDATA,
5778 		PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5779 		PCI_ANY_ID,
5780 		PCI_ANY_ID,
5781 		0,
5782 		0,
5783 		pbn_b0_1_115200 },
5784 
5785 	{	PCI_VENDOR_ID_ADDIDATA,
5786 		PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5787 		PCI_ANY_ID,
5788 		PCI_ANY_ID,
5789 		0,
5790 		0,
5791 		pbn_b0_8_115200 },
5792 
5793 	{	PCI_VENDOR_ID_ADDIDATA,
5794 		PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5795 		PCI_ANY_ID,
5796 		PCI_ANY_ID,
5797 		0,
5798 		0,
5799 		pbn_ADDIDATA_PCIe_4_3906250 },
5800 
5801 	{	PCI_VENDOR_ID_ADDIDATA,
5802 		PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5803 		PCI_ANY_ID,
5804 		PCI_ANY_ID,
5805 		0,
5806 		0,
5807 		pbn_ADDIDATA_PCIe_2_3906250 },
5808 
5809 	{	PCI_VENDOR_ID_ADDIDATA,
5810 		PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5811 		PCI_ANY_ID,
5812 		PCI_ANY_ID,
5813 		0,
5814 		0,
5815 		pbn_ADDIDATA_PCIe_1_3906250 },
5816 
5817 	{	PCI_VENDOR_ID_ADDIDATA,
5818 		PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5819 		PCI_ANY_ID,
5820 		PCI_ANY_ID,
5821 		0,
5822 		0,
5823 		pbn_ADDIDATA_PCIe_8_3906250 },
5824 
5825 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5826 		PCI_VENDOR_ID_IBM, 0x0299,
5827 		0, 0, pbn_b0_bt_2_115200 },
5828 
5829 	/*
5830 	 * other NetMos 9835 devices are most likely handled by the
5831 	 * parport_serial driver, check drivers/parport/parport_serial.c
5832 	 * before adding them here.
5833 	 */
5834 
5835 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5836 		0xA000, 0x1000,
5837 		0, 0, pbn_b0_1_115200 },
5838 
5839 	/* the 9901 is a rebranded 9912 */
5840 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5841 		0xA000, 0x1000,
5842 		0, 0, pbn_b0_1_115200 },
5843 
5844 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5845 		0xA000, 0x1000,
5846 		0, 0, pbn_b0_1_115200 },
5847 
5848 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5849 		0xA000, 0x1000,
5850 		0, 0, pbn_b0_1_115200 },
5851 
5852 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5853 		0xA000, 0x1000,
5854 		0, 0, pbn_b0_1_115200 },
5855 
5856 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5857 		0xA000, 0x3002,
5858 		0, 0, pbn_NETMOS9900_2s_115200 },
5859 
5860 	/*
5861 	 * Best Connectivity and Rosewill PCI Multi I/O cards
5862 	 */
5863 
5864 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5865 		0xA000, 0x1000,
5866 		0, 0, pbn_b0_1_115200 },
5867 
5868 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5869 		0xA000, 0x3002,
5870 		0, 0, pbn_b0_bt_2_115200 },
5871 
5872 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5873 		0xA000, 0x3004,
5874 		0, 0, pbn_b0_bt_4_115200 },
5875 
5876 	/*
5877 	 * ASIX AX99100 PCIe to Multi I/O Controller
5878 	 */
5879 	{	PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
5880 		0xA000, 0x1000,
5881 		0, 0, pbn_b0_1_115200 },
5882 
5883 	/* Intel CE4100 */
5884 	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5885 		PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5886 		pbn_ce4100_1_115200 },
5887 
5888 	/*
5889 	 * Cronyx Omega PCI
5890 	 */
5891 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5892 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5893 		pbn_omegapci },
5894 
5895 	/*
5896 	 * Broadcom TruManage
5897 	 */
5898 	{	PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5899 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5900 		pbn_brcm_trumanage },
5901 
5902 	/*
5903 	 * AgeStar as-prs2-009
5904 	 */
5905 	{	PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5906 		PCI_ANY_ID, PCI_ANY_ID,
5907 		0, 0, pbn_b0_bt_2_115200 },
5908 
5909 	/*
5910 	 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5911 	 * so not listed here.
5912 	 */
5913 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5914 		PCI_ANY_ID, PCI_ANY_ID,
5915 		0, 0, pbn_b0_bt_4_115200 },
5916 
5917 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5918 		PCI_ANY_ID, PCI_ANY_ID,
5919 		0, 0, pbn_b0_bt_2_115200 },
5920 
5921 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5922 		PCI_ANY_ID, PCI_ANY_ID,
5923 		0, 0, pbn_b0_bt_4_115200 },
5924 
5925 	{	PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5926 		PCI_ANY_ID, PCI_ANY_ID,
5927 		0, 0, pbn_wch382_2 },
5928 
5929 	{	PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5930 		PCI_ANY_ID, PCI_ANY_ID,
5931 		0, 0, pbn_wch384_4 },
5932 
5933 	{	PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
5934 		PCI_ANY_ID, PCI_ANY_ID,
5935 		0, 0, pbn_wch384_8 },
5936 	/*
5937 	 * Realtek RealManage
5938 	 */
5939 	{	PCI_VENDOR_ID_REALTEK, 0x816a,
5940 		PCI_ANY_ID, PCI_ANY_ID,
5941 		0, 0, pbn_b0_1_115200 },
5942 
5943 	{	PCI_VENDOR_ID_REALTEK, 0x816b,
5944 		PCI_ANY_ID, PCI_ANY_ID,
5945 		0, 0, pbn_b0_1_115200 },
5946 
5947 	/* Fintek PCI serial cards */
5948 	{ PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5949 	{ PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5950 	{ PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5951 	{ PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5952 	{ PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5953 	{ PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5954 
5955 	/* MKS Tenta SCOM-080x serial cards */
5956 	{ PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5957 	{ PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5958 
5959 	/* Amazon PCI serial device */
5960 	{ PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5961 
5962 	/*
5963 	 * These entries match devices with class COMMUNICATION_SERIAL,
5964 	 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5965 	 */
5966 	{	PCI_ANY_ID, PCI_ANY_ID,
5967 		PCI_ANY_ID, PCI_ANY_ID,
5968 		PCI_CLASS_COMMUNICATION_SERIAL << 8,
5969 		0xffff00, pbn_default },
5970 	{	PCI_ANY_ID, PCI_ANY_ID,
5971 		PCI_ANY_ID, PCI_ANY_ID,
5972 		PCI_CLASS_COMMUNICATION_MODEM << 8,
5973 		0xffff00, pbn_default },
5974 	{	PCI_ANY_ID, PCI_ANY_ID,
5975 		PCI_ANY_ID, PCI_ANY_ID,
5976 		PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5977 		0xffff00, pbn_default },
5978 	{ 0, }
5979 };
5980 
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5981 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5982 						pci_channel_state_t state)
5983 {
5984 	struct serial_private *priv = pci_get_drvdata(dev);
5985 
5986 	if (state == pci_channel_io_perm_failure)
5987 		return PCI_ERS_RESULT_DISCONNECT;
5988 
5989 	if (priv)
5990 		pciserial_detach_ports(priv);
5991 
5992 	pci_disable_device(dev);
5993 
5994 	return PCI_ERS_RESULT_NEED_RESET;
5995 }
5996 
serial8250_io_slot_reset(struct pci_dev * dev)5997 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5998 {
5999 	int rc;
6000 
6001 	rc = pci_enable_device(dev);
6002 
6003 	if (rc)
6004 		return PCI_ERS_RESULT_DISCONNECT;
6005 
6006 	pci_restore_state(dev);
6007 	pci_save_state(dev);
6008 
6009 	return PCI_ERS_RESULT_RECOVERED;
6010 }
6011 
serial8250_io_resume(struct pci_dev * dev)6012 static void serial8250_io_resume(struct pci_dev *dev)
6013 {
6014 	struct serial_private *priv = pci_get_drvdata(dev);
6015 	struct serial_private *new;
6016 
6017 	if (!priv)
6018 		return;
6019 
6020 	new = pciserial_init_ports(dev, priv->board);
6021 	if (!IS_ERR(new)) {
6022 		pci_set_drvdata(dev, new);
6023 		kfree(priv);
6024 	}
6025 }
6026 
6027 static const struct pci_error_handlers serial8250_err_handler = {
6028 	.error_detected = serial8250_io_error_detected,
6029 	.slot_reset = serial8250_io_slot_reset,
6030 	.resume = serial8250_io_resume,
6031 };
6032 
6033 static struct pci_driver serial_pci_driver = {
6034 	.name		= "serial",
6035 	.probe		= pciserial_init_one,
6036 	.remove		= pciserial_remove_one,
6037 	.driver         = {
6038 		.pm     = &pciserial_pm_ops,
6039 	},
6040 	.id_table	= serial_pci_tbl,
6041 	.err_handler	= &serial8250_err_handler,
6042 };
6043 
6044 module_pci_driver(serial_pci_driver);
6045 
6046 MODULE_LICENSE("GPL");
6047 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6048 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6049 MODULE_IMPORT_NS(SERIAL_8250_PCI);
6050