1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014 STMicroelectronics Limited. 4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 5 */ 6 #include "stih407-pinctrl.dtsi" 7 #include <dt-bindings/mfd/st-lpc.h> 8 #include <dt-bindings/phy/phy.h> 9 #include <dt-bindings/reset/stih407-resets.h> 10 #include <dt-bindings/interrupt-controller/irq-st.h> 11 / { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 reserved-memory { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 ranges; 19 20 gp0_reserved: rproc@45000000 { 21 compatible = "shared-dma-pool"; 22 reg = <0x45000000 0x00400000>; 23 no-map; 24 }; 25 26 delta_reserved: rproc@44000000 { 27 compatible = "shared-dma-pool"; 28 reg = <0x44000000 0x01000000>; 29 no-map; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a9"; 39 reg = <0>; 40 41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 42 cpu-release-addr = <0x94100A4>; 43 44 /* kHz uV */ 45 operating-points = <1500000 0 46 1200000 0 47 800000 0 48 500000 0>; 49 50 clocks = <&clk_m_a9>; 51 clock-names = "cpu"; 52 clock-latency = <100000>; 53 cpu0-supply = <&pwm_regulator>; 54 st,syscfg = <&syscfg_core 0x8e0>; 55 }; 56 cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a9"; 59 reg = <1>; 60 61 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 62 cpu-release-addr = <0x94100A4>; 63 64 /* kHz uV */ 65 operating-points = <1500000 0 66 1200000 0 67 800000 0 68 500000 0>; 69 }; 70 }; 71 72 intc: interrupt-controller@8761000 { 73 compatible = "arm,cortex-a9-gic"; 74 #interrupt-cells = <3>; 75 interrupt-controller; 76 reg = <0x08761000 0x1000>, <0x08760100 0x100>; 77 }; 78 79 scu@8760000 { 80 compatible = "arm,cortex-a9-scu"; 81 reg = <0x08760000 0x1000>; 82 }; 83 84 timer@8760200 { 85 interrupt-parent = <&intc>; 86 compatible = "arm,cortex-a9-global-timer"; 87 reg = <0x08760200 0x100>; 88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&arm_periph_clk>; 90 }; 91 92 l2: cache-controller@8762000 { 93 compatible = "arm,pl310-cache"; 94 reg = <0x08762000 0x1000>; 95 arm,data-latency = <3 3 3>; 96 arm,tag-latency = <2 2 2>; 97 cache-unified; 98 cache-level = <2>; 99 }; 100 101 arm-pmu { 102 interrupt-parent = <&intc>; 103 compatible = "arm,cortex-a9-pmu"; 104 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 pwm_regulator: pwm-regulator { 108 compatible = "pwm-regulator"; 109 pwms = <&pwm1 3 8448>; 110 regulator-name = "CPU_1V0_AVS"; 111 regulator-min-microvolt = <784000>; 112 regulator-max-microvolt = <1299000>; 113 regulator-always-on; 114 max-duty-cycle = <255>; 115 status = "okay"; 116 }; 117 118 restart: restart-controller { 119 compatible = "st,stih407-restart"; 120 st,syscfg = <&syscfg_sbc_reg>; 121 status = "okay"; 122 }; 123 124 powerdown: powerdown-controller { 125 compatible = "st,stih407-powerdown"; 126 #reset-cells = <1>; 127 }; 128 129 softreset: softreset-controller { 130 compatible = "st,stih407-softreset"; 131 #reset-cells = <1>; 132 }; 133 134 picophyreset: picophyreset-controller { 135 compatible = "st,stih407-picophyreset"; 136 #reset-cells = <1>; 137 }; 138 139 irq-syscfg { 140 compatible = "st,stih407-irq-syscfg"; 141 st,syscfg = <&syscfg_core>; 142 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 143 <ST_IRQ_SYSCFG_PMU_1>; 144 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 145 <ST_IRQ_SYSCFG_DISABLED>; 146 }; 147 148 usb2_picophy0: phy1 { 149 compatible = "st,stih407-usb2-phy"; 150 #phy-cells = <0>; 151 st,syscfg = <&syscfg_core 0x100 0xf4>; 152 resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 153 <&picophyreset STIH407_PICOPHY2_RESET>; 154 reset-names = "global", "port"; 155 }; 156 157 miphy28lp_phy: miphy28lp { 158 compatible = "st,miphy28lp-phy"; 159 st,syscfg = <&syscfg_core>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges; 163 164 phy_port0: port@9b22000 { 165 reg = <0x9b22000 0xff>, 166 <0x9b09000 0xff>, 167 <0x9b04000 0xff>; 168 reg-names = "sata-up", 169 "pcie-up", 170 "pipew"; 171 172 st,syscfg = <0x114 0x818 0xe0 0xec>; 173 #phy-cells = <1>; 174 175 reset-names = "miphy-sw-rst"; 176 resets = <&softreset STIH407_MIPHY0_SOFTRESET>; 177 }; 178 179 phy_port1: port@9b2a000 { 180 reg = <0x9b2a000 0xff>, 181 <0x9b19000 0xff>, 182 <0x9b14000 0xff>; 183 reg-names = "sata-up", 184 "pcie-up", 185 "pipew"; 186 187 st,syscfg = <0x118 0x81c 0xe4 0xf0>; 188 189 #phy-cells = <1>; 190 191 reset-names = "miphy-sw-rst"; 192 resets = <&softreset STIH407_MIPHY1_SOFTRESET>; 193 }; 194 195 phy_port2: port@8f95000 { 196 reg = <0x8f95000 0xff>, 197 <0x8f90000 0xff>; 198 reg-names = "pipew", 199 "usb3-up"; 200 201 st,syscfg = <0x11c 0x820>; 202 203 #phy-cells = <1>; 204 205 reset-names = "miphy-sw-rst"; 206 resets = <&softreset STIH407_MIPHY2_SOFTRESET>; 207 }; 208 }; 209 210 st231_gp0: st231-gp0 { 211 compatible = "st,st231-rproc"; 212 memory-region = <&gp0_reserved>; 213 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; 214 reset-names = "sw_reset"; 215 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; 216 clock-frequency = <600000000>; 217 st,syscfg = <&syscfg_core 0x22c>; 218 #mbox-cells = <1>; 219 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 220 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; 221 }; 222 223 st231_delta: st231-delta { 224 compatible = "st,st231-rproc"; 225 memory-region = <&delta_reserved>; 226 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; 227 reset-names = "sw_reset"; 228 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; 229 clock-frequency = <600000000>; 230 st,syscfg = <&syscfg_core 0x224>; 231 #mbox-cells = <1>; 232 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 233 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; 234 }; 235 236 delta0 { 237 compatible = "st,st-delta"; 238 clock-names = "delta", 239 "delta-st231", 240 "delta-flash-promip"; 241 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, 242 <&clk_s_c0_flexgen CLK_ST231_DMU>, 243 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 244 }; 245 246 soc { 247 #address-cells = <1>; 248 #size-cells = <1>; 249 interrupt-parent = <&intc>; 250 ranges; 251 compatible = "simple-bus"; 252 253 syscfg_sbc: sbc-syscfg@9620000 { 254 compatible = "st,stih407-sbc-syscfg", "syscon"; 255 reg = <0x9620000 0x1000>; 256 }; 257 258 syscfg_front: front-syscfg@9280000 { 259 compatible = "st,stih407-front-syscfg", "syscon"; 260 reg = <0x9280000 0x1000>; 261 }; 262 263 syscfg_rear: rear-syscfg@9290000 { 264 compatible = "st,stih407-rear-syscfg", "syscon"; 265 reg = <0x9290000 0x1000>; 266 }; 267 268 syscfg_flash: flash-syscfg@92a0000 { 269 compatible = "st,stih407-flash-syscfg", "syscon"; 270 reg = <0x92a0000 0x1000>; 271 }; 272 273 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { 274 compatible = "st,stih407-sbc-reg-syscfg", "syscon"; 275 reg = <0x9600000 0x1000>; 276 }; 277 278 syscfg_core: core-syscfg@92b0000 { 279 compatible = "st,stih407-core-syscfg", "syscon"; 280 reg = <0x92b0000 0x1000>; 281 282 sti_sasg_codec: sti-sasg-codec { 283 compatible = "st,stih407-sas-codec"; 284 #sound-dai-cells = <1>; 285 status = "disabled"; 286 st,syscfg = <&syscfg_core>; 287 }; 288 }; 289 290 syscfg_lpm: lpm-syscfg@94b5100 { 291 compatible = "st,stih407-lpm-syscfg", "syscon"; 292 reg = <0x94b5100 0x1000>; 293 }; 294 295 /* Display */ 296 vtg_main: sti-vtg-main@8d02800 { 297 compatible = "st,vtg"; 298 reg = <0x8d02800 0x200>; 299 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 300 }; 301 302 vtg_aux: sti-vtg-aux@8d00200 { 303 compatible = "st,vtg"; 304 reg = <0x8d00200 0x100>; 305 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 306 }; 307 308 serial@9830000 { 309 compatible = "st,asc"; 310 reg = <0x9830000 0x2c>; 311 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 313 /* Pinctrl moved out to a per-board configuration */ 314 315 status = "disabled"; 316 }; 317 318 serial@9831000 { 319 compatible = "st,asc"; 320 reg = <0x9831000 0x2c>; 321 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_serial1>; 324 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 325 326 status = "disabled"; 327 }; 328 329 serial@9832000 { 330 compatible = "st,asc"; 331 reg = <0x9832000 0x2c>; 332 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_serial2>; 335 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 336 337 status = "disabled"; 338 }; 339 340 /* SBC_ASC0 - UART10 */ 341 sbc_serial0: serial@9530000 { 342 compatible = "st,asc"; 343 reg = <0x9530000 0x2c>; 344 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_sbc_serial0>; 347 clocks = <&clk_sysin>; 348 349 status = "disabled"; 350 }; 351 352 serial@9531000 { 353 compatible = "st,asc"; 354 reg = <0x9531000 0x2c>; 355 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_sbc_serial1>; 358 clocks = <&clk_sysin>; 359 360 status = "disabled"; 361 }; 362 363 i2c@9840000 { 364 compatible = "st,comms-ssc4-i2c"; 365 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 366 reg = <0x9840000 0x110>; 367 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 368 clock-names = "ssc"; 369 clock-frequency = <400000>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_i2c0_default>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 375 status = "disabled"; 376 }; 377 378 i2c@9841000 { 379 compatible = "st,comms-ssc4-i2c"; 380 reg = <0x9841000 0x110>; 381 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 383 clock-names = "ssc"; 384 clock-frequency = <400000>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_i2c1_default>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 390 status = "disabled"; 391 }; 392 393 i2c@9842000 { 394 compatible = "st,comms-ssc4-i2c"; 395 reg = <0x9842000 0x110>; 396 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 398 clock-names = "ssc"; 399 clock-frequency = <400000>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_i2c2_default>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 405 status = "disabled"; 406 }; 407 408 i2c@9843000 { 409 compatible = "st,comms-ssc4-i2c"; 410 reg = <0x9843000 0x110>; 411 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 413 clock-names = "ssc"; 414 clock-frequency = <400000>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_i2c3_default>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 420 status = "disabled"; 421 }; 422 423 i2c@9844000 { 424 compatible = "st,comms-ssc4-i2c"; 425 reg = <0x9844000 0x110>; 426 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 428 clock-names = "ssc"; 429 clock-frequency = <400000>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_i2c4_default>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 435 status = "disabled"; 436 }; 437 438 i2c@9845000 { 439 compatible = "st,comms-ssc4-i2c"; 440 reg = <0x9845000 0x110>; 441 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 443 clock-names = "ssc"; 444 clock-frequency = <400000>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_i2c5_default>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 450 status = "disabled"; 451 }; 452 453 454 /* SSCs on SBC */ 455 i2c@9540000 { 456 compatible = "st,comms-ssc4-i2c"; 457 reg = <0x9540000 0x110>; 458 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clk_sysin>; 460 clock-names = "ssc"; 461 clock-frequency = <400000>; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_i2c10_default>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 467 status = "disabled"; 468 }; 469 470 i2c@9541000 { 471 compatible = "st,comms-ssc4-i2c"; 472 reg = <0x9541000 0x110>; 473 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clk_sysin>; 475 clock-names = "ssc"; 476 clock-frequency = <400000>; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&pinctrl_i2c11_default>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 482 status = "disabled"; 483 }; 484 485 spi@9840000 { 486 compatible = "st,comms-ssc4-spi"; 487 reg = <0x9840000 0x110>; 488 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 490 clock-names = "ssc"; 491 pinctrl-0 = <&pinctrl_spi0_default>; 492 pinctrl-names = "default"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 496 status = "disabled"; 497 }; 498 499 spi@9841000 { 500 compatible = "st,comms-ssc4-spi"; 501 reg = <0x9841000 0x110>; 502 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 504 clock-names = "ssc"; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pinctrl_spi1_default>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 510 status = "disabled"; 511 }; 512 513 spi@9842000 { 514 compatible = "st,comms-ssc4-spi"; 515 reg = <0x9842000 0x110>; 516 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 518 clock-names = "ssc"; 519 pinctrl-names = "default"; 520 pinctrl-0 = <&pinctrl_spi2_default>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 524 status = "disabled"; 525 }; 526 527 spi@9843000 { 528 compatible = "st,comms-ssc4-spi"; 529 reg = <0x9843000 0x110>; 530 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 532 clock-names = "ssc"; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&pinctrl_spi3_default>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 538 status = "disabled"; 539 }; 540 541 spi@9844000 { 542 compatible = "st,comms-ssc4-spi"; 543 reg = <0x9844000 0x110>; 544 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 546 clock-names = "ssc"; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_spi4_default>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 552 status = "disabled"; 553 }; 554 555 /* SBC SSC */ 556 spi@9540000 { 557 compatible = "st,comms-ssc4-spi"; 558 reg = <0x9540000 0x110>; 559 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clk_sysin>; 561 clock-names = "ssc"; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_spi10_default>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 567 status = "disabled"; 568 }; 569 570 spi@9541000 { 571 compatible = "st,comms-ssc4-spi"; 572 reg = <0x9541000 0x110>; 573 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clk_sysin>; 575 clock-names = "ssc"; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_spi11_default>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 581 status = "disabled"; 582 }; 583 584 spi@9542000 { 585 compatible = "st,comms-ssc4-spi"; 586 reg = <0x9542000 0x110>; 587 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clk_sysin>; 589 clock-names = "ssc"; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&pinctrl_spi12_default>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 595 status = "disabled"; 596 }; 597 598 mmc0: sdhci@9060000 { 599 compatible = "st,sdhci-stih407", "st,sdhci"; 600 status = "disabled"; 601 reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 602 reg-names = "mmc", "top-mmc-delay"; 603 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 604 interrupt-names = "mmcirq"; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&pinctrl_mmc0>; 607 clock-names = "mmc", "icn"; 608 clocks = <&clk_s_c0_flexgen CLK_MMC_0>, 609 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 610 bus-width = <8>; 611 }; 612 613 mmc1: sdhci@9080000 { 614 compatible = "st,sdhci-stih407", "st,sdhci"; 615 status = "disabled"; 616 reg = <0x09080000 0x7ff>; 617 reg-names = "mmc"; 618 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 619 interrupt-names = "mmcirq"; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&pinctrl_sd1>; 622 clock-names = "mmc", "icn"; 623 clocks = <&clk_s_c0_flexgen CLK_MMC_1>, 624 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 625 resets = <&softreset STIH407_MMC1_SOFTRESET>; 626 bus-width = <4>; 627 }; 628 629 /* Watchdog and Real-Time Clock */ 630 lpc@8787000 { 631 compatible = "st,stih407-lpc"; 632 reg = <0x8787000 0x1000>; 633 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; 634 clocks = <&clk_s_d3_flexgen CLK_LPC_0>; 635 timeout-sec = <120>; 636 st,syscfg = <&syscfg_core>; 637 st,lpc-mode = <ST_LPC_MODE_WDT>; 638 }; 639 640 lpc@8788000 { 641 compatible = "st,stih407-lpc"; 642 reg = <0x8788000 0x1000>; 643 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; 644 clocks = <&clk_s_d3_flexgen CLK_LPC_1>; 645 st,lpc-mode = <ST_LPC_MODE_CLKSRC>; 646 }; 647 648 spifsm: spifsm@9022000 { 649 compatible = "st,spi-fsm"; 650 reg = <0x9022000 0x1000>; 651 reg-names = "spi-fsm"; 652 clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 653 clock-names = "emi_clk"; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&pinctrl_fsm>; 656 st,syscfg = <&syscfg_core>; 657 st,boot-device-reg = <0x8c4>; 658 st,boot-device-spi = <0x68>; 659 660 status = "disabled"; 661 }; 662 663 sata0: sata@9b20000 { 664 compatible = "st,ahci"; 665 reg = <0x9b20000 0x1000>; 666 667 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 668 interrupt-names = "hostc"; 669 670 phys = <&phy_port0 PHY_TYPE_SATA>; 671 phy-names = "ahci_phy"; 672 673 resets = <&powerdown STIH407_SATA0_POWERDOWN>, 674 <&softreset STIH407_SATA0_SOFTRESET>, 675 <&softreset STIH407_SATA0_PWR_SOFTRESET>; 676 reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; 677 678 clock-names = "ahci_clk"; 679 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 680 681 ports-implemented = <0x1>; 682 683 status = "disabled"; 684 }; 685 686 sata1: sata@9b28000 { 687 compatible = "st,ahci"; 688 reg = <0x9b28000 0x1000>; 689 690 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 691 interrupt-names = "hostc"; 692 693 phys = <&phy_port1 PHY_TYPE_SATA>; 694 phy-names = "ahci_phy"; 695 696 resets = <&powerdown STIH407_SATA1_POWERDOWN>, 697 <&softreset STIH407_SATA1_SOFTRESET>, 698 <&softreset STIH407_SATA1_PWR_SOFTRESET>; 699 reset-names = "pwr-dwn", 700 "sw-rst", 701 "pwr-rst"; 702 703 clock-names = "ahci_clk"; 704 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 705 706 ports-implemented = <0x1>; 707 708 status = "disabled"; 709 }; 710 711 712 st_dwc3: dwc3@8f94000 { 713 compatible = "st,stih407-dwc3"; 714 reg = <0x08f94000 0x1000>, <0x110 0x4>; 715 reg-names = "reg-glue", "syscfg-reg"; 716 st,syscfg = <&syscfg_core>; 717 resets = <&powerdown STIH407_USB3_POWERDOWN>, 718 <&softreset STIH407_MIPHY2_SOFTRESET>; 719 reset-names = "powerdown", "softreset"; 720 #address-cells = <1>; 721 #size-cells = <1>; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&pinctrl_usb3>; 724 ranges; 725 726 status = "disabled"; 727 728 dwc3: usb@9900000 { 729 compatible = "snps,dwc3"; 730 reg = <0x09900000 0x100000>; 731 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 732 dr_mode = "host"; 733 phy-names = "usb2-phy", "usb3-phy"; 734 phys = <&usb2_picophy0>, 735 <&phy_port2 PHY_TYPE_USB3>; 736 snps,dis_u3_susphy_quirk; 737 }; 738 }; 739 740 /* COMMS PWM Module */ 741 pwm0: pwm@9810000 { 742 compatible = "st,sti-pwm"; 743 #pwm-cells = <2>; 744 reg = <0x9810000 0x68>; 745 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&pinctrl_pwm0_chan0_default>; 748 clock-names = "pwm"; 749 clocks = <&clk_sysin>; 750 st,pwm-num-chan = <1>; 751 752 status = "disabled"; 753 }; 754 755 /* SBC PWM Module */ 756 pwm1: pwm@9510000 { 757 compatible = "st,sti-pwm"; 758 #pwm-cells = <2>; 759 reg = <0x9510000 0x68>; 760 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 761 pinctrl-names = "default"; 762 pinctrl-0 = <&pinctrl_pwm1_chan0_default 763 &pinctrl_pwm1_chan1_default 764 &pinctrl_pwm1_chan2_default 765 &pinctrl_pwm1_chan3_default>; 766 clock-names = "pwm"; 767 clocks = <&clk_sysin>; 768 st,pwm-num-chan = <4>; 769 770 status = "disabled"; 771 }; 772 773 rng10: rng@8a89000 { 774 compatible = "st,rng"; 775 reg = <0x08a89000 0x1000>; 776 clocks = <&clk_sysin>; 777 status = "okay"; 778 }; 779 780 rng11: rng@8a8a000 { 781 compatible = "st,rng"; 782 reg = <0x08a8a000 0x1000>; 783 clocks = <&clk_sysin>; 784 status = "okay"; 785 }; 786 787 ethernet0: dwmac@9630000 { 788 device_type = "network"; 789 status = "disabled"; 790 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 791 reg = <0x9630000 0x8000>, <0x80 0x4>; 792 reg-names = "stmmaceth", "sti-ethconf"; 793 794 st,syscon = <&syscfg_sbc_reg 0x80>; 795 st,gmac_en; 796 resets = <&softreset STIH407_ETH1_SOFTRESET>; 797 reset-names = "stmmaceth"; 798 799 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 801 interrupt-names = "macirq", "eth_wake_irq"; 802 803 /* DMA Bus Mode */ 804 snps,pbl = <8>; 805 806 pinctrl-names = "default"; 807 pinctrl-0 = <&pinctrl_rgmii1>; 808 809 clock-names = "stmmaceth", "sti-ethclk"; 810 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, 811 <&clk_s_c0_flexgen CLK_ETH_PHY>; 812 }; 813 814 mailbox0: mailbox@8f00000 { 815 compatible = "st,stih407-mailbox"; 816 reg = <0x8f00000 0x1000>; 817 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 818 #mbox-cells = <2>; 819 mbox-name = "a9"; 820 status = "okay"; 821 }; 822 823 mailbox1: mailbox@8f01000 { 824 compatible = "st,stih407-mailbox"; 825 reg = <0x8f01000 0x1000>; 826 #mbox-cells = <2>; 827 mbox-name = "st231_gp_1"; 828 status = "okay"; 829 }; 830 831 mailbox2: mailbox@8f02000 { 832 compatible = "st,stih407-mailbox"; 833 reg = <0x8f02000 0x1000>; 834 #mbox-cells = <2>; 835 mbox-name = "st231_gp_0"; 836 status = "okay"; 837 }; 838 839 mailbox3: mailbox@8f03000 { 840 compatible = "st,stih407-mailbox"; 841 reg = <0x8f03000 0x1000>; 842 #mbox-cells = <2>; 843 mbox-name = "st231_audio_video"; 844 status = "okay"; 845 }; 846 847 /* fdma audio */ 848 fdma0: dma-controller@8e20000 { 849 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 850 reg = <0x8e20000 0x8000>, 851 <0x8e30000 0x3000>, 852 <0x8e37000 0x1000>, 853 <0x8e38000 0x8000>; 854 reg-names = "slimcore", "dmem", "peripherals", "imem"; 855 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 856 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 857 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 858 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 859 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 860 dma-channels = <16>; 861 #dma-cells = <3>; 862 }; 863 864 /* fdma app */ 865 fdma1: dma-controller@8e40000 { 866 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; 867 reg = <0x8e40000 0x8000>, 868 <0x8e50000 0x3000>, 869 <0x8e57000 0x1000>, 870 <0x8e58000 0x8000>; 871 reg-names = "slimcore", "dmem", "peripherals", "imem"; 872 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 873 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 874 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 875 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 876 877 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 878 dma-channels = <16>; 879 #dma-cells = <3>; 880 881 status = "disabled"; 882 }; 883 884 /* fdma free running */ 885 fdma2: dma-controller@8e60000 { 886 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; 887 reg = <0x8e60000 0x8000>, 888 <0x8e70000 0x3000>, 889 <0x8e77000 0x1000>, 890 <0x8e78000 0x8000>; 891 reg-names = "slimcore", "dmem", "peripherals", "imem"; 892 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 893 dma-channels = <16>; 894 #dma-cells = <3>; 895 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 896 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 897 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 898 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 899 900 status = "disabled"; 901 }; 902 903 sti_uni_player0: sti-uni-player@8d80000 { 904 compatible = "st,stih407-uni-player-hdmi"; 905 #sound-dai-cells = <0>; 906 st,syscfg = <&syscfg_core>; 907 clocks = <&clk_s_d0_flexgen CLK_PCM_0>; 908 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; 909 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; 910 assigned-clock-rates = <50000000>; 911 reg = <0x8d80000 0x158>; 912 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 913 dmas = <&fdma0 2 0 1>; 914 dma-names = "tx"; 915 916 status = "disabled"; 917 }; 918 919 sti_uni_player1: sti-uni-player@8d81000 { 920 compatible = "st,stih407-uni-player-pcm-out"; 921 #sound-dai-cells = <0>; 922 st,syscfg = <&syscfg_core>; 923 clocks = <&clk_s_d0_flexgen CLK_PCM_1>; 924 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; 925 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; 926 assigned-clock-rates = <50000000>; 927 reg = <0x8d81000 0x158>; 928 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 929 dmas = <&fdma0 3 0 1>; 930 dma-names = "tx"; 931 932 status = "disabled"; 933 }; 934 935 sti_uni_player2: sti-uni-player@8d82000 { 936 compatible = "st,stih407-uni-player-dac"; 937 #sound-dai-cells = <0>; 938 st,syscfg = <&syscfg_core>; 939 clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 940 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; 941 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; 942 assigned-clock-rates = <50000000>; 943 reg = <0x8d82000 0x158>; 944 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 945 dmas = <&fdma0 4 0 1>; 946 dma-names = "tx"; 947 948 status = "disabled"; 949 }; 950 951 sti_uni_player3: sti-uni-player@8d85000 { 952 compatible = "st,stih407-uni-player-spdif"; 953 #sound-dai-cells = <0>; 954 st,syscfg = <&syscfg_core>; 955 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; 956 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; 957 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; 958 assigned-clock-rates = <50000000>; 959 reg = <0x8d85000 0x158>; 960 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 961 dmas = <&fdma0 7 0 1>; 962 dma-names = "tx"; 963 964 status = "disabled"; 965 }; 966 967 sti_uni_reader0: sti-uni-reader@8d83000 { 968 compatible = "st,stih407-uni-reader-pcm_in"; 969 #sound-dai-cells = <0>; 970 st,syscfg = <&syscfg_core>; 971 reg = <0x8d83000 0x158>; 972 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 973 dmas = <&fdma0 5 0 1>; 974 dma-names = "rx"; 975 976 status = "disabled"; 977 }; 978 979 sti_uni_reader1: sti-uni-reader@8d84000 { 980 compatible = "st,stih407-uni-reader-hdmi"; 981 #sound-dai-cells = <0>; 982 st,syscfg = <&syscfg_core>; 983 reg = <0x8d84000 0x158>; 984 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 985 dmas = <&fdma0 6 0 1>; 986 dma-names = "rx"; 987 988 status = "disabled"; 989 }; 990 }; 991 }; 992