1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2021-2021 Hisilicon Limited.
3
4 #include "hnae3.h"
5 #include "hclge_comm_cmd.h"
6
hclge_comm_cmd_config_regs(struct hclge_comm_hw * hw,struct hclge_comm_cmq_ring * ring)7 static void hclge_comm_cmd_config_regs(struct hclge_comm_hw *hw,
8 struct hclge_comm_cmq_ring *ring)
9 {
10 dma_addr_t dma = ring->desc_dma_addr;
11 u32 reg_val;
12
13 if (ring->ring_type == HCLGE_COMM_TYPE_CSQ) {
14 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
15 lower_32_bits(dma));
16 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
17 upper_32_bits(dma));
18 reg_val = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
19 reg_val &= HCLGE_COMM_NIC_SW_RST_RDY;
20 reg_val |= ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
21 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
22 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG, 0);
23 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG, 0);
24 } else {
25 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
26 lower_32_bits(dma));
27 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
28 upper_32_bits(dma));
29 reg_val = ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
30 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_DEPTH_REG, reg_val);
31 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_HEAD_REG, 0);
32 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG, 0);
33 }
34 }
35
hclge_comm_cmd_init_regs(struct hclge_comm_hw * hw)36 void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw)
37 {
38 hclge_comm_cmd_config_regs(hw, &hw->cmq.csq);
39 hclge_comm_cmd_config_regs(hw, &hw->cmq.crq);
40 }
41
hclge_comm_cmd_reuse_desc(struct hclge_desc * desc,bool is_read)42 void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
43 {
44 desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
45 HCLGE_COMM_CMD_FLAG_IN);
46 if (is_read)
47 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
48 else
49 desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR);
50 }
51
hclge_comm_set_default_capability(struct hnae3_ae_dev * ae_dev,bool is_pf)52 static void hclge_comm_set_default_capability(struct hnae3_ae_dev *ae_dev,
53 bool is_pf)
54 {
55 set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
56 if (is_pf) {
57 set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
58 set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
59 set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
60 }
61 }
62
hclge_comm_cmd_setup_basic_desc(struct hclge_desc * desc,enum hclge_opcode_type opcode,bool is_read)63 void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
64 enum hclge_opcode_type opcode,
65 bool is_read)
66 {
67 memset((void *)desc, 0, sizeof(struct hclge_desc));
68 desc->opcode = cpu_to_le16(opcode);
69 desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
70 HCLGE_COMM_CMD_FLAG_IN);
71
72 if (is_read)
73 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
74 }
75
hclge_comm_firmware_compat_config(struct hnae3_ae_dev * ae_dev,struct hclge_comm_hw * hw,bool en)76 int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
77 struct hclge_comm_hw *hw, bool en)
78 {
79 struct hclge_comm_firmware_compat_cmd *req;
80 struct hclge_desc desc;
81 u32 compat = 0;
82
83 hclge_comm_cmd_setup_basic_desc(&desc, HCLGE_OPC_IMP_COMPAT_CFG, false);
84
85 if (en) {
86 req = (struct hclge_comm_firmware_compat_cmd *)desc.data;
87
88 hnae3_set_bit(compat, HCLGE_COMM_LINK_EVENT_REPORT_EN_B, 1);
89 hnae3_set_bit(compat, HCLGE_COMM_NCSI_ERROR_REPORT_EN_B, 1);
90 if (hclge_comm_dev_phy_imp_supported(ae_dev))
91 hnae3_set_bit(compat, HCLGE_COMM_PHY_IMP_EN_B, 1);
92 hnae3_set_bit(compat, HCLGE_COMM_MAC_STATS_EXT_EN_B, 1);
93 hnae3_set_bit(compat, HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B, 1);
94 hnae3_set_bit(compat, HCLGE_COMM_LLRS_FEC_EN_B, 1);
95
96 req->compat = cpu_to_le32(compat);
97 }
98
99 return hclge_comm_cmd_send(hw, &desc, 1);
100 }
101
hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring * ring)102 void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
103 {
104 int size = ring->desc_num * sizeof(struct hclge_desc);
105
106 if (!ring->desc)
107 return;
108
109 dma_free_coherent(&ring->pdev->dev, size,
110 ring->desc, ring->desc_dma_addr);
111 ring->desc = NULL;
112 }
113
hclge_comm_alloc_cmd_desc(struct hclge_comm_cmq_ring * ring)114 static int hclge_comm_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
115 {
116 int size = ring->desc_num * sizeof(struct hclge_desc);
117
118 ring->desc = dma_alloc_coherent(&ring->pdev->dev,
119 size, &ring->desc_dma_addr, GFP_KERNEL);
120 if (!ring->desc)
121 return -ENOMEM;
122
123 return 0;
124 }
125
hclge_comm_build_api_caps(void)126 static __le32 hclge_comm_build_api_caps(void)
127 {
128 u32 api_caps = 0;
129
130 hnae3_set_bit(api_caps, HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B, 1);
131
132 return cpu_to_le32(api_caps);
133 }
134
135 static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
136 {HCLGE_COMM_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
137 {HCLGE_COMM_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
138 {HCLGE_COMM_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
139 {HCLGE_COMM_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
140 {HCLGE_COMM_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
141 {HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
142 {HCLGE_COMM_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
143 {HCLGE_COMM_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
144 {HCLGE_COMM_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
145 {HCLGE_COMM_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
146 {HCLGE_COMM_CAP_QB_B, HNAE3_DEV_SUPPORT_QB_B},
147 {HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},
148 {HCLGE_COMM_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
149 {HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
150 {HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B,
151 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
152 {HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
153 {HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},
154 {HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},
155 {HCLGE_COMM_CAP_FD_B, HNAE3_DEV_SUPPORT_FD_B},
156 {HCLGE_COMM_CAP_FEC_STATS_B, HNAE3_DEV_SUPPORT_FEC_STATS_B},
157 {HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},
158 {HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},
159 {HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},
160 };
161
162 static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
163 {HCLGE_COMM_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
164 {HCLGE_COMM_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
165 {HCLGE_COMM_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
166 {HCLGE_COMM_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
167 {HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
168 {HCLGE_COMM_CAP_QB_B, HNAE3_DEV_SUPPORT_QB_B},
169 {HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},
170 {HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
171 {HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},
172 {HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},
173 };
174
175 static void
hclge_comm_capability_to_bitmap(unsigned long * bitmap,__le32 * caps)176 hclge_comm_capability_to_bitmap(unsigned long *bitmap, __le32 *caps)
177 {
178 const unsigned int words = HCLGE_COMM_QUERY_CAP_LENGTH;
179 u32 val[HCLGE_COMM_QUERY_CAP_LENGTH];
180 unsigned int i;
181
182 for (i = 0; i < words; i++)
183 val[i] = __le32_to_cpu(caps[i]);
184
185 bitmap_from_arr32(bitmap, val,
186 HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32));
187 }
188
189 static void
hclge_comm_parse_capability(struct hnae3_ae_dev * ae_dev,bool is_pf,struct hclge_comm_query_version_cmd * cmd)190 hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf,
191 struct hclge_comm_query_version_cmd *cmd)
192 {
193 const struct hclge_comm_caps_bit_map *caps_map =
194 is_pf ? hclge_pf_cmd_caps : hclge_vf_cmd_caps;
195 u32 size = is_pf ? ARRAY_SIZE(hclge_pf_cmd_caps) :
196 ARRAY_SIZE(hclge_vf_cmd_caps);
197 DECLARE_BITMAP(caps, HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32));
198 u32 i;
199
200 hclge_comm_capability_to_bitmap(caps, cmd->caps);
201 for (i = 0; i < size; i++)
202 if (test_bit(caps_map[i].imp_bit, caps))
203 set_bit(caps_map[i].local_bit, ae_dev->caps);
204 }
205
hclge_comm_alloc_cmd_queue(struct hclge_comm_hw * hw,int ring_type)206 int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type)
207 {
208 struct hclge_comm_cmq_ring *ring =
209 (ring_type == HCLGE_COMM_TYPE_CSQ) ? &hw->cmq.csq :
210 &hw->cmq.crq;
211 int ret;
212
213 ring->ring_type = ring_type;
214
215 ret = hclge_comm_alloc_cmd_desc(ring);
216 if (ret)
217 dev_err(&ring->pdev->dev, "descriptor %s alloc error %d\n",
218 (ring_type == HCLGE_COMM_TYPE_CSQ) ? "CSQ" : "CRQ",
219 ret);
220
221 return ret;
222 }
223
hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev * ae_dev,struct hclge_comm_hw * hw,u32 * fw_version,bool is_pf)224 int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
225 struct hclge_comm_hw *hw,
226 u32 *fw_version, bool is_pf)
227 {
228 struct hclge_comm_query_version_cmd *resp;
229 struct hclge_desc desc;
230 int ret;
231
232 hclge_comm_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
233 resp = (struct hclge_comm_query_version_cmd *)desc.data;
234 resp->api_caps = hclge_comm_build_api_caps();
235
236 ret = hclge_comm_cmd_send(hw, &desc, 1);
237 if (ret)
238 return ret;
239
240 *fw_version = le32_to_cpu(resp->firmware);
241
242 ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
243 HNAE3_PCI_REVISION_BIT_SIZE;
244 ae_dev->dev_version |= ae_dev->pdev->revision;
245
246 if (ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
247 hclge_comm_set_default_capability(ae_dev, is_pf);
248 return 0;
249 }
250
251 hclge_comm_parse_capability(ae_dev, is_pf, resp);
252
253 return ret;
254 }
255
256 static const u16 spec_opcode[] = { HCLGE_OPC_STATS_64_BIT,
257 HCLGE_OPC_STATS_32_BIT,
258 HCLGE_OPC_STATS_MAC,
259 HCLGE_OPC_STATS_MAC_ALL,
260 HCLGE_OPC_QUERY_32_BIT_REG,
261 HCLGE_OPC_QUERY_64_BIT_REG,
262 HCLGE_QUERY_CLEAR_MPF_RAS_INT,
263 HCLGE_QUERY_CLEAR_PF_RAS_INT,
264 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
265 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
266 HCLGE_QUERY_ALL_ERR_INFO };
267
hclge_comm_is_special_opcode(u16 opcode)268 static bool hclge_comm_is_special_opcode(u16 opcode)
269 {
270 /* these commands have several descriptors,
271 * and use the first one to save opcode and return value
272 */
273 u32 i;
274
275 for (i = 0; i < ARRAY_SIZE(spec_opcode); i++)
276 if (spec_opcode[i] == opcode)
277 return true;
278
279 return false;
280 }
281
hclge_comm_ring_space(struct hclge_comm_cmq_ring * ring)282 static int hclge_comm_ring_space(struct hclge_comm_cmq_ring *ring)
283 {
284 int ntc = ring->next_to_clean;
285 int ntu = ring->next_to_use;
286 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
287
288 return ring->desc_num - used - 1;
289 }
290
hclge_comm_cmd_copy_desc(struct hclge_comm_hw * hw,struct hclge_desc * desc,int num)291 static void hclge_comm_cmd_copy_desc(struct hclge_comm_hw *hw,
292 struct hclge_desc *desc, int num)
293 {
294 struct hclge_desc *desc_to_use;
295 int handle = 0;
296
297 while (handle < num) {
298 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
299 *desc_to_use = desc[handle];
300 (hw->cmq.csq.next_to_use)++;
301 if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num)
302 hw->cmq.csq.next_to_use = 0;
303 handle++;
304 }
305 }
306
hclge_comm_is_valid_csq_clean_head(struct hclge_comm_cmq_ring * ring,int head)307 static int hclge_comm_is_valid_csq_clean_head(struct hclge_comm_cmq_ring *ring,
308 int head)
309 {
310 int ntc = ring->next_to_clean;
311 int ntu = ring->next_to_use;
312
313 if (ntu > ntc)
314 return head >= ntc && head <= ntu;
315
316 return head >= ntc || head <= ntu;
317 }
318
hclge_comm_cmd_csq_clean(struct hclge_comm_hw * hw)319 static int hclge_comm_cmd_csq_clean(struct hclge_comm_hw *hw)
320 {
321 struct hclge_comm_cmq_ring *csq = &hw->cmq.csq;
322 int clean;
323 u32 head;
324
325 head = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG);
326 rmb(); /* Make sure head is ready before touch any data */
327
328 if (!hclge_comm_is_valid_csq_clean_head(csq, head)) {
329 dev_warn(&hw->cmq.csq.pdev->dev, "wrong cmd head (%u, %d-%d)\n",
330 head, csq->next_to_use, csq->next_to_clean);
331 dev_warn(&hw->cmq.csq.pdev->dev,
332 "Disabling any further commands to IMP firmware\n");
333 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
334 dev_warn(&hw->cmq.csq.pdev->dev,
335 "IMP firmware watchdog reset soon expected!\n");
336 return -EIO;
337 }
338
339 clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
340 csq->next_to_clean = head;
341 return clean;
342 }
343
hclge_comm_cmd_csq_done(struct hclge_comm_hw * hw)344 static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw)
345 {
346 u32 head = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG);
347 return head == hw->cmq.csq.next_to_use;
348 }
349
hclge_get_cmdq_tx_timeout(u16 opcode,u32 tx_timeout)350 static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)
351 {
352 static const struct hclge_cmdq_tx_timeout_map cmdq_tx_timeout_map[] = {
353 {HCLGE_OPC_CFG_RST_TRIGGER, HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS},
354 };
355 u32 i;
356
357 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout_map); i++)
358 if (cmdq_tx_timeout_map[i].opcode == opcode)
359 return cmdq_tx_timeout_map[i].tx_timeout;
360
361 return tx_timeout;
362 }
363
hclge_comm_wait_for_resp(struct hclge_comm_hw * hw,u16 opcode,bool * is_completed)364 static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, u16 opcode,
365 bool *is_completed)
366 {
367 u32 cmdq_tx_timeout = hclge_get_cmdq_tx_timeout(opcode,
368 hw->cmq.tx_timeout);
369 u32 timeout = 0;
370
371 do {
372 if (hclge_comm_cmd_csq_done(hw)) {
373 *is_completed = true;
374 break;
375 }
376 udelay(1);
377 timeout++;
378 } while (timeout < cmdq_tx_timeout);
379 }
380
hclge_comm_cmd_convert_err_code(u16 desc_ret)381 static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
382 {
383 struct hclge_comm_errcode hclge_comm_cmd_errcode[] = {
384 { HCLGE_COMM_CMD_EXEC_SUCCESS, 0 },
385 { HCLGE_COMM_CMD_NO_AUTH, -EPERM },
386 { HCLGE_COMM_CMD_NOT_SUPPORTED, -EOPNOTSUPP },
387 { HCLGE_COMM_CMD_QUEUE_FULL, -EXFULL },
388 { HCLGE_COMM_CMD_NEXT_ERR, -ENOSR },
389 { HCLGE_COMM_CMD_UNEXE_ERR, -ENOTBLK },
390 { HCLGE_COMM_CMD_PARA_ERR, -EINVAL },
391 { HCLGE_COMM_CMD_RESULT_ERR, -ERANGE },
392 { HCLGE_COMM_CMD_TIMEOUT, -ETIME },
393 { HCLGE_COMM_CMD_HILINK_ERR, -ENOLINK },
394 { HCLGE_COMM_CMD_QUEUE_ILLEGAL, -ENXIO },
395 { HCLGE_COMM_CMD_INVALID, -EBADR },
396 };
397 u32 errcode_count = ARRAY_SIZE(hclge_comm_cmd_errcode);
398 u32 i;
399
400 for (i = 0; i < errcode_count; i++)
401 if (hclge_comm_cmd_errcode[i].imp_errcode == desc_ret)
402 return hclge_comm_cmd_errcode[i].common_errno;
403
404 return -EIO;
405 }
406
hclge_comm_cmd_check_retval(struct hclge_comm_hw * hw,struct hclge_desc * desc,int num,int ntc)407 static int hclge_comm_cmd_check_retval(struct hclge_comm_hw *hw,
408 struct hclge_desc *desc, int num,
409 int ntc)
410 {
411 u16 opcode, desc_ret;
412 int handle;
413
414 opcode = le16_to_cpu(desc[0].opcode);
415 for (handle = 0; handle < num; handle++) {
416 desc[handle] = hw->cmq.csq.desc[ntc];
417 ntc++;
418 if (ntc >= hw->cmq.csq.desc_num)
419 ntc = 0;
420 }
421 if (likely(!hclge_comm_is_special_opcode(opcode)))
422 desc_ret = le16_to_cpu(desc[num - 1].retval);
423 else
424 desc_ret = le16_to_cpu(desc[0].retval);
425
426 hw->cmq.last_status = desc_ret;
427
428 return hclge_comm_cmd_convert_err_code(desc_ret);
429 }
430
hclge_comm_cmd_check_result(struct hclge_comm_hw * hw,struct hclge_desc * desc,int num,int ntc)431 static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
432 struct hclge_desc *desc,
433 int num, int ntc)
434 {
435 bool is_completed = false;
436 int handle, ret;
437
438 /* If the command is sync, wait for the firmware to write back,
439 * if multi descriptors to be sent, use the first one to check
440 */
441 if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))
442 hclge_comm_wait_for_resp(hw, le16_to_cpu(desc->opcode),
443 &is_completed);
444
445 if (!is_completed)
446 ret = -EBADE;
447 else
448 ret = hclge_comm_cmd_check_retval(hw, desc, num, ntc);
449
450 /* Clean the command send queue */
451 handle = hclge_comm_cmd_csq_clean(hw);
452 if (handle < 0)
453 ret = handle;
454 else if (handle != num)
455 dev_warn(&hw->cmq.csq.pdev->dev,
456 "cleaned %d, need to clean %d\n", handle, num);
457 return ret;
458 }
459
460 /**
461 * hclge_comm_cmd_send - send command to command queue
462 * @hw: pointer to the hw struct
463 * @desc: prefilled descriptor for describing the command
464 * @num : the number of descriptors to be sent
465 *
466 * This is the main send command for command queue, it
467 * sends the queue, cleans the queue, etc
468 **/
hclge_comm_cmd_send(struct hclge_comm_hw * hw,struct hclge_desc * desc,int num)469 int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
470 int num)
471 {
472 struct hclge_comm_cmq_ring *csq = &hw->cmq.csq;
473 int ret;
474 int ntc;
475
476 spin_lock_bh(&hw->cmq.csq.lock);
477
478 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state)) {
479 spin_unlock_bh(&hw->cmq.csq.lock);
480 return -EBUSY;
481 }
482
483 if (num > hclge_comm_ring_space(&hw->cmq.csq)) {
484 /* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
485 * need update the SW HEAD pointer csq->next_to_clean
486 */
487 csq->next_to_clean =
488 hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG);
489 spin_unlock_bh(&hw->cmq.csq.lock);
490 return -EBUSY;
491 }
492
493 /**
494 * Record the location of desc in the ring for this time
495 * which will be use for hardware to write back
496 */
497 ntc = hw->cmq.csq.next_to_use;
498
499 hclge_comm_cmd_copy_desc(hw, desc, num);
500
501 /* Write to hardware */
502 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG,
503 hw->cmq.csq.next_to_use);
504
505 ret = hclge_comm_cmd_check_result(hw, desc, num, ntc);
506
507 spin_unlock_bh(&hw->cmq.csq.lock);
508
509 return ret;
510 }
511
hclge_comm_cmd_uninit_regs(struct hclge_comm_hw * hw)512 static void hclge_comm_cmd_uninit_regs(struct hclge_comm_hw *hw)
513 {
514 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 0);
515 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 0);
516 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 0);
517 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG, 0);
518 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG, 0);
519 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 0);
520 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 0);
521 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_DEPTH_REG, 0);
522 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_HEAD_REG, 0);
523 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG, 0);
524 }
525
hclge_comm_cmd_uninit(struct hnae3_ae_dev * ae_dev,struct hclge_comm_hw * hw)526 void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
527 struct hclge_comm_hw *hw)
528 {
529 struct hclge_comm_cmq *cmdq = &hw->cmq;
530
531 hclge_comm_firmware_compat_config(ae_dev, hw, false);
532 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
533
534 /* wait to ensure that the firmware completes the possible left
535 * over commands.
536 */
537 msleep(HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME);
538 spin_lock_bh(&cmdq->csq.lock);
539 spin_lock(&cmdq->crq.lock);
540 hclge_comm_cmd_uninit_regs(hw);
541 spin_unlock(&cmdq->crq.lock);
542 spin_unlock_bh(&cmdq->csq.lock);
543
544 hclge_comm_free_cmd_desc(&cmdq->csq);
545 hclge_comm_free_cmd_desc(&cmdq->crq);
546 }
547
hclge_comm_cmd_queue_init(struct pci_dev * pdev,struct hclge_comm_hw * hw)548 int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw)
549 {
550 struct hclge_comm_cmq *cmdq = &hw->cmq;
551 int ret;
552
553 /* Setup the lock for command queue */
554 spin_lock_init(&cmdq->csq.lock);
555 spin_lock_init(&cmdq->crq.lock);
556
557 cmdq->csq.pdev = pdev;
558 cmdq->crq.pdev = pdev;
559
560 /* Setup the queue entries for use cmd queue */
561 cmdq->csq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;
562 cmdq->crq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;
563
564 /* Setup Tx write back timeout */
565 cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT;
566
567 /* Setup queue rings */
568 ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CSQ);
569 if (ret) {
570 dev_err(&pdev->dev, "CSQ ring setup error %d\n", ret);
571 return ret;
572 }
573
574 ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CRQ);
575 if (ret) {
576 dev_err(&pdev->dev, "CRQ ring setup error %d\n", ret);
577 goto err_csq;
578 }
579
580 return 0;
581 err_csq:
582 hclge_comm_free_cmd_desc(&hw->cmq.csq);
583 return ret;
584 }
585
hclge_comm_cmd_init(struct hnae3_ae_dev * ae_dev,struct hclge_comm_hw * hw,u32 * fw_version,bool is_pf,unsigned long reset_pending)586 int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
587 u32 *fw_version, bool is_pf,
588 unsigned long reset_pending)
589 {
590 struct hclge_comm_cmq *cmdq = &hw->cmq;
591 int ret;
592
593 spin_lock_bh(&cmdq->csq.lock);
594 spin_lock(&cmdq->crq.lock);
595
596 cmdq->csq.next_to_clean = 0;
597 cmdq->csq.next_to_use = 0;
598 cmdq->crq.next_to_clean = 0;
599 cmdq->crq.next_to_use = 0;
600
601 hclge_comm_cmd_init_regs(hw);
602
603 spin_unlock(&cmdq->crq.lock);
604 spin_unlock_bh(&cmdq->csq.lock);
605
606 clear_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
607
608 /* Check if there is new reset pending, because the higher level
609 * reset may happen when lower level reset is being processed.
610 */
611 if (reset_pending) {
612 ret = -EBUSY;
613 goto err_cmd_init;
614 }
615
616 /* get version and device capabilities */
617 ret = hclge_comm_cmd_query_version_and_capability(ae_dev, hw,
618 fw_version, is_pf);
619 if (ret) {
620 dev_err(&ae_dev->pdev->dev,
621 "failed to query version and capabilities, ret = %d\n",
622 ret);
623 goto err_cmd_init;
624 }
625
626 dev_info(&ae_dev->pdev->dev,
627 "The firmware version is %lu.%lu.%lu.%lu\n",
628 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
629 HNAE3_FW_VERSION_BYTE3_SHIFT),
630 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
631 HNAE3_FW_VERSION_BYTE2_SHIFT),
632 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
633 HNAE3_FW_VERSION_BYTE1_SHIFT),
634 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
635 HNAE3_FW_VERSION_BYTE0_SHIFT));
636
637 if (!is_pf && ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3)
638 return 0;
639
640 /* ask the firmware to enable some features, driver can work without
641 * it.
642 */
643 ret = hclge_comm_firmware_compat_config(ae_dev, hw, true);
644 if (ret)
645 dev_warn(&ae_dev->pdev->dev,
646 "Firmware compatible features not enabled(%d).\n",
647 ret);
648 return 0;
649
650 err_cmd_init:
651 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
652
653 return ret;
654 }
655