1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * Common board functions for OMAP3 based boards.
5 *
6 * (C) Copyright 2004-2008
7 * Texas Instruments, <www.ti.com>
8 *
9 * Author :
10 * Sunil Kumar <sunilsaini05@gmail.com>
11 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 *
13 * Derived from Beagle Board and 3430 SDP code by
14 * Richard Woodruff <r-woodruff2@ti.com>
15 * Syed Mohammed Khasim <khasim@ti.com>
16 *
17 */
18 #include <common.h>
19 #include <dm.h>
20 #include <spl.h>
21 #include <asm/io.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mem.h>
24 #include <asm/cache.h>
25 #include <asm/armv7.h>
26 #include <asm/gpio.h>
27 #include <asm/omap_common.h>
28 #include <linux/compiler.h>
29
30 /* Declarations */
31 extern omap3_sysinfo sysinfo;
32 #ifndef CONFIG_SYS_L2CACHE_OFF
33 static void omap3_invalidate_l2_cache_secure(void);
34 #endif
35
36 #ifdef CONFIG_DM_GPIO
37 static const struct omap_gpio_platdata omap34xx_gpio[] = {
38 { 0, OMAP34XX_GPIO1_BASE },
39 { 1, OMAP34XX_GPIO2_BASE },
40 { 2, OMAP34XX_GPIO3_BASE },
41 { 3, OMAP34XX_GPIO4_BASE },
42 { 4, OMAP34XX_GPIO5_BASE },
43 { 5, OMAP34XX_GPIO6_BASE },
44 };
45
46 U_BOOT_DEVICES(omap34xx_gpios) = {
47 { "gpio_omap", &omap34xx_gpio[0] },
48 { "gpio_omap", &omap34xx_gpio[1] },
49 { "gpio_omap", &omap34xx_gpio[2] },
50 { "gpio_omap", &omap34xx_gpio[3] },
51 { "gpio_omap", &omap34xx_gpio[4] },
52 { "gpio_omap", &omap34xx_gpio[5] },
53 };
54
55 #else
56
57 static const struct gpio_bank gpio_bank_34xx[6] = {
58 { (void *)OMAP34XX_GPIO1_BASE },
59 { (void *)OMAP34XX_GPIO2_BASE },
60 { (void *)OMAP34XX_GPIO3_BASE },
61 { (void *)OMAP34XX_GPIO4_BASE },
62 { (void *)OMAP34XX_GPIO5_BASE },
63 { (void *)OMAP34XX_GPIO6_BASE },
64 };
65
66 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
67
68 #endif
69
70 /******************************************************************************
71 * Routine: secure_unlock
72 * Description: Setup security registers for access
73 * (GP Device only)
74 *****************************************************************************/
secure_unlock_mem(void)75 void secure_unlock_mem(void)
76 {
77 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
78 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
79 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
80 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
81 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
82
83 /* Protection Module Register Target APE (PM_RT) */
84 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
85 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
86 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
87 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
88
89 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
90 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
91 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
92
93 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
94 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
95 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
96 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
97
98 /* IVA Changes */
99 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
100 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
101 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
102
103 /* SDRC region 0 public */
104 writel(UNLOCK_1, &sms_base->rg_att0);
105 }
106
107 /******************************************************************************
108 * Routine: secureworld_exit()
109 * Description: If chip is EMU and boot type is external
110 * configure secure registers and exit secure world
111 * general use.
112 *****************************************************************************/
secureworld_exit(void)113 void secureworld_exit(void)
114 {
115 unsigned long i;
116
117 /* configure non-secure access control register */
118 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
119 /* enabling co-processor CP10 and CP11 accesses in NS world */
120 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
121 /*
122 * allow allocation of locked TLBs and L2 lines in NS world
123 * allow use of PLE registers in NS world also
124 */
125 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
126 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
127
128 /* Enable ASA in ACR register */
129 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
130 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
131 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
132
133 /* Exiting secure world */
134 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
135 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
136 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
137 }
138
139 /******************************************************************************
140 * Routine: try_unlock_sram()
141 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
142 * general use.
143 *****************************************************************************/
try_unlock_memory(void)144 void try_unlock_memory(void)
145 {
146 int mode;
147 int in_sdram = is_running_in_sdram();
148
149 /*
150 * if GP device unlock device SRAM for general use
151 * secure code breaks for Secure/Emulation device - HS/E/T
152 */
153 mode = get_device_type();
154 if (mode == GP_DEVICE)
155 secure_unlock_mem();
156
157 /*
158 * If device is EMU and boot is XIP external booting
159 * Unlock firewalls and disable L2 and put chip
160 * out of secure world
161 *
162 * Assuming memories are unlocked by the demon who put us in SDRAM
163 */
164 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
165 && (!in_sdram)) {
166 secure_unlock_mem();
167 secureworld_exit();
168 }
169
170 return;
171 }
172
early_system_init(void)173 void early_system_init(void)
174 {
175 hw_data_init();
176 }
177
178 /******************************************************************************
179 * Routine: s_init
180 * Description: Does early system init of muxing and clocks.
181 * - Called path is with SRAM stack.
182 *****************************************************************************/
s_init(void)183 void s_init(void)
184 {
185 watchdog_init();
186 early_system_init();
187
188 try_unlock_memory();
189
190 #ifndef CONFIG_SYS_L2CACHE_OFF
191 /* Invalidate L2-cache from secure mode */
192 omap3_invalidate_l2_cache_secure();
193 #endif
194
195 set_muxconf_regs();
196 sdelay(100);
197
198 prcm_init();
199
200 per_clocks_enable();
201
202 #ifdef CONFIG_USB_EHCI_OMAP
203 ehci_clocks_enable();
204 #endif
205 }
206
207 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)208 void board_init_f(ulong dummy)
209 {
210 early_system_init();
211 mem_init();
212 /*
213 * Save the boot parameters passed from romcode.
214 * We cannot delay the saving further than this,
215 * to prevent overwrites.
216 */
217 save_omap_boot_params();
218 }
219 #endif
220
221 /*
222 * Routine: misc_init_r
223 * Description: A basic misc_init_r that just displays the die ID
224 */
misc_init_r(void)225 int __weak misc_init_r(void)
226 {
227 omap_die_id_display();
228
229 return 0;
230 }
231
232 /******************************************************************************
233 * Routine: wait_for_command_complete
234 * Description: Wait for posting to finish on watchdog
235 *****************************************************************************/
wait_for_command_complete(struct watchdog * wd_base)236 static void wait_for_command_complete(struct watchdog *wd_base)
237 {
238 int pending = 1;
239 do {
240 pending = readl(&wd_base->wwps);
241 } while (pending);
242 }
243
244 /******************************************************************************
245 * Routine: watchdog_init
246 * Description: Shut down watch dogs
247 *****************************************************************************/
watchdog_init(void)248 void watchdog_init(void)
249 {
250 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
251 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
252
253 /*
254 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
255 * either taken care of by ROM (HS/EMU) or not accessible (GP).
256 * We need to take care of WD2-MPU or take a PRCM reset. WD3
257 * should not be running and does not generate a PRCM reset.
258 */
259
260 setbits_le32(&prcm_base->fclken_wkup, 0x20);
261 setbits_le32(&prcm_base->iclken_wkup, 0x20);
262 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
263
264 writel(WD_UNLOCK1, &wd2_base->wspr);
265 wait_for_command_complete(wd2_base);
266 writel(WD_UNLOCK2, &wd2_base->wspr);
267 }
268
269 /******************************************************************************
270 * Dummy function to handle errors for EABI incompatibility
271 *****************************************************************************/
abort(void)272 void abort(void)
273 {
274 }
275
276 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
277 /******************************************************************************
278 * OMAP3 specific command to switch between NAND HW and SW ecc
279 *****************************************************************************/
do_switch_ecc(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])280 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
281 {
282 int hw, strength = 1;
283
284 if (argc < 2 || argc > 3)
285 goto usage;
286
287 if (strncmp(argv[1], "hw", 2) == 0) {
288 hw = 1;
289 if (argc == 3) {
290 if (strncmp(argv[2], "bch8", 4) == 0)
291 strength = 8;
292 else if (strncmp(argv[2], "bch16", 5) == 0)
293 strength = 16;
294 else if (strncmp(argv[2], "hamming", 7) != 0)
295 goto usage;
296 }
297 } else if (strncmp(argv[1], "sw", 2) == 0) {
298 hw = 0;
299 if (argc == 3) {
300 if (strncmp(argv[2], "bch8", 4) == 0)
301 strength = 8;
302 else if (strncmp(argv[2], "hamming", 7) != 0)
303 goto usage;
304 }
305 } else {
306 goto usage;
307 }
308
309 return -omap_nand_switch_ecc(hw, strength);
310
311 usage:
312 printf ("Usage: nandecc %s\n", cmdtp->usage);
313 return 1;
314 }
315
316 U_BOOT_CMD(
317 nandecc, 3, 1, do_switch_ecc,
318 "switch OMAP3 NAND ECC calculation algorithm",
319 "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
320 " and 8-bit/16-bit BCH\n"
321 " ecc calculation (second parameter may"
322 " be omitted).\n"
323 "nandecc sw - Switch to NAND software ecc algorithm."
324 );
325
326 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
327
328 #ifdef CONFIG_DISPLAY_BOARDINFO
329 /**
330 * Print board information
331 */
checkboard(void)332 int checkboard (void)
333 {
334 char *mem_s ;
335
336 if (is_mem_sdr())
337 mem_s = "mSDR";
338 else
339 mem_s = "LPDDR";
340
341 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
342 sysinfo.nand_string);
343
344 return 0;
345 }
346 #endif /* CONFIG_DISPLAY_BOARDINFO */
347
omap3_emu_romcode_call(u32 service_id,u32 * parameters)348 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
349 {
350 u32 i, num_params = *parameters;
351 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
352
353 /*
354 * copy the parameters to an un-cached area to avoid coherency
355 * issues
356 */
357 for (i = 0; i < num_params; i++) {
358 __raw_writel(*parameters, sram_scratch_space);
359 parameters++;
360 sram_scratch_space++;
361 }
362
363 /* Now make the PPA call */
364 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
365 }
366
omap3_set_aux_cr_secure(u32 acr)367 void __weak omap3_set_aux_cr_secure(u32 acr)
368 {
369 struct emu_hal_params emu_romcode_params;
370
371 emu_romcode_params.num_params = 1;
372 emu_romcode_params.param1 = acr;
373 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
374 (u32 *)&emu_romcode_params);
375 }
376
v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)377 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
378 u32 cpu_rev_comb, u32 cpu_variant,
379 u32 cpu_rev)
380 {
381 if (get_device_type() == GP_DEVICE)
382 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
383
384 /* L2 Cache Auxiliary Control Register is not banked */
385 }
386
v7_arch_cp15_set_acr(u32 acr,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)387 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
388 u32 cpu_variant, u32 cpu_rev)
389 {
390 /* Write ACR - affects secure banked bits */
391 if (get_device_type() == GP_DEVICE)
392 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
393 else
394 omap3_set_aux_cr_secure(acr);
395
396 /* Write ACR - affects non-secure banked bits - some erratas need it */
397 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
398 }
399
400
401 #ifndef CONFIG_SYS_L2CACHE_OFF
omap3_update_aux_cr(u32 set_bits,u32 clear_bits)402 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
403 {
404 u32 acr;
405
406 /* Read ACR */
407 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
408 acr &= ~clear_bits;
409 acr |= set_bits;
410 v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
411
412 }
413
414 /* Invalidate the entire L2 cache from secure mode */
omap3_invalidate_l2_cache_secure(void)415 static void omap3_invalidate_l2_cache_secure(void)
416 {
417 if (get_device_type() == GP_DEVICE) {
418 omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
419 } else {
420 struct emu_hal_params emu_romcode_params;
421 emu_romcode_params.num_params = 1;
422 emu_romcode_params.param1 = 0;
423 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
424 (u32 *)&emu_romcode_params);
425 }
426 }
427
v7_outer_cache_enable(void)428 void v7_outer_cache_enable(void)
429 {
430
431 /*
432 * Set L2EN
433 * On some revisions L2EN bit is banked on some revisions it's not
434 * No harm in setting both banked bits(in fact this is required
435 * by an erratum)
436 */
437 omap3_update_aux_cr(0x2, 0);
438 }
439
omap3_outer_cache_disable(void)440 void omap3_outer_cache_disable(void)
441 {
442 /*
443 * Clear L2EN
444 * On some revisions L2EN bit is banked on some revisions it's not
445 * No harm in clearing both banked bits(in fact this is required
446 * by an erratum)
447 */
448 omap3_update_aux_cr(0, 0x2);
449 }
450 #endif /* !CONFIG_SYS_L2CACHE_OFF */
451