xref: /openbmc/qemu/hw/intc/i8259.c (revision ecb0e98b)
1 /*
2  * QEMU 8259 interrupt controller emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "hw/intc/i8259.h"
27 #include "hw/irq.h"
28 #include "hw/isa/isa.h"
29 #include "qemu/timer.h"
30 #include "qemu/log.h"
31 #include "hw/isa/i8259_internal.h"
32 #include "trace.h"
33 #include "qom/object.h"
34 
35 /* debug PIC */
36 //#define DEBUG_PIC
37 
38 //#define DEBUG_IRQ_LATENCY
39 
40 #define TYPE_I8259 "isa-i8259"
41 typedef struct PICClass PICClass;
42 DECLARE_CLASS_CHECKERS(PICClass, PIC,
43                        TYPE_I8259)
44 
45 /**
46  * PICClass:
47  * @parent_realize: The parent's realizefn.
48  */
49 struct PICClass {
50     PICCommonClass parent_class;
51 
52     DeviceRealize parent_realize;
53 };
54 
55 #ifdef DEBUG_IRQ_LATENCY
56 static int64_t irq_time[16];
57 #endif
58 PICCommonState *isa_pic;
59 static PICCommonState *slave_pic;
60 
61 /* return the highest priority found in mask (highest = smallest
62    number). Return 8 if no irq */
get_priority(PICCommonState * s,int mask)63 static int get_priority(PICCommonState *s, int mask)
64 {
65     int priority;
66 
67     if (mask == 0) {
68         return 8;
69     }
70     priority = 0;
71     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) {
72         priority++;
73     }
74     return priority;
75 }
76 
77 /* return the pic wanted interrupt. return -1 if none */
pic_get_irq(PICCommonState * s)78 static int pic_get_irq(PICCommonState *s)
79 {
80     int mask, cur_priority, priority;
81 
82     mask = s->irr & ~s->imr;
83     priority = get_priority(s, mask);
84     if (priority == 8) {
85         return -1;
86     }
87     /* compute current priority. If special fully nested mode on the
88        master, the IRQ coming from the slave is not taken into account
89        for the priority computation. */
90     mask = s->isr;
91     if (s->special_mask) {
92         mask &= ~s->imr;
93     }
94     if (s->special_fully_nested_mode && s->master) {
95         mask &= ~(1 << 2);
96     }
97     cur_priority = get_priority(s, mask);
98     if (priority < cur_priority) {
99         /* higher priority found: an irq should be generated */
100         return (priority + s->priority_add) & 7;
101     } else {
102         return -1;
103     }
104 }
105 
106 /* Update INT output. Must be called every time the output may have changed. */
pic_update_irq(PICCommonState * s)107 static void pic_update_irq(PICCommonState *s)
108 {
109     int irq;
110 
111     irq = pic_get_irq(s);
112     if (irq >= 0) {
113         trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add);
114         qemu_irq_raise(s->int_out[0]);
115     } else {
116         qemu_irq_lower(s->int_out[0]);
117     }
118 }
119 
120 /* set irq level. If an edge is detected, then the IRR is set to 1 */
pic_set_irq(void * opaque,int irq,int level)121 static void pic_set_irq(void *opaque, int irq, int level)
122 {
123     PICCommonState *s = opaque;
124     int mask = 1 << irq;
125     int irq_index = s->master ? irq : irq + 8;
126 
127     trace_pic_set_irq(s->master, irq, level);
128     pic_stat_update_irq(irq_index, level);
129 
130 #ifdef DEBUG_IRQ_LATENCY
131     if (level) {
132         irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
133     }
134 #endif
135 
136     if (s->ltim || (s->elcr & mask)) {
137         /* level triggered */
138         if (level) {
139             s->irr |= mask;
140             s->last_irr |= mask;
141         } else {
142             s->irr &= ~mask;
143             s->last_irr &= ~mask;
144         }
145     } else {
146         /* edge triggered */
147         if (level) {
148             if ((s->last_irr & mask) == 0) {
149                 s->irr |= mask;
150             }
151             s->last_irr |= mask;
152         } else {
153             s->last_irr &= ~mask;
154         }
155     }
156     pic_update_irq(s);
157 }
158 
159 /* acknowledge interrupt 'irq' */
pic_intack(PICCommonState * s,int irq)160 static void pic_intack(PICCommonState *s, int irq)
161 {
162     if (s->auto_eoi) {
163         if (s->rotate_on_auto_eoi) {
164             s->priority_add = (irq + 1) & 7;
165         }
166     } else {
167         s->isr |= (1 << irq);
168     }
169     /* We don't clear a level sensitive interrupt here */
170     if (!s->ltim && !(s->elcr & (1 << irq))) {
171         s->irr &= ~(1 << irq);
172     }
173     pic_update_irq(s);
174 }
175 
pic_read_irq(PICCommonState * s)176 int pic_read_irq(PICCommonState *s)
177 {
178     int irq, intno;
179 
180     irq = pic_get_irq(s);
181     if (irq >= 0) {
182         int irq2;
183 
184         if (irq == 2) {
185             irq2 = pic_get_irq(slave_pic);
186             if (irq2 >= 0) {
187                 pic_intack(slave_pic, irq2);
188             } else {
189                 /* spurious IRQ on slave controller */
190                 irq2 = 7;
191             }
192             intno = slave_pic->irq_base + irq2;
193             pic_intack(s, irq);
194             irq = irq2 + 8;
195         } else {
196             intno = s->irq_base + irq;
197             pic_intack(s, irq);
198         }
199     } else {
200         /* spurious IRQ on host controller */
201         irq = 7;
202         intno = s->irq_base + irq;
203     }
204 
205 #ifdef DEBUG_IRQ_LATENCY
206     printf("IRQ%d latency=%0.3fus\n",
207            irq,
208            (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
209                     irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND);
210 #endif
211 
212     trace_pic_interrupt(irq, intno);
213     return intno;
214 }
215 
pic_init_reset(PICCommonState * s)216 static void pic_init_reset(PICCommonState *s)
217 {
218     pic_reset_common(s);
219     pic_update_irq(s);
220 }
221 
pic_reset(DeviceState * dev)222 static void pic_reset(DeviceState *dev)
223 {
224     PICCommonState *s = PIC_COMMON(dev);
225 
226     s->elcr = 0;
227     s->ltim = 0;
228     pic_init_reset(s);
229 }
230 
pic_ioport_write(void * opaque,hwaddr addr64,uint64_t val64,unsigned size)231 static void pic_ioport_write(void *opaque, hwaddr addr64,
232                              uint64_t val64, unsigned size)
233 {
234     PICCommonState *s = opaque;
235     uint32_t addr = addr64;
236     uint32_t val = val64;
237     int priority, cmd, irq;
238 
239     trace_pic_ioport_write(s->master, addr, val);
240 
241     if (addr == 0) {
242         if (val & 0x10) {
243             pic_init_reset(s);
244             s->init_state = 1;
245             s->init4 = val & 1;
246             s->single_mode = val & 2;
247             s->ltim = val & 8;
248         } else if (val & 0x08) {
249             if (val & 0x04) {
250                 s->poll = 1;
251             }
252             if (val & 0x02) {
253                 s->read_reg_select = val & 1;
254             }
255             if (val & 0x40) {
256                 s->special_mask = (val >> 5) & 1;
257             }
258         } else {
259             cmd = val >> 5;
260             switch (cmd) {
261             case 0:
262             case 4:
263                 s->rotate_on_auto_eoi = cmd >> 2;
264                 break;
265             case 1: /* end of interrupt */
266             case 5:
267                 priority = get_priority(s, s->isr);
268                 if (priority != 8) {
269                     irq = (priority + s->priority_add) & 7;
270                     s->isr &= ~(1 << irq);
271                     if (cmd == 5) {
272                         s->priority_add = (irq + 1) & 7;
273                     }
274                     pic_update_irq(s);
275                 }
276                 break;
277             case 3:
278                 irq = val & 7;
279                 s->isr &= ~(1 << irq);
280                 pic_update_irq(s);
281                 break;
282             case 6:
283                 s->priority_add = (val + 1) & 7;
284                 pic_update_irq(s);
285                 break;
286             case 7:
287                 irq = val & 7;
288                 s->isr &= ~(1 << irq);
289                 s->priority_add = (irq + 1) & 7;
290                 pic_update_irq(s);
291                 break;
292             default:
293                 /* no operation */
294                 break;
295             }
296         }
297     } else {
298         switch (s->init_state) {
299         case 0:
300             /* normal mode */
301             s->imr = val;
302             pic_update_irq(s);
303             break;
304         case 1:
305             s->irq_base = val & 0xf8;
306             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
307             break;
308         case 2:
309             if (s->init4) {
310                 s->init_state = 3;
311             } else {
312                 s->init_state = 0;
313             }
314             break;
315         case 3:
316             s->special_fully_nested_mode = (val >> 4) & 1;
317             s->auto_eoi = (val >> 1) & 1;
318             s->init_state = 0;
319             break;
320         }
321     }
322 }
323 
pic_ioport_read(void * opaque,hwaddr addr,unsigned size)324 static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
325                                 unsigned size)
326 {
327     PICCommonState *s = opaque;
328     int ret;
329 
330     if (s->poll) {
331         ret = pic_get_irq(s);
332         if (ret >= 0) {
333             pic_intack(s, ret);
334             ret |= 0x80;
335         } else {
336             ret = 0;
337         }
338         s->poll = 0;
339     } else {
340         if (addr == 0) {
341             if (s->read_reg_select) {
342                 ret = s->isr;
343             } else {
344                 ret = s->irr;
345             }
346         } else {
347             ret = s->imr;
348         }
349     }
350     trace_pic_ioport_read(s->master, addr, ret);
351     return ret;
352 }
353 
pic_get_output(PICCommonState * s)354 int pic_get_output(PICCommonState *s)
355 {
356     return (pic_get_irq(s) >= 0);
357 }
358 
elcr_ioport_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)359 static void elcr_ioport_write(void *opaque, hwaddr addr,
360                               uint64_t val, unsigned size)
361 {
362     PICCommonState *s = opaque;
363     s->elcr = val & s->elcr_mask;
364 }
365 
elcr_ioport_read(void * opaque,hwaddr addr,unsigned size)366 static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
367                                  unsigned size)
368 {
369     PICCommonState *s = opaque;
370     return s->elcr;
371 }
372 
373 static const MemoryRegionOps pic_base_ioport_ops = {
374     .read = pic_ioport_read,
375     .write = pic_ioport_write,
376     .impl = {
377         .min_access_size = 1,
378         .max_access_size = 1,
379     },
380 };
381 
382 static const MemoryRegionOps pic_elcr_ioport_ops = {
383     .read = elcr_ioport_read,
384     .write = elcr_ioport_write,
385     .impl = {
386         .min_access_size = 1,
387         .max_access_size = 1,
388     },
389 };
390 
pic_realize(DeviceState * dev,Error ** errp)391 static void pic_realize(DeviceState *dev, Error **errp)
392 {
393     PICCommonState *s = PIC_COMMON(dev);
394     PICClass *pc = PIC_GET_CLASS(dev);
395 
396     memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s,
397                           "pic", 2);
398     memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s,
399                           "elcr", 1);
400 
401     qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out));
402     qdev_init_gpio_in(dev, pic_set_irq, 8);
403 
404     pc->parent_realize(dev, errp);
405 }
406 
i8259_init(ISABus * bus,qemu_irq parent_irq_in)407 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in)
408 {
409     qemu_irq *irq_set;
410     DeviceState *dev;
411     ISADevice *isadev;
412     int i;
413 
414     irq_set = g_new0(qemu_irq, ISA_NUM_IRQS);
415 
416     isadev = i8259_init_chip(TYPE_I8259, bus, true);
417     dev = DEVICE(isadev);
418 
419     qdev_connect_gpio_out(dev, 0, parent_irq_in);
420     for (i = 0 ; i < 8; i++) {
421         irq_set[i] = qdev_get_gpio_in(dev, i);
422     }
423 
424     isa_pic = PIC_COMMON(dev);
425 
426     isadev = i8259_init_chip(TYPE_I8259, bus, false);
427     dev = DEVICE(isadev);
428 
429     qdev_connect_gpio_out(dev, 0, irq_set[2]);
430     for (i = 0 ; i < 8; i++) {
431         irq_set[i + 8] = qdev_get_gpio_in(dev, i);
432     }
433 
434     slave_pic = PIC_COMMON(dev);
435 
436     return irq_set;
437 }
438 
i8259_class_init(ObjectClass * klass,void * data)439 static void i8259_class_init(ObjectClass *klass, void *data)
440 {
441     PICClass *k = PIC_CLASS(klass);
442     DeviceClass *dc = DEVICE_CLASS(klass);
443 
444     device_class_set_parent_realize(dc, pic_realize, &k->parent_realize);
445     dc->reset = pic_reset;
446 }
447 
448 static const TypeInfo i8259_info = {
449     .name       = TYPE_I8259,
450     .instance_size = sizeof(PICCommonState),
451     .parent     = TYPE_PIC_COMMON,
452     .class_init = i8259_class_init,
453     .class_size = sizeof(PICClass),
454 };
455 
pic_register_types(void)456 static void pic_register_types(void)
457 {
458     type_register_static(&i8259_info);
459 }
460 
461 type_init(pic_register_types)
462