1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_PIP_DEFS_H__ 29 #define __CVMX_PIP_DEFS_H__ 30 31 /* 32 * Enumeration representing the amount of packet processing 33 * and validation performed by the input hardware. 34 */ 35 enum cvmx_pip_port_parse_mode { 36 /* 37 * Packet input doesn't perform any processing of the input 38 * packet. 39 */ 40 CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, 41 /* 42 * Full packet processing is performed with pointer starting 43 * at the L2 (ethernet MAC) header. 44 */ 45 CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, 46 /* 47 * Input packets are assumed to be IP. Results from non IP 48 * packets is undefined. Pointers reference the beginning of 49 * the IP header. 50 */ 51 CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull 52 }; 53 54 #define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8) 55 #define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull)) 56 #define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull)) 57 #define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16) 58 #define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16) 59 #define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8) 60 #define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull)) 61 #define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8) 62 #define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8) 63 #define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8) 64 #define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull)) 65 #define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull)) 66 #define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8) 67 #define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull)) 68 #define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull)) 69 #define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull)) 70 #define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull)) 71 #define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull)) 72 #define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull)) 73 #define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8) 74 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8) 75 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8) 76 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8) 77 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8) 78 #define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8) 79 #define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8) 80 #define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull)) 81 #define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull)) 82 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80) 83 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128) 84 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16) 85 #define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128) 86 #define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16) 87 #define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128) 88 #define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80) 89 #define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128) 90 #define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80) 91 #define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128) 92 #define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80) 93 #define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128) 94 #define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80) 95 #define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128) 96 #define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80) 97 #define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128) 98 #define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80) 99 #define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128) 100 #define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80) 101 #define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128) 102 #define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80) 103 #define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128) 104 #define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80) 105 #define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128) 106 #define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull)) 107 #define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32) 108 #define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32) 109 #define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32) 110 #define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32) 111 #define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32) 112 #define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32) 113 #define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull)) 114 #define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8) 115 #define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull)) 116 #define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull)) 117 #define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull)) 118 #define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8) 119 #define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40) 120 #define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40) 121 #define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40) 122 #define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40) 123 #define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40) 124 #define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40) 125 #define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40) 126 #define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40) 127 #define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40) 128 #define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40) 129 #define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40) 130 #define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40) 131 132 union cvmx_pip_alt_skip_cfgx { 133 uint64_t u64; 134 struct cvmx_pip_alt_skip_cfgx_s { 135 #ifdef __BIG_ENDIAN_BITFIELD 136 uint64_t reserved_57_63:7; 137 uint64_t len:1; 138 uint64_t reserved_46_55:10; 139 uint64_t bit1:6; 140 uint64_t reserved_38_39:2; 141 uint64_t bit0:6; 142 uint64_t reserved_23_31:9; 143 uint64_t skip3:7; 144 uint64_t reserved_15_15:1; 145 uint64_t skip2:7; 146 uint64_t reserved_7_7:1; 147 uint64_t skip1:7; 148 #else 149 uint64_t skip1:7; 150 uint64_t reserved_7_7:1; 151 uint64_t skip2:7; 152 uint64_t reserved_15_15:1; 153 uint64_t skip3:7; 154 uint64_t reserved_23_31:9; 155 uint64_t bit0:6; 156 uint64_t reserved_38_39:2; 157 uint64_t bit1:6; 158 uint64_t reserved_46_55:10; 159 uint64_t len:1; 160 uint64_t reserved_57_63:7; 161 #endif 162 } s; 163 }; 164 165 union cvmx_pip_bck_prs { 166 uint64_t u64; 167 struct cvmx_pip_bck_prs_s { 168 #ifdef __BIG_ENDIAN_BITFIELD 169 uint64_t bckprs:1; 170 uint64_t reserved_13_62:50; 171 uint64_t hiwater:5; 172 uint64_t reserved_5_7:3; 173 uint64_t lowater:5; 174 #else 175 uint64_t lowater:5; 176 uint64_t reserved_5_7:3; 177 uint64_t hiwater:5; 178 uint64_t reserved_13_62:50; 179 uint64_t bckprs:1; 180 #endif 181 } s; 182 }; 183 184 union cvmx_pip_bist_status { 185 uint64_t u64; 186 struct cvmx_pip_bist_status_s { 187 #ifdef __BIG_ENDIAN_BITFIELD 188 uint64_t reserved_22_63:42; 189 uint64_t bist:22; 190 #else 191 uint64_t bist:22; 192 uint64_t reserved_22_63:42; 193 #endif 194 } s; 195 struct cvmx_pip_bist_status_cn30xx { 196 #ifdef __BIG_ENDIAN_BITFIELD 197 uint64_t reserved_18_63:46; 198 uint64_t bist:18; 199 #else 200 uint64_t bist:18; 201 uint64_t reserved_18_63:46; 202 #endif 203 } cn30xx; 204 struct cvmx_pip_bist_status_cn50xx { 205 #ifdef __BIG_ENDIAN_BITFIELD 206 uint64_t reserved_17_63:47; 207 uint64_t bist:17; 208 #else 209 uint64_t bist:17; 210 uint64_t reserved_17_63:47; 211 #endif 212 } cn50xx; 213 struct cvmx_pip_bist_status_cn61xx { 214 #ifdef __BIG_ENDIAN_BITFIELD 215 uint64_t reserved_20_63:44; 216 uint64_t bist:20; 217 #else 218 uint64_t bist:20; 219 uint64_t reserved_20_63:44; 220 #endif 221 } cn61xx; 222 }; 223 224 union cvmx_pip_bsel_ext_cfgx { 225 uint64_t u64; 226 struct cvmx_pip_bsel_ext_cfgx_s { 227 #ifdef __BIG_ENDIAN_BITFIELD 228 uint64_t reserved_56_63:8; 229 uint64_t upper_tag:16; 230 uint64_t tag:8; 231 uint64_t reserved_25_31:7; 232 uint64_t offset:9; 233 uint64_t reserved_7_15:9; 234 uint64_t skip:7; 235 #else 236 uint64_t skip:7; 237 uint64_t reserved_7_15:9; 238 uint64_t offset:9; 239 uint64_t reserved_25_31:7; 240 uint64_t tag:8; 241 uint64_t upper_tag:16; 242 uint64_t reserved_56_63:8; 243 #endif 244 } s; 245 }; 246 247 union cvmx_pip_bsel_ext_posx { 248 uint64_t u64; 249 struct cvmx_pip_bsel_ext_posx_s { 250 #ifdef __BIG_ENDIAN_BITFIELD 251 uint64_t pos7_val:1; 252 uint64_t pos7:7; 253 uint64_t pos6_val:1; 254 uint64_t pos6:7; 255 uint64_t pos5_val:1; 256 uint64_t pos5:7; 257 uint64_t pos4_val:1; 258 uint64_t pos4:7; 259 uint64_t pos3_val:1; 260 uint64_t pos3:7; 261 uint64_t pos2_val:1; 262 uint64_t pos2:7; 263 uint64_t pos1_val:1; 264 uint64_t pos1:7; 265 uint64_t pos0_val:1; 266 uint64_t pos0:7; 267 #else 268 uint64_t pos0:7; 269 uint64_t pos0_val:1; 270 uint64_t pos1:7; 271 uint64_t pos1_val:1; 272 uint64_t pos2:7; 273 uint64_t pos2_val:1; 274 uint64_t pos3:7; 275 uint64_t pos3_val:1; 276 uint64_t pos4:7; 277 uint64_t pos4_val:1; 278 uint64_t pos5:7; 279 uint64_t pos5_val:1; 280 uint64_t pos6:7; 281 uint64_t pos6_val:1; 282 uint64_t pos7:7; 283 uint64_t pos7_val:1; 284 #endif 285 } s; 286 }; 287 288 union cvmx_pip_bsel_tbl_entx { 289 uint64_t u64; 290 struct cvmx_pip_bsel_tbl_entx_s { 291 #ifdef __BIG_ENDIAN_BITFIELD 292 uint64_t tag_en:1; 293 uint64_t grp_en:1; 294 uint64_t tt_en:1; 295 uint64_t qos_en:1; 296 uint64_t reserved_40_59:20; 297 uint64_t tag:8; 298 uint64_t reserved_22_31:10; 299 uint64_t grp:6; 300 uint64_t reserved_10_15:6; 301 uint64_t tt:2; 302 uint64_t reserved_3_7:5; 303 uint64_t qos:3; 304 #else 305 uint64_t qos:3; 306 uint64_t reserved_3_7:5; 307 uint64_t tt:2; 308 uint64_t reserved_10_15:6; 309 uint64_t grp:6; 310 uint64_t reserved_22_31:10; 311 uint64_t tag:8; 312 uint64_t reserved_40_59:20; 313 uint64_t qos_en:1; 314 uint64_t tt_en:1; 315 uint64_t grp_en:1; 316 uint64_t tag_en:1; 317 #endif 318 } s; 319 struct cvmx_pip_bsel_tbl_entx_cn61xx { 320 #ifdef __BIG_ENDIAN_BITFIELD 321 uint64_t tag_en:1; 322 uint64_t grp_en:1; 323 uint64_t tt_en:1; 324 uint64_t qos_en:1; 325 uint64_t reserved_40_59:20; 326 uint64_t tag:8; 327 uint64_t reserved_20_31:12; 328 uint64_t grp:4; 329 uint64_t reserved_10_15:6; 330 uint64_t tt:2; 331 uint64_t reserved_3_7:5; 332 uint64_t qos:3; 333 #else 334 uint64_t qos:3; 335 uint64_t reserved_3_7:5; 336 uint64_t tt:2; 337 uint64_t reserved_10_15:6; 338 uint64_t grp:4; 339 uint64_t reserved_20_31:12; 340 uint64_t tag:8; 341 uint64_t reserved_40_59:20; 342 uint64_t qos_en:1; 343 uint64_t tt_en:1; 344 uint64_t grp_en:1; 345 uint64_t tag_en:1; 346 #endif 347 } cn61xx; 348 }; 349 350 union cvmx_pip_clken { 351 uint64_t u64; 352 struct cvmx_pip_clken_s { 353 #ifdef __BIG_ENDIAN_BITFIELD 354 uint64_t reserved_1_63:63; 355 uint64_t clken:1; 356 #else 357 uint64_t clken:1; 358 uint64_t reserved_1_63:63; 359 #endif 360 } s; 361 }; 362 363 union cvmx_pip_crc_ctlx { 364 uint64_t u64; 365 struct cvmx_pip_crc_ctlx_s { 366 #ifdef __BIG_ENDIAN_BITFIELD 367 uint64_t reserved_2_63:62; 368 uint64_t invres:1; 369 uint64_t reflect:1; 370 #else 371 uint64_t reflect:1; 372 uint64_t invres:1; 373 uint64_t reserved_2_63:62; 374 #endif 375 } s; 376 }; 377 378 union cvmx_pip_crc_ivx { 379 uint64_t u64; 380 struct cvmx_pip_crc_ivx_s { 381 #ifdef __BIG_ENDIAN_BITFIELD 382 uint64_t reserved_32_63:32; 383 uint64_t iv:32; 384 #else 385 uint64_t iv:32; 386 uint64_t reserved_32_63:32; 387 #endif 388 } s; 389 }; 390 391 union cvmx_pip_dec_ipsecx { 392 uint64_t u64; 393 struct cvmx_pip_dec_ipsecx_s { 394 #ifdef __BIG_ENDIAN_BITFIELD 395 uint64_t reserved_18_63:46; 396 uint64_t tcp:1; 397 uint64_t udp:1; 398 uint64_t dprt:16; 399 #else 400 uint64_t dprt:16; 401 uint64_t udp:1; 402 uint64_t tcp:1; 403 uint64_t reserved_18_63:46; 404 #endif 405 } s; 406 }; 407 408 union cvmx_pip_dsa_src_grp { 409 uint64_t u64; 410 struct cvmx_pip_dsa_src_grp_s { 411 #ifdef __BIG_ENDIAN_BITFIELD 412 uint64_t map15:4; 413 uint64_t map14:4; 414 uint64_t map13:4; 415 uint64_t map12:4; 416 uint64_t map11:4; 417 uint64_t map10:4; 418 uint64_t map9:4; 419 uint64_t map8:4; 420 uint64_t map7:4; 421 uint64_t map6:4; 422 uint64_t map5:4; 423 uint64_t map4:4; 424 uint64_t map3:4; 425 uint64_t map2:4; 426 uint64_t map1:4; 427 uint64_t map0:4; 428 #else 429 uint64_t map0:4; 430 uint64_t map1:4; 431 uint64_t map2:4; 432 uint64_t map3:4; 433 uint64_t map4:4; 434 uint64_t map5:4; 435 uint64_t map6:4; 436 uint64_t map7:4; 437 uint64_t map8:4; 438 uint64_t map9:4; 439 uint64_t map10:4; 440 uint64_t map11:4; 441 uint64_t map12:4; 442 uint64_t map13:4; 443 uint64_t map14:4; 444 uint64_t map15:4; 445 #endif 446 } s; 447 }; 448 449 union cvmx_pip_dsa_vid_grp { 450 uint64_t u64; 451 struct cvmx_pip_dsa_vid_grp_s { 452 #ifdef __BIG_ENDIAN_BITFIELD 453 uint64_t map15:4; 454 uint64_t map14:4; 455 uint64_t map13:4; 456 uint64_t map12:4; 457 uint64_t map11:4; 458 uint64_t map10:4; 459 uint64_t map9:4; 460 uint64_t map8:4; 461 uint64_t map7:4; 462 uint64_t map6:4; 463 uint64_t map5:4; 464 uint64_t map4:4; 465 uint64_t map3:4; 466 uint64_t map2:4; 467 uint64_t map1:4; 468 uint64_t map0:4; 469 #else 470 uint64_t map0:4; 471 uint64_t map1:4; 472 uint64_t map2:4; 473 uint64_t map3:4; 474 uint64_t map4:4; 475 uint64_t map5:4; 476 uint64_t map6:4; 477 uint64_t map7:4; 478 uint64_t map8:4; 479 uint64_t map9:4; 480 uint64_t map10:4; 481 uint64_t map11:4; 482 uint64_t map12:4; 483 uint64_t map13:4; 484 uint64_t map14:4; 485 uint64_t map15:4; 486 #endif 487 } s; 488 }; 489 490 union cvmx_pip_frm_len_chkx { 491 uint64_t u64; 492 struct cvmx_pip_frm_len_chkx_s { 493 #ifdef __BIG_ENDIAN_BITFIELD 494 uint64_t reserved_32_63:32; 495 uint64_t maxlen:16; 496 uint64_t minlen:16; 497 #else 498 uint64_t minlen:16; 499 uint64_t maxlen:16; 500 uint64_t reserved_32_63:32; 501 #endif 502 } s; 503 }; 504 505 union cvmx_pip_gbl_cfg { 506 uint64_t u64; 507 struct cvmx_pip_gbl_cfg_s { 508 #ifdef __BIG_ENDIAN_BITFIELD 509 uint64_t reserved_19_63:45; 510 uint64_t tag_syn:1; 511 uint64_t ip6_udp:1; 512 uint64_t max_l2:1; 513 uint64_t reserved_11_15:5; 514 uint64_t raw_shf:3; 515 uint64_t reserved_3_7:5; 516 uint64_t nip_shf:3; 517 #else 518 uint64_t nip_shf:3; 519 uint64_t reserved_3_7:5; 520 uint64_t raw_shf:3; 521 uint64_t reserved_11_15:5; 522 uint64_t max_l2:1; 523 uint64_t ip6_udp:1; 524 uint64_t tag_syn:1; 525 uint64_t reserved_19_63:45; 526 #endif 527 } s; 528 }; 529 530 union cvmx_pip_gbl_ctl { 531 uint64_t u64; 532 struct cvmx_pip_gbl_ctl_s { 533 #ifdef __BIG_ENDIAN_BITFIELD 534 uint64_t reserved_29_63:35; 535 uint64_t egrp_dis:1; 536 uint64_t ihmsk_dis:1; 537 uint64_t dsa_grp_tvid:1; 538 uint64_t dsa_grp_scmd:1; 539 uint64_t dsa_grp_sid:1; 540 uint64_t reserved_21_23:3; 541 uint64_t ring_en:1; 542 uint64_t reserved_17_19:3; 543 uint64_t ignrs:1; 544 uint64_t vs_wqe:1; 545 uint64_t vs_qos:1; 546 uint64_t l2_mal:1; 547 uint64_t tcp_flag:1; 548 uint64_t l4_len:1; 549 uint64_t l4_chk:1; 550 uint64_t l4_prt:1; 551 uint64_t l4_mal:1; 552 uint64_t reserved_6_7:2; 553 uint64_t ip6_eext:2; 554 uint64_t ip4_opts:1; 555 uint64_t ip_hop:1; 556 uint64_t ip_mal:1; 557 uint64_t ip_chk:1; 558 #else 559 uint64_t ip_chk:1; 560 uint64_t ip_mal:1; 561 uint64_t ip_hop:1; 562 uint64_t ip4_opts:1; 563 uint64_t ip6_eext:2; 564 uint64_t reserved_6_7:2; 565 uint64_t l4_mal:1; 566 uint64_t l4_prt:1; 567 uint64_t l4_chk:1; 568 uint64_t l4_len:1; 569 uint64_t tcp_flag:1; 570 uint64_t l2_mal:1; 571 uint64_t vs_qos:1; 572 uint64_t vs_wqe:1; 573 uint64_t ignrs:1; 574 uint64_t reserved_17_19:3; 575 uint64_t ring_en:1; 576 uint64_t reserved_21_23:3; 577 uint64_t dsa_grp_sid:1; 578 uint64_t dsa_grp_scmd:1; 579 uint64_t dsa_grp_tvid:1; 580 uint64_t ihmsk_dis:1; 581 uint64_t egrp_dis:1; 582 uint64_t reserved_29_63:35; 583 #endif 584 } s; 585 struct cvmx_pip_gbl_ctl_cn30xx { 586 #ifdef __BIG_ENDIAN_BITFIELD 587 uint64_t reserved_17_63:47; 588 uint64_t ignrs:1; 589 uint64_t vs_wqe:1; 590 uint64_t vs_qos:1; 591 uint64_t l2_mal:1; 592 uint64_t tcp_flag:1; 593 uint64_t l4_len:1; 594 uint64_t l4_chk:1; 595 uint64_t l4_prt:1; 596 uint64_t l4_mal:1; 597 uint64_t reserved_6_7:2; 598 uint64_t ip6_eext:2; 599 uint64_t ip4_opts:1; 600 uint64_t ip_hop:1; 601 uint64_t ip_mal:1; 602 uint64_t ip_chk:1; 603 #else 604 uint64_t ip_chk:1; 605 uint64_t ip_mal:1; 606 uint64_t ip_hop:1; 607 uint64_t ip4_opts:1; 608 uint64_t ip6_eext:2; 609 uint64_t reserved_6_7:2; 610 uint64_t l4_mal:1; 611 uint64_t l4_prt:1; 612 uint64_t l4_chk:1; 613 uint64_t l4_len:1; 614 uint64_t tcp_flag:1; 615 uint64_t l2_mal:1; 616 uint64_t vs_qos:1; 617 uint64_t vs_wqe:1; 618 uint64_t ignrs:1; 619 uint64_t reserved_17_63:47; 620 #endif 621 } cn30xx; 622 struct cvmx_pip_gbl_ctl_cn52xx { 623 #ifdef __BIG_ENDIAN_BITFIELD 624 uint64_t reserved_27_63:37; 625 uint64_t dsa_grp_tvid:1; 626 uint64_t dsa_grp_scmd:1; 627 uint64_t dsa_grp_sid:1; 628 uint64_t reserved_21_23:3; 629 uint64_t ring_en:1; 630 uint64_t reserved_17_19:3; 631 uint64_t ignrs:1; 632 uint64_t vs_wqe:1; 633 uint64_t vs_qos:1; 634 uint64_t l2_mal:1; 635 uint64_t tcp_flag:1; 636 uint64_t l4_len:1; 637 uint64_t l4_chk:1; 638 uint64_t l4_prt:1; 639 uint64_t l4_mal:1; 640 uint64_t reserved_6_7:2; 641 uint64_t ip6_eext:2; 642 uint64_t ip4_opts:1; 643 uint64_t ip_hop:1; 644 uint64_t ip_mal:1; 645 uint64_t ip_chk:1; 646 #else 647 uint64_t ip_chk:1; 648 uint64_t ip_mal:1; 649 uint64_t ip_hop:1; 650 uint64_t ip4_opts:1; 651 uint64_t ip6_eext:2; 652 uint64_t reserved_6_7:2; 653 uint64_t l4_mal:1; 654 uint64_t l4_prt:1; 655 uint64_t l4_chk:1; 656 uint64_t l4_len:1; 657 uint64_t tcp_flag:1; 658 uint64_t l2_mal:1; 659 uint64_t vs_qos:1; 660 uint64_t vs_wqe:1; 661 uint64_t ignrs:1; 662 uint64_t reserved_17_19:3; 663 uint64_t ring_en:1; 664 uint64_t reserved_21_23:3; 665 uint64_t dsa_grp_sid:1; 666 uint64_t dsa_grp_scmd:1; 667 uint64_t dsa_grp_tvid:1; 668 uint64_t reserved_27_63:37; 669 #endif 670 } cn52xx; 671 struct cvmx_pip_gbl_ctl_cn56xxp1 { 672 #ifdef __BIG_ENDIAN_BITFIELD 673 uint64_t reserved_21_63:43; 674 uint64_t ring_en:1; 675 uint64_t reserved_17_19:3; 676 uint64_t ignrs:1; 677 uint64_t vs_wqe:1; 678 uint64_t vs_qos:1; 679 uint64_t l2_mal:1; 680 uint64_t tcp_flag:1; 681 uint64_t l4_len:1; 682 uint64_t l4_chk:1; 683 uint64_t l4_prt:1; 684 uint64_t l4_mal:1; 685 uint64_t reserved_6_7:2; 686 uint64_t ip6_eext:2; 687 uint64_t ip4_opts:1; 688 uint64_t ip_hop:1; 689 uint64_t ip_mal:1; 690 uint64_t ip_chk:1; 691 #else 692 uint64_t ip_chk:1; 693 uint64_t ip_mal:1; 694 uint64_t ip_hop:1; 695 uint64_t ip4_opts:1; 696 uint64_t ip6_eext:2; 697 uint64_t reserved_6_7:2; 698 uint64_t l4_mal:1; 699 uint64_t l4_prt:1; 700 uint64_t l4_chk:1; 701 uint64_t l4_len:1; 702 uint64_t tcp_flag:1; 703 uint64_t l2_mal:1; 704 uint64_t vs_qos:1; 705 uint64_t vs_wqe:1; 706 uint64_t ignrs:1; 707 uint64_t reserved_17_19:3; 708 uint64_t ring_en:1; 709 uint64_t reserved_21_63:43; 710 #endif 711 } cn56xxp1; 712 struct cvmx_pip_gbl_ctl_cn61xx { 713 #ifdef __BIG_ENDIAN_BITFIELD 714 uint64_t reserved_28_63:36; 715 uint64_t ihmsk_dis:1; 716 uint64_t dsa_grp_tvid:1; 717 uint64_t dsa_grp_scmd:1; 718 uint64_t dsa_grp_sid:1; 719 uint64_t reserved_21_23:3; 720 uint64_t ring_en:1; 721 uint64_t reserved_17_19:3; 722 uint64_t ignrs:1; 723 uint64_t vs_wqe:1; 724 uint64_t vs_qos:1; 725 uint64_t l2_mal:1; 726 uint64_t tcp_flag:1; 727 uint64_t l4_len:1; 728 uint64_t l4_chk:1; 729 uint64_t l4_prt:1; 730 uint64_t l4_mal:1; 731 uint64_t reserved_6_7:2; 732 uint64_t ip6_eext:2; 733 uint64_t ip4_opts:1; 734 uint64_t ip_hop:1; 735 uint64_t ip_mal:1; 736 uint64_t ip_chk:1; 737 #else 738 uint64_t ip_chk:1; 739 uint64_t ip_mal:1; 740 uint64_t ip_hop:1; 741 uint64_t ip4_opts:1; 742 uint64_t ip6_eext:2; 743 uint64_t reserved_6_7:2; 744 uint64_t l4_mal:1; 745 uint64_t l4_prt:1; 746 uint64_t l4_chk:1; 747 uint64_t l4_len:1; 748 uint64_t tcp_flag:1; 749 uint64_t l2_mal:1; 750 uint64_t vs_qos:1; 751 uint64_t vs_wqe:1; 752 uint64_t ignrs:1; 753 uint64_t reserved_17_19:3; 754 uint64_t ring_en:1; 755 uint64_t reserved_21_23:3; 756 uint64_t dsa_grp_sid:1; 757 uint64_t dsa_grp_scmd:1; 758 uint64_t dsa_grp_tvid:1; 759 uint64_t ihmsk_dis:1; 760 uint64_t reserved_28_63:36; 761 #endif 762 } cn61xx; 763 struct cvmx_pip_gbl_ctl_cn68xx { 764 #ifdef __BIG_ENDIAN_BITFIELD 765 uint64_t reserved_29_63:35; 766 uint64_t egrp_dis:1; 767 uint64_t ihmsk_dis:1; 768 uint64_t dsa_grp_tvid:1; 769 uint64_t dsa_grp_scmd:1; 770 uint64_t dsa_grp_sid:1; 771 uint64_t reserved_17_23:7; 772 uint64_t ignrs:1; 773 uint64_t vs_wqe:1; 774 uint64_t vs_qos:1; 775 uint64_t l2_mal:1; 776 uint64_t tcp_flag:1; 777 uint64_t l4_len:1; 778 uint64_t l4_chk:1; 779 uint64_t l4_prt:1; 780 uint64_t l4_mal:1; 781 uint64_t reserved_6_7:2; 782 uint64_t ip6_eext:2; 783 uint64_t ip4_opts:1; 784 uint64_t ip_hop:1; 785 uint64_t ip_mal:1; 786 uint64_t ip_chk:1; 787 #else 788 uint64_t ip_chk:1; 789 uint64_t ip_mal:1; 790 uint64_t ip_hop:1; 791 uint64_t ip4_opts:1; 792 uint64_t ip6_eext:2; 793 uint64_t reserved_6_7:2; 794 uint64_t l4_mal:1; 795 uint64_t l4_prt:1; 796 uint64_t l4_chk:1; 797 uint64_t l4_len:1; 798 uint64_t tcp_flag:1; 799 uint64_t l2_mal:1; 800 uint64_t vs_qos:1; 801 uint64_t vs_wqe:1; 802 uint64_t ignrs:1; 803 uint64_t reserved_17_23:7; 804 uint64_t dsa_grp_sid:1; 805 uint64_t dsa_grp_scmd:1; 806 uint64_t dsa_grp_tvid:1; 807 uint64_t ihmsk_dis:1; 808 uint64_t egrp_dis:1; 809 uint64_t reserved_29_63:35; 810 #endif 811 } cn68xx; 812 struct cvmx_pip_gbl_ctl_cn68xxp1 { 813 #ifdef __BIG_ENDIAN_BITFIELD 814 uint64_t reserved_28_63:36; 815 uint64_t ihmsk_dis:1; 816 uint64_t dsa_grp_tvid:1; 817 uint64_t dsa_grp_scmd:1; 818 uint64_t dsa_grp_sid:1; 819 uint64_t reserved_17_23:7; 820 uint64_t ignrs:1; 821 uint64_t vs_wqe:1; 822 uint64_t vs_qos:1; 823 uint64_t l2_mal:1; 824 uint64_t tcp_flag:1; 825 uint64_t l4_len:1; 826 uint64_t l4_chk:1; 827 uint64_t l4_prt:1; 828 uint64_t l4_mal:1; 829 uint64_t reserved_6_7:2; 830 uint64_t ip6_eext:2; 831 uint64_t ip4_opts:1; 832 uint64_t ip_hop:1; 833 uint64_t ip_mal:1; 834 uint64_t ip_chk:1; 835 #else 836 uint64_t ip_chk:1; 837 uint64_t ip_mal:1; 838 uint64_t ip_hop:1; 839 uint64_t ip4_opts:1; 840 uint64_t ip6_eext:2; 841 uint64_t reserved_6_7:2; 842 uint64_t l4_mal:1; 843 uint64_t l4_prt:1; 844 uint64_t l4_chk:1; 845 uint64_t l4_len:1; 846 uint64_t tcp_flag:1; 847 uint64_t l2_mal:1; 848 uint64_t vs_qos:1; 849 uint64_t vs_wqe:1; 850 uint64_t ignrs:1; 851 uint64_t reserved_17_23:7; 852 uint64_t dsa_grp_sid:1; 853 uint64_t dsa_grp_scmd:1; 854 uint64_t dsa_grp_tvid:1; 855 uint64_t ihmsk_dis:1; 856 uint64_t reserved_28_63:36; 857 #endif 858 } cn68xxp1; 859 }; 860 861 union cvmx_pip_hg_pri_qos { 862 uint64_t u64; 863 struct cvmx_pip_hg_pri_qos_s { 864 #ifdef __BIG_ENDIAN_BITFIELD 865 uint64_t reserved_13_63:51; 866 uint64_t up_qos:1; 867 uint64_t reserved_11_11:1; 868 uint64_t qos:3; 869 uint64_t reserved_6_7:2; 870 uint64_t pri:6; 871 #else 872 uint64_t pri:6; 873 uint64_t reserved_6_7:2; 874 uint64_t qos:3; 875 uint64_t reserved_11_11:1; 876 uint64_t up_qos:1; 877 uint64_t reserved_13_63:51; 878 #endif 879 } s; 880 }; 881 882 union cvmx_pip_int_en { 883 uint64_t u64; 884 struct cvmx_pip_int_en_s { 885 #ifdef __BIG_ENDIAN_BITFIELD 886 uint64_t reserved_13_63:51; 887 uint64_t punyerr:1; 888 uint64_t lenerr:1; 889 uint64_t maxerr:1; 890 uint64_t minerr:1; 891 uint64_t beperr:1; 892 uint64_t feperr:1; 893 uint64_t todoovr:1; 894 uint64_t skprunt:1; 895 uint64_t badtag:1; 896 uint64_t prtnxa:1; 897 uint64_t bckprs:1; 898 uint64_t crcerr:1; 899 uint64_t pktdrp:1; 900 #else 901 uint64_t pktdrp:1; 902 uint64_t crcerr:1; 903 uint64_t bckprs:1; 904 uint64_t prtnxa:1; 905 uint64_t badtag:1; 906 uint64_t skprunt:1; 907 uint64_t todoovr:1; 908 uint64_t feperr:1; 909 uint64_t beperr:1; 910 uint64_t minerr:1; 911 uint64_t maxerr:1; 912 uint64_t lenerr:1; 913 uint64_t punyerr:1; 914 uint64_t reserved_13_63:51; 915 #endif 916 } s; 917 struct cvmx_pip_int_en_cn30xx { 918 #ifdef __BIG_ENDIAN_BITFIELD 919 uint64_t reserved_9_63:55; 920 uint64_t beperr:1; 921 uint64_t feperr:1; 922 uint64_t todoovr:1; 923 uint64_t skprunt:1; 924 uint64_t badtag:1; 925 uint64_t prtnxa:1; 926 uint64_t bckprs:1; 927 uint64_t crcerr:1; 928 uint64_t pktdrp:1; 929 #else 930 uint64_t pktdrp:1; 931 uint64_t crcerr:1; 932 uint64_t bckprs:1; 933 uint64_t prtnxa:1; 934 uint64_t badtag:1; 935 uint64_t skprunt:1; 936 uint64_t todoovr:1; 937 uint64_t feperr:1; 938 uint64_t beperr:1; 939 uint64_t reserved_9_63:55; 940 #endif 941 } cn30xx; 942 struct cvmx_pip_int_en_cn50xx { 943 #ifdef __BIG_ENDIAN_BITFIELD 944 uint64_t reserved_12_63:52; 945 uint64_t lenerr:1; 946 uint64_t maxerr:1; 947 uint64_t minerr:1; 948 uint64_t beperr:1; 949 uint64_t feperr:1; 950 uint64_t todoovr:1; 951 uint64_t skprunt:1; 952 uint64_t badtag:1; 953 uint64_t prtnxa:1; 954 uint64_t bckprs:1; 955 uint64_t reserved_1_1:1; 956 uint64_t pktdrp:1; 957 #else 958 uint64_t pktdrp:1; 959 uint64_t reserved_1_1:1; 960 uint64_t bckprs:1; 961 uint64_t prtnxa:1; 962 uint64_t badtag:1; 963 uint64_t skprunt:1; 964 uint64_t todoovr:1; 965 uint64_t feperr:1; 966 uint64_t beperr:1; 967 uint64_t minerr:1; 968 uint64_t maxerr:1; 969 uint64_t lenerr:1; 970 uint64_t reserved_12_63:52; 971 #endif 972 } cn50xx; 973 struct cvmx_pip_int_en_cn52xx { 974 #ifdef __BIG_ENDIAN_BITFIELD 975 uint64_t reserved_13_63:51; 976 uint64_t punyerr:1; 977 uint64_t lenerr:1; 978 uint64_t maxerr:1; 979 uint64_t minerr:1; 980 uint64_t beperr:1; 981 uint64_t feperr:1; 982 uint64_t todoovr:1; 983 uint64_t skprunt:1; 984 uint64_t badtag:1; 985 uint64_t prtnxa:1; 986 uint64_t bckprs:1; 987 uint64_t reserved_1_1:1; 988 uint64_t pktdrp:1; 989 #else 990 uint64_t pktdrp:1; 991 uint64_t reserved_1_1:1; 992 uint64_t bckprs:1; 993 uint64_t prtnxa:1; 994 uint64_t badtag:1; 995 uint64_t skprunt:1; 996 uint64_t todoovr:1; 997 uint64_t feperr:1; 998 uint64_t beperr:1; 999 uint64_t minerr:1; 1000 uint64_t maxerr:1; 1001 uint64_t lenerr:1; 1002 uint64_t punyerr:1; 1003 uint64_t reserved_13_63:51; 1004 #endif 1005 } cn52xx; 1006 struct cvmx_pip_int_en_cn56xxp1 { 1007 #ifdef __BIG_ENDIAN_BITFIELD 1008 uint64_t reserved_12_63:52; 1009 uint64_t lenerr:1; 1010 uint64_t maxerr:1; 1011 uint64_t minerr:1; 1012 uint64_t beperr:1; 1013 uint64_t feperr:1; 1014 uint64_t todoovr:1; 1015 uint64_t skprunt:1; 1016 uint64_t badtag:1; 1017 uint64_t prtnxa:1; 1018 uint64_t bckprs:1; 1019 uint64_t crcerr:1; 1020 uint64_t pktdrp:1; 1021 #else 1022 uint64_t pktdrp:1; 1023 uint64_t crcerr:1; 1024 uint64_t bckprs:1; 1025 uint64_t prtnxa:1; 1026 uint64_t badtag:1; 1027 uint64_t skprunt:1; 1028 uint64_t todoovr:1; 1029 uint64_t feperr:1; 1030 uint64_t beperr:1; 1031 uint64_t minerr:1; 1032 uint64_t maxerr:1; 1033 uint64_t lenerr:1; 1034 uint64_t reserved_12_63:52; 1035 #endif 1036 } cn56xxp1; 1037 struct cvmx_pip_int_en_cn58xx { 1038 #ifdef __BIG_ENDIAN_BITFIELD 1039 uint64_t reserved_13_63:51; 1040 uint64_t punyerr:1; 1041 uint64_t reserved_9_11:3; 1042 uint64_t beperr:1; 1043 uint64_t feperr:1; 1044 uint64_t todoovr:1; 1045 uint64_t skprunt:1; 1046 uint64_t badtag:1; 1047 uint64_t prtnxa:1; 1048 uint64_t bckprs:1; 1049 uint64_t crcerr:1; 1050 uint64_t pktdrp:1; 1051 #else 1052 uint64_t pktdrp:1; 1053 uint64_t crcerr:1; 1054 uint64_t bckprs:1; 1055 uint64_t prtnxa:1; 1056 uint64_t badtag:1; 1057 uint64_t skprunt:1; 1058 uint64_t todoovr:1; 1059 uint64_t feperr:1; 1060 uint64_t beperr:1; 1061 uint64_t reserved_9_11:3; 1062 uint64_t punyerr:1; 1063 uint64_t reserved_13_63:51; 1064 #endif 1065 } cn58xx; 1066 }; 1067 1068 union cvmx_pip_int_reg { 1069 uint64_t u64; 1070 struct cvmx_pip_int_reg_s { 1071 #ifdef __BIG_ENDIAN_BITFIELD 1072 uint64_t reserved_13_63:51; 1073 uint64_t punyerr:1; 1074 uint64_t lenerr:1; 1075 uint64_t maxerr:1; 1076 uint64_t minerr:1; 1077 uint64_t beperr:1; 1078 uint64_t feperr:1; 1079 uint64_t todoovr:1; 1080 uint64_t skprunt:1; 1081 uint64_t badtag:1; 1082 uint64_t prtnxa:1; 1083 uint64_t bckprs:1; 1084 uint64_t crcerr:1; 1085 uint64_t pktdrp:1; 1086 #else 1087 uint64_t pktdrp:1; 1088 uint64_t crcerr:1; 1089 uint64_t bckprs:1; 1090 uint64_t prtnxa:1; 1091 uint64_t badtag:1; 1092 uint64_t skprunt:1; 1093 uint64_t todoovr:1; 1094 uint64_t feperr:1; 1095 uint64_t beperr:1; 1096 uint64_t minerr:1; 1097 uint64_t maxerr:1; 1098 uint64_t lenerr:1; 1099 uint64_t punyerr:1; 1100 uint64_t reserved_13_63:51; 1101 #endif 1102 } s; 1103 struct cvmx_pip_int_reg_cn30xx { 1104 #ifdef __BIG_ENDIAN_BITFIELD 1105 uint64_t reserved_9_63:55; 1106 uint64_t beperr:1; 1107 uint64_t feperr:1; 1108 uint64_t todoovr:1; 1109 uint64_t skprunt:1; 1110 uint64_t badtag:1; 1111 uint64_t prtnxa:1; 1112 uint64_t bckprs:1; 1113 uint64_t crcerr:1; 1114 uint64_t pktdrp:1; 1115 #else 1116 uint64_t pktdrp:1; 1117 uint64_t crcerr:1; 1118 uint64_t bckprs:1; 1119 uint64_t prtnxa:1; 1120 uint64_t badtag:1; 1121 uint64_t skprunt:1; 1122 uint64_t todoovr:1; 1123 uint64_t feperr:1; 1124 uint64_t beperr:1; 1125 uint64_t reserved_9_63:55; 1126 #endif 1127 } cn30xx; 1128 struct cvmx_pip_int_reg_cn50xx { 1129 #ifdef __BIG_ENDIAN_BITFIELD 1130 uint64_t reserved_12_63:52; 1131 uint64_t lenerr:1; 1132 uint64_t maxerr:1; 1133 uint64_t minerr:1; 1134 uint64_t beperr:1; 1135 uint64_t feperr:1; 1136 uint64_t todoovr:1; 1137 uint64_t skprunt:1; 1138 uint64_t badtag:1; 1139 uint64_t prtnxa:1; 1140 uint64_t bckprs:1; 1141 uint64_t reserved_1_1:1; 1142 uint64_t pktdrp:1; 1143 #else 1144 uint64_t pktdrp:1; 1145 uint64_t reserved_1_1:1; 1146 uint64_t bckprs:1; 1147 uint64_t prtnxa:1; 1148 uint64_t badtag:1; 1149 uint64_t skprunt:1; 1150 uint64_t todoovr:1; 1151 uint64_t feperr:1; 1152 uint64_t beperr:1; 1153 uint64_t minerr:1; 1154 uint64_t maxerr:1; 1155 uint64_t lenerr:1; 1156 uint64_t reserved_12_63:52; 1157 #endif 1158 } cn50xx; 1159 struct cvmx_pip_int_reg_cn52xx { 1160 #ifdef __BIG_ENDIAN_BITFIELD 1161 uint64_t reserved_13_63:51; 1162 uint64_t punyerr:1; 1163 uint64_t lenerr:1; 1164 uint64_t maxerr:1; 1165 uint64_t minerr:1; 1166 uint64_t beperr:1; 1167 uint64_t feperr:1; 1168 uint64_t todoovr:1; 1169 uint64_t skprunt:1; 1170 uint64_t badtag:1; 1171 uint64_t prtnxa:1; 1172 uint64_t bckprs:1; 1173 uint64_t reserved_1_1:1; 1174 uint64_t pktdrp:1; 1175 #else 1176 uint64_t pktdrp:1; 1177 uint64_t reserved_1_1:1; 1178 uint64_t bckprs:1; 1179 uint64_t prtnxa:1; 1180 uint64_t badtag:1; 1181 uint64_t skprunt:1; 1182 uint64_t todoovr:1; 1183 uint64_t feperr:1; 1184 uint64_t beperr:1; 1185 uint64_t minerr:1; 1186 uint64_t maxerr:1; 1187 uint64_t lenerr:1; 1188 uint64_t punyerr:1; 1189 uint64_t reserved_13_63:51; 1190 #endif 1191 } cn52xx; 1192 struct cvmx_pip_int_reg_cn56xxp1 { 1193 #ifdef __BIG_ENDIAN_BITFIELD 1194 uint64_t reserved_12_63:52; 1195 uint64_t lenerr:1; 1196 uint64_t maxerr:1; 1197 uint64_t minerr:1; 1198 uint64_t beperr:1; 1199 uint64_t feperr:1; 1200 uint64_t todoovr:1; 1201 uint64_t skprunt:1; 1202 uint64_t badtag:1; 1203 uint64_t prtnxa:1; 1204 uint64_t bckprs:1; 1205 uint64_t crcerr:1; 1206 uint64_t pktdrp:1; 1207 #else 1208 uint64_t pktdrp:1; 1209 uint64_t crcerr:1; 1210 uint64_t bckprs:1; 1211 uint64_t prtnxa:1; 1212 uint64_t badtag:1; 1213 uint64_t skprunt:1; 1214 uint64_t todoovr:1; 1215 uint64_t feperr:1; 1216 uint64_t beperr:1; 1217 uint64_t minerr:1; 1218 uint64_t maxerr:1; 1219 uint64_t lenerr:1; 1220 uint64_t reserved_12_63:52; 1221 #endif 1222 } cn56xxp1; 1223 struct cvmx_pip_int_reg_cn58xx { 1224 #ifdef __BIG_ENDIAN_BITFIELD 1225 uint64_t reserved_13_63:51; 1226 uint64_t punyerr:1; 1227 uint64_t reserved_9_11:3; 1228 uint64_t beperr:1; 1229 uint64_t feperr:1; 1230 uint64_t todoovr:1; 1231 uint64_t skprunt:1; 1232 uint64_t badtag:1; 1233 uint64_t prtnxa:1; 1234 uint64_t bckprs:1; 1235 uint64_t crcerr:1; 1236 uint64_t pktdrp:1; 1237 #else 1238 uint64_t pktdrp:1; 1239 uint64_t crcerr:1; 1240 uint64_t bckprs:1; 1241 uint64_t prtnxa:1; 1242 uint64_t badtag:1; 1243 uint64_t skprunt:1; 1244 uint64_t todoovr:1; 1245 uint64_t feperr:1; 1246 uint64_t beperr:1; 1247 uint64_t reserved_9_11:3; 1248 uint64_t punyerr:1; 1249 uint64_t reserved_13_63:51; 1250 #endif 1251 } cn58xx; 1252 }; 1253 1254 union cvmx_pip_ip_offset { 1255 uint64_t u64; 1256 struct cvmx_pip_ip_offset_s { 1257 #ifdef __BIG_ENDIAN_BITFIELD 1258 uint64_t reserved_3_63:61; 1259 uint64_t offset:3; 1260 #else 1261 uint64_t offset:3; 1262 uint64_t reserved_3_63:61; 1263 #endif 1264 } s; 1265 }; 1266 1267 union cvmx_pip_pri_tblx { 1268 uint64_t u64; 1269 struct cvmx_pip_pri_tblx_s { 1270 #ifdef __BIG_ENDIAN_BITFIELD 1271 uint64_t diff2_padd:8; 1272 uint64_t hg2_padd:8; 1273 uint64_t vlan2_padd:8; 1274 uint64_t reserved_38_39:2; 1275 uint64_t diff2_bpid:6; 1276 uint64_t reserved_30_31:2; 1277 uint64_t hg2_bpid:6; 1278 uint64_t reserved_22_23:2; 1279 uint64_t vlan2_bpid:6; 1280 uint64_t reserved_11_15:5; 1281 uint64_t diff2_qos:3; 1282 uint64_t reserved_7_7:1; 1283 uint64_t hg2_qos:3; 1284 uint64_t reserved_3_3:1; 1285 uint64_t vlan2_qos:3; 1286 #else 1287 uint64_t vlan2_qos:3; 1288 uint64_t reserved_3_3:1; 1289 uint64_t hg2_qos:3; 1290 uint64_t reserved_7_7:1; 1291 uint64_t diff2_qos:3; 1292 uint64_t reserved_11_15:5; 1293 uint64_t vlan2_bpid:6; 1294 uint64_t reserved_22_23:2; 1295 uint64_t hg2_bpid:6; 1296 uint64_t reserved_30_31:2; 1297 uint64_t diff2_bpid:6; 1298 uint64_t reserved_38_39:2; 1299 uint64_t vlan2_padd:8; 1300 uint64_t hg2_padd:8; 1301 uint64_t diff2_padd:8; 1302 #endif 1303 } s; 1304 }; 1305 1306 union cvmx_pip_prt_cfgx { 1307 uint64_t u64; 1308 struct cvmx_pip_prt_cfgx_s { 1309 #ifdef __BIG_ENDIAN_BITFIELD 1310 uint64_t reserved_55_63:9; 1311 uint64_t ih_pri:1; 1312 uint64_t len_chk_sel:1; 1313 uint64_t pad_len:1; 1314 uint64_t vlan_len:1; 1315 uint64_t lenerr_en:1; 1316 uint64_t maxerr_en:1; 1317 uint64_t minerr_en:1; 1318 uint64_t grp_wat_47:4; 1319 uint64_t qos_wat_47:4; 1320 uint64_t reserved_37_39:3; 1321 uint64_t rawdrp:1; 1322 uint64_t tag_inc:2; 1323 uint64_t dyn_rs:1; 1324 uint64_t inst_hdr:1; 1325 uint64_t grp_wat:4; 1326 uint64_t hg_qos:1; 1327 uint64_t qos:3; 1328 uint64_t qos_wat:4; 1329 uint64_t qos_vsel:1; 1330 uint64_t qos_vod:1; 1331 uint64_t qos_diff:1; 1332 uint64_t qos_vlan:1; 1333 uint64_t reserved_13_15:3; 1334 uint64_t crc_en:1; 1335 uint64_t higig_en:1; 1336 uint64_t dsa_en:1; 1337 uint64_t mode:2; 1338 uint64_t reserved_7_7:1; 1339 uint64_t skip:7; 1340 #else 1341 uint64_t skip:7; 1342 uint64_t reserved_7_7:1; 1343 uint64_t mode:2; 1344 uint64_t dsa_en:1; 1345 uint64_t higig_en:1; 1346 uint64_t crc_en:1; 1347 uint64_t reserved_13_15:3; 1348 uint64_t qos_vlan:1; 1349 uint64_t qos_diff:1; 1350 uint64_t qos_vod:1; 1351 uint64_t qos_vsel:1; 1352 uint64_t qos_wat:4; 1353 uint64_t qos:3; 1354 uint64_t hg_qos:1; 1355 uint64_t grp_wat:4; 1356 uint64_t inst_hdr:1; 1357 uint64_t dyn_rs:1; 1358 uint64_t tag_inc:2; 1359 uint64_t rawdrp:1; 1360 uint64_t reserved_37_39:3; 1361 uint64_t qos_wat_47:4; 1362 uint64_t grp_wat_47:4; 1363 uint64_t minerr_en:1; 1364 uint64_t maxerr_en:1; 1365 uint64_t lenerr_en:1; 1366 uint64_t vlan_len:1; 1367 uint64_t pad_len:1; 1368 uint64_t len_chk_sel:1; 1369 uint64_t ih_pri:1; 1370 uint64_t reserved_55_63:9; 1371 #endif 1372 } s; 1373 struct cvmx_pip_prt_cfgx_cn30xx { 1374 #ifdef __BIG_ENDIAN_BITFIELD 1375 uint64_t reserved_37_63:27; 1376 uint64_t rawdrp:1; 1377 uint64_t tag_inc:2; 1378 uint64_t dyn_rs:1; 1379 uint64_t inst_hdr:1; 1380 uint64_t grp_wat:4; 1381 uint64_t reserved_27_27:1; 1382 uint64_t qos:3; 1383 uint64_t qos_wat:4; 1384 uint64_t reserved_18_19:2; 1385 uint64_t qos_diff:1; 1386 uint64_t qos_vlan:1; 1387 uint64_t reserved_10_15:6; 1388 uint64_t mode:2; 1389 uint64_t reserved_7_7:1; 1390 uint64_t skip:7; 1391 #else 1392 uint64_t skip:7; 1393 uint64_t reserved_7_7:1; 1394 uint64_t mode:2; 1395 uint64_t reserved_10_15:6; 1396 uint64_t qos_vlan:1; 1397 uint64_t qos_diff:1; 1398 uint64_t reserved_18_19:2; 1399 uint64_t qos_wat:4; 1400 uint64_t qos:3; 1401 uint64_t reserved_27_27:1; 1402 uint64_t grp_wat:4; 1403 uint64_t inst_hdr:1; 1404 uint64_t dyn_rs:1; 1405 uint64_t tag_inc:2; 1406 uint64_t rawdrp:1; 1407 uint64_t reserved_37_63:27; 1408 #endif 1409 } cn30xx; 1410 struct cvmx_pip_prt_cfgx_cn38xx { 1411 #ifdef __BIG_ENDIAN_BITFIELD 1412 uint64_t reserved_37_63:27; 1413 uint64_t rawdrp:1; 1414 uint64_t tag_inc:2; 1415 uint64_t dyn_rs:1; 1416 uint64_t inst_hdr:1; 1417 uint64_t grp_wat:4; 1418 uint64_t reserved_27_27:1; 1419 uint64_t qos:3; 1420 uint64_t qos_wat:4; 1421 uint64_t reserved_18_19:2; 1422 uint64_t qos_diff:1; 1423 uint64_t qos_vlan:1; 1424 uint64_t reserved_13_15:3; 1425 uint64_t crc_en:1; 1426 uint64_t reserved_10_11:2; 1427 uint64_t mode:2; 1428 uint64_t reserved_7_7:1; 1429 uint64_t skip:7; 1430 #else 1431 uint64_t skip:7; 1432 uint64_t reserved_7_7:1; 1433 uint64_t mode:2; 1434 uint64_t reserved_10_11:2; 1435 uint64_t crc_en:1; 1436 uint64_t reserved_13_15:3; 1437 uint64_t qos_vlan:1; 1438 uint64_t qos_diff:1; 1439 uint64_t reserved_18_19:2; 1440 uint64_t qos_wat:4; 1441 uint64_t qos:3; 1442 uint64_t reserved_27_27:1; 1443 uint64_t grp_wat:4; 1444 uint64_t inst_hdr:1; 1445 uint64_t dyn_rs:1; 1446 uint64_t tag_inc:2; 1447 uint64_t rawdrp:1; 1448 uint64_t reserved_37_63:27; 1449 #endif 1450 } cn38xx; 1451 struct cvmx_pip_prt_cfgx_cn50xx { 1452 #ifdef __BIG_ENDIAN_BITFIELD 1453 uint64_t reserved_53_63:11; 1454 uint64_t pad_len:1; 1455 uint64_t vlan_len:1; 1456 uint64_t lenerr_en:1; 1457 uint64_t maxerr_en:1; 1458 uint64_t minerr_en:1; 1459 uint64_t grp_wat_47:4; 1460 uint64_t qos_wat_47:4; 1461 uint64_t reserved_37_39:3; 1462 uint64_t rawdrp:1; 1463 uint64_t tag_inc:2; 1464 uint64_t dyn_rs:1; 1465 uint64_t inst_hdr:1; 1466 uint64_t grp_wat:4; 1467 uint64_t reserved_27_27:1; 1468 uint64_t qos:3; 1469 uint64_t qos_wat:4; 1470 uint64_t reserved_19_19:1; 1471 uint64_t qos_vod:1; 1472 uint64_t qos_diff:1; 1473 uint64_t qos_vlan:1; 1474 uint64_t reserved_13_15:3; 1475 uint64_t crc_en:1; 1476 uint64_t reserved_10_11:2; 1477 uint64_t mode:2; 1478 uint64_t reserved_7_7:1; 1479 uint64_t skip:7; 1480 #else 1481 uint64_t skip:7; 1482 uint64_t reserved_7_7:1; 1483 uint64_t mode:2; 1484 uint64_t reserved_10_11:2; 1485 uint64_t crc_en:1; 1486 uint64_t reserved_13_15:3; 1487 uint64_t qos_vlan:1; 1488 uint64_t qos_diff:1; 1489 uint64_t qos_vod:1; 1490 uint64_t reserved_19_19:1; 1491 uint64_t qos_wat:4; 1492 uint64_t qos:3; 1493 uint64_t reserved_27_27:1; 1494 uint64_t grp_wat:4; 1495 uint64_t inst_hdr:1; 1496 uint64_t dyn_rs:1; 1497 uint64_t tag_inc:2; 1498 uint64_t rawdrp:1; 1499 uint64_t reserved_37_39:3; 1500 uint64_t qos_wat_47:4; 1501 uint64_t grp_wat_47:4; 1502 uint64_t minerr_en:1; 1503 uint64_t maxerr_en:1; 1504 uint64_t lenerr_en:1; 1505 uint64_t vlan_len:1; 1506 uint64_t pad_len:1; 1507 uint64_t reserved_53_63:11; 1508 #endif 1509 } cn50xx; 1510 struct cvmx_pip_prt_cfgx_cn52xx { 1511 #ifdef __BIG_ENDIAN_BITFIELD 1512 uint64_t reserved_53_63:11; 1513 uint64_t pad_len:1; 1514 uint64_t vlan_len:1; 1515 uint64_t lenerr_en:1; 1516 uint64_t maxerr_en:1; 1517 uint64_t minerr_en:1; 1518 uint64_t grp_wat_47:4; 1519 uint64_t qos_wat_47:4; 1520 uint64_t reserved_37_39:3; 1521 uint64_t rawdrp:1; 1522 uint64_t tag_inc:2; 1523 uint64_t dyn_rs:1; 1524 uint64_t inst_hdr:1; 1525 uint64_t grp_wat:4; 1526 uint64_t hg_qos:1; 1527 uint64_t qos:3; 1528 uint64_t qos_wat:4; 1529 uint64_t qos_vsel:1; 1530 uint64_t qos_vod:1; 1531 uint64_t qos_diff:1; 1532 uint64_t qos_vlan:1; 1533 uint64_t reserved_13_15:3; 1534 uint64_t crc_en:1; 1535 uint64_t higig_en:1; 1536 uint64_t dsa_en:1; 1537 uint64_t mode:2; 1538 uint64_t reserved_7_7:1; 1539 uint64_t skip:7; 1540 #else 1541 uint64_t skip:7; 1542 uint64_t reserved_7_7:1; 1543 uint64_t mode:2; 1544 uint64_t dsa_en:1; 1545 uint64_t higig_en:1; 1546 uint64_t crc_en:1; 1547 uint64_t reserved_13_15:3; 1548 uint64_t qos_vlan:1; 1549 uint64_t qos_diff:1; 1550 uint64_t qos_vod:1; 1551 uint64_t qos_vsel:1; 1552 uint64_t qos_wat:4; 1553 uint64_t qos:3; 1554 uint64_t hg_qos:1; 1555 uint64_t grp_wat:4; 1556 uint64_t inst_hdr:1; 1557 uint64_t dyn_rs:1; 1558 uint64_t tag_inc:2; 1559 uint64_t rawdrp:1; 1560 uint64_t reserved_37_39:3; 1561 uint64_t qos_wat_47:4; 1562 uint64_t grp_wat_47:4; 1563 uint64_t minerr_en:1; 1564 uint64_t maxerr_en:1; 1565 uint64_t lenerr_en:1; 1566 uint64_t vlan_len:1; 1567 uint64_t pad_len:1; 1568 uint64_t reserved_53_63:11; 1569 #endif 1570 } cn52xx; 1571 struct cvmx_pip_prt_cfgx_cn58xx { 1572 #ifdef __BIG_ENDIAN_BITFIELD 1573 uint64_t reserved_37_63:27; 1574 uint64_t rawdrp:1; 1575 uint64_t tag_inc:2; 1576 uint64_t dyn_rs:1; 1577 uint64_t inst_hdr:1; 1578 uint64_t grp_wat:4; 1579 uint64_t reserved_27_27:1; 1580 uint64_t qos:3; 1581 uint64_t qos_wat:4; 1582 uint64_t reserved_19_19:1; 1583 uint64_t qos_vod:1; 1584 uint64_t qos_diff:1; 1585 uint64_t qos_vlan:1; 1586 uint64_t reserved_13_15:3; 1587 uint64_t crc_en:1; 1588 uint64_t reserved_10_11:2; 1589 uint64_t mode:2; 1590 uint64_t reserved_7_7:1; 1591 uint64_t skip:7; 1592 #else 1593 uint64_t skip:7; 1594 uint64_t reserved_7_7:1; 1595 uint64_t mode:2; 1596 uint64_t reserved_10_11:2; 1597 uint64_t crc_en:1; 1598 uint64_t reserved_13_15:3; 1599 uint64_t qos_vlan:1; 1600 uint64_t qos_diff:1; 1601 uint64_t qos_vod:1; 1602 uint64_t reserved_19_19:1; 1603 uint64_t qos_wat:4; 1604 uint64_t qos:3; 1605 uint64_t reserved_27_27:1; 1606 uint64_t grp_wat:4; 1607 uint64_t inst_hdr:1; 1608 uint64_t dyn_rs:1; 1609 uint64_t tag_inc:2; 1610 uint64_t rawdrp:1; 1611 uint64_t reserved_37_63:27; 1612 #endif 1613 } cn58xx; 1614 struct cvmx_pip_prt_cfgx_cn68xx { 1615 #ifdef __BIG_ENDIAN_BITFIELD 1616 uint64_t reserved_55_63:9; 1617 uint64_t ih_pri:1; 1618 uint64_t len_chk_sel:1; 1619 uint64_t pad_len:1; 1620 uint64_t vlan_len:1; 1621 uint64_t lenerr_en:1; 1622 uint64_t maxerr_en:1; 1623 uint64_t minerr_en:1; 1624 uint64_t grp_wat_47:4; 1625 uint64_t qos_wat_47:4; 1626 uint64_t reserved_37_39:3; 1627 uint64_t rawdrp:1; 1628 uint64_t tag_inc:2; 1629 uint64_t dyn_rs:1; 1630 uint64_t inst_hdr:1; 1631 uint64_t grp_wat:4; 1632 uint64_t hg_qos:1; 1633 uint64_t qos:3; 1634 uint64_t qos_wat:4; 1635 uint64_t reserved_19_19:1; 1636 uint64_t qos_vod:1; 1637 uint64_t qos_diff:1; 1638 uint64_t qos_vlan:1; 1639 uint64_t reserved_13_15:3; 1640 uint64_t crc_en:1; 1641 uint64_t higig_en:1; 1642 uint64_t dsa_en:1; 1643 uint64_t mode:2; 1644 uint64_t reserved_7_7:1; 1645 uint64_t skip:7; 1646 #else 1647 uint64_t skip:7; 1648 uint64_t reserved_7_7:1; 1649 uint64_t mode:2; 1650 uint64_t dsa_en:1; 1651 uint64_t higig_en:1; 1652 uint64_t crc_en:1; 1653 uint64_t reserved_13_15:3; 1654 uint64_t qos_vlan:1; 1655 uint64_t qos_diff:1; 1656 uint64_t qos_vod:1; 1657 uint64_t reserved_19_19:1; 1658 uint64_t qos_wat:4; 1659 uint64_t qos:3; 1660 uint64_t hg_qos:1; 1661 uint64_t grp_wat:4; 1662 uint64_t inst_hdr:1; 1663 uint64_t dyn_rs:1; 1664 uint64_t tag_inc:2; 1665 uint64_t rawdrp:1; 1666 uint64_t reserved_37_39:3; 1667 uint64_t qos_wat_47:4; 1668 uint64_t grp_wat_47:4; 1669 uint64_t minerr_en:1; 1670 uint64_t maxerr_en:1; 1671 uint64_t lenerr_en:1; 1672 uint64_t vlan_len:1; 1673 uint64_t pad_len:1; 1674 uint64_t len_chk_sel:1; 1675 uint64_t ih_pri:1; 1676 uint64_t reserved_55_63:9; 1677 #endif 1678 } cn68xx; 1679 }; 1680 1681 union cvmx_pip_prt_cfgbx { 1682 uint64_t u64; 1683 struct cvmx_pip_prt_cfgbx_s { 1684 #ifdef __BIG_ENDIAN_BITFIELD 1685 uint64_t reserved_39_63:25; 1686 uint64_t alt_skp_sel:2; 1687 uint64_t alt_skp_en:1; 1688 uint64_t reserved_35_35:1; 1689 uint64_t bsel_num:2; 1690 uint64_t bsel_en:1; 1691 uint64_t reserved_24_31:8; 1692 uint64_t base:8; 1693 uint64_t reserved_6_15:10; 1694 uint64_t bpid:6; 1695 #else 1696 uint64_t bpid:6; 1697 uint64_t reserved_6_15:10; 1698 uint64_t base:8; 1699 uint64_t reserved_24_31:8; 1700 uint64_t bsel_en:1; 1701 uint64_t bsel_num:2; 1702 uint64_t reserved_35_35:1; 1703 uint64_t alt_skp_en:1; 1704 uint64_t alt_skp_sel:2; 1705 uint64_t reserved_39_63:25; 1706 #endif 1707 } s; 1708 struct cvmx_pip_prt_cfgbx_cn61xx { 1709 #ifdef __BIG_ENDIAN_BITFIELD 1710 uint64_t reserved_39_63:25; 1711 uint64_t alt_skp_sel:2; 1712 uint64_t alt_skp_en:1; 1713 uint64_t reserved_35_35:1; 1714 uint64_t bsel_num:2; 1715 uint64_t bsel_en:1; 1716 uint64_t reserved_0_31:32; 1717 #else 1718 uint64_t reserved_0_31:32; 1719 uint64_t bsel_en:1; 1720 uint64_t bsel_num:2; 1721 uint64_t reserved_35_35:1; 1722 uint64_t alt_skp_en:1; 1723 uint64_t alt_skp_sel:2; 1724 uint64_t reserved_39_63:25; 1725 #endif 1726 } cn61xx; 1727 struct cvmx_pip_prt_cfgbx_cn66xx { 1728 #ifdef __BIG_ENDIAN_BITFIELD 1729 uint64_t reserved_39_63:25; 1730 uint64_t alt_skp_sel:2; 1731 uint64_t alt_skp_en:1; 1732 uint64_t reserved_0_35:36; 1733 #else 1734 uint64_t reserved_0_35:36; 1735 uint64_t alt_skp_en:1; 1736 uint64_t alt_skp_sel:2; 1737 uint64_t reserved_39_63:25; 1738 #endif 1739 } cn66xx; 1740 struct cvmx_pip_prt_cfgbx_cn68xxp1 { 1741 #ifdef __BIG_ENDIAN_BITFIELD 1742 uint64_t reserved_24_63:40; 1743 uint64_t base:8; 1744 uint64_t reserved_6_15:10; 1745 uint64_t bpid:6; 1746 #else 1747 uint64_t bpid:6; 1748 uint64_t reserved_6_15:10; 1749 uint64_t base:8; 1750 uint64_t reserved_24_63:40; 1751 #endif 1752 } cn68xxp1; 1753 }; 1754 1755 union cvmx_pip_prt_tagx { 1756 uint64_t u64; 1757 struct cvmx_pip_prt_tagx_s { 1758 #ifdef __BIG_ENDIAN_BITFIELD 1759 uint64_t reserved_54_63:10; 1760 uint64_t portadd_en:1; 1761 uint64_t inc_hwchk:1; 1762 uint64_t reserved_50_51:2; 1763 uint64_t grptagbase_msb:2; 1764 uint64_t reserved_46_47:2; 1765 uint64_t grptagmask_msb:2; 1766 uint64_t reserved_42_43:2; 1767 uint64_t grp_msb:2; 1768 uint64_t grptagbase:4; 1769 uint64_t grptagmask:4; 1770 uint64_t grptag:1; 1771 uint64_t grptag_mskip:1; 1772 uint64_t tag_mode:2; 1773 uint64_t inc_vs:2; 1774 uint64_t inc_vlan:1; 1775 uint64_t inc_prt_flag:1; 1776 uint64_t ip6_dprt_flag:1; 1777 uint64_t ip4_dprt_flag:1; 1778 uint64_t ip6_sprt_flag:1; 1779 uint64_t ip4_sprt_flag:1; 1780 uint64_t ip6_nxth_flag:1; 1781 uint64_t ip4_pctl_flag:1; 1782 uint64_t ip6_dst_flag:1; 1783 uint64_t ip4_dst_flag:1; 1784 uint64_t ip6_src_flag:1; 1785 uint64_t ip4_src_flag:1; 1786 uint64_t tcp6_tag_type:2; 1787 uint64_t tcp4_tag_type:2; 1788 uint64_t ip6_tag_type:2; 1789 uint64_t ip4_tag_type:2; 1790 uint64_t non_tag_type:2; 1791 uint64_t grp:4; 1792 #else 1793 uint64_t grp:4; 1794 uint64_t non_tag_type:2; 1795 uint64_t ip4_tag_type:2; 1796 uint64_t ip6_tag_type:2; 1797 uint64_t tcp4_tag_type:2; 1798 uint64_t tcp6_tag_type:2; 1799 uint64_t ip4_src_flag:1; 1800 uint64_t ip6_src_flag:1; 1801 uint64_t ip4_dst_flag:1; 1802 uint64_t ip6_dst_flag:1; 1803 uint64_t ip4_pctl_flag:1; 1804 uint64_t ip6_nxth_flag:1; 1805 uint64_t ip4_sprt_flag:1; 1806 uint64_t ip6_sprt_flag:1; 1807 uint64_t ip4_dprt_flag:1; 1808 uint64_t ip6_dprt_flag:1; 1809 uint64_t inc_prt_flag:1; 1810 uint64_t inc_vlan:1; 1811 uint64_t inc_vs:2; 1812 uint64_t tag_mode:2; 1813 uint64_t grptag_mskip:1; 1814 uint64_t grptag:1; 1815 uint64_t grptagmask:4; 1816 uint64_t grptagbase:4; 1817 uint64_t grp_msb:2; 1818 uint64_t reserved_42_43:2; 1819 uint64_t grptagmask_msb:2; 1820 uint64_t reserved_46_47:2; 1821 uint64_t grptagbase_msb:2; 1822 uint64_t reserved_50_51:2; 1823 uint64_t inc_hwchk:1; 1824 uint64_t portadd_en:1; 1825 uint64_t reserved_54_63:10; 1826 #endif 1827 } s; 1828 struct cvmx_pip_prt_tagx_cn30xx { 1829 #ifdef __BIG_ENDIAN_BITFIELD 1830 uint64_t reserved_40_63:24; 1831 uint64_t grptagbase:4; 1832 uint64_t grptagmask:4; 1833 uint64_t grptag:1; 1834 uint64_t reserved_30_30:1; 1835 uint64_t tag_mode:2; 1836 uint64_t inc_vs:2; 1837 uint64_t inc_vlan:1; 1838 uint64_t inc_prt_flag:1; 1839 uint64_t ip6_dprt_flag:1; 1840 uint64_t ip4_dprt_flag:1; 1841 uint64_t ip6_sprt_flag:1; 1842 uint64_t ip4_sprt_flag:1; 1843 uint64_t ip6_nxth_flag:1; 1844 uint64_t ip4_pctl_flag:1; 1845 uint64_t ip6_dst_flag:1; 1846 uint64_t ip4_dst_flag:1; 1847 uint64_t ip6_src_flag:1; 1848 uint64_t ip4_src_flag:1; 1849 uint64_t tcp6_tag_type:2; 1850 uint64_t tcp4_tag_type:2; 1851 uint64_t ip6_tag_type:2; 1852 uint64_t ip4_tag_type:2; 1853 uint64_t non_tag_type:2; 1854 uint64_t grp:4; 1855 #else 1856 uint64_t grp:4; 1857 uint64_t non_tag_type:2; 1858 uint64_t ip4_tag_type:2; 1859 uint64_t ip6_tag_type:2; 1860 uint64_t tcp4_tag_type:2; 1861 uint64_t tcp6_tag_type:2; 1862 uint64_t ip4_src_flag:1; 1863 uint64_t ip6_src_flag:1; 1864 uint64_t ip4_dst_flag:1; 1865 uint64_t ip6_dst_flag:1; 1866 uint64_t ip4_pctl_flag:1; 1867 uint64_t ip6_nxth_flag:1; 1868 uint64_t ip4_sprt_flag:1; 1869 uint64_t ip6_sprt_flag:1; 1870 uint64_t ip4_dprt_flag:1; 1871 uint64_t ip6_dprt_flag:1; 1872 uint64_t inc_prt_flag:1; 1873 uint64_t inc_vlan:1; 1874 uint64_t inc_vs:2; 1875 uint64_t tag_mode:2; 1876 uint64_t reserved_30_30:1; 1877 uint64_t grptag:1; 1878 uint64_t grptagmask:4; 1879 uint64_t grptagbase:4; 1880 uint64_t reserved_40_63:24; 1881 #endif 1882 } cn30xx; 1883 struct cvmx_pip_prt_tagx_cn50xx { 1884 #ifdef __BIG_ENDIAN_BITFIELD 1885 uint64_t reserved_40_63:24; 1886 uint64_t grptagbase:4; 1887 uint64_t grptagmask:4; 1888 uint64_t grptag:1; 1889 uint64_t grptag_mskip:1; 1890 uint64_t tag_mode:2; 1891 uint64_t inc_vs:2; 1892 uint64_t inc_vlan:1; 1893 uint64_t inc_prt_flag:1; 1894 uint64_t ip6_dprt_flag:1; 1895 uint64_t ip4_dprt_flag:1; 1896 uint64_t ip6_sprt_flag:1; 1897 uint64_t ip4_sprt_flag:1; 1898 uint64_t ip6_nxth_flag:1; 1899 uint64_t ip4_pctl_flag:1; 1900 uint64_t ip6_dst_flag:1; 1901 uint64_t ip4_dst_flag:1; 1902 uint64_t ip6_src_flag:1; 1903 uint64_t ip4_src_flag:1; 1904 uint64_t tcp6_tag_type:2; 1905 uint64_t tcp4_tag_type:2; 1906 uint64_t ip6_tag_type:2; 1907 uint64_t ip4_tag_type:2; 1908 uint64_t non_tag_type:2; 1909 uint64_t grp:4; 1910 #else 1911 uint64_t grp:4; 1912 uint64_t non_tag_type:2; 1913 uint64_t ip4_tag_type:2; 1914 uint64_t ip6_tag_type:2; 1915 uint64_t tcp4_tag_type:2; 1916 uint64_t tcp6_tag_type:2; 1917 uint64_t ip4_src_flag:1; 1918 uint64_t ip6_src_flag:1; 1919 uint64_t ip4_dst_flag:1; 1920 uint64_t ip6_dst_flag:1; 1921 uint64_t ip4_pctl_flag:1; 1922 uint64_t ip6_nxth_flag:1; 1923 uint64_t ip4_sprt_flag:1; 1924 uint64_t ip6_sprt_flag:1; 1925 uint64_t ip4_dprt_flag:1; 1926 uint64_t ip6_dprt_flag:1; 1927 uint64_t inc_prt_flag:1; 1928 uint64_t inc_vlan:1; 1929 uint64_t inc_vs:2; 1930 uint64_t tag_mode:2; 1931 uint64_t grptag_mskip:1; 1932 uint64_t grptag:1; 1933 uint64_t grptagmask:4; 1934 uint64_t grptagbase:4; 1935 uint64_t reserved_40_63:24; 1936 #endif 1937 } cn50xx; 1938 }; 1939 1940 union cvmx_pip_qos_diffx { 1941 uint64_t u64; 1942 struct cvmx_pip_qos_diffx_s { 1943 #ifdef __BIG_ENDIAN_BITFIELD 1944 uint64_t reserved_3_63:61; 1945 uint64_t qos:3; 1946 #else 1947 uint64_t qos:3; 1948 uint64_t reserved_3_63:61; 1949 #endif 1950 } s; 1951 }; 1952 1953 union cvmx_pip_qos_vlanx { 1954 uint64_t u64; 1955 struct cvmx_pip_qos_vlanx_s { 1956 #ifdef __BIG_ENDIAN_BITFIELD 1957 uint64_t reserved_7_63:57; 1958 uint64_t qos1:3; 1959 uint64_t reserved_3_3:1; 1960 uint64_t qos:3; 1961 #else 1962 uint64_t qos:3; 1963 uint64_t reserved_3_3:1; 1964 uint64_t qos1:3; 1965 uint64_t reserved_7_63:57; 1966 #endif 1967 } s; 1968 struct cvmx_pip_qos_vlanx_cn30xx { 1969 #ifdef __BIG_ENDIAN_BITFIELD 1970 uint64_t reserved_3_63:61; 1971 uint64_t qos:3; 1972 #else 1973 uint64_t qos:3; 1974 uint64_t reserved_3_63:61; 1975 #endif 1976 } cn30xx; 1977 }; 1978 1979 union cvmx_pip_qos_watchx { 1980 uint64_t u64; 1981 struct cvmx_pip_qos_watchx_s { 1982 #ifdef __BIG_ENDIAN_BITFIELD 1983 uint64_t reserved_48_63:16; 1984 uint64_t mask:16; 1985 uint64_t reserved_30_31:2; 1986 uint64_t grp:6; 1987 uint64_t reserved_23_23:1; 1988 uint64_t qos:3; 1989 uint64_t reserved_19_19:1; 1990 uint64_t match_type:3; 1991 uint64_t match_value:16; 1992 #else 1993 uint64_t match_value:16; 1994 uint64_t match_type:3; 1995 uint64_t reserved_19_19:1; 1996 uint64_t qos:3; 1997 uint64_t reserved_23_23:1; 1998 uint64_t grp:6; 1999 uint64_t reserved_30_31:2; 2000 uint64_t mask:16; 2001 uint64_t reserved_48_63:16; 2002 #endif 2003 } s; 2004 struct cvmx_pip_qos_watchx_cn30xx { 2005 #ifdef __BIG_ENDIAN_BITFIELD 2006 uint64_t reserved_48_63:16; 2007 uint64_t mask:16; 2008 uint64_t reserved_28_31:4; 2009 uint64_t grp:4; 2010 uint64_t reserved_23_23:1; 2011 uint64_t qos:3; 2012 uint64_t reserved_18_19:2; 2013 uint64_t match_type:2; 2014 uint64_t match_value:16; 2015 #else 2016 uint64_t match_value:16; 2017 uint64_t match_type:2; 2018 uint64_t reserved_18_19:2; 2019 uint64_t qos:3; 2020 uint64_t reserved_23_23:1; 2021 uint64_t grp:4; 2022 uint64_t reserved_28_31:4; 2023 uint64_t mask:16; 2024 uint64_t reserved_48_63:16; 2025 #endif 2026 } cn30xx; 2027 struct cvmx_pip_qos_watchx_cn50xx { 2028 #ifdef __BIG_ENDIAN_BITFIELD 2029 uint64_t reserved_48_63:16; 2030 uint64_t mask:16; 2031 uint64_t reserved_28_31:4; 2032 uint64_t grp:4; 2033 uint64_t reserved_23_23:1; 2034 uint64_t qos:3; 2035 uint64_t reserved_19_19:1; 2036 uint64_t match_type:3; 2037 uint64_t match_value:16; 2038 #else 2039 uint64_t match_value:16; 2040 uint64_t match_type:3; 2041 uint64_t reserved_19_19:1; 2042 uint64_t qos:3; 2043 uint64_t reserved_23_23:1; 2044 uint64_t grp:4; 2045 uint64_t reserved_28_31:4; 2046 uint64_t mask:16; 2047 uint64_t reserved_48_63:16; 2048 #endif 2049 } cn50xx; 2050 }; 2051 2052 union cvmx_pip_raw_word { 2053 uint64_t u64; 2054 struct cvmx_pip_raw_word_s { 2055 #ifdef __BIG_ENDIAN_BITFIELD 2056 uint64_t reserved_56_63:8; 2057 uint64_t word:56; 2058 #else 2059 uint64_t word:56; 2060 uint64_t reserved_56_63:8; 2061 #endif 2062 } s; 2063 }; 2064 2065 union cvmx_pip_sft_rst { 2066 uint64_t u64; 2067 struct cvmx_pip_sft_rst_s { 2068 #ifdef __BIG_ENDIAN_BITFIELD 2069 uint64_t reserved_1_63:63; 2070 uint64_t rst:1; 2071 #else 2072 uint64_t rst:1; 2073 uint64_t reserved_1_63:63; 2074 #endif 2075 } s; 2076 }; 2077 2078 union cvmx_pip_stat0_x { 2079 uint64_t u64; 2080 struct cvmx_pip_stat0_x_s { 2081 #ifdef __BIG_ENDIAN_BITFIELD 2082 uint64_t drp_pkts:32; 2083 uint64_t drp_octs:32; 2084 #else 2085 uint64_t drp_octs:32; 2086 uint64_t drp_pkts:32; 2087 #endif 2088 } s; 2089 }; 2090 2091 union cvmx_pip_stat0_prtx { 2092 uint64_t u64; 2093 struct cvmx_pip_stat0_prtx_s { 2094 #ifdef __BIG_ENDIAN_BITFIELD 2095 uint64_t drp_pkts:32; 2096 uint64_t drp_octs:32; 2097 #else 2098 uint64_t drp_octs:32; 2099 uint64_t drp_pkts:32; 2100 #endif 2101 } s; 2102 }; 2103 2104 union cvmx_pip_stat10_x { 2105 uint64_t u64; 2106 struct cvmx_pip_stat10_x_s { 2107 #ifdef __BIG_ENDIAN_BITFIELD 2108 uint64_t bcast:32; 2109 uint64_t mcast:32; 2110 #else 2111 uint64_t mcast:32; 2112 uint64_t bcast:32; 2113 #endif 2114 } s; 2115 }; 2116 2117 union cvmx_pip_stat10_prtx { 2118 uint64_t u64; 2119 struct cvmx_pip_stat10_prtx_s { 2120 #ifdef __BIG_ENDIAN_BITFIELD 2121 uint64_t bcast:32; 2122 uint64_t mcast:32; 2123 #else 2124 uint64_t mcast:32; 2125 uint64_t bcast:32; 2126 #endif 2127 } s; 2128 }; 2129 2130 union cvmx_pip_stat11_x { 2131 uint64_t u64; 2132 struct cvmx_pip_stat11_x_s { 2133 #ifdef __BIG_ENDIAN_BITFIELD 2134 uint64_t bcast:32; 2135 uint64_t mcast:32; 2136 #else 2137 uint64_t mcast:32; 2138 uint64_t bcast:32; 2139 #endif 2140 } s; 2141 }; 2142 2143 union cvmx_pip_stat11_prtx { 2144 uint64_t u64; 2145 struct cvmx_pip_stat11_prtx_s { 2146 #ifdef __BIG_ENDIAN_BITFIELD 2147 uint64_t bcast:32; 2148 uint64_t mcast:32; 2149 #else 2150 uint64_t mcast:32; 2151 uint64_t bcast:32; 2152 #endif 2153 } s; 2154 }; 2155 2156 union cvmx_pip_stat1_x { 2157 uint64_t u64; 2158 struct cvmx_pip_stat1_x_s { 2159 #ifdef __BIG_ENDIAN_BITFIELD 2160 uint64_t reserved_48_63:16; 2161 uint64_t octs:48; 2162 #else 2163 uint64_t octs:48; 2164 uint64_t reserved_48_63:16; 2165 #endif 2166 } s; 2167 }; 2168 2169 union cvmx_pip_stat1_prtx { 2170 uint64_t u64; 2171 struct cvmx_pip_stat1_prtx_s { 2172 #ifdef __BIG_ENDIAN_BITFIELD 2173 uint64_t reserved_48_63:16; 2174 uint64_t octs:48; 2175 #else 2176 uint64_t octs:48; 2177 uint64_t reserved_48_63:16; 2178 #endif 2179 } s; 2180 }; 2181 2182 union cvmx_pip_stat2_x { 2183 uint64_t u64; 2184 struct cvmx_pip_stat2_x_s { 2185 #ifdef __BIG_ENDIAN_BITFIELD 2186 uint64_t pkts:32; 2187 uint64_t raw:32; 2188 #else 2189 uint64_t raw:32; 2190 uint64_t pkts:32; 2191 #endif 2192 } s; 2193 }; 2194 2195 union cvmx_pip_stat2_prtx { 2196 uint64_t u64; 2197 struct cvmx_pip_stat2_prtx_s { 2198 #ifdef __BIG_ENDIAN_BITFIELD 2199 uint64_t pkts:32; 2200 uint64_t raw:32; 2201 #else 2202 uint64_t raw:32; 2203 uint64_t pkts:32; 2204 #endif 2205 } s; 2206 }; 2207 2208 union cvmx_pip_stat3_x { 2209 uint64_t u64; 2210 struct cvmx_pip_stat3_x_s { 2211 #ifdef __BIG_ENDIAN_BITFIELD 2212 uint64_t bcst:32; 2213 uint64_t mcst:32; 2214 #else 2215 uint64_t mcst:32; 2216 uint64_t bcst:32; 2217 #endif 2218 } s; 2219 }; 2220 2221 union cvmx_pip_stat3_prtx { 2222 uint64_t u64; 2223 struct cvmx_pip_stat3_prtx_s { 2224 #ifdef __BIG_ENDIAN_BITFIELD 2225 uint64_t bcst:32; 2226 uint64_t mcst:32; 2227 #else 2228 uint64_t mcst:32; 2229 uint64_t bcst:32; 2230 #endif 2231 } s; 2232 }; 2233 2234 union cvmx_pip_stat4_x { 2235 uint64_t u64; 2236 struct cvmx_pip_stat4_x_s { 2237 #ifdef __BIG_ENDIAN_BITFIELD 2238 uint64_t h65to127:32; 2239 uint64_t h64:32; 2240 #else 2241 uint64_t h64:32; 2242 uint64_t h65to127:32; 2243 #endif 2244 } s; 2245 }; 2246 2247 union cvmx_pip_stat4_prtx { 2248 uint64_t u64; 2249 struct cvmx_pip_stat4_prtx_s { 2250 #ifdef __BIG_ENDIAN_BITFIELD 2251 uint64_t h65to127:32; 2252 uint64_t h64:32; 2253 #else 2254 uint64_t h64:32; 2255 uint64_t h65to127:32; 2256 #endif 2257 } s; 2258 }; 2259 2260 union cvmx_pip_stat5_x { 2261 uint64_t u64; 2262 struct cvmx_pip_stat5_x_s { 2263 #ifdef __BIG_ENDIAN_BITFIELD 2264 uint64_t h256to511:32; 2265 uint64_t h128to255:32; 2266 #else 2267 uint64_t h128to255:32; 2268 uint64_t h256to511:32; 2269 #endif 2270 } s; 2271 }; 2272 2273 union cvmx_pip_stat5_prtx { 2274 uint64_t u64; 2275 struct cvmx_pip_stat5_prtx_s { 2276 #ifdef __BIG_ENDIAN_BITFIELD 2277 uint64_t h256to511:32; 2278 uint64_t h128to255:32; 2279 #else 2280 uint64_t h128to255:32; 2281 uint64_t h256to511:32; 2282 #endif 2283 } s; 2284 }; 2285 2286 union cvmx_pip_stat6_x { 2287 uint64_t u64; 2288 struct cvmx_pip_stat6_x_s { 2289 #ifdef __BIG_ENDIAN_BITFIELD 2290 uint64_t h1024to1518:32; 2291 uint64_t h512to1023:32; 2292 #else 2293 uint64_t h512to1023:32; 2294 uint64_t h1024to1518:32; 2295 #endif 2296 } s; 2297 }; 2298 2299 union cvmx_pip_stat6_prtx { 2300 uint64_t u64; 2301 struct cvmx_pip_stat6_prtx_s { 2302 #ifdef __BIG_ENDIAN_BITFIELD 2303 uint64_t h1024to1518:32; 2304 uint64_t h512to1023:32; 2305 #else 2306 uint64_t h512to1023:32; 2307 uint64_t h1024to1518:32; 2308 #endif 2309 } s; 2310 }; 2311 2312 union cvmx_pip_stat7_x { 2313 uint64_t u64; 2314 struct cvmx_pip_stat7_x_s { 2315 #ifdef __BIG_ENDIAN_BITFIELD 2316 uint64_t fcs:32; 2317 uint64_t h1519:32; 2318 #else 2319 uint64_t h1519:32; 2320 uint64_t fcs:32; 2321 #endif 2322 } s; 2323 }; 2324 2325 union cvmx_pip_stat7_prtx { 2326 uint64_t u64; 2327 struct cvmx_pip_stat7_prtx_s { 2328 #ifdef __BIG_ENDIAN_BITFIELD 2329 uint64_t fcs:32; 2330 uint64_t h1519:32; 2331 #else 2332 uint64_t h1519:32; 2333 uint64_t fcs:32; 2334 #endif 2335 } s; 2336 }; 2337 2338 union cvmx_pip_stat8_x { 2339 uint64_t u64; 2340 struct cvmx_pip_stat8_x_s { 2341 #ifdef __BIG_ENDIAN_BITFIELD 2342 uint64_t frag:32; 2343 uint64_t undersz:32; 2344 #else 2345 uint64_t undersz:32; 2346 uint64_t frag:32; 2347 #endif 2348 } s; 2349 }; 2350 2351 union cvmx_pip_stat8_prtx { 2352 uint64_t u64; 2353 struct cvmx_pip_stat8_prtx_s { 2354 #ifdef __BIG_ENDIAN_BITFIELD 2355 uint64_t frag:32; 2356 uint64_t undersz:32; 2357 #else 2358 uint64_t undersz:32; 2359 uint64_t frag:32; 2360 #endif 2361 } s; 2362 }; 2363 2364 union cvmx_pip_stat9_x { 2365 uint64_t u64; 2366 struct cvmx_pip_stat9_x_s { 2367 #ifdef __BIG_ENDIAN_BITFIELD 2368 uint64_t jabber:32; 2369 uint64_t oversz:32; 2370 #else 2371 uint64_t oversz:32; 2372 uint64_t jabber:32; 2373 #endif 2374 } s; 2375 }; 2376 2377 union cvmx_pip_stat9_prtx { 2378 uint64_t u64; 2379 struct cvmx_pip_stat9_prtx_s { 2380 #ifdef __BIG_ENDIAN_BITFIELD 2381 uint64_t jabber:32; 2382 uint64_t oversz:32; 2383 #else 2384 uint64_t oversz:32; 2385 uint64_t jabber:32; 2386 #endif 2387 } s; 2388 }; 2389 2390 union cvmx_pip_stat_ctl { 2391 uint64_t u64; 2392 struct cvmx_pip_stat_ctl_s { 2393 #ifdef __BIG_ENDIAN_BITFIELD 2394 uint64_t reserved_9_63:55; 2395 uint64_t mode:1; 2396 uint64_t reserved_1_7:7; 2397 uint64_t rdclr:1; 2398 #else 2399 uint64_t rdclr:1; 2400 uint64_t reserved_1_7:7; 2401 uint64_t mode:1; 2402 uint64_t reserved_9_63:55; 2403 #endif 2404 } s; 2405 struct cvmx_pip_stat_ctl_cn30xx { 2406 #ifdef __BIG_ENDIAN_BITFIELD 2407 uint64_t reserved_1_63:63; 2408 uint64_t rdclr:1; 2409 #else 2410 uint64_t rdclr:1; 2411 uint64_t reserved_1_63:63; 2412 #endif 2413 } cn30xx; 2414 }; 2415 2416 union cvmx_pip_stat_inb_errsx { 2417 uint64_t u64; 2418 struct cvmx_pip_stat_inb_errsx_s { 2419 #ifdef __BIG_ENDIAN_BITFIELD 2420 uint64_t reserved_16_63:48; 2421 uint64_t errs:16; 2422 #else 2423 uint64_t errs:16; 2424 uint64_t reserved_16_63:48; 2425 #endif 2426 } s; 2427 }; 2428 2429 union cvmx_pip_stat_inb_errs_pkndx { 2430 uint64_t u64; 2431 struct cvmx_pip_stat_inb_errs_pkndx_s { 2432 #ifdef __BIG_ENDIAN_BITFIELD 2433 uint64_t reserved_16_63:48; 2434 uint64_t errs:16; 2435 #else 2436 uint64_t errs:16; 2437 uint64_t reserved_16_63:48; 2438 #endif 2439 } s; 2440 }; 2441 2442 union cvmx_pip_stat_inb_octsx { 2443 uint64_t u64; 2444 struct cvmx_pip_stat_inb_octsx_s { 2445 #ifdef __BIG_ENDIAN_BITFIELD 2446 uint64_t reserved_48_63:16; 2447 uint64_t octs:48; 2448 #else 2449 uint64_t octs:48; 2450 uint64_t reserved_48_63:16; 2451 #endif 2452 } s; 2453 }; 2454 2455 union cvmx_pip_stat_inb_octs_pkndx { 2456 uint64_t u64; 2457 struct cvmx_pip_stat_inb_octs_pkndx_s { 2458 #ifdef __BIG_ENDIAN_BITFIELD 2459 uint64_t reserved_48_63:16; 2460 uint64_t octs:48; 2461 #else 2462 uint64_t octs:48; 2463 uint64_t reserved_48_63:16; 2464 #endif 2465 } s; 2466 }; 2467 2468 union cvmx_pip_stat_inb_pktsx { 2469 uint64_t u64; 2470 struct cvmx_pip_stat_inb_pktsx_s { 2471 #ifdef __BIG_ENDIAN_BITFIELD 2472 uint64_t reserved_32_63:32; 2473 uint64_t pkts:32; 2474 #else 2475 uint64_t pkts:32; 2476 uint64_t reserved_32_63:32; 2477 #endif 2478 } s; 2479 }; 2480 2481 union cvmx_pip_stat_inb_pkts_pkndx { 2482 uint64_t u64; 2483 struct cvmx_pip_stat_inb_pkts_pkndx_s { 2484 #ifdef __BIG_ENDIAN_BITFIELD 2485 uint64_t reserved_32_63:32; 2486 uint64_t pkts:32; 2487 #else 2488 uint64_t pkts:32; 2489 uint64_t reserved_32_63:32; 2490 #endif 2491 } s; 2492 }; 2493 2494 union cvmx_pip_sub_pkind_fcsx { 2495 uint64_t u64; 2496 struct cvmx_pip_sub_pkind_fcsx_s { 2497 #ifdef __BIG_ENDIAN_BITFIELD 2498 uint64_t port_bit:64; 2499 #else 2500 uint64_t port_bit:64; 2501 #endif 2502 } s; 2503 }; 2504 2505 union cvmx_pip_tag_incx { 2506 uint64_t u64; 2507 struct cvmx_pip_tag_incx_s { 2508 #ifdef __BIG_ENDIAN_BITFIELD 2509 uint64_t reserved_8_63:56; 2510 uint64_t en:8; 2511 #else 2512 uint64_t en:8; 2513 uint64_t reserved_8_63:56; 2514 #endif 2515 } s; 2516 }; 2517 2518 union cvmx_pip_tag_mask { 2519 uint64_t u64; 2520 struct cvmx_pip_tag_mask_s { 2521 #ifdef __BIG_ENDIAN_BITFIELD 2522 uint64_t reserved_16_63:48; 2523 uint64_t mask:16; 2524 #else 2525 uint64_t mask:16; 2526 uint64_t reserved_16_63:48; 2527 #endif 2528 } s; 2529 }; 2530 2531 union cvmx_pip_tag_secret { 2532 uint64_t u64; 2533 struct cvmx_pip_tag_secret_s { 2534 #ifdef __BIG_ENDIAN_BITFIELD 2535 uint64_t reserved_32_63:32; 2536 uint64_t dst:16; 2537 uint64_t src:16; 2538 #else 2539 uint64_t src:16; 2540 uint64_t dst:16; 2541 uint64_t reserved_32_63:32; 2542 #endif 2543 } s; 2544 }; 2545 2546 union cvmx_pip_todo_entry { 2547 uint64_t u64; 2548 struct cvmx_pip_todo_entry_s { 2549 #ifdef __BIG_ENDIAN_BITFIELD 2550 uint64_t val:1; 2551 uint64_t reserved_62_62:1; 2552 uint64_t entry:62; 2553 #else 2554 uint64_t entry:62; 2555 uint64_t reserved_62_62:1; 2556 uint64_t val:1; 2557 #endif 2558 } s; 2559 }; 2560 2561 union cvmx_pip_vlan_etypesx { 2562 uint64_t u64; 2563 struct cvmx_pip_vlan_etypesx_s { 2564 #ifdef __BIG_ENDIAN_BITFIELD 2565 uint64_t type3:16; 2566 uint64_t type2:16; 2567 uint64_t type1:16; 2568 uint64_t type0:16; 2569 #else 2570 uint64_t type0:16; 2571 uint64_t type1:16; 2572 uint64_t type2:16; 2573 uint64_t type3:16; 2574 #endif 2575 } s; 2576 }; 2577 2578 union cvmx_pip_xstat0_prtx { 2579 uint64_t u64; 2580 struct cvmx_pip_xstat0_prtx_s { 2581 #ifdef __BIG_ENDIAN_BITFIELD 2582 uint64_t drp_pkts:32; 2583 uint64_t drp_octs:32; 2584 #else 2585 uint64_t drp_octs:32; 2586 uint64_t drp_pkts:32; 2587 #endif 2588 } s; 2589 }; 2590 2591 union cvmx_pip_xstat10_prtx { 2592 uint64_t u64; 2593 struct cvmx_pip_xstat10_prtx_s { 2594 #ifdef __BIG_ENDIAN_BITFIELD 2595 uint64_t bcast:32; 2596 uint64_t mcast:32; 2597 #else 2598 uint64_t mcast:32; 2599 uint64_t bcast:32; 2600 #endif 2601 } s; 2602 }; 2603 2604 union cvmx_pip_xstat11_prtx { 2605 uint64_t u64; 2606 struct cvmx_pip_xstat11_prtx_s { 2607 #ifdef __BIG_ENDIAN_BITFIELD 2608 uint64_t bcast:32; 2609 uint64_t mcast:32; 2610 #else 2611 uint64_t mcast:32; 2612 uint64_t bcast:32; 2613 #endif 2614 } s; 2615 }; 2616 2617 union cvmx_pip_xstat1_prtx { 2618 uint64_t u64; 2619 struct cvmx_pip_xstat1_prtx_s { 2620 #ifdef __BIG_ENDIAN_BITFIELD 2621 uint64_t reserved_48_63:16; 2622 uint64_t octs:48; 2623 #else 2624 uint64_t octs:48; 2625 uint64_t reserved_48_63:16; 2626 #endif 2627 } s; 2628 }; 2629 2630 union cvmx_pip_xstat2_prtx { 2631 uint64_t u64; 2632 struct cvmx_pip_xstat2_prtx_s { 2633 #ifdef __BIG_ENDIAN_BITFIELD 2634 uint64_t pkts:32; 2635 uint64_t raw:32; 2636 #else 2637 uint64_t raw:32; 2638 uint64_t pkts:32; 2639 #endif 2640 } s; 2641 }; 2642 2643 union cvmx_pip_xstat3_prtx { 2644 uint64_t u64; 2645 struct cvmx_pip_xstat3_prtx_s { 2646 #ifdef __BIG_ENDIAN_BITFIELD 2647 uint64_t bcst:32; 2648 uint64_t mcst:32; 2649 #else 2650 uint64_t mcst:32; 2651 uint64_t bcst:32; 2652 #endif 2653 } s; 2654 }; 2655 2656 union cvmx_pip_xstat4_prtx { 2657 uint64_t u64; 2658 struct cvmx_pip_xstat4_prtx_s { 2659 #ifdef __BIG_ENDIAN_BITFIELD 2660 uint64_t h65to127:32; 2661 uint64_t h64:32; 2662 #else 2663 uint64_t h64:32; 2664 uint64_t h65to127:32; 2665 #endif 2666 } s; 2667 }; 2668 2669 union cvmx_pip_xstat5_prtx { 2670 uint64_t u64; 2671 struct cvmx_pip_xstat5_prtx_s { 2672 #ifdef __BIG_ENDIAN_BITFIELD 2673 uint64_t h256to511:32; 2674 uint64_t h128to255:32; 2675 #else 2676 uint64_t h128to255:32; 2677 uint64_t h256to511:32; 2678 #endif 2679 } s; 2680 }; 2681 2682 union cvmx_pip_xstat6_prtx { 2683 uint64_t u64; 2684 struct cvmx_pip_xstat6_prtx_s { 2685 #ifdef __BIG_ENDIAN_BITFIELD 2686 uint64_t h1024to1518:32; 2687 uint64_t h512to1023:32; 2688 #else 2689 uint64_t h512to1023:32; 2690 uint64_t h1024to1518:32; 2691 #endif 2692 } s; 2693 }; 2694 2695 union cvmx_pip_xstat7_prtx { 2696 uint64_t u64; 2697 struct cvmx_pip_xstat7_prtx_s { 2698 #ifdef __BIG_ENDIAN_BITFIELD 2699 uint64_t fcs:32; 2700 uint64_t h1519:32; 2701 #else 2702 uint64_t h1519:32; 2703 uint64_t fcs:32; 2704 #endif 2705 } s; 2706 }; 2707 2708 union cvmx_pip_xstat8_prtx { 2709 uint64_t u64; 2710 struct cvmx_pip_xstat8_prtx_s { 2711 #ifdef __BIG_ENDIAN_BITFIELD 2712 uint64_t frag:32; 2713 uint64_t undersz:32; 2714 #else 2715 uint64_t undersz:32; 2716 uint64_t frag:32; 2717 #endif 2718 } s; 2719 }; 2720 2721 union cvmx_pip_xstat9_prtx { 2722 uint64_t u64; 2723 struct cvmx_pip_xstat9_prtx_s { 2724 #ifdef __BIG_ENDIAN_BITFIELD 2725 uint64_t jabber:32; 2726 uint64_t oversz:32; 2727 #else 2728 uint64_t oversz:32; 2729 uint64_t jabber:32; 2730 #endif 2731 } s; 2732 }; 2733 2734 #endif 2735