1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 * Based on:
7 * Copyright (c) 2011 IDS GmbH, Germany
8 * ids8313.c - ids8313 board support.
9 *
10 * Sergej Stepanov <ste@ids.de>
11 * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
12 */
13
14 #include <common.h>
15 #include <mpc83xx.h>
16 #include <spi.h>
17 #include <linux/libfdt.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20 /** CPLD contains the info about:
21 * - board type: *pCpld & 0xF0
22 * - hw-revision: *pCpld & 0x0F
23 * - cpld-revision: *pCpld+1
24 */
checkboard(void)25 int checkboard(void)
26 {
27 char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
28 u8 u8Vers = readb(pcpld);
29 u8 u8Revs = readb(pcpld + 1);
30
31 printf("Board: ");
32 switch (u8Vers & 0xF0) {
33 case '\x40':
34 printf("CU73X");
35 break;
36 case '\x50':
37 printf("CC73X");
38 break;
39 default:
40 printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
41 return 0;
42 }
43 printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
44 u8Vers & 0x0F, u8Revs & 0xFF);
45 return 0;
46 }
47
48 /*
49 * fixed sdram init
50 */
fixed_sdram(unsigned long config)51 int fixed_sdram(unsigned long config)
52 {
53 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
54 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
55
56 #ifndef CONFIG_SYS_RAMBOOT
57 u32 msize_log2 = __ilog2(msize);
58
59 out_be32(&im->sysconf.ddrlaw[0].bar,
60 (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
61 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
62 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
63 sync();
64
65 /*
66 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
67 * or the DDR2 controller may fail to initialize correctly.
68 */
69 udelay(50000);
70
71 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
72 out_be32(&im->ddr.cs_config[0], config);
73
74 /* currently we use only one CS, so disable the other banks */
75 out_be32(&im->ddr.cs_config[1], 0);
76 out_be32(&im->ddr.cs_config[2], 0);
77 out_be32(&im->ddr.cs_config[3], 0);
78
79 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
80 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
81 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
82 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
83
84 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
85 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
86
87 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
88 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
89
90 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
91 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
92 sync();
93 udelay(300);
94
95 /* enable DDR controller */
96 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
97 /* now check the real size */
98 disable_addr_trans();
99 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
100 enable_addr_trans();
101 #endif
102 return msize;
103 }
104
setup_sdram(void)105 static int setup_sdram(void)
106 {
107 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
108 long int size_01, size_02;
109
110 size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
111 size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
112
113 if (size_01 > size_02)
114 msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
115 else
116 msize = size_02;
117
118 return msize;
119 }
120
dram_init(void)121 int dram_init(void)
122 {
123 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
124 fsl_lbc_t *lbc = &im->im_lbc;
125 u32 msize = 0;
126
127 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
128 return -ENXIO;
129
130 msize = setup_sdram();
131
132 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
133 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
134 sync();
135
136 gd->ram_size = msize;
137
138 return 0;
139 }
140
141 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)142 int ft_board_setup(void *blob, bd_t *bd)
143 {
144 ft_cpu_setup(blob, bd);
145
146 return 0;
147 }
148 #endif
149
150 /* gpio mask for spi_cs */
151 #define IDSCPLD_SPI_CS_MASK 0x00000001
152 /* spi_cs multiplexed through cpld */
153 #define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
154
155 #if defined(CONFIG_MISC_INIT_R)
156 /* srp umcr mask for rts */
157 #define IDSUMCR_RTS_MASK 0x04
misc_init_r(void)158 int misc_init_r(void)
159 {
160 /*srp*/
161 duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
162 duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
163
164 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
165 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
166
167 /* deactivate spi_cs channels */
168 out_8(spi_base, 0);
169 /* deactivate the spi_cs */
170 setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
171 /*srp - deactivate rts*/
172 out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
173 out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
174
175
176 gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
177 return 0;
178 }
179 #endif
180
181 #ifdef CONFIG_MPC8XXX_SPI
182 /*
183 * The following are used to control the SPI chip selects
184 */
spi_cs_is_valid(unsigned int bus,unsigned int cs)185 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
186 {
187 return bus == 0 && ((cs >= 0) && (cs <= 2));
188 }
189
spi_cs_activate(struct spi_slave * slave)190 void spi_cs_activate(struct spi_slave *slave)
191 {
192 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
193 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
194
195 /* select the spi_cs channel */
196 out_8(spi_base, 1 << slave->cs);
197 /* activate the spi_cs */
198 clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
199 }
200
spi_cs_deactivate(struct spi_slave * slave)201 void spi_cs_deactivate(struct spi_slave *slave)
202 {
203 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
204 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
205
206 /* select the spi_cs channel */
207 out_8(spi_base, 1 << slave->cs);
208 /* deactivate the spi_cs */
209 setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
210 }
211 #endif
212