1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 // Jaswinder Singh <jassi.brar@samsung.com>
5
6 #include <linux/bitops.h>
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_data/spi-s3c64xx.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20
21 #define MAX_SPI_PORTS 12
22 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
23 #define AUTOSUSPEND_TIMEOUT 2000
24
25 /* Registers and bit-fields */
26
27 #define S3C64XX_SPI_CH_CFG 0x00
28 #define S3C64XX_SPI_CLK_CFG 0x04
29 #define S3C64XX_SPI_MODE_CFG 0x08
30 #define S3C64XX_SPI_CS_REG 0x0C
31 #define S3C64XX_SPI_INT_EN 0x10
32 #define S3C64XX_SPI_STATUS 0x14
33 #define S3C64XX_SPI_TX_DATA 0x18
34 #define S3C64XX_SPI_RX_DATA 0x1C
35 #define S3C64XX_SPI_PACKET_CNT 0x20
36 #define S3C64XX_SPI_PENDING_CLR 0x24
37 #define S3C64XX_SPI_SWAP_CFG 0x28
38 #define S3C64XX_SPI_FB_CLK 0x2C
39
40 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
41 #define S3C64XX_SPI_CH_SW_RST (1<<5)
42 #define S3C64XX_SPI_CH_SLAVE (1<<4)
43 #define S3C64XX_SPI_CPOL_L (1<<3)
44 #define S3C64XX_SPI_CPHA_B (1<<2)
45 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
46 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
47
48 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
49 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
50 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
51 #define S3C64XX_SPI_PSR_MASK 0xff
52
53 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
54 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
55 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
56 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
57 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
58 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
59 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
60 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
61 #define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11)
62 #define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11
63 #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3)
64 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
65 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
66 #define S3C64XX_SPI_MODE_4BURST (1<<0)
67
68 #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
69 #define S3C64XX_SPI_CS_AUTO (1<<1)
70 #define S3C64XX_SPI_CS_SIG_INACT (1<<0)
71
72 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
73 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
74 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
75 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
76 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
77 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
78 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
79
80 #define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6
81 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
82 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
83 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
84 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
85 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
86 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
87
88 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
89 #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
90
91 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
92 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
93 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
94 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
95 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
96
97 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
98 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
99 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
100 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
101 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
102 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
103 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
104 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
105
106 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
107
108 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
109 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
110 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
111 #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \
112 __ffs((sdd)->tx_fifomask))
113 #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \
114 __ffs((sdd)->rx_fifomask))
115 #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1)
116
117 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
118 #define S3C64XX_SPI_TRAILCNT_OFF 19
119
120 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
121
122 #define S3C64XX_SPI_POLLING_SIZE 32
123
124 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
125 #define is_polling(x) (x->cntrlr_info->polling)
126
127 #define RXBUSY (1<<2)
128 #define TXBUSY (1<<3)
129
130 struct s3c64xx_spi_dma_data {
131 struct dma_chan *ch;
132 dma_cookie_t cookie;
133 enum dma_transfer_direction direction;
134 };
135
136 /**
137 * struct s3c64xx_spi_port_config - SPI Controller hardware info
138 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
139 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
140 * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's
141 * length and position.
142 * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's
143 * length and position.
144 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
145 * @clk_div: Internal clock divider
146 * @quirks: Bitmask of known quirks
147 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
148 * @clk_from_cmu: True, if the controller does not include a clock mux and
149 * prescaler unit.
150 * @clk_ioclk: True if clock is present on this device
151 * @has_loopback: True if loopback mode can be supported
152 *
153 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
154 * differ in some aspects such as the size of the fifo and spi bus clock
155 * setup. Such differences are specified to the driver using this structure
156 * which is provided as driver data to the driver.
157 */
158 struct s3c64xx_spi_port_config {
159 int fifo_lvl_mask[MAX_SPI_PORTS];
160 int rx_lvl_offset;
161 u32 rx_fifomask;
162 u32 tx_fifomask;
163 int tx_st_done;
164 int quirks;
165 int clk_div;
166 bool high_speed;
167 bool clk_from_cmu;
168 bool clk_ioclk;
169 bool has_loopback;
170 };
171
172 /**
173 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
174 * @clk: Pointer to the spi clock.
175 * @src_clk: Pointer to the clock used to generate SPI signals.
176 * @ioclk: Pointer to the i/o clock between host and target
177 * @pdev: Pointer to device's platform device data
178 * @host: Pointer to the SPI Protocol host.
179 * @cntrlr_info: Platform specific data for the controller this driver manages.
180 * @lock: Controller specific lock.
181 * @state: Set of FLAGS to indicate status.
182 * @sfr_start: BUS address of SPI controller regs.
183 * @regs: Pointer to ioremap'ed controller registers.
184 * @xfer_completion: To indicate completion of xfer task.
185 * @cur_mode: Stores the active configuration of the controller.
186 * @cur_bpw: Stores the active bits per word settings.
187 * @cur_speed: Current clock speed
188 * @rx_dma: Local receive DMA data (e.g. chan and direction)
189 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
190 * @port_conf: Local SPI port configuartion data
191 * @port_id: Port identification number
192 * @fifo_depth: depth of the FIFO.
193 * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's
194 * length and position.
195 * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's
196 * length and position.
197 */
198 struct s3c64xx_spi_driver_data {
199 void __iomem *regs;
200 struct clk *clk;
201 struct clk *src_clk;
202 struct clk *ioclk;
203 struct platform_device *pdev;
204 struct spi_controller *host;
205 struct s3c64xx_spi_info *cntrlr_info;
206 spinlock_t lock;
207 unsigned long sfr_start;
208 struct completion xfer_completion;
209 unsigned state;
210 unsigned cur_mode, cur_bpw;
211 unsigned cur_speed;
212 struct s3c64xx_spi_dma_data rx_dma;
213 struct s3c64xx_spi_dma_data tx_dma;
214 const struct s3c64xx_spi_port_config *port_conf;
215 unsigned int port_id;
216 unsigned int fifo_depth;
217 u32 rx_fifomask;
218 u32 tx_fifomask;
219 };
220
s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data * sdd)221 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
222 {
223 void __iomem *regs = sdd->regs;
224 unsigned long loops;
225 u32 val;
226
227 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
228
229 val = readl(regs + S3C64XX_SPI_CH_CFG);
230 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
231 writel(val, regs + S3C64XX_SPI_CH_CFG);
232
233 val = readl(regs + S3C64XX_SPI_CH_CFG);
234 val |= S3C64XX_SPI_CH_SW_RST;
235 val &= ~S3C64XX_SPI_CH_HS_EN;
236 writel(val, regs + S3C64XX_SPI_CH_CFG);
237
238 /* Flush TxFIFO*/
239 loops = msecs_to_loops(1);
240 do {
241 val = readl(regs + S3C64XX_SPI_STATUS);
242 } while (TX_FIFO_LVL(val, sdd) && loops--);
243
244 if (loops == 0)
245 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
246
247 /* Flush RxFIFO*/
248 loops = msecs_to_loops(1);
249 do {
250 val = readl(regs + S3C64XX_SPI_STATUS);
251 if (RX_FIFO_LVL(val, sdd))
252 readl(regs + S3C64XX_SPI_RX_DATA);
253 else
254 break;
255 } while (loops--);
256
257 if (loops == 0)
258 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
259
260 val = readl(regs + S3C64XX_SPI_CH_CFG);
261 val &= ~S3C64XX_SPI_CH_SW_RST;
262 writel(val, regs + S3C64XX_SPI_CH_CFG);
263
264 val = readl(regs + S3C64XX_SPI_MODE_CFG);
265 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
266 writel(val, regs + S3C64XX_SPI_MODE_CFG);
267 }
268
s3c64xx_spi_dmacb(void * data)269 static void s3c64xx_spi_dmacb(void *data)
270 {
271 struct s3c64xx_spi_driver_data *sdd;
272 struct s3c64xx_spi_dma_data *dma = data;
273 unsigned long flags;
274
275 if (dma->direction == DMA_DEV_TO_MEM)
276 sdd = container_of(data,
277 struct s3c64xx_spi_driver_data, rx_dma);
278 else
279 sdd = container_of(data,
280 struct s3c64xx_spi_driver_data, tx_dma);
281
282 spin_lock_irqsave(&sdd->lock, flags);
283
284 if (dma->direction == DMA_DEV_TO_MEM) {
285 sdd->state &= ~RXBUSY;
286 if (!(sdd->state & TXBUSY))
287 complete(&sdd->xfer_completion);
288 } else {
289 sdd->state &= ~TXBUSY;
290 if (!(sdd->state & RXBUSY))
291 complete(&sdd->xfer_completion);
292 }
293
294 spin_unlock_irqrestore(&sdd->lock, flags);
295 }
296
prepare_dma(struct s3c64xx_spi_dma_data * dma,struct sg_table * sgt)297 static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
298 struct sg_table *sgt)
299 {
300 struct s3c64xx_spi_driver_data *sdd;
301 struct dma_slave_config config;
302 struct dma_async_tx_descriptor *desc;
303 int ret;
304
305 memset(&config, 0, sizeof(config));
306
307 if (dma->direction == DMA_DEV_TO_MEM) {
308 sdd = container_of((void *)dma,
309 struct s3c64xx_spi_driver_data, rx_dma);
310 config.direction = dma->direction;
311 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
312 config.src_addr_width = sdd->cur_bpw / 8;
313 config.src_maxburst = 1;
314 dmaengine_slave_config(dma->ch, &config);
315 } else {
316 sdd = container_of((void *)dma,
317 struct s3c64xx_spi_driver_data, tx_dma);
318 config.direction = dma->direction;
319 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
320 config.dst_addr_width = sdd->cur_bpw / 8;
321 config.dst_maxburst = 1;
322 dmaengine_slave_config(dma->ch, &config);
323 }
324
325 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
326 dma->direction, DMA_PREP_INTERRUPT);
327 if (!desc) {
328 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
329 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
330 return -ENOMEM;
331 }
332
333 desc->callback = s3c64xx_spi_dmacb;
334 desc->callback_param = dma;
335
336 dma->cookie = dmaengine_submit(desc);
337 ret = dma_submit_error(dma->cookie);
338 if (ret) {
339 dev_err(&sdd->pdev->dev, "DMA submission failed");
340 return -EIO;
341 }
342
343 dma_async_issue_pending(dma->ch);
344 return 0;
345 }
346
s3c64xx_spi_set_cs(struct spi_device * spi,bool enable)347 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
348 {
349 struct s3c64xx_spi_driver_data *sdd =
350 spi_controller_get_devdata(spi->controller);
351
352 if (sdd->cntrlr_info->no_cs)
353 return;
354
355 if (enable) {
356 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
357 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
358 } else {
359 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
360
361 ssel |= (S3C64XX_SPI_CS_AUTO |
362 S3C64XX_SPI_CS_NSC_CNT_2);
363 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
364 }
365 } else {
366 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
367 writel(S3C64XX_SPI_CS_SIG_INACT,
368 sdd->regs + S3C64XX_SPI_CS_REG);
369 }
370 }
371
s3c64xx_spi_prepare_transfer(struct spi_controller * spi)372 static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi)
373 {
374 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
375
376 if (is_polling(sdd))
377 return 0;
378
379 /* Requests DMA channels */
380 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
381 if (IS_ERR(sdd->rx_dma.ch)) {
382 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
383 sdd->rx_dma.ch = NULL;
384 return 0;
385 }
386
387 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
388 if (IS_ERR(sdd->tx_dma.ch)) {
389 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
390 dma_release_channel(sdd->rx_dma.ch);
391 sdd->tx_dma.ch = NULL;
392 sdd->rx_dma.ch = NULL;
393 return 0;
394 }
395
396 spi->dma_rx = sdd->rx_dma.ch;
397 spi->dma_tx = sdd->tx_dma.ch;
398
399 return 0;
400 }
401
s3c64xx_spi_unprepare_transfer(struct spi_controller * spi)402 static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi)
403 {
404 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
405
406 if (is_polling(sdd))
407 return 0;
408
409 /* Releases DMA channels if they are allocated */
410 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
411 dma_release_channel(sdd->rx_dma.ch);
412 dma_release_channel(sdd->tx_dma.ch);
413 sdd->rx_dma.ch = NULL;
414 sdd->tx_dma.ch = NULL;
415 }
416
417 return 0;
418 }
419
s3c64xx_spi_can_dma(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * xfer)420 static bool s3c64xx_spi_can_dma(struct spi_controller *host,
421 struct spi_device *spi,
422 struct spi_transfer *xfer)
423 {
424 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
425
426 if (sdd->rx_dma.ch && sdd->tx_dma.ch)
427 return xfer->len >= sdd->fifo_depth;
428
429 return false;
430 }
431
s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer,int dma_mode)432 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
433 struct spi_transfer *xfer, int dma_mode)
434 {
435 void __iomem *regs = sdd->regs;
436 u32 modecfg, chcfg;
437 int ret = 0;
438
439 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
440 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
441
442 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
443 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
444
445 if (dma_mode) {
446 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
447 } else {
448 /* Always shift in data in FIFO, even if xfer is Tx only,
449 * this helps setting PCKT_CNT value for generating clocks
450 * as exactly needed.
451 */
452 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
453 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
454 | S3C64XX_SPI_PACKET_CNT_EN,
455 regs + S3C64XX_SPI_PACKET_CNT);
456 }
457
458 if (xfer->tx_buf != NULL) {
459 sdd->state |= TXBUSY;
460 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
461 if (dma_mode) {
462 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
463 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
464 } else {
465 switch (sdd->cur_bpw) {
466 case 32:
467 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
468 xfer->tx_buf, xfer->len / 4);
469 break;
470 case 16:
471 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
472 xfer->tx_buf, xfer->len / 2);
473 break;
474 default:
475 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
476 xfer->tx_buf, xfer->len);
477 break;
478 }
479 }
480 }
481
482 if (xfer->rx_buf != NULL) {
483 sdd->state |= RXBUSY;
484
485 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
486 && !(sdd->cur_mode & SPI_CPHA))
487 chcfg |= S3C64XX_SPI_CH_HS_EN;
488
489 if (dma_mode) {
490 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
491 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
492 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
493 | S3C64XX_SPI_PACKET_CNT_EN,
494 regs + S3C64XX_SPI_PACKET_CNT);
495 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
496 }
497 }
498
499 if (ret)
500 return ret;
501
502 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
503 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
504
505 return 0;
506 }
507
s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data * sdd,int timeout_ms)508 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
509 int timeout_ms)
510 {
511 void __iomem *regs = sdd->regs;
512 unsigned long val = 1;
513 u32 status;
514 u32 max_fifo = sdd->fifo_depth;
515
516 if (timeout_ms)
517 val = msecs_to_loops(timeout_ms);
518
519 do {
520 status = readl(regs + S3C64XX_SPI_STATUS);
521 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
522
523 /* return the actual received data length */
524 return RX_FIFO_LVL(status, sdd);
525 }
526
s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer)527 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
528 struct spi_transfer *xfer)
529 {
530 void __iomem *regs = sdd->regs;
531 unsigned long val;
532 u32 status;
533 int ms;
534
535 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
536 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
537 ms += 30; /* some tolerance */
538 ms = max(ms, 100); /* minimum timeout */
539
540 val = msecs_to_jiffies(ms) + 10;
541 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
542
543 /*
544 * If the previous xfer was completed within timeout, then
545 * proceed further else return -EIO.
546 * DmaTx returns after simply writing data in the FIFO,
547 * w/o waiting for real transmission on the bus to finish.
548 * DmaRx returns only after Dma read data from FIFO which
549 * needs bus transmission to finish, so we don't worry if
550 * Xfer involved Rx(with or without Tx).
551 */
552 if (val && !xfer->rx_buf) {
553 val = msecs_to_loops(10);
554 status = readl(regs + S3C64XX_SPI_STATUS);
555 while ((TX_FIFO_LVL(status, sdd)
556 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
557 && --val) {
558 cpu_relax();
559 status = readl(regs + S3C64XX_SPI_STATUS);
560 }
561
562 }
563
564 /* If timed out while checking rx/tx status return error */
565 if (!val)
566 return -EIO;
567
568 return 0;
569 }
570
s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer,bool use_irq)571 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
572 struct spi_transfer *xfer, bool use_irq)
573 {
574 void __iomem *regs = sdd->regs;
575 unsigned long val;
576 u32 status;
577 int loops;
578 u32 cpy_len;
579 u8 *buf;
580 int ms;
581 unsigned long time_us;
582
583 /* microsecs to xfer 'len' bytes @ 'cur_speed' */
584 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed;
585 ms = (time_us / 1000);
586 ms += 10; /* some tolerance */
587
588 /* sleep during signal transfer time */
589 status = readl(regs + S3C64XX_SPI_STATUS);
590 if (RX_FIFO_LVL(status, sdd) < xfer->len)
591 usleep_range(time_us / 2, time_us);
592
593 if (use_irq) {
594 val = msecs_to_jiffies(ms);
595 if (!wait_for_completion_timeout(&sdd->xfer_completion, val))
596 return -EIO;
597 }
598
599 val = msecs_to_loops(ms);
600 do {
601 status = readl(regs + S3C64XX_SPI_STATUS);
602 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
603
604 if (!val)
605 return -EIO;
606
607 /* If it was only Tx */
608 if (!xfer->rx_buf) {
609 sdd->state &= ~TXBUSY;
610 return 0;
611 }
612
613 /*
614 * If the receive length is bigger than the controller fifo
615 * size, calculate the loops and read the fifo as many times.
616 * loops = length / max fifo size (calculated by using the
617 * fifo mask).
618 * For any size less than the fifo size the below code is
619 * executed atleast once.
620 */
621 loops = xfer->len / sdd->fifo_depth;
622 buf = xfer->rx_buf;
623 do {
624 /* wait for data to be received in the fifo */
625 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
626 (loops ? ms : 0));
627
628 switch (sdd->cur_bpw) {
629 case 32:
630 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
631 buf, cpy_len / 4);
632 break;
633 case 16:
634 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
635 buf, cpy_len / 2);
636 break;
637 default:
638 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
639 buf, cpy_len);
640 break;
641 }
642
643 buf = buf + cpy_len;
644 } while (loops--);
645 sdd->state &= ~RXBUSY;
646
647 return 0;
648 }
649
s3c64xx_spi_config(struct s3c64xx_spi_driver_data * sdd)650 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
651 {
652 void __iomem *regs = sdd->regs;
653 int ret;
654 u32 val;
655 int div = sdd->port_conf->clk_div;
656
657 /* Disable Clock */
658 if (!sdd->port_conf->clk_from_cmu) {
659 val = readl(regs + S3C64XX_SPI_CLK_CFG);
660 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
661 writel(val, regs + S3C64XX_SPI_CLK_CFG);
662 }
663
664 /* Set Polarity and Phase */
665 val = readl(regs + S3C64XX_SPI_CH_CFG);
666 val &= ~(S3C64XX_SPI_CH_SLAVE |
667 S3C64XX_SPI_CPOL_L |
668 S3C64XX_SPI_CPHA_B);
669
670 if (sdd->cur_mode & SPI_CPOL)
671 val |= S3C64XX_SPI_CPOL_L;
672
673 if (sdd->cur_mode & SPI_CPHA)
674 val |= S3C64XX_SPI_CPHA_B;
675
676 writel(val, regs + S3C64XX_SPI_CH_CFG);
677
678 /* Set Channel & DMA Mode */
679 val = readl(regs + S3C64XX_SPI_MODE_CFG);
680 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
681 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
682
683 switch (sdd->cur_bpw) {
684 case 32:
685 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
686 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
687 break;
688 case 16:
689 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
690 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
691 break;
692 default:
693 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
694 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
695 break;
696 }
697
698 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
699 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK;
700 else
701 val &= ~S3C64XX_SPI_MODE_SELF_LOOPBACK;
702
703 writel(val, regs + S3C64XX_SPI_MODE_CFG);
704
705 if (sdd->port_conf->clk_from_cmu) {
706 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
707 if (ret)
708 return ret;
709 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
710 } else {
711 /* Configure Clock */
712 val = readl(regs + S3C64XX_SPI_CLK_CFG);
713 val &= ~S3C64XX_SPI_PSR_MASK;
714 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
715 & S3C64XX_SPI_PSR_MASK);
716 writel(val, regs + S3C64XX_SPI_CLK_CFG);
717
718 /* Enable Clock */
719 val = readl(regs + S3C64XX_SPI_CLK_CFG);
720 val |= S3C64XX_SPI_ENCLK_ENABLE;
721 writel(val, regs + S3C64XX_SPI_CLK_CFG);
722 }
723
724 return 0;
725 }
726
727 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
728
s3c64xx_spi_prepare_message(struct spi_controller * host,struct spi_message * msg)729 static int s3c64xx_spi_prepare_message(struct spi_controller *host,
730 struct spi_message *msg)
731 {
732 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
733 struct spi_device *spi = msg->spi;
734 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
735
736 /* Configure feedback delay */
737 if (!cs)
738 /* No delay if not defined */
739 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
740 else
741 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
742
743 return 0;
744 }
745
s3c64xx_spi_max_transfer_size(struct spi_device * spi)746 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
747 {
748 struct spi_controller *ctlr = spi->controller;
749
750 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
751 }
752
s3c64xx_spi_transfer_one(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * xfer)753 static int s3c64xx_spi_transfer_one(struct spi_controller *host,
754 struct spi_device *spi,
755 struct spi_transfer *xfer)
756 {
757 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
758 const unsigned int fifo_len = sdd->fifo_depth;
759 const void *tx_buf = NULL;
760 void *rx_buf = NULL;
761 int target_len = 0, origin_len = 0;
762 int use_dma = 0;
763 bool use_irq = false;
764 int status;
765 u32 speed;
766 u8 bpw;
767 unsigned long flags;
768 u32 rdy_lv;
769 u32 val;
770
771 reinit_completion(&sdd->xfer_completion);
772
773 /* Only BPW and Speed may change across transfers */
774 bpw = xfer->bits_per_word;
775 speed = xfer->speed_hz;
776
777 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
778 sdd->cur_bpw = bpw;
779 sdd->cur_speed = speed;
780 sdd->cur_mode = spi->mode;
781 status = s3c64xx_spi_config(sdd);
782 if (status)
783 return status;
784 }
785
786 if (!is_polling(sdd) && xfer->len >= fifo_len &&
787 sdd->rx_dma.ch && sdd->tx_dma.ch) {
788 use_dma = 1;
789 } else if (xfer->len >= fifo_len) {
790 tx_buf = xfer->tx_buf;
791 rx_buf = xfer->rx_buf;
792 origin_len = xfer->len;
793 target_len = xfer->len;
794 xfer->len = fifo_len - 1;
795 }
796
797 do {
798 /* transfer size is greater than 32, change to IRQ mode */
799 if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE)
800 use_irq = true;
801
802 if (use_irq) {
803 reinit_completion(&sdd->xfer_completion);
804
805 rdy_lv = xfer->len;
806 /* Setup RDY_FIFO trigger Level
807 * RDY_LVL =
808 * fifo_lvl up to 64 byte -> N bytes
809 * 128 byte -> RDY_LVL * 2 bytes
810 * 256 byte -> RDY_LVL * 4 bytes
811 */
812 if (fifo_len == 128)
813 rdy_lv /= 2;
814 else if (fifo_len == 256)
815 rdy_lv /= 4;
816
817 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG);
818 val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL;
819 val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT);
820 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG);
821
822 /* Enable FIFO_RDY_EN IRQ */
823 val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
824 writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN),
825 sdd->regs + S3C64XX_SPI_INT_EN);
826
827 }
828
829 spin_lock_irqsave(&sdd->lock, flags);
830
831 /* Pending only which is to be done */
832 sdd->state &= ~RXBUSY;
833 sdd->state &= ~TXBUSY;
834
835 /* Start the signals */
836 s3c64xx_spi_set_cs(spi, true);
837
838 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
839
840 spin_unlock_irqrestore(&sdd->lock, flags);
841
842 if (status) {
843 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
844 break;
845 }
846
847 if (use_dma)
848 status = s3c64xx_wait_for_dma(sdd, xfer);
849 else
850 status = s3c64xx_wait_for_pio(sdd, xfer, use_irq);
851
852 if (status) {
853 dev_err(&spi->dev,
854 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
855 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
856 (sdd->state & RXBUSY) ? 'f' : 'p',
857 (sdd->state & TXBUSY) ? 'f' : 'p',
858 xfer->len, use_dma ? 1 : 0, status);
859
860 if (use_dma) {
861 struct dma_tx_state s;
862
863 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
864 dmaengine_pause(sdd->tx_dma.ch);
865 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
866 dmaengine_terminate_all(sdd->tx_dma.ch);
867 dev_err(&spi->dev, "TX residue: %d\n", s.residue);
868
869 }
870 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
871 dmaengine_pause(sdd->rx_dma.ch);
872 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
873 dmaengine_terminate_all(sdd->rx_dma.ch);
874 dev_err(&spi->dev, "RX residue: %d\n", s.residue);
875 }
876 }
877 } else {
878 s3c64xx_flush_fifo(sdd);
879 }
880 if (target_len > 0) {
881 target_len -= xfer->len;
882
883 if (xfer->tx_buf)
884 xfer->tx_buf += xfer->len;
885
886 if (xfer->rx_buf)
887 xfer->rx_buf += xfer->len;
888
889 if (target_len >= fifo_len)
890 xfer->len = fifo_len - 1;
891 else
892 xfer->len = target_len;
893 }
894 } while (target_len > 0);
895
896 if (origin_len) {
897 /* Restore original xfer buffers and length */
898 xfer->tx_buf = tx_buf;
899 xfer->rx_buf = rx_buf;
900 xfer->len = origin_len;
901 }
902
903 return status;
904 }
905
s3c64xx_get_target_ctrldata(struct spi_device * spi)906 static struct s3c64xx_spi_csinfo *s3c64xx_get_target_ctrldata(
907 struct spi_device *spi)
908 {
909 struct s3c64xx_spi_csinfo *cs;
910 struct device_node *target_np, *data_np = NULL;
911 u32 fb_delay = 0;
912
913 target_np = spi->dev.of_node;
914 if (!target_np) {
915 dev_err(&spi->dev, "device node not found\n");
916 return ERR_PTR(-EINVAL);
917 }
918
919 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
920 if (!cs)
921 return ERR_PTR(-ENOMEM);
922
923 data_np = of_get_child_by_name(target_np, "controller-data");
924 if (!data_np) {
925 dev_info(&spi->dev, "feedback delay set to default (0)\n");
926 return cs;
927 }
928
929 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
930 cs->fb_delay = fb_delay;
931 of_node_put(data_np);
932 return cs;
933 }
934
935 /*
936 * Here we only check the validity of requested configuration
937 * and save the configuration in a local data-structure.
938 * The controller is actually configured only just before we
939 * get a message to transfer.
940 */
s3c64xx_spi_setup(struct spi_device * spi)941 static int s3c64xx_spi_setup(struct spi_device *spi)
942 {
943 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
944 struct s3c64xx_spi_driver_data *sdd;
945 int err;
946 int div;
947
948 sdd = spi_controller_get_devdata(spi->controller);
949 if (spi->dev.of_node) {
950 cs = s3c64xx_get_target_ctrldata(spi);
951 spi->controller_data = cs;
952 }
953
954 /* NULL is fine, we just avoid using the FB delay (=0) */
955 if (IS_ERR(cs)) {
956 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0));
957 return -ENODEV;
958 }
959
960 if (!spi_get_ctldata(spi))
961 spi_set_ctldata(spi, cs);
962
963 pm_runtime_get_sync(&sdd->pdev->dev);
964
965 div = sdd->port_conf->clk_div;
966
967 /* Check if we can provide the requested rate */
968 if (!sdd->port_conf->clk_from_cmu) {
969 u32 psr, speed;
970
971 /* Max possible */
972 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
973
974 if (spi->max_speed_hz > speed)
975 spi->max_speed_hz = speed;
976
977 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
978 psr &= S3C64XX_SPI_PSR_MASK;
979 if (psr == S3C64XX_SPI_PSR_MASK)
980 psr--;
981
982 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
983 if (spi->max_speed_hz < speed) {
984 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
985 psr++;
986 } else {
987 err = -EINVAL;
988 goto setup_exit;
989 }
990 }
991
992 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
993 if (spi->max_speed_hz >= speed) {
994 spi->max_speed_hz = speed;
995 } else {
996 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
997 spi->max_speed_hz);
998 err = -EINVAL;
999 goto setup_exit;
1000 }
1001 }
1002
1003 pm_runtime_mark_last_busy(&sdd->pdev->dev);
1004 pm_runtime_put_autosuspend(&sdd->pdev->dev);
1005 s3c64xx_spi_set_cs(spi, false);
1006
1007 return 0;
1008
1009 setup_exit:
1010 pm_runtime_mark_last_busy(&sdd->pdev->dev);
1011 pm_runtime_put_autosuspend(&sdd->pdev->dev);
1012 /* setup() returns with device de-selected */
1013 s3c64xx_spi_set_cs(spi, false);
1014
1015 spi_set_ctldata(spi, NULL);
1016
1017 /* This was dynamically allocated on the DT path */
1018 if (spi->dev.of_node)
1019 kfree(cs);
1020
1021 return err;
1022 }
1023
s3c64xx_spi_cleanup(struct spi_device * spi)1024 static void s3c64xx_spi_cleanup(struct spi_device *spi)
1025 {
1026 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1027
1028 /* This was dynamically allocated on the DT path */
1029 if (spi->dev.of_node)
1030 kfree(cs);
1031
1032 spi_set_ctldata(spi, NULL);
1033 }
1034
s3c64xx_spi_irq(int irq,void * data)1035 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1036 {
1037 struct s3c64xx_spi_driver_data *sdd = data;
1038 struct spi_controller *spi = sdd->host;
1039 unsigned int val, clr = 0;
1040
1041 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1042
1043 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1044 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1045 dev_err(&spi->dev, "RX overrun\n");
1046 }
1047 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1048 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1049 dev_err(&spi->dev, "RX underrun\n");
1050 }
1051 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1052 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1053 dev_err(&spi->dev, "TX overrun\n");
1054 }
1055 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1056 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1057 dev_err(&spi->dev, "TX underrun\n");
1058 }
1059
1060 if (val & S3C64XX_SPI_ST_RX_FIFORDY) {
1061 complete(&sdd->xfer_completion);
1062 /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */
1063 val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
1064 writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN),
1065 sdd->regs + S3C64XX_SPI_INT_EN);
1066 }
1067
1068 /* Clear the pending irq by setting and then clearing it */
1069 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1070 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1071
1072 return IRQ_HANDLED;
1073 }
1074
s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data * sdd)1075 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
1076 {
1077 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1078 void __iomem *regs = sdd->regs;
1079 unsigned int val;
1080
1081 sdd->cur_speed = 0;
1082
1083 if (sci->no_cs)
1084 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
1085 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
1086 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
1087
1088 /* Disable Interrupts - we use Polling if not DMA mode */
1089 writel(0, regs + S3C64XX_SPI_INT_EN);
1090
1091 if (!sdd->port_conf->clk_from_cmu)
1092 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1093 regs + S3C64XX_SPI_CLK_CFG);
1094 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1095 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1096
1097 /* Clear any irq pending bits, should set and clear the bits */
1098 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1099 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1100 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1101 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1102 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1103 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1104
1105 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1106
1107 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1108 val &= ~S3C64XX_SPI_MODE_4BURST;
1109 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1110 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1111 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1112
1113 s3c64xx_flush_fifo(sdd);
1114 }
1115
1116 #ifdef CONFIG_OF
s3c64xx_spi_parse_dt(struct device * dev)1117 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1118 {
1119 struct s3c64xx_spi_info *sci;
1120 u32 temp;
1121
1122 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1123 if (!sci)
1124 return ERR_PTR(-ENOMEM);
1125
1126 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1127 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1128 sci->src_clk_nr = 0;
1129 } else {
1130 sci->src_clk_nr = temp;
1131 }
1132
1133 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1134 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1135 sci->num_cs = 1;
1136 } else {
1137 sci->num_cs = temp;
1138 }
1139
1140 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1141 sci->polling = !of_property_present(dev->of_node, "dmas");
1142
1143 return sci;
1144 }
1145 #else
s3c64xx_spi_parse_dt(struct device * dev)1146 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1147 {
1148 return dev_get_platdata(dev);
1149 }
1150 #endif
1151
s3c64xx_spi_get_port_config(struct platform_device * pdev)1152 static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1153 struct platform_device *pdev)
1154 {
1155 #ifdef CONFIG_OF
1156 if (pdev->dev.of_node)
1157 return of_device_get_match_data(&pdev->dev);
1158 #endif
1159 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1160 }
1161
s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data * sdd)1162 static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd)
1163 {
1164 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf;
1165
1166 if (port_conf->rx_fifomask)
1167 sdd->rx_fifomask = port_conf->rx_fifomask;
1168 else
1169 sdd->rx_fifomask = FIFO_LVL_MASK(sdd) <<
1170 port_conf->rx_lvl_offset;
1171
1172 if (port_conf->tx_fifomask)
1173 sdd->tx_fifomask = port_conf->tx_fifomask;
1174 else
1175 sdd->tx_fifomask = FIFO_LVL_MASK(sdd) <<
1176 S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT;
1177 }
1178
s3c64xx_spi_probe(struct platform_device * pdev)1179 static int s3c64xx_spi_probe(struct platform_device *pdev)
1180 {
1181 struct resource *mem_res;
1182 struct s3c64xx_spi_driver_data *sdd;
1183 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1184 struct spi_controller *host;
1185 int ret, irq;
1186 char clk_name[16];
1187
1188 if (!sci && pdev->dev.of_node) {
1189 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1190 if (IS_ERR(sci))
1191 return PTR_ERR(sci);
1192 }
1193
1194 if (!sci)
1195 return dev_err_probe(&pdev->dev, -ENODEV,
1196 "Platform_data missing!\n");
1197
1198 irq = platform_get_irq(pdev, 0);
1199 if (irq < 0)
1200 return irq;
1201
1202 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd));
1203 if (!host)
1204 return dev_err_probe(&pdev->dev, -ENOMEM,
1205 "Unable to allocate SPI Host\n");
1206
1207 platform_set_drvdata(pdev, host);
1208
1209 sdd = spi_controller_get_devdata(host);
1210 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1211 sdd->host = host;
1212 sdd->cntrlr_info = sci;
1213 sdd->pdev = pdev;
1214 if (pdev->dev.of_node) {
1215 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1216 if (ret < 0)
1217 return dev_err_probe(&pdev->dev, ret,
1218 "Failed to get alias id\n");
1219 sdd->port_id = ret;
1220 } else {
1221 sdd->port_id = pdev->id;
1222 }
1223
1224 sdd->fifo_depth = FIFO_DEPTH(sdd);
1225
1226 s3c64xx_spi_set_fifomask(sdd);
1227
1228 sdd->cur_bpw = 8;
1229
1230 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1231 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1232
1233 host->dev.of_node = pdev->dev.of_node;
1234 host->bus_num = sdd->port_id;
1235 host->setup = s3c64xx_spi_setup;
1236 host->cleanup = s3c64xx_spi_cleanup;
1237 host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1238 host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1239 host->prepare_message = s3c64xx_spi_prepare_message;
1240 host->transfer_one = s3c64xx_spi_transfer_one;
1241 host->max_transfer_size = s3c64xx_spi_max_transfer_size;
1242 host->num_chipselect = sci->num_cs;
1243 host->use_gpio_descriptors = true;
1244 host->dma_alignment = 8;
1245 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1246 SPI_BPW_MASK(8);
1247 /* the spi->mode bits understood by this driver: */
1248 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1249 if (sdd->port_conf->has_loopback)
1250 host->mode_bits |= SPI_LOOP;
1251 host->auto_runtime_pm = true;
1252 if (!is_polling(sdd))
1253 host->can_dma = s3c64xx_spi_can_dma;
1254
1255 sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
1256 if (IS_ERR(sdd->regs))
1257 return PTR_ERR(sdd->regs);
1258 sdd->sfr_start = mem_res->start;
1259
1260 if (sci->cfg_gpio && sci->cfg_gpio())
1261 return dev_err_probe(&pdev->dev, -EBUSY,
1262 "Unable to config gpio\n");
1263
1264 /* Setup clocks */
1265 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi");
1266 if (IS_ERR(sdd->clk))
1267 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk),
1268 "Unable to acquire clock 'spi'\n");
1269
1270 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1271 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name);
1272 if (IS_ERR(sdd->src_clk))
1273 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk),
1274 "Unable to acquire clock '%s'\n",
1275 clk_name);
1276
1277 if (sdd->port_conf->clk_ioclk) {
1278 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk");
1279 if (IS_ERR(sdd->ioclk))
1280 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk),
1281 "Unable to acquire 'ioclk'\n");
1282 }
1283
1284 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1285 pm_runtime_use_autosuspend(&pdev->dev);
1286 pm_runtime_set_active(&pdev->dev);
1287 pm_runtime_enable(&pdev->dev);
1288 pm_runtime_get_sync(&pdev->dev);
1289
1290 /* Setup Deufult Mode */
1291 s3c64xx_spi_hwinit(sdd);
1292
1293 spin_lock_init(&sdd->lock);
1294 init_completion(&sdd->xfer_completion);
1295
1296 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1297 "spi-s3c64xx", sdd);
1298 if (ret != 0) {
1299 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1300 irq, ret);
1301 goto err_pm_put;
1302 }
1303
1304 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1305 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1306 sdd->regs + S3C64XX_SPI_INT_EN);
1307
1308 ret = devm_spi_register_controller(&pdev->dev, host);
1309 if (ret != 0) {
1310 dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret);
1311 goto err_pm_put;
1312 }
1313
1314 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n",
1315 sdd->port_id, host->num_chipselect);
1316 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1317 mem_res, sdd->fifo_depth);
1318
1319 pm_runtime_mark_last_busy(&pdev->dev);
1320 pm_runtime_put_autosuspend(&pdev->dev);
1321
1322 return 0;
1323
1324 err_pm_put:
1325 pm_runtime_put_noidle(&pdev->dev);
1326 pm_runtime_disable(&pdev->dev);
1327 pm_runtime_set_suspended(&pdev->dev);
1328
1329 return ret;
1330 }
1331
s3c64xx_spi_remove(struct platform_device * pdev)1332 static void s3c64xx_spi_remove(struct platform_device *pdev)
1333 {
1334 struct spi_controller *host = platform_get_drvdata(pdev);
1335 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1336
1337 pm_runtime_get_sync(&pdev->dev);
1338
1339 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1340
1341 if (!is_polling(sdd)) {
1342 dma_release_channel(sdd->rx_dma.ch);
1343 dma_release_channel(sdd->tx_dma.ch);
1344 }
1345
1346 pm_runtime_put_noidle(&pdev->dev);
1347 pm_runtime_disable(&pdev->dev);
1348 pm_runtime_set_suspended(&pdev->dev);
1349 }
1350
1351 #ifdef CONFIG_PM_SLEEP
s3c64xx_spi_suspend(struct device * dev)1352 static int s3c64xx_spi_suspend(struct device *dev)
1353 {
1354 struct spi_controller *host = dev_get_drvdata(dev);
1355 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1356
1357 int ret = spi_controller_suspend(host);
1358 if (ret)
1359 return ret;
1360
1361 ret = pm_runtime_force_suspend(dev);
1362 if (ret < 0)
1363 return ret;
1364
1365 sdd->cur_speed = 0; /* Output Clock is stopped */
1366
1367 return 0;
1368 }
1369
s3c64xx_spi_resume(struct device * dev)1370 static int s3c64xx_spi_resume(struct device *dev)
1371 {
1372 struct spi_controller *host = dev_get_drvdata(dev);
1373 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1374 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1375 int ret;
1376
1377 if (sci->cfg_gpio)
1378 sci->cfg_gpio();
1379
1380 ret = pm_runtime_force_resume(dev);
1381 if (ret < 0)
1382 return ret;
1383
1384 return spi_controller_resume(host);
1385 }
1386 #endif /* CONFIG_PM_SLEEP */
1387
1388 #ifdef CONFIG_PM
s3c64xx_spi_runtime_suspend(struct device * dev)1389 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1390 {
1391 struct spi_controller *host = dev_get_drvdata(dev);
1392 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1393
1394 clk_disable_unprepare(sdd->clk);
1395 clk_disable_unprepare(sdd->src_clk);
1396 clk_disable_unprepare(sdd->ioclk);
1397
1398 return 0;
1399 }
1400
s3c64xx_spi_runtime_resume(struct device * dev)1401 static int s3c64xx_spi_runtime_resume(struct device *dev)
1402 {
1403 struct spi_controller *host = dev_get_drvdata(dev);
1404 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1405 int ret;
1406
1407 if (sdd->port_conf->clk_ioclk) {
1408 ret = clk_prepare_enable(sdd->ioclk);
1409 if (ret != 0)
1410 return ret;
1411 }
1412
1413 ret = clk_prepare_enable(sdd->src_clk);
1414 if (ret != 0)
1415 goto err_disable_ioclk;
1416
1417 ret = clk_prepare_enable(sdd->clk);
1418 if (ret != 0)
1419 goto err_disable_src_clk;
1420
1421 s3c64xx_spi_hwinit(sdd);
1422
1423 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1424 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1425 sdd->regs + S3C64XX_SPI_INT_EN);
1426
1427 return 0;
1428
1429 err_disable_src_clk:
1430 clk_disable_unprepare(sdd->src_clk);
1431 err_disable_ioclk:
1432 clk_disable_unprepare(sdd->ioclk);
1433
1434 return ret;
1435 }
1436 #endif /* CONFIG_PM */
1437
1438 static const struct dev_pm_ops s3c64xx_spi_pm = {
1439 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1440 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1441 s3c64xx_spi_runtime_resume, NULL)
1442 };
1443
1444 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1445 .fifo_lvl_mask = { 0x7f },
1446 .rx_lvl_offset = 13,
1447 .tx_st_done = 21,
1448 .clk_div = 2,
1449 .high_speed = true,
1450 };
1451
1452 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1453 .fifo_lvl_mask = { 0x7f, 0x7F },
1454 .rx_lvl_offset = 13,
1455 .tx_st_done = 21,
1456 .clk_div = 2,
1457 };
1458
1459 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1460 .fifo_lvl_mask = { 0x1ff, 0x7F },
1461 .rx_lvl_offset = 15,
1462 .tx_st_done = 25,
1463 .clk_div = 2,
1464 .high_speed = true,
1465 };
1466
1467 static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1468 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1469 .rx_lvl_offset = 15,
1470 .tx_st_done = 25,
1471 .clk_div = 2,
1472 .high_speed = true,
1473 .clk_from_cmu = true,
1474 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1475 };
1476
1477 static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1478 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1479 .rx_lvl_offset = 15,
1480 .tx_st_done = 25,
1481 .clk_div = 2,
1482 .high_speed = true,
1483 .clk_from_cmu = true,
1484 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1485 };
1486
1487 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1488 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1489 .rx_lvl_offset = 15,
1490 .tx_st_done = 25,
1491 .clk_div = 2,
1492 .high_speed = true,
1493 .clk_from_cmu = true,
1494 .clk_ioclk = true,
1495 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1496 };
1497
1498 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
1499 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
1500 0x7f, 0x7f, 0x7f, 0x7f},
1501 .rx_lvl_offset = 15,
1502 .tx_st_done = 25,
1503 .clk_div = 4,
1504 .high_speed = true,
1505 .clk_from_cmu = true,
1506 .clk_ioclk = true,
1507 .has_loopback = true,
1508 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1509 };
1510
1511 static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
1512 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
1513 .rx_lvl_offset = 15,
1514 .tx_st_done = 25,
1515 .clk_div = 2,
1516 .high_speed = true,
1517 .clk_from_cmu = true,
1518 .clk_ioclk = false,
1519 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1520 };
1521
1522 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1523 {
1524 .name = "s3c2443-spi",
1525 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1526 }, {
1527 .name = "s3c6410-spi",
1528 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1529 },
1530 { },
1531 };
1532
1533 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1534 { .compatible = "samsung,s3c2443-spi",
1535 .data = (void *)&s3c2443_spi_port_config,
1536 },
1537 { .compatible = "samsung,s3c6410-spi",
1538 .data = (void *)&s3c6410_spi_port_config,
1539 },
1540 { .compatible = "samsung,s5pv210-spi",
1541 .data = (void *)&s5pv210_spi_port_config,
1542 },
1543 { .compatible = "samsung,exynos4210-spi",
1544 .data = (void *)&exynos4_spi_port_config,
1545 },
1546 { .compatible = "samsung,exynos7-spi",
1547 .data = (void *)&exynos7_spi_port_config,
1548 },
1549 { .compatible = "samsung,exynos5433-spi",
1550 .data = (void *)&exynos5433_spi_port_config,
1551 },
1552 { .compatible = "samsung,exynosautov9-spi",
1553 .data = (void *)&exynosautov9_spi_port_config,
1554 },
1555 { .compatible = "tesla,fsd-spi",
1556 .data = (void *)&fsd_spi_port_config,
1557 },
1558 { },
1559 };
1560 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1561
1562 static struct platform_driver s3c64xx_spi_driver = {
1563 .driver = {
1564 .name = "s3c64xx-spi",
1565 .pm = &s3c64xx_spi_pm,
1566 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1567 },
1568 .probe = s3c64xx_spi_probe,
1569 .remove_new = s3c64xx_spi_remove,
1570 .id_table = s3c64xx_spi_driver_ids,
1571 };
1572 MODULE_ALIAS("platform:s3c64xx-spi");
1573
1574 module_platform_driver(s3c64xx_spi_driver);
1575
1576 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1577 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1578 MODULE_LICENSE("GPL");
1579