1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "system/block-backend.h"
27 #include "hw/block/block.h"
28 #include "hw/block/flash.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
31 #include "hw/ssi/ssi.h"
32 #include "migration/vmstate.h"
33 #include "qemu/bitops.h"
34 #include "qemu/log.h"
35 #include "qemu/module.h"
36 #include "qemu/error-report.h"
37 #include "qapi/error.h"
38 #include "trace.h"
39 #include "qom/object.h"
40 #include "m25p80_sfdp.h"
41
42 /* 16 MiB max in 3 byte address mode */
43 #define MAX_3BYTES_SIZE 0x1000000
44 #define SPI_NOR_MAX_ID_LEN 6
45
46 /* Fields for FlashPartInfo->flags */
47 enum spi_flash_option_flags {
48 ER_4K = BIT(0),
49 ER_32K = BIT(1),
50 EEPROM = BIT(2),
51 HAS_SR_TB = BIT(3),
52 HAS_SR_BP3_BIT6 = BIT(4),
53 };
54
55 typedef struct FlashPartInfo {
56 const char *part_name;
57 /*
58 * This array stores the ID bytes.
59 * The first three bytes are the JEDIC ID.
60 * JEDEC ID zero means "no ID" (mostly older chips).
61 */
62 uint8_t id[SPI_NOR_MAX_ID_LEN];
63 uint8_t id_len;
64 /*
65 * there is confusion between manufacturers as to what a sector is. In this
66 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
67 * command (opcode 0xd8).
68 */
69 uint32_t sector_size;
70 uint32_t n_sectors;
71 uint32_t page_size;
72 uint16_t flags;
73 /*
74 * Big sized spi nor are often stacked devices, thus sometime
75 * replace chip erase with die erase.
76 * This field inform how many die is in the chip.
77 */
78 uint8_t die_cnt;
79 uint8_t (*sfdp_read)(uint32_t sfdp_addr);
80 } FlashPartInfo;
81
82 /* adapted from linux */
83 /* Used when the "_ext_id" is two bytes at most */
84 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
85 .part_name = _part_name,\
86 .id = {\
87 ((_jedec_id) >> 16) & 0xff,\
88 ((_jedec_id) >> 8) & 0xff,\
89 (_jedec_id) & 0xff,\
90 ((_ext_id) >> 8) & 0xff,\
91 (_ext_id) & 0xff,\
92 },\
93 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
94 .sector_size = (_sector_size),\
95 .n_sectors = (_n_sectors),\
96 .page_size = 256,\
97 .flags = (_flags),\
98 .die_cnt = 0
99
100 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
101 .part_name = _part_name,\
102 .id = {\
103 ((_jedec_id) >> 16) & 0xff,\
104 ((_jedec_id) >> 8) & 0xff,\
105 (_jedec_id) & 0xff,\
106 ((_ext_id) >> 16) & 0xff,\
107 ((_ext_id) >> 8) & 0xff,\
108 (_ext_id) & 0xff,\
109 },\
110 .id_len = 6,\
111 .sector_size = (_sector_size),\
112 .n_sectors = (_n_sectors),\
113 .page_size = 256,\
114 .flags = (_flags),\
115 .die_cnt = 0
116
117 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
118 _flags, _die_cnt)\
119 .part_name = _part_name,\
120 .id = {\
121 ((_jedec_id) >> 16) & 0xff,\
122 ((_jedec_id) >> 8) & 0xff,\
123 (_jedec_id) & 0xff,\
124 ((_ext_id) >> 8) & 0xff,\
125 (_ext_id) & 0xff,\
126 },\
127 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
128 .sector_size = (_sector_size),\
129 .n_sectors = (_n_sectors),\
130 .page_size = 256,\
131 .flags = (_flags),\
132 .die_cnt = _die_cnt
133
134 #define JEDEC_NUMONYX 0x20
135 #define JEDEC_WINBOND 0xEF
136 #define JEDEC_SPANSION 0x01
137
138 /* Numonyx (Micron) Configuration register macros */
139 #define VCFG_DUMMY 0x1
140 #define VCFG_WRAP_SEQUENTIAL 0x2
141 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
142 #define NVCFG_XIP_MODE_MASK (7 << 9)
143 #define VCFG_XIP_MODE_DISABLED (1 << 3)
144 #define CFG_DUMMY_CLK_LEN 4
145 #define NVCFG_DUMMY_CLK_POS 12
146 #define VCFG_DUMMY_CLK_POS 4
147 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
148 #define EVCFG_VPP_ACCELERATOR (1 << 3)
149 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
150 #define NVCFG_DUAL_IO_MASK (1 << 2)
151 #define EVCFG_DUAL_IO_DISABLED (1 << 6)
152 #define NVCFG_QUAD_IO_MASK (1 << 3)
153 #define EVCFG_QUAD_IO_DISABLED (1 << 7)
154 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
155 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
156
157 /* Numonyx (Micron) Flag Status Register macros */
158 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
159 #define FSR_FLASH_READY (1 << 7)
160
161 /* Spansion configuration registers macros. */
162 #define SPANSION_QUAD_CFG_POS 0
163 #define SPANSION_QUAD_CFG_LEN 1
164 #define SPANSION_DUMMY_CLK_POS 0
165 #define SPANSION_DUMMY_CLK_LEN 4
166 #define SPANSION_ADDR_LEN_POS 7
167 #define SPANSION_ADDR_LEN_LEN 1
168
169 /*
170 * Spansion read mode command length in bytes,
171 * the mode is currently not supported.
172 */
173
174 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
175 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
176
177 static const FlashPartInfo known_devices[] = {
178 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
179 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
180 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
181
182 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
183 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
184 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
185
186 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
187 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
188 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
189 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
190
191 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
192
193 /*
194 * Atmel EEPROMS - it is assumed, that don't care bit in command
195 * is set to 0. Block protection is not supported.
196 */
197 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
198 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
199
200 /* EON -- en25xxx */
201 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
202 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
203 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
204 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
205 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
206
207 /* GigaDevice */
208 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
209 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
210
211 /* Intel/Numonyx -- xxxs33b */
212 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
213 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
214 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
215 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
216
217 /* ISSI */
218 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
219 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
220 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
221 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
222 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
223 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
224 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) },
225 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
226 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
227 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
228 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K),
229 .sfdp_read = m25p80_sfdp_is25wp256 },
230
231 /* Macronix */
232 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
233 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
234 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
235 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
236 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
237 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
238 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
239 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
240 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512,
241 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
242 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512,
243 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f },
244 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
245 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
246 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
247 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
248 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K),
249 .sfdp_read = m25p80_sfdp_mx66l1g45g },
250
251 /* Micron */
252 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
253 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
254 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
255 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
256 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
257 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
258 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
259 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K),
260 .sfdp_read = m25p80_sfdp_n25q256a },
261 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
262 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
263 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
264 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512,
265 ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB),
266 .sfdp_read = m25p80_sfdp_n25q256a },
267 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
268 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
269 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
270 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
271 ER_4K | ER_32K, 2),
272 .sfdp_read = m25p80_sfdp_mt35xu01g },
273 { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048,
274 ER_4K | ER_32K, 4),
275 .sfdp_read = m25p80_sfdp_mt35xu02g },
276 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
277 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
278 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
279 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
280 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096,
281 ER_4K | ER_32K, 2) },
282 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096,
283 ER_4K | ER_32K, 2) },
284
285 /*
286 * Spansion -- single (large) sector size only, at least
287 * for the chips listed here (without boot sectors).
288 */
289 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
290 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
291 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
292 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
293 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
294 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
295 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
296 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
297 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
298 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
299 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
300 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
301 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
302 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
303 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
304 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
305 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
306
307 /* Spansion -- boot sectors support */
308 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
309 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
310
311 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
312 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
313 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
314 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
315 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
316 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
317 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
318 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
319 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
320 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
321
322 /* ST Microelectronics -- newer production may have feature updates */
323 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
324 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
325 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
326 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
327 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
328 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
329 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
330 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
331 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
332 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
333
334 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
335 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
336 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
337
338 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
339 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
340 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
341
342 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
343 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
344 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
345 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
346
347 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
348 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
349 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
350 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
351 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
352 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
353 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
354 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
355 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
356 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
357 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
358 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
359 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K),
360 .sfdp_read = m25p80_sfdp_w25q80bl },
361 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K),
362 .sfdp_read = m25p80_sfdp_w25q256 },
363 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K),
364 .sfdp_read = m25p80_sfdp_w25q512jv },
365 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K),
366 .sfdp_read = m25p80_sfdp_w25q01jvq },
367 { INFO("w25q02jvm", 0xef7022, 0, 64 << 10, 4096, ER_4K),
368 .sfdp_read = m25p80_sfdp_w25q02jvm },
369
370 /* Microchip */
371 { INFO("25csm04", 0x29cc00, 0x100, 64 << 10, 8, 0) },
372 };
373
374 typedef enum {
375 NOP = 0,
376 WRSR = 0x1,
377 WRDI = 0x4,
378 RDSR = 0x5,
379 WREN = 0x6,
380 BRRD = 0x16,
381 BRWR = 0x17,
382 JEDEC_READ = 0x9f,
383 BULK_ERASE_60 = 0x60,
384 BULK_ERASE = 0xc7,
385 READ_FSR = 0x70,
386 RDCR = 0x15,
387 RDSFDP = 0x5a,
388
389 READ = 0x03,
390 READ4 = 0x13,
391 FAST_READ = 0x0b,
392 FAST_READ4 = 0x0c,
393 DOR = 0x3b,
394 DOR4 = 0x3c,
395 QOR = 0x6b,
396 QOR4 = 0x6c,
397 DIOR = 0xbb,
398 DIOR4 = 0xbc,
399 QIOR = 0xeb,
400 QIOR4 = 0xec,
401
402 PP = 0x02,
403 PP4 = 0x12,
404 PP4_4 = 0x3e,
405 DPP = 0xa2,
406 QPP = 0x32,
407 QPP_4 = 0x34,
408 RDID_90 = 0x90,
409 RDID_AB = 0xab,
410 AAI_WP = 0xad,
411
412 ERASE_4K = 0x20,
413 ERASE4_4K = 0x21,
414 ERASE_32K = 0x52,
415 ERASE4_32K = 0x5c,
416 ERASE_SECTOR = 0xd8,
417 ERASE4_SECTOR = 0xdc,
418
419 EN_4BYTE_ADDR = 0xB7,
420 EX_4BYTE_ADDR = 0xE9,
421
422 EXTEND_ADDR_READ = 0xC8,
423 EXTEND_ADDR_WRITE = 0xC5,
424
425 RESET_ENABLE = 0x66,
426 RESET_MEMORY = 0x99,
427
428 /*
429 * Micron: 0x35 - enable QPI
430 * Spansion: 0x35 - read control register
431 * Winbond: 0x35 - quad enable
432 */
433 RDCR_EQIO = 0x35,
434 RSTQIO = 0xf5,
435
436 /*
437 * Winbond: 0x31 - write status register 2
438 */
439 WRSR2 = 0x31,
440
441 RNVCR = 0xB5,
442 WNVCR = 0xB1,
443
444 RVCR = 0x85,
445 WVCR = 0x81,
446
447 REVCR = 0x65,
448 WEVCR = 0x61,
449
450 DIE_ERASE = 0xC4,
451 } FlashCMD;
452
453 typedef enum {
454 STATE_IDLE,
455 STATE_PAGE_PROGRAM,
456 STATE_READ,
457 STATE_COLLECTING_DATA,
458 STATE_COLLECTING_VAR_LEN_DATA,
459 STATE_READING_DATA,
460 STATE_READING_SFDP,
461 } CMDState;
462
463 typedef enum {
464 MAN_SPANSION,
465 MAN_MACRONIX,
466 MAN_NUMONYX,
467 MAN_WINBOND,
468 MAN_SST,
469 MAN_ISSI,
470 MAN_GENERIC,
471 } Manufacturer;
472
473 typedef enum {
474 MODE_STD = 0,
475 MODE_DIO = 1,
476 MODE_QIO = 2
477 } SPIMode;
478
479 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
480
481 struct Flash {
482 SSIPeripheral parent_obj;
483
484 BlockBackend *blk;
485
486 uint8_t *storage;
487 uint32_t size;
488 int page_size;
489
490 uint8_t state;
491 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
492 uint32_t len;
493 uint32_t pos;
494 bool data_read_loop;
495 uint8_t needed_bytes;
496 uint8_t cmd_in_progress;
497 uint32_t cur_addr;
498 uint32_t nonvolatile_cfg;
499 /* Configuration register for Macronix */
500 uint32_t volatile_cfg;
501 uint32_t enh_volatile_cfg;
502 /* Spansion cfg registers. */
503 uint8_t spansion_cr1nv;
504 uint8_t spansion_cr2nv;
505 uint8_t spansion_cr3nv;
506 uint8_t spansion_cr4nv;
507 uint8_t spansion_cr1v;
508 uint8_t spansion_cr2v;
509 uint8_t spansion_cr3v;
510 uint8_t spansion_cr4v;
511 bool wp_level;
512 bool write_enable;
513 bool four_bytes_address_mode;
514 bool reset_enable;
515 bool quad_enable;
516 bool aai_enable;
517 bool block_protect0;
518 bool block_protect1;
519 bool block_protect2;
520 bool block_protect3;
521 bool top_bottom_bit;
522 bool status_register_write_disabled;
523 uint8_t ear;
524
525 int64_t dirty_page;
526
527 const FlashPartInfo *pi;
528
529 };
530
531 struct M25P80Class {
532 SSIPeripheralClass parent_class;
533 const FlashPartInfo *pi;
534 };
535
OBJECT_DECLARE_TYPE(Flash,M25P80Class,M25P80)536 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
537
538 static inline Manufacturer get_man(Flash *s)
539 {
540 switch (s->pi->id[0]) {
541 case 0x20:
542 return MAN_NUMONYX;
543 case 0xEF:
544 return MAN_WINBOND;
545 case 0x01:
546 return MAN_SPANSION;
547 case 0xC2:
548 return MAN_MACRONIX;
549 case 0xBF:
550 return MAN_SST;
551 case 0x9D:
552 return MAN_ISSI;
553 default:
554 return MAN_GENERIC;
555 }
556 }
557
blk_sync_complete(void * opaque,int ret)558 static void blk_sync_complete(void *opaque, int ret)
559 {
560 QEMUIOVector *iov = opaque;
561
562 qemu_iovec_destroy(iov);
563 g_free(iov);
564
565 /*
566 * do nothing. Masters do not directly interact with the backing store,
567 * only the working copy so no mutexing required.
568 */
569 }
570
flash_sync_page(Flash * s,int page)571 static void flash_sync_page(Flash *s, int page)
572 {
573 QEMUIOVector *iov;
574
575 if (!s->blk || !blk_is_writable(s->blk)) {
576 return;
577 }
578
579 iov = g_new(QEMUIOVector, 1);
580 qemu_iovec_init(iov, 1);
581 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
582 s->pi->page_size);
583 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
584 blk_sync_complete, iov);
585 }
586
flash_sync_area(Flash * s,int64_t off,int64_t len)587 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
588 {
589 QEMUIOVector *iov;
590
591 if (!s->blk || !blk_is_writable(s->blk)) {
592 return;
593 }
594
595 assert(!(len % BDRV_SECTOR_SIZE));
596 iov = g_new(QEMUIOVector, 1);
597 qemu_iovec_init(iov, 1);
598 qemu_iovec_add(iov, s->storage + off, len);
599 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
600 }
601
flash_erase(Flash * s,int offset,FlashCMD cmd)602 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
603 {
604 uint32_t len;
605 uint8_t capa_to_assert = 0;
606
607 switch (cmd) {
608 case ERASE_4K:
609 case ERASE4_4K:
610 len = 4 * KiB;
611 capa_to_assert = ER_4K;
612 break;
613 case ERASE_32K:
614 case ERASE4_32K:
615 len = 32 * KiB;
616 capa_to_assert = ER_32K;
617 break;
618 case ERASE_SECTOR:
619 case ERASE4_SECTOR:
620 len = s->pi->sector_size;
621 break;
622 case BULK_ERASE:
623 len = s->size;
624 break;
625 case DIE_ERASE:
626 if (s->pi->die_cnt) {
627 len = s->size / s->pi->die_cnt;
628 offset = offset & (~(len - 1));
629 } else {
630 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
631 " by device\n");
632 return;
633 }
634 break;
635 default:
636 abort();
637 }
638
639 trace_m25p80_flash_erase(s, offset, len);
640
641 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
642 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
643 " device\n", len);
644 }
645
646 if (!s->write_enable) {
647 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
648 return;
649 }
650 memset(s->storage + offset, 0xff, len);
651 flash_sync_area(s, offset, len);
652 }
653
flash_sync_dirty(Flash * s,int64_t newpage)654 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
655 {
656 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
657 flash_sync_page(s, s->dirty_page);
658 s->dirty_page = newpage;
659 }
660 }
661
662 static inline
flash_write8(Flash * s,uint32_t addr,uint8_t data)663 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
664 {
665 uint32_t page = addr / s->pi->page_size;
666 uint8_t prev = s->storage[s->cur_addr];
667 uint32_t block_protect_value = (s->block_protect3 << 3) |
668 (s->block_protect2 << 2) |
669 (s->block_protect1 << 1) |
670 (s->block_protect0 << 0);
671
672 if (!s->write_enable) {
673 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
674 return;
675 }
676
677 if (block_protect_value > 0) {
678 uint32_t num_protected_sectors = 1 << (block_protect_value - 1);
679 uint32_t sector = addr / s->pi->sector_size;
680
681 /* top_bottom_bit == 0 means TOP */
682 if (!s->top_bottom_bit) {
683 if (s->pi->n_sectors <= sector + num_protected_sectors) {
684 qemu_log_mask(LOG_GUEST_ERROR,
685 "M25P80: write with write protect!\n");
686 return;
687 }
688 } else {
689 if (sector < num_protected_sectors) {
690 qemu_log_mask(LOG_GUEST_ERROR,
691 "M25P80: write with write protect!\n");
692 return;
693 }
694 }
695 }
696
697 if ((prev ^ data) & data) {
698 trace_m25p80_programming_zero_to_one(s, addr, prev, data);
699 }
700
701 if (s->pi->flags & EEPROM) {
702 s->storage[s->cur_addr] = data;
703 } else {
704 s->storage[s->cur_addr] &= data;
705 }
706
707 flash_sync_dirty(s, page);
708 s->dirty_page = page;
709 }
710
get_addr_length(Flash * s)711 static inline int get_addr_length(Flash *s)
712 {
713 /* check if eeprom is in use */
714 if (s->pi->flags == EEPROM) {
715 return 2;
716 }
717
718 switch (s->cmd_in_progress) {
719 case RDSFDP:
720 return 3;
721 case PP4:
722 case PP4_4:
723 case QPP_4:
724 case READ4:
725 case QIOR4:
726 case ERASE4_4K:
727 case ERASE4_32K:
728 case ERASE4_SECTOR:
729 case FAST_READ4:
730 case DOR4:
731 case QOR4:
732 case DIOR4:
733 return 4;
734 default:
735 return s->four_bytes_address_mode ? 4 : 3;
736 }
737 }
738
complete_collecting_data(Flash * s)739 static void complete_collecting_data(Flash *s)
740 {
741 int i, n;
742
743 n = get_addr_length(s);
744 s->cur_addr = (n == 3 ? s->ear : 0);
745 for (i = 0; i < n; ++i) {
746 s->cur_addr <<= 8;
747 s->cur_addr |= s->data[i];
748 }
749
750 s->cur_addr &= s->size - 1;
751
752 s->state = STATE_IDLE;
753
754 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
755 s->cur_addr);
756
757 switch (s->cmd_in_progress) {
758 case DPP:
759 case QPP:
760 case QPP_4:
761 case PP:
762 case PP4:
763 case PP4_4:
764 s->state = STATE_PAGE_PROGRAM;
765 break;
766 case AAI_WP:
767 /* AAI programming starts from the even address */
768 s->cur_addr &= ~BIT(0);
769 s->state = STATE_PAGE_PROGRAM;
770 break;
771 case READ:
772 case READ4:
773 case FAST_READ:
774 case FAST_READ4:
775 case DOR:
776 case DOR4:
777 case QOR:
778 case QOR4:
779 case DIOR:
780 case DIOR4:
781 case QIOR:
782 case QIOR4:
783 s->state = STATE_READ;
784 break;
785 case ERASE_4K:
786 case ERASE4_4K:
787 case ERASE_32K:
788 case ERASE4_32K:
789 case ERASE_SECTOR:
790 case ERASE4_SECTOR:
791 case DIE_ERASE:
792 flash_erase(s, s->cur_addr, s->cmd_in_progress);
793 break;
794 case WRSR:
795 s->status_register_write_disabled = extract32(s->data[0], 7, 1);
796 s->block_protect0 = extract32(s->data[0], 2, 1);
797 s->block_protect1 = extract32(s->data[0], 3, 1);
798 s->block_protect2 = extract32(s->data[0], 4, 1);
799 if (s->pi->flags & HAS_SR_TB) {
800 s->top_bottom_bit = extract32(s->data[0], 5, 1);
801 }
802 if (s->pi->flags & HAS_SR_BP3_BIT6) {
803 s->block_protect3 = extract32(s->data[0], 6, 1);
804 }
805
806 switch (get_man(s)) {
807 case MAN_SPANSION:
808 s->quad_enable = !!(s->data[1] & 0x02);
809 break;
810 case MAN_ISSI:
811 s->quad_enable = extract32(s->data[0], 6, 1);
812 break;
813 case MAN_MACRONIX:
814 s->quad_enable = extract32(s->data[0], 6, 1);
815 if (s->len > 1) {
816 s->volatile_cfg = s->data[1];
817 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
818 }
819 break;
820 case MAN_WINBOND:
821 if (s->len > 1) {
822 s->quad_enable = !!(s->data[1] & 0x02);
823 }
824 break;
825 default:
826 break;
827 }
828 if (s->write_enable) {
829 s->write_enable = false;
830 }
831 break;
832 case WRSR2:
833 switch (get_man(s)) {
834 case MAN_WINBOND:
835 s->quad_enable = !!(s->data[0] & 0x02);
836 break;
837 default:
838 break;
839 }
840 break;
841 case BRWR:
842 case EXTEND_ADDR_WRITE:
843 s->ear = s->data[0];
844 break;
845 case WNVCR:
846 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
847 break;
848 case WVCR:
849 s->volatile_cfg = s->data[0];
850 break;
851 case WEVCR:
852 s->enh_volatile_cfg = s->data[0];
853 break;
854 case RDID_90:
855 case RDID_AB:
856 if (get_man(s) == MAN_SST) {
857 if (s->cur_addr <= 1) {
858 if (s->cur_addr) {
859 s->data[0] = s->pi->id[2];
860 s->data[1] = s->pi->id[0];
861 } else {
862 s->data[0] = s->pi->id[0];
863 s->data[1] = s->pi->id[2];
864 }
865 s->pos = 0;
866 s->len = 2;
867 s->data_read_loop = true;
868 s->state = STATE_READING_DATA;
869 } else {
870 qemu_log_mask(LOG_GUEST_ERROR,
871 "M25P80: Invalid read id address\n");
872 }
873 } else {
874 qemu_log_mask(LOG_GUEST_ERROR,
875 "M25P80: Read id (command 0x90/0xAB) is not supported"
876 " by device\n");
877 }
878 break;
879
880 case RDSFDP:
881 s->state = STATE_READING_SFDP;
882 break;
883
884 default:
885 break;
886 }
887 }
888
reset_memory(Flash * s)889 static void reset_memory(Flash *s)
890 {
891 s->cmd_in_progress = NOP;
892 s->cur_addr = 0;
893 s->ear = 0;
894 s->four_bytes_address_mode = false;
895 s->len = 0;
896 s->needed_bytes = 0;
897 s->pos = 0;
898 s->state = STATE_IDLE;
899 s->write_enable = false;
900 s->reset_enable = false;
901 s->quad_enable = false;
902 s->aai_enable = false;
903
904 switch (get_man(s)) {
905 case MAN_NUMONYX:
906 s->volatile_cfg = 0;
907 s->volatile_cfg |= VCFG_DUMMY;
908 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
909 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
910 == NVCFG_XIP_MODE_DISABLED) {
911 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
912 }
913 s->volatile_cfg |= deposit32(s->volatile_cfg,
914 VCFG_DUMMY_CLK_POS,
915 CFG_DUMMY_CLK_LEN,
916 extract32(s->nonvolatile_cfg,
917 NVCFG_DUMMY_CLK_POS,
918 CFG_DUMMY_CLK_LEN)
919 );
920
921 s->enh_volatile_cfg = 0;
922 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
923 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
924 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
925 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
926 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
927 }
928 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
929 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
930 }
931 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
932 s->four_bytes_address_mode = true;
933 }
934 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
935 s->ear = s->size / MAX_3BYTES_SIZE - 1;
936 }
937 break;
938 case MAN_MACRONIX:
939 s->volatile_cfg = 0x7;
940 break;
941 case MAN_SPANSION:
942 s->spansion_cr1v = s->spansion_cr1nv;
943 s->spansion_cr2v = s->spansion_cr2nv;
944 s->spansion_cr3v = s->spansion_cr3nv;
945 s->spansion_cr4v = s->spansion_cr4nv;
946 s->quad_enable = extract32(s->spansion_cr1v,
947 SPANSION_QUAD_CFG_POS,
948 SPANSION_QUAD_CFG_LEN
949 );
950 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
951 SPANSION_ADDR_LEN_POS,
952 SPANSION_ADDR_LEN_LEN
953 );
954 break;
955 default:
956 break;
957 }
958
959 trace_m25p80_reset_done(s);
960 }
961
numonyx_mode(Flash * s)962 static uint8_t numonyx_mode(Flash *s)
963 {
964 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
965 return MODE_QIO;
966 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
967 return MODE_DIO;
968 } else {
969 return MODE_STD;
970 }
971 }
972
numonyx_extract_cfg_num_dummies(Flash * s)973 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
974 {
975 uint8_t num_dummies;
976 uint8_t mode;
977 assert(get_man(s) == MAN_NUMONYX);
978
979 mode = numonyx_mode(s);
980 num_dummies = extract32(s->volatile_cfg, 4, 4);
981
982 if (num_dummies == 0x0 || num_dummies == 0xf) {
983 switch (s->cmd_in_progress) {
984 case QIOR:
985 case QIOR4:
986 num_dummies = 10;
987 break;
988 default:
989 num_dummies = (mode == MODE_QIO) ? 10 : 8;
990 break;
991 }
992 }
993
994 return num_dummies;
995 }
996
decode_fast_read_cmd(Flash * s)997 static void decode_fast_read_cmd(Flash *s)
998 {
999 s->needed_bytes = get_addr_length(s);
1000 switch (get_man(s)) {
1001 /* Dummy cycles - modeled with bytes writes instead of bits */
1002 case MAN_SST:
1003 s->needed_bytes += 1;
1004 break;
1005 case MAN_WINBOND:
1006 s->needed_bytes += 8;
1007 break;
1008 case MAN_NUMONYX:
1009 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1010 break;
1011 case MAN_MACRONIX:
1012 if (extract32(s->volatile_cfg, 6, 2) == 1) {
1013 s->needed_bytes += 6;
1014 } else {
1015 s->needed_bytes += 8;
1016 }
1017 break;
1018 case MAN_SPANSION:
1019 s->needed_bytes += extract32(s->spansion_cr2v,
1020 SPANSION_DUMMY_CLK_POS,
1021 SPANSION_DUMMY_CLK_LEN
1022 );
1023 break;
1024 case MAN_ISSI:
1025 /*
1026 * The Fast Read instruction code is followed by address bytes and
1027 * dummy cycles, transmitted via the SI line.
1028 *
1029 * The number of dummy cycles is configurable but this is currently
1030 * unmodeled, hence the default value 8 is used.
1031 *
1032 * QPI (Quad Peripheral Interface) mode has different default value
1033 * of dummy cycles, but this is unsupported at the time being.
1034 */
1035 s->needed_bytes += 1;
1036 break;
1037 default:
1038 break;
1039 }
1040 s->pos = 0;
1041 s->len = 0;
1042 s->state = STATE_COLLECTING_DATA;
1043 }
1044
decode_dio_read_cmd(Flash * s)1045 static void decode_dio_read_cmd(Flash *s)
1046 {
1047 s->needed_bytes = get_addr_length(s);
1048 /* Dummy cycles modeled with bytes writes instead of bits */
1049 switch (get_man(s)) {
1050 case MAN_WINBOND:
1051 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
1052 break;
1053 case MAN_SPANSION:
1054 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
1055 s->needed_bytes += extract32(s->spansion_cr2v,
1056 SPANSION_DUMMY_CLK_POS,
1057 SPANSION_DUMMY_CLK_LEN
1058 );
1059 break;
1060 case MAN_NUMONYX:
1061 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1062 break;
1063 case MAN_MACRONIX:
1064 switch (extract32(s->volatile_cfg, 6, 2)) {
1065 case 1:
1066 s->needed_bytes += 6;
1067 break;
1068 case 2:
1069 s->needed_bytes += 8;
1070 break;
1071 default:
1072 s->needed_bytes += 4;
1073 break;
1074 }
1075 break;
1076 case MAN_ISSI:
1077 /*
1078 * The Fast Read Dual I/O instruction code is followed by address bytes
1079 * and dummy cycles, transmitted via the IO1 and IO0 line.
1080 *
1081 * The number of dummy cycles is configurable but this is currently
1082 * unmodeled, hence the default value 4 is used.
1083 */
1084 s->needed_bytes += 1;
1085 break;
1086 default:
1087 break;
1088 }
1089 s->pos = 0;
1090 s->len = 0;
1091 s->state = STATE_COLLECTING_DATA;
1092 }
1093
decode_qio_read_cmd(Flash * s)1094 static void decode_qio_read_cmd(Flash *s)
1095 {
1096 s->needed_bytes = get_addr_length(s);
1097 /* Dummy cycles modeled with bytes writes instead of bits */
1098 switch (get_man(s)) {
1099 case MAN_WINBOND:
1100 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
1101 s->needed_bytes += 4;
1102 break;
1103 case MAN_SPANSION:
1104 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
1105 s->needed_bytes += extract32(s->spansion_cr2v,
1106 SPANSION_DUMMY_CLK_POS,
1107 SPANSION_DUMMY_CLK_LEN
1108 );
1109 break;
1110 case MAN_NUMONYX:
1111 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1112 break;
1113 case MAN_MACRONIX:
1114 switch (extract32(s->volatile_cfg, 6, 2)) {
1115 case 1:
1116 s->needed_bytes += 4;
1117 break;
1118 case 2:
1119 s->needed_bytes += 8;
1120 break;
1121 default:
1122 s->needed_bytes += 6;
1123 break;
1124 }
1125 break;
1126 case MAN_ISSI:
1127 /*
1128 * The Fast Read Quad I/O instruction code is followed by address bytes
1129 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.
1130 *
1131 * The number of dummy cycles is configurable but this is currently
1132 * unmodeled, hence the default value 6 is used.
1133 *
1134 * QPI (Quad Peripheral Interface) mode has different default value
1135 * of dummy cycles, but this is unsupported at the time being.
1136 */
1137 s->needed_bytes += 3;
1138 break;
1139 default:
1140 break;
1141 }
1142 s->pos = 0;
1143 s->len = 0;
1144 s->state = STATE_COLLECTING_DATA;
1145 }
1146
is_valid_aai_cmd(uint32_t cmd)1147 static bool is_valid_aai_cmd(uint32_t cmd)
1148 {
1149 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
1150 }
1151
decode_new_cmd(Flash * s,uint32_t value)1152 static void decode_new_cmd(Flash *s, uint32_t value)
1153 {
1154 int i;
1155
1156 s->cmd_in_progress = value;
1157 trace_m25p80_command_decoded(s, value);
1158
1159 if (value != RESET_MEMORY) {
1160 s->reset_enable = false;
1161 }
1162
1163 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
1164 qemu_log_mask(LOG_GUEST_ERROR,
1165 "M25P80: Invalid cmd within AAI programming sequence");
1166 }
1167
1168 switch (value) {
1169
1170 case ERASE_4K:
1171 case ERASE4_4K:
1172 case ERASE_32K:
1173 case ERASE4_32K:
1174 case ERASE_SECTOR:
1175 case ERASE4_SECTOR:
1176 case PP:
1177 case PP4:
1178 case DIE_ERASE:
1179 case RDID_90:
1180 case RDID_AB:
1181 s->needed_bytes = get_addr_length(s);
1182 s->pos = 0;
1183 s->len = 0;
1184 s->state = STATE_COLLECTING_DATA;
1185 break;
1186 case READ:
1187 case READ4:
1188 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1189 s->needed_bytes = get_addr_length(s);
1190 s->pos = 0;
1191 s->len = 0;
1192 s->state = STATE_COLLECTING_DATA;
1193 } else {
1194 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1195 "DIO or QIO mode\n", s->cmd_in_progress);
1196 }
1197 break;
1198 case DPP:
1199 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1200 s->needed_bytes = get_addr_length(s);
1201 s->pos = 0;
1202 s->len = 0;
1203 s->state = STATE_COLLECTING_DATA;
1204 } else {
1205 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1206 "QIO mode\n", s->cmd_in_progress);
1207 }
1208 break;
1209 case QPP:
1210 case QPP_4:
1211 case PP4_4:
1212 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1213 s->needed_bytes = get_addr_length(s);
1214 s->pos = 0;
1215 s->len = 0;
1216 s->state = STATE_COLLECTING_DATA;
1217 } else {
1218 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1219 "DIO mode\n", s->cmd_in_progress);
1220 }
1221 break;
1222
1223 case FAST_READ:
1224 case FAST_READ4:
1225 decode_fast_read_cmd(s);
1226 break;
1227 case DOR:
1228 case DOR4:
1229 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1230 decode_fast_read_cmd(s);
1231 } else {
1232 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1233 "QIO mode\n", s->cmd_in_progress);
1234 }
1235 break;
1236 case QOR:
1237 case QOR4:
1238 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1239 decode_fast_read_cmd(s);
1240 } else {
1241 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1242 "DIO mode\n", s->cmd_in_progress);
1243 }
1244 break;
1245
1246 case DIOR:
1247 case DIOR4:
1248 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1249 decode_dio_read_cmd(s);
1250 } else {
1251 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1252 "QIO mode\n", s->cmd_in_progress);
1253 }
1254 break;
1255
1256 case QIOR:
1257 case QIOR4:
1258 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1259 decode_qio_read_cmd(s);
1260 } else {
1261 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1262 "DIO mode\n", s->cmd_in_progress);
1263 }
1264 break;
1265
1266 case WRSR:
1267 /*
1268 * If WP# is low and status_register_write_disabled is high,
1269 * status register writes are disabled.
1270 * This is also called "hardware protected mode" (HPM). All other
1271 * combinations of the two states are called "software protected mode"
1272 * (SPM), and status register writes are permitted.
1273 */
1274 if ((s->wp_level == 0 && s->status_register_write_disabled)
1275 || !s->write_enable) {
1276 qemu_log_mask(LOG_GUEST_ERROR,
1277 "M25P80: Status register write is disabled!\n");
1278 break;
1279 }
1280
1281 switch (get_man(s)) {
1282 case MAN_SPANSION:
1283 s->needed_bytes = 2;
1284 s->state = STATE_COLLECTING_DATA;
1285 break;
1286 case MAN_MACRONIX:
1287 s->needed_bytes = 2;
1288 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1289 break;
1290 case MAN_WINBOND:
1291 s->needed_bytes = 2;
1292 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1293 break;
1294 default:
1295 s->needed_bytes = 1;
1296 s->state = STATE_COLLECTING_DATA;
1297 }
1298 s->pos = 0;
1299 break;
1300 case WRSR2:
1301 /*
1302 * If WP# is low and status_register_write_disabled is high,
1303 * status register writes are disabled.
1304 * This is also called "hardware protected mode" (HPM). All other
1305 * combinations of the two states are called "software protected mode"
1306 * (SPM), and status register writes are permitted.
1307 */
1308 if ((s->wp_level == 0 && s->status_register_write_disabled)
1309 || !s->write_enable) {
1310 qemu_log_mask(LOG_GUEST_ERROR,
1311 "M25P80: Status register 2 write is disabled!\n");
1312 break;
1313 }
1314
1315 switch (get_man(s)) {
1316 case MAN_WINBOND:
1317 s->needed_bytes = 1;
1318 s->state = STATE_COLLECTING_DATA;
1319 s->pos = 0;
1320 break;
1321 default:
1322 break;
1323 }
1324 break;
1325 case WRDI:
1326 s->write_enable = false;
1327 if (get_man(s) == MAN_SST) {
1328 s->aai_enable = false;
1329 }
1330 break;
1331 case WREN:
1332 s->write_enable = true;
1333 break;
1334
1335 case RDSR:
1336 s->data[0] = (!!s->write_enable) << 1;
1337 s->data[0] |= (!!s->status_register_write_disabled) << 7;
1338 s->data[0] |= (!!s->block_protect0) << 2;
1339 s->data[0] |= (!!s->block_protect1) << 3;
1340 s->data[0] |= (!!s->block_protect2) << 4;
1341 if (s->pi->flags & HAS_SR_TB) {
1342 s->data[0] |= (!!s->top_bottom_bit) << 5;
1343 }
1344 if (s->pi->flags & HAS_SR_BP3_BIT6) {
1345 s->data[0] |= (!!s->block_protect3) << 6;
1346 }
1347
1348 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
1349 s->data[0] |= (!!s->quad_enable) << 6;
1350 }
1351 if (get_man(s) == MAN_SST) {
1352 s->data[0] |= (!!s->aai_enable) << 6;
1353 }
1354
1355 s->pos = 0;
1356 s->len = 1;
1357 s->data_read_loop = true;
1358 s->state = STATE_READING_DATA;
1359 break;
1360
1361 case READ_FSR:
1362 s->data[0] = FSR_FLASH_READY;
1363 if (s->four_bytes_address_mode) {
1364 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1365 }
1366 s->pos = 0;
1367 s->len = 1;
1368 s->data_read_loop = true;
1369 s->state = STATE_READING_DATA;
1370 break;
1371
1372 case JEDEC_READ:
1373 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1374 trace_m25p80_populated_jedec(s);
1375 for (i = 0; i < s->pi->id_len; i++) {
1376 s->data[i] = s->pi->id[i];
1377 }
1378 for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1379 s->data[i] = 0;
1380 }
1381
1382 s->len = SPI_NOR_MAX_ID_LEN;
1383 s->pos = 0;
1384 s->state = STATE_READING_DATA;
1385 } else {
1386 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
1387 "in DIO or QIO mode\n");
1388 }
1389 break;
1390
1391 case RDCR:
1392 s->data[0] = s->volatile_cfg & 0xFF;
1393 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1394 s->pos = 0;
1395 s->len = 1;
1396 s->state = STATE_READING_DATA;
1397 break;
1398
1399 case BULK_ERASE_60:
1400 case BULK_ERASE:
1401 if (s->write_enable) {
1402 trace_m25p80_chip_erase(s);
1403 flash_erase(s, 0, BULK_ERASE);
1404 } else {
1405 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1406 "protect!\n");
1407 }
1408 break;
1409 case NOP:
1410 break;
1411 case EN_4BYTE_ADDR:
1412 s->four_bytes_address_mode = true;
1413 break;
1414 case EX_4BYTE_ADDR:
1415 s->four_bytes_address_mode = false;
1416 break;
1417 case BRRD:
1418 case EXTEND_ADDR_READ:
1419 s->data[0] = s->ear;
1420 s->pos = 0;
1421 s->len = 1;
1422 s->state = STATE_READING_DATA;
1423 break;
1424 case BRWR:
1425 case EXTEND_ADDR_WRITE:
1426 if (s->write_enable) {
1427 s->needed_bytes = 1;
1428 s->pos = 0;
1429 s->len = 0;
1430 s->state = STATE_COLLECTING_DATA;
1431 }
1432 break;
1433 case RNVCR:
1434 s->data[0] = s->nonvolatile_cfg & 0xFF;
1435 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1436 s->pos = 0;
1437 s->len = 2;
1438 s->state = STATE_READING_DATA;
1439 break;
1440 case WNVCR:
1441 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1442 s->needed_bytes = 2;
1443 s->pos = 0;
1444 s->len = 0;
1445 s->state = STATE_COLLECTING_DATA;
1446 }
1447 break;
1448 case RVCR:
1449 s->data[0] = s->volatile_cfg & 0xFF;
1450 s->pos = 0;
1451 s->len = 1;
1452 s->state = STATE_READING_DATA;
1453 break;
1454 case WVCR:
1455 if (s->write_enable) {
1456 s->needed_bytes = 1;
1457 s->pos = 0;
1458 s->len = 0;
1459 s->state = STATE_COLLECTING_DATA;
1460 }
1461 break;
1462 case REVCR:
1463 s->data[0] = s->enh_volatile_cfg & 0xFF;
1464 s->pos = 0;
1465 s->len = 1;
1466 s->state = STATE_READING_DATA;
1467 break;
1468 case WEVCR:
1469 if (s->write_enable) {
1470 s->needed_bytes = 1;
1471 s->pos = 0;
1472 s->len = 0;
1473 s->state = STATE_COLLECTING_DATA;
1474 }
1475 break;
1476 case RESET_ENABLE:
1477 s->reset_enable = true;
1478 break;
1479 case RESET_MEMORY:
1480 if (s->reset_enable) {
1481 reset_memory(s);
1482 }
1483 break;
1484 case RDCR_EQIO:
1485 switch (get_man(s)) {
1486 case MAN_SPANSION:
1487 s->data[0] = (!!s->quad_enable) << 1;
1488 s->pos = 0;
1489 s->len = 1;
1490 s->state = STATE_READING_DATA;
1491 break;
1492 case MAN_MACRONIX:
1493 s->quad_enable = true;
1494 break;
1495 case MAN_WINBOND:
1496 s->data[0] = (!!s->quad_enable) << 1;
1497 s->pos = 0;
1498 s->len = 1;
1499 s->state = STATE_READING_DATA;
1500 break;
1501 default:
1502 break;
1503 }
1504 break;
1505 case RSTQIO:
1506 s->quad_enable = false;
1507 break;
1508 case AAI_WP:
1509 if (get_man(s) == MAN_SST) {
1510 if (s->write_enable) {
1511 if (s->aai_enable) {
1512 s->state = STATE_PAGE_PROGRAM;
1513 } else {
1514 s->aai_enable = true;
1515 s->needed_bytes = get_addr_length(s);
1516 s->state = STATE_COLLECTING_DATA;
1517 }
1518 } else {
1519 qemu_log_mask(LOG_GUEST_ERROR,
1520 "M25P80: AAI_WP with write protect\n");
1521 }
1522 } else {
1523 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1524 }
1525 break;
1526 case RDSFDP:
1527 if (s->pi->sfdp_read) {
1528 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */
1529 s->pos = 0;
1530 s->len = 0;
1531 s->state = STATE_COLLECTING_DATA;
1532 break;
1533 }
1534 /* Fallthrough */
1535
1536 default:
1537 s->pos = 0;
1538 s->len = 1;
1539 s->state = STATE_READING_DATA;
1540 s->data_read_loop = true;
1541 s->data[0] = 0;
1542 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1543 break;
1544 }
1545 }
1546
m25p80_cs(SSIPeripheral * ss,bool select)1547 static int m25p80_cs(SSIPeripheral *ss, bool select)
1548 {
1549 Flash *s = M25P80(ss);
1550
1551 if (select) {
1552 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1553 complete_collecting_data(s);
1554 }
1555 s->len = 0;
1556 s->pos = 0;
1557 s->state = STATE_IDLE;
1558 flash_sync_dirty(s, -1);
1559 s->data_read_loop = false;
1560 }
1561
1562 trace_m25p80_select(s, select ? "de" : "");
1563
1564 return 0;
1565 }
1566
m25p80_transfer8(SSIPeripheral * ss,uint32_t tx)1567 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
1568 {
1569 Flash *s = M25P80(ss);
1570 uint32_t r = 0;
1571
1572 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1573 s->cur_addr, (uint8_t)tx);
1574
1575 switch (s->state) {
1576
1577 case STATE_PAGE_PROGRAM:
1578 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1579 flash_write8(s, s->cur_addr, (uint8_t)tx);
1580 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1581
1582 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
1583 /*
1584 * There is no wrap mode during AAI programming once the highest
1585 * unprotected memory address is reached. The Write-Enable-Latch
1586 * bit is automatically reset, and AAI programming mode aborts.
1587 */
1588 s->write_enable = false;
1589 s->aai_enable = false;
1590 }
1591
1592 break;
1593
1594 case STATE_READ:
1595 r = s->storage[s->cur_addr];
1596 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1597 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1598 break;
1599
1600 case STATE_COLLECTING_DATA:
1601 case STATE_COLLECTING_VAR_LEN_DATA:
1602
1603 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1604 qemu_log_mask(LOG_GUEST_ERROR,
1605 "M25P80: Write overrun internal data buffer. "
1606 "SPI controller (QEMU emulator or guest driver) "
1607 "is misbehaving\n");
1608 s->len = s->pos = 0;
1609 s->state = STATE_IDLE;
1610 break;
1611 }
1612
1613 s->data[s->len] = (uint8_t)tx;
1614 s->len++;
1615
1616 if (s->len == s->needed_bytes) {
1617 complete_collecting_data(s);
1618 }
1619 break;
1620
1621 case STATE_READING_DATA:
1622
1623 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1624 qemu_log_mask(LOG_GUEST_ERROR,
1625 "M25P80: Read overrun internal data buffer. "
1626 "SPI controller (QEMU emulator or guest driver) "
1627 "is misbehaving\n");
1628 s->len = s->pos = 0;
1629 s->state = STATE_IDLE;
1630 break;
1631 }
1632
1633 r = s->data[s->pos];
1634 trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1635 s->pos++;
1636 if (s->pos == s->len) {
1637 s->pos = 0;
1638 if (!s->data_read_loop) {
1639 s->state = STATE_IDLE;
1640 }
1641 }
1642 break;
1643 case STATE_READING_SFDP:
1644 assert(s->pi->sfdp_read);
1645 r = s->pi->sfdp_read(s->cur_addr);
1646 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r);
1647 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1);
1648 break;
1649
1650 default:
1651 case STATE_IDLE:
1652 decode_new_cmd(s, (uint8_t)tx);
1653 break;
1654 }
1655
1656 return r;
1657 }
1658
m25p80_write_protect_pin_irq_handler(void * opaque,int n,int level)1659 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level)
1660 {
1661 Flash *s = M25P80(opaque);
1662 /* WP# is just a single pin. */
1663 assert(n == 0);
1664 s->wp_level = !!level;
1665 }
1666
m25p80_realize(SSIPeripheral * ss,Error ** errp)1667 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
1668 {
1669 Flash *s = M25P80(ss);
1670 M25P80Class *mc = M25P80_GET_CLASS(s);
1671 int ret;
1672
1673 s->pi = mc->pi;
1674
1675 s->size = s->pi->sector_size * s->pi->n_sectors;
1676 s->dirty_page = -1;
1677
1678 if (s->blk) {
1679 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1680 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
1681 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1682 if (ret < 0) {
1683 return;
1684 }
1685
1686 trace_m25p80_binding(s);
1687 s->storage = blk_blockalign(s->blk, s->size);
1688
1689 if (!blk_check_size_and_read_all(s->blk, DEVICE(s),
1690 s->storage, s->size, errp)) {
1691 return;
1692 }
1693 } else {
1694 trace_m25p80_binding_no_bdrv(s);
1695 s->storage = blk_blockalign(NULL, s->size);
1696 memset(s->storage, 0xFF, s->size);
1697 }
1698
1699 qdev_init_gpio_in_named(DEVICE(s),
1700 m25p80_write_protect_pin_irq_handler, "WP#", 1);
1701 }
1702
m25p80_reset(DeviceState * d)1703 static void m25p80_reset(DeviceState *d)
1704 {
1705 Flash *s = M25P80(d);
1706
1707 s->wp_level = true;
1708 s->status_register_write_disabled = false;
1709 s->block_protect0 = false;
1710 s->block_protect1 = false;
1711 s->block_protect2 = false;
1712 s->block_protect3 = false;
1713 s->top_bottom_bit = false;
1714
1715 reset_memory(s);
1716 }
1717
m25p80_pre_save(void * opaque)1718 static int m25p80_pre_save(void *opaque)
1719 {
1720 flash_sync_dirty((Flash *)opaque, -1);
1721
1722 return 0;
1723 }
1724
1725 static const Property m25p80_properties[] = {
1726 /* This is default value for Micron flash */
1727 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false),
1728 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1729 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1730 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1731 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1732 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1733 DEFINE_PROP_DRIVE("drive", Flash, blk),
1734 };
1735
m25p80_pre_load(void * opaque)1736 static int m25p80_pre_load(void *opaque)
1737 {
1738 Flash *s = (Flash *)opaque;
1739
1740 s->data_read_loop = false;
1741 return 0;
1742 }
1743
m25p80_data_read_loop_needed(void * opaque)1744 static bool m25p80_data_read_loop_needed(void *opaque)
1745 {
1746 Flash *s = (Flash *)opaque;
1747
1748 return s->data_read_loop;
1749 }
1750
1751 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1752 .name = "m25p80/data_read_loop",
1753 .version_id = 1,
1754 .minimum_version_id = 1,
1755 .needed = m25p80_data_read_loop_needed,
1756 .fields = (const VMStateField[]) {
1757 VMSTATE_BOOL(data_read_loop, Flash),
1758 VMSTATE_END_OF_LIST()
1759 }
1760 };
1761
m25p80_aai_enable_needed(void * opaque)1762 static bool m25p80_aai_enable_needed(void *opaque)
1763 {
1764 Flash *s = (Flash *)opaque;
1765
1766 return s->aai_enable;
1767 }
1768
1769 static const VMStateDescription vmstate_m25p80_aai_enable = {
1770 .name = "m25p80/aai_enable",
1771 .version_id = 1,
1772 .minimum_version_id = 1,
1773 .needed = m25p80_aai_enable_needed,
1774 .fields = (const VMStateField[]) {
1775 VMSTATE_BOOL(aai_enable, Flash),
1776 VMSTATE_END_OF_LIST()
1777 }
1778 };
1779
m25p80_wp_level_srwd_needed(void * opaque)1780 static bool m25p80_wp_level_srwd_needed(void *opaque)
1781 {
1782 Flash *s = (Flash *)opaque;
1783
1784 return !s->wp_level || s->status_register_write_disabled;
1785 }
1786
1787 static const VMStateDescription vmstate_m25p80_write_protect = {
1788 .name = "m25p80/write_protect",
1789 .version_id = 1,
1790 .minimum_version_id = 1,
1791 .needed = m25p80_wp_level_srwd_needed,
1792 .fields = (const VMStateField[]) {
1793 VMSTATE_BOOL(wp_level, Flash),
1794 VMSTATE_BOOL(status_register_write_disabled, Flash),
1795 VMSTATE_END_OF_LIST()
1796 }
1797 };
1798
m25p80_block_protect_needed(void * opaque)1799 static bool m25p80_block_protect_needed(void *opaque)
1800 {
1801 Flash *s = (Flash *)opaque;
1802
1803 return s->block_protect0 ||
1804 s->block_protect1 ||
1805 s->block_protect2 ||
1806 s->block_protect3 ||
1807 s->top_bottom_bit;
1808 }
1809
1810 static const VMStateDescription vmstate_m25p80_block_protect = {
1811 .name = "m25p80/block_protect",
1812 .version_id = 1,
1813 .minimum_version_id = 1,
1814 .needed = m25p80_block_protect_needed,
1815 .fields = (const VMStateField[]) {
1816 VMSTATE_BOOL(block_protect0, Flash),
1817 VMSTATE_BOOL(block_protect1, Flash),
1818 VMSTATE_BOOL(block_protect2, Flash),
1819 VMSTATE_BOOL(block_protect3, Flash),
1820 VMSTATE_BOOL(top_bottom_bit, Flash),
1821 VMSTATE_END_OF_LIST()
1822 }
1823 };
1824
1825 static const VMStateDescription vmstate_m25p80 = {
1826 .name = "m25p80",
1827 .version_id = 0,
1828 .minimum_version_id = 0,
1829 .pre_save = m25p80_pre_save,
1830 .pre_load = m25p80_pre_load,
1831 .fields = (const VMStateField[]) {
1832 VMSTATE_UINT8(state, Flash),
1833 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1834 VMSTATE_UINT32(len, Flash),
1835 VMSTATE_UINT32(pos, Flash),
1836 VMSTATE_UINT8(needed_bytes, Flash),
1837 VMSTATE_UINT8(cmd_in_progress, Flash),
1838 VMSTATE_UINT32(cur_addr, Flash),
1839 VMSTATE_BOOL(write_enable, Flash),
1840 VMSTATE_BOOL(reset_enable, Flash),
1841 VMSTATE_UINT8(ear, Flash),
1842 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1843 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1844 VMSTATE_UINT32(volatile_cfg, Flash),
1845 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1846 VMSTATE_BOOL(quad_enable, Flash),
1847 VMSTATE_UINT8(spansion_cr1nv, Flash),
1848 VMSTATE_UINT8(spansion_cr2nv, Flash),
1849 VMSTATE_UINT8(spansion_cr3nv, Flash),
1850 VMSTATE_UINT8(spansion_cr4nv, Flash),
1851 VMSTATE_END_OF_LIST()
1852 },
1853 .subsections = (const VMStateDescription * const []) {
1854 &vmstate_m25p80_data_read_loop,
1855 &vmstate_m25p80_aai_enable,
1856 &vmstate_m25p80_write_protect,
1857 &vmstate_m25p80_block_protect,
1858 NULL
1859 }
1860 };
1861
m25p80_class_init(ObjectClass * klass,const void * data)1862 static void m25p80_class_init(ObjectClass *klass, const void *data)
1863 {
1864 DeviceClass *dc = DEVICE_CLASS(klass);
1865 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
1866 M25P80Class *mc = M25P80_CLASS(klass);
1867
1868 k->realize = m25p80_realize;
1869 k->transfer = m25p80_transfer8;
1870 k->set_cs = m25p80_cs;
1871 k->cs_polarity = SSI_CS_LOW;
1872 dc->vmsd = &vmstate_m25p80;
1873 device_class_set_props(dc, m25p80_properties);
1874 device_class_set_legacy_reset(dc, m25p80_reset);
1875 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1876 mc->pi = data;
1877 dc->desc = "Serial Flash";
1878 }
1879
1880 static const TypeInfo m25p80_info = {
1881 .name = TYPE_M25P80,
1882 .parent = TYPE_SSI_PERIPHERAL,
1883 .instance_size = sizeof(Flash),
1884 .class_size = sizeof(M25P80Class),
1885 .abstract = true,
1886 };
1887
m25p80_register_types(void)1888 static void m25p80_register_types(void)
1889 {
1890 int i;
1891
1892 type_register_static(&m25p80_info);
1893 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1894 const TypeInfo ti = {
1895 .name = known_devices[i].part_name,
1896 .parent = TYPE_M25P80,
1897 .class_init = m25p80_class_init,
1898 .class_data = &known_devices[i],
1899 };
1900 type_register_static(&ti);
1901 }
1902 }
1903
type_init(m25p80_register_types)1904 type_init(m25p80_register_types)
1905
1906 BlockBackend *m25p80_get_blk(DeviceState *dev)
1907 {
1908 return M25P80(dev)->blk;
1909 }
1910