1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 2; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) " 51 "1: track usage per queue, 2: track usage per adapter"); 52 53 /* 54 * CT6 CTX allocation cache 55 */ 56 static struct kmem_cache *ctx_cachep; 57 /* 58 * error level for logging 59 */ 60 uint ql_errlev = 0x8001; 61 62 int ql2xsecenable; 63 module_param(ql2xsecenable, int, S_IRUGO); 64 MODULE_PARM_DESC(ql2xsecenable, 65 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 66 67 static int ql2xenableclass2; 68 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 69 MODULE_PARM_DESC(ql2xenableclass2, 70 "Specify if Class 2 operations are supported from the very " 71 "beginning. Default is 0 - class 2 not supported."); 72 73 74 int ql2xlogintimeout = 20; 75 module_param(ql2xlogintimeout, int, S_IRUGO); 76 MODULE_PARM_DESC(ql2xlogintimeout, 77 "Login timeout value in seconds."); 78 79 int qlport_down_retry; 80 module_param(qlport_down_retry, int, S_IRUGO); 81 MODULE_PARM_DESC(qlport_down_retry, 82 "Maximum number of command retries to a port that returns " 83 "a PORT-DOWN status."); 84 85 int ql2xplogiabsentdevice; 86 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xplogiabsentdevice, 88 "Option to enable PLOGI to devices that are not present after " 89 "a Fabric scan. This is needed for several broken switches. " 90 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 91 92 int ql2xloginretrycount; 93 module_param(ql2xloginretrycount, int, S_IRUGO); 94 MODULE_PARM_DESC(ql2xloginretrycount, 95 "Specify an alternate value for the NVRAM login retry count."); 96 97 int ql2xallocfwdump = 1; 98 module_param(ql2xallocfwdump, int, S_IRUGO); 99 MODULE_PARM_DESC(ql2xallocfwdump, 100 "Option to enable allocation of memory for a firmware dump " 101 "during HBA initialization. Memory allocation requirements " 102 "vary by ISP type. Default is 1 - allocate memory."); 103 104 int ql2xextended_error_logging; 105 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 107 MODULE_PARM_DESC(ql2xextended_error_logging, 108 "Option to enable extended error logging,\n" 109 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 110 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 111 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 112 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 113 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 114 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 115 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 116 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 117 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 118 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 119 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 120 "\t\t0x1e400000 - Preferred value for capturing essential " 121 "debug information (equivalent to old " 122 "ql2xextended_error_logging=1).\n" 123 "\t\tDo LOGICAL OR of the value to enable more than one level"); 124 125 int ql2xextended_error_logging_ktrace = 1; 126 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 127 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 128 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 129 130 int ql2xshiftctondsd = 6; 131 module_param(ql2xshiftctondsd, int, S_IRUGO); 132 MODULE_PARM_DESC(ql2xshiftctondsd, 133 "Set to control shifting of command type processing " 134 "based on total number of SG elements."); 135 136 int ql2xfdmienable = 1; 137 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 139 MODULE_PARM_DESC(ql2xfdmienable, 140 "Enables FDMI registrations. " 141 "0 - no FDMI registrations. " 142 "1 - provide FDMI registrations (default)."); 143 144 #define MAX_Q_DEPTH 64 145 static int ql2xmaxqdepth = MAX_Q_DEPTH; 146 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 147 MODULE_PARM_DESC(ql2xmaxqdepth, 148 "Maximum queue depth to set for each LUN. " 149 "Default is 64."); 150 151 int ql2xenabledif = 2; 152 module_param(ql2xenabledif, int, S_IRUGO); 153 MODULE_PARM_DESC(ql2xenabledif, 154 " Enable T10-CRC-DIF:\n" 155 " Default is 2.\n" 156 " 0 -- No DIF Support\n" 157 " 1 -- Enable DIF for all types\n" 158 " 2 -- Enable DIF for all types, except Type 0.\n"); 159 160 #if (IS_ENABLED(CONFIG_NVME_FC)) 161 int ql2xnvmeenable = 1; 162 #else 163 int ql2xnvmeenable; 164 #endif 165 module_param(ql2xnvmeenable, int, 0644); 166 MODULE_PARM_DESC(ql2xnvmeenable, 167 "Enables NVME support. " 168 "0 - no NVMe. Default is Y"); 169 170 int ql2xenablehba_err_chk = 2; 171 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 172 MODULE_PARM_DESC(ql2xenablehba_err_chk, 173 " Enable T10-CRC-DIF Error isolation by HBA:\n" 174 " Default is 2.\n" 175 " 0 -- Error isolation disabled\n" 176 " 1 -- Error isolation enabled only for DIX Type 0\n" 177 " 2 -- Error isolation enabled for all Types\n"); 178 179 int ql2xiidmaenable = 1; 180 module_param(ql2xiidmaenable, int, S_IRUGO); 181 MODULE_PARM_DESC(ql2xiidmaenable, 182 "Enables iIDMA settings " 183 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 184 185 int ql2xmqsupport = 1; 186 module_param(ql2xmqsupport, int, S_IRUGO); 187 MODULE_PARM_DESC(ql2xmqsupport, 188 "Enable on demand multiple queue pairs support " 189 "Default is 1 for supported. " 190 "Set it to 0 to turn off mq qpair support."); 191 192 int ql2xfwloadbin; 193 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 195 MODULE_PARM_DESC(ql2xfwloadbin, 196 "Option to specify location from which to load ISP firmware:.\n" 197 " 2 -- load firmware via the request_firmware() (hotplug).\n" 198 " interface.\n" 199 " 1 -- load firmware from flash.\n" 200 " 0 -- use default semantics.\n"); 201 202 int ql2xetsenable; 203 module_param(ql2xetsenable, int, S_IRUGO); 204 MODULE_PARM_DESC(ql2xetsenable, 205 "Enables firmware ETS burst." 206 "Default is 0 - skip ETS enablement."); 207 208 int ql2xdbwr = 1; 209 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 210 MODULE_PARM_DESC(ql2xdbwr, 211 "Option to specify scheme for request queue posting.\n" 212 " 0 -- Regular doorbell.\n" 213 " 1 -- CAMRAM doorbell (faster).\n"); 214 215 int ql2xgffidenable; 216 module_param(ql2xgffidenable, int, S_IRUGO); 217 MODULE_PARM_DESC(ql2xgffidenable, 218 "Enables GFF_ID checks of port type. " 219 "Default is 0 - Do not use GFF_ID information."); 220 221 int ql2xasynctmfenable = 1; 222 module_param(ql2xasynctmfenable, int, S_IRUGO); 223 MODULE_PARM_DESC(ql2xasynctmfenable, 224 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 225 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 226 227 int ql2xdontresethba; 228 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 229 MODULE_PARM_DESC(ql2xdontresethba, 230 "Option to specify reset behaviour.\n" 231 " 0 (Default) -- Reset on failure.\n" 232 " 1 -- Do not reset on failure.\n"); 233 234 uint64_t ql2xmaxlun = MAX_LUNS; 235 module_param(ql2xmaxlun, ullong, S_IRUGO); 236 MODULE_PARM_DESC(ql2xmaxlun, 237 "Defines the maximum LU number to register with the SCSI " 238 "midlayer. Default is 65535."); 239 240 int ql2xmdcapmask = 0x1F; 241 module_param(ql2xmdcapmask, int, S_IRUGO); 242 MODULE_PARM_DESC(ql2xmdcapmask, 243 "Set the Minidump driver capture mask level. " 244 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 245 246 int ql2xmdenable = 1; 247 module_param(ql2xmdenable, int, S_IRUGO); 248 MODULE_PARM_DESC(ql2xmdenable, 249 "Enable/disable MiniDump. " 250 "0 - MiniDump disabled. " 251 "1 (Default) - MiniDump enabled."); 252 253 int ql2xexlogins; 254 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 255 MODULE_PARM_DESC(ql2xexlogins, 256 "Number of extended Logins. " 257 "0 (Default)- Disabled."); 258 259 int ql2xexchoffld = 1024; 260 module_param(ql2xexchoffld, uint, 0644); 261 MODULE_PARM_DESC(ql2xexchoffld, 262 "Number of target exchanges."); 263 264 int ql2xiniexchg = 1024; 265 module_param(ql2xiniexchg, uint, 0644); 266 MODULE_PARM_DESC(ql2xiniexchg, 267 "Number of initiator exchanges."); 268 269 int ql2xfwholdabts; 270 module_param(ql2xfwholdabts, int, S_IRUGO); 271 MODULE_PARM_DESC(ql2xfwholdabts, 272 "Allow FW to hold status IOCB until ABTS rsp received. " 273 "0 (Default) Do not set fw option. " 274 "1 - Set fw option to hold ABTS."); 275 276 int ql2xmvasynctoatio = 1; 277 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 278 MODULE_PARM_DESC(ql2xmvasynctoatio, 279 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 280 "0 (Default). Do not move IOCBs" 281 "1 - Move IOCBs."); 282 283 int ql2xautodetectsfp = 1; 284 module_param(ql2xautodetectsfp, int, 0444); 285 MODULE_PARM_DESC(ql2xautodetectsfp, 286 "Detect SFP range and set appropriate distance.\n" 287 "1 (Default): Enable\n"); 288 289 int ql2xenablemsix = 1; 290 module_param(ql2xenablemsix, int, 0444); 291 MODULE_PARM_DESC(ql2xenablemsix, 292 "Set to enable MSI or MSI-X interrupt mechanism.\n" 293 " Default is 1, enable MSI-X interrupt mechanism.\n" 294 " 0 -- enable traditional pin-based mechanism.\n" 295 " 1 -- enable MSI-X interrupt mechanism.\n" 296 " 2 -- enable MSI interrupt mechanism.\n"); 297 298 int qla2xuseresexchforels; 299 module_param(qla2xuseresexchforels, int, 0444); 300 MODULE_PARM_DESC(qla2xuseresexchforels, 301 "Reserve 1/2 of emergency exchanges for ELS.\n" 302 " 0 (default): disabled"); 303 304 static int ql2xprotmask; 305 module_param(ql2xprotmask, int, 0644); 306 MODULE_PARM_DESC(ql2xprotmask, 307 "Override DIF/DIX protection capabilities mask\n" 308 "Default is 0 which sets protection mask based on " 309 "capabilities reported by HBA firmware.\n"); 310 311 static int ql2xprotguard; 312 module_param(ql2xprotguard, int, 0644); 313 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 314 " 0 -- Let HBA firmware decide\n" 315 " 1 -- Force T10 CRC\n" 316 " 2 -- Force IP checksum\n"); 317 318 int ql2xdifbundlinginternalbuffers; 319 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 320 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 321 "Force using internal buffers for DIF information\n" 322 "0 (Default). Based on check.\n" 323 "1 Force using internal buffers\n"); 324 325 int ql2xsmartsan; 326 module_param(ql2xsmartsan, int, 0444); 327 module_param_named(smartsan, ql2xsmartsan, int, 0444); 328 MODULE_PARM_DESC(ql2xsmartsan, 329 "Send SmartSAN Management Attributes for FDMI Registration." 330 " Default is 0 - No SmartSAN registration," 331 " 1 - Register SmartSAN Management Attributes."); 332 333 int ql2xrdpenable; 334 module_param(ql2xrdpenable, int, 0444); 335 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 336 MODULE_PARM_DESC(ql2xrdpenable, 337 "Enables RDP responses. " 338 "0 - no RDP responses (default). " 339 "1 - provide RDP responses."); 340 int ql2xabts_wait_nvme = 1; 341 module_param(ql2xabts_wait_nvme, int, 0444); 342 MODULE_PARM_DESC(ql2xabts_wait_nvme, 343 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 344 345 346 static u32 ql2xdelay_before_pci_error_handling = 5; 347 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 348 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 349 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 350 351 static void qla2x00_clear_drv_active(struct qla_hw_data *); 352 static void qla2x00_free_device(scsi_qla_host_t *); 353 static void qla2xxx_map_queues(struct Scsi_Host *shost); 354 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 355 356 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 357 module_param(ql2xnvme_queues, uint, S_IRUGO); 358 MODULE_PARM_DESC(ql2xnvme_queues, 359 "Number of NVMe Queues that can be configured.\n" 360 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 361 "1 - Minimum number of queues supported\n" 362 "8 - Default value"); 363 364 int ql2xfc2target = 1; 365 module_param(ql2xfc2target, int, 0444); 366 MODULE_PARM_DESC(qla2xfc2target, 367 "Enables FC2 Target support. " 368 "0 - FC2 Target support is disabled. " 369 "1 - FC2 Target support is enabled (default)."); 370 371 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 372 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 373 374 /* TODO Convert to inlines 375 * 376 * Timer routines 377 */ 378 379 __inline__ void qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)380 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 381 { 382 timer_setup(&vha->timer, qla2x00_timer, 0); 383 vha->timer.expires = jiffies + interval * HZ; 384 add_timer(&vha->timer); 385 vha->timer_active = 1; 386 } 387 388 static inline void qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)389 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 390 { 391 /* Currently used for 82XX only. */ 392 if (vha->device_flags & DFLG_DEV_FAILED) { 393 ql_dbg(ql_dbg_timer, vha, 0x600d, 394 "Device in a failed state, returning.\n"); 395 return; 396 } 397 398 mod_timer(&vha->timer, jiffies + interval * HZ); 399 } 400 401 static __inline__ void qla2x00_stop_timer(scsi_qla_host_t * vha)402 qla2x00_stop_timer(scsi_qla_host_t *vha) 403 { 404 del_timer_sync(&vha->timer); 405 vha->timer_active = 0; 406 } 407 408 static int qla2x00_do_dpc(void *data); 409 410 static void qla2x00_rst_aen(scsi_qla_host_t *); 411 412 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 413 struct req_que **, struct rsp_que **); 414 static void qla2x00_free_fw_dump(struct qla_hw_data *); 415 static void qla2x00_mem_free(struct qla_hw_data *); 416 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 417 struct qla_qpair *qpair); 418 419 /* -------------------------------------------------------------------------- */ qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)420 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 421 struct rsp_que *rsp) 422 { 423 struct qla_hw_data *ha = vha->hw; 424 425 rsp->qpair = ha->base_qpair; 426 rsp->req = req; 427 ha->base_qpair->hw = ha; 428 ha->base_qpair->req = req; 429 ha->base_qpair->rsp = rsp; 430 ha->base_qpair->vha = vha; 431 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 432 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 433 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 434 ha->base_qpair->srb_mempool = ha->srb_mempool; 435 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 436 INIT_LIST_HEAD(&ha->base_qpair->dsd_list); 437 ha->base_qpair->enable_class_2 = ql2xenableclass2; 438 /* init qpair to this cpu. Will adjust at run time. */ 439 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 440 ha->base_qpair->pdev = ha->pdev; 441 442 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 443 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 444 } 445 qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)446 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 447 struct rsp_que *rsp) 448 { 449 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 450 451 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 452 GFP_KERNEL); 453 if (!ha->req_q_map) { 454 ql_log(ql_log_fatal, vha, 0x003b, 455 "Unable to allocate memory for request queue ptrs.\n"); 456 goto fail_req_map; 457 } 458 459 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 460 GFP_KERNEL); 461 if (!ha->rsp_q_map) { 462 ql_log(ql_log_fatal, vha, 0x003c, 463 "Unable to allocate memory for response queue ptrs.\n"); 464 goto fail_rsp_map; 465 } 466 467 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 468 if (ha->base_qpair == NULL) { 469 ql_log(ql_log_warn, vha, 0x00e0, 470 "Failed to allocate base queue pair memory.\n"); 471 goto fail_base_qpair; 472 } 473 474 qla_init_base_qpair(vha, req, rsp); 475 476 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 477 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 478 GFP_KERNEL); 479 if (!ha->queue_pair_map) { 480 ql_log(ql_log_fatal, vha, 0x0180, 481 "Unable to allocate memory for queue pair ptrs.\n"); 482 goto fail_qpair_map; 483 } 484 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 485 kfree(ha->queue_pair_map); 486 ha->queue_pair_map = NULL; 487 goto fail_qpair_map; 488 } 489 } 490 491 /* 492 * Make sure we record at least the request and response queue zero in 493 * case we need to free them if part of the probe fails. 494 */ 495 ha->rsp_q_map[0] = rsp; 496 ha->req_q_map[0] = req; 497 set_bit(0, ha->rsp_qid_map); 498 set_bit(0, ha->req_qid_map); 499 return 0; 500 501 fail_qpair_map: 502 kfree(ha->base_qpair); 503 ha->base_qpair = NULL; 504 fail_base_qpair: 505 kfree(ha->rsp_q_map); 506 ha->rsp_q_map = NULL; 507 fail_rsp_map: 508 kfree(ha->req_q_map); 509 ha->req_q_map = NULL; 510 fail_req_map: 511 return -ENOMEM; 512 } 513 qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)514 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 515 { 516 if (IS_QLAFX00(ha)) { 517 if (req && req->ring_fx00) 518 dma_free_coherent(&ha->pdev->dev, 519 (req->length_fx00 + 1) * sizeof(request_t), 520 req->ring_fx00, req->dma_fx00); 521 } else if (req && req->ring) 522 dma_free_coherent(&ha->pdev->dev, 523 (req->length + 1) * sizeof(request_t), 524 req->ring, req->dma); 525 526 if (req) 527 kfree(req->outstanding_cmds); 528 529 kfree(req); 530 } 531 qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)532 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 533 { 534 if (IS_QLAFX00(ha)) { 535 if (rsp && rsp->ring_fx00) 536 dma_free_coherent(&ha->pdev->dev, 537 (rsp->length_fx00 + 1) * sizeof(request_t), 538 rsp->ring_fx00, rsp->dma_fx00); 539 } else if (rsp && rsp->ring) { 540 dma_free_coherent(&ha->pdev->dev, 541 (rsp->length + 1) * sizeof(response_t), 542 rsp->ring, rsp->dma); 543 } 544 kfree(rsp); 545 } 546 qla2x00_free_queues(struct qla_hw_data * ha)547 static void qla2x00_free_queues(struct qla_hw_data *ha) 548 { 549 struct req_que *req; 550 struct rsp_que *rsp; 551 int cnt; 552 unsigned long flags; 553 554 if (ha->queue_pair_map) { 555 kfree(ha->queue_pair_map); 556 ha->queue_pair_map = NULL; 557 } 558 if (ha->base_qpair) { 559 kfree(ha->base_qpair); 560 ha->base_qpair = NULL; 561 } 562 563 qla_mapq_free_qp_cpu_map(ha); 564 spin_lock_irqsave(&ha->hardware_lock, flags); 565 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 566 if (!test_bit(cnt, ha->req_qid_map)) 567 continue; 568 569 req = ha->req_q_map[cnt]; 570 clear_bit(cnt, ha->req_qid_map); 571 ha->req_q_map[cnt] = NULL; 572 573 spin_unlock_irqrestore(&ha->hardware_lock, flags); 574 qla2x00_free_req_que(ha, req); 575 spin_lock_irqsave(&ha->hardware_lock, flags); 576 } 577 spin_unlock_irqrestore(&ha->hardware_lock, flags); 578 579 kfree(ha->req_q_map); 580 ha->req_q_map = NULL; 581 582 583 spin_lock_irqsave(&ha->hardware_lock, flags); 584 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 585 if (!test_bit(cnt, ha->rsp_qid_map)) 586 continue; 587 588 rsp = ha->rsp_q_map[cnt]; 589 clear_bit(cnt, ha->rsp_qid_map); 590 ha->rsp_q_map[cnt] = NULL; 591 spin_unlock_irqrestore(&ha->hardware_lock, flags); 592 qla2x00_free_rsp_que(ha, rsp); 593 spin_lock_irqsave(&ha->hardware_lock, flags); 594 } 595 spin_unlock_irqrestore(&ha->hardware_lock, flags); 596 597 kfree(ha->rsp_q_map); 598 ha->rsp_q_map = NULL; 599 } 600 601 static char * qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)602 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 603 { 604 struct qla_hw_data *ha = vha->hw; 605 static const char *const pci_bus_modes[] = { 606 "33", "66", "100", "133", 607 }; 608 uint16_t pci_bus; 609 610 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 611 if (pci_bus) { 612 snprintf(str, str_len, "PCI-X (%s MHz)", 613 pci_bus_modes[pci_bus]); 614 } else { 615 pci_bus = (ha->pci_attr & BIT_8) >> 8; 616 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 617 } 618 619 return str; 620 } 621 622 static char * qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)623 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 624 { 625 static const char *const pci_bus_modes[] = { 626 "33", "66", "100", "133", 627 }; 628 struct qla_hw_data *ha = vha->hw; 629 uint32_t pci_bus; 630 631 if (pci_is_pcie(ha->pdev)) { 632 uint32_t lstat, lspeed, lwidth; 633 const char *speed_str; 634 635 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 636 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 637 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 638 639 switch (lspeed) { 640 case 1: 641 speed_str = "2.5GT/s"; 642 break; 643 case 2: 644 speed_str = "5.0GT/s"; 645 break; 646 case 3: 647 speed_str = "8.0GT/s"; 648 break; 649 case 4: 650 speed_str = "16.0GT/s"; 651 break; 652 default: 653 speed_str = "<unknown>"; 654 break; 655 } 656 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 657 658 return str; 659 } 660 661 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 662 if (pci_bus == 0 || pci_bus == 8) 663 snprintf(str, str_len, "PCI (%s MHz)", 664 pci_bus_modes[pci_bus >> 3]); 665 else 666 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 667 pci_bus & 4 ? 2 : 1, 668 pci_bus_modes[pci_bus & 3]); 669 670 return str; 671 } 672 673 static char * qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)674 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 675 { 676 char un_str[10]; 677 struct qla_hw_data *ha = vha->hw; 678 679 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 680 ha->fw_minor_version, ha->fw_subminor_version); 681 682 if (ha->fw_attributes & BIT_9) { 683 strcat(str, "FLX"); 684 return (str); 685 } 686 687 switch (ha->fw_attributes & 0xFF) { 688 case 0x7: 689 strcat(str, "EF"); 690 break; 691 case 0x17: 692 strcat(str, "TP"); 693 break; 694 case 0x37: 695 strcat(str, "IP"); 696 break; 697 case 0x77: 698 strcat(str, "VI"); 699 break; 700 default: 701 sprintf(un_str, "(%x)", ha->fw_attributes); 702 strcat(str, un_str); 703 break; 704 } 705 if (ha->fw_attributes & 0x100) 706 strcat(str, "X"); 707 708 return (str); 709 } 710 711 static char * qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)712 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 713 { 714 struct qla_hw_data *ha = vha->hw; 715 716 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 717 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 718 return str; 719 } 720 qla2x00_sp_free_dma(srb_t * sp)721 void qla2x00_sp_free_dma(srb_t *sp) 722 { 723 struct qla_hw_data *ha = sp->vha->hw; 724 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 725 726 if (sp->flags & SRB_DMA_VALID) { 727 scsi_dma_unmap(cmd); 728 sp->flags &= ~SRB_DMA_VALID; 729 } 730 731 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 732 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 733 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 734 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 735 } 736 737 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 738 /* List assured to be having elements */ 739 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 740 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 741 } 742 743 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 744 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 745 746 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 747 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 748 } 749 750 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 751 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 752 753 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 754 ctx1->fcp_cmnd_dma); 755 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list); 756 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt; 757 sp->qpair->dsd_avail += ctx1->dsd_use_cnt; 758 } 759 760 if (sp->flags & SRB_GOT_BUF) 761 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 762 } 763 qla2x00_sp_compl(srb_t * sp,int res)764 void qla2x00_sp_compl(srb_t *sp, int res) 765 { 766 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 767 struct completion *comp = sp->comp; 768 769 /* kref: INIT */ 770 kref_put(&sp->cmd_kref, qla2x00_sp_release); 771 cmd->result = res; 772 sp->type = 0; 773 scsi_done(cmd); 774 if (comp) 775 complete(comp); 776 } 777 qla2xxx_qpair_sp_free_dma(srb_t * sp)778 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 779 { 780 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 781 struct qla_hw_data *ha = sp->fcport->vha->hw; 782 783 if (sp->flags & SRB_DMA_VALID) { 784 scsi_dma_unmap(cmd); 785 sp->flags &= ~SRB_DMA_VALID; 786 } 787 788 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 789 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 790 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 791 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 792 } 793 794 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 795 /* List assured to be having elements */ 796 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 797 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 798 } 799 800 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 801 struct crc_context *difctx = sp->u.scmd.crc_ctx; 802 struct dsd_dma *dif_dsd, *nxt_dsd; 803 804 list_for_each_entry_safe(dif_dsd, nxt_dsd, 805 &difctx->ldif_dma_hndl_list, list) { 806 list_del(&dif_dsd->list); 807 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 808 dif_dsd->dsd_list_dma); 809 kfree(dif_dsd); 810 difctx->no_dif_bundl--; 811 } 812 813 list_for_each_entry_safe(dif_dsd, nxt_dsd, 814 &difctx->ldif_dsd_list, list) { 815 list_del(&dif_dsd->list); 816 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 817 dif_dsd->dsd_list_dma); 818 kfree(dif_dsd); 819 difctx->no_ldif_dsd--; 820 } 821 822 if (difctx->no_ldif_dsd) { 823 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 824 "%s: difctx->no_ldif_dsd=%x\n", 825 __func__, difctx->no_ldif_dsd); 826 } 827 828 if (difctx->no_dif_bundl) { 829 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 830 "%s: difctx->no_dif_bundl=%x\n", 831 __func__, difctx->no_dif_bundl); 832 } 833 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 834 } 835 836 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 837 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 838 839 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 840 ctx1->fcp_cmnd_dma); 841 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list); 842 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt; 843 sp->qpair->dsd_avail += ctx1->dsd_use_cnt; 844 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 845 } 846 847 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 848 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 849 850 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 851 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 852 } 853 854 if (sp->flags & SRB_GOT_BUF) 855 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 856 } 857 qla2xxx_qpair_sp_compl(srb_t * sp,int res)858 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 859 { 860 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 861 struct completion *comp = sp->comp; 862 863 /* ref: INIT */ 864 kref_put(&sp->cmd_kref, qla2x00_sp_release); 865 cmd->result = res; 866 sp->type = 0; 867 scsi_done(cmd); 868 if (comp) 869 complete(comp); 870 } 871 872 static int qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)873 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 874 { 875 scsi_qla_host_t *vha = shost_priv(host); 876 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 877 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 878 struct qla_hw_data *ha = vha->hw; 879 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 880 srb_t *sp; 881 int rval; 882 883 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 884 WARN_ON_ONCE(!rport)) { 885 cmd->result = DID_NO_CONNECT << 16; 886 goto qc24_fail_command; 887 } 888 889 if (ha->mqenable) { 890 uint32_t tag; 891 uint16_t hwq; 892 struct qla_qpair *qpair = NULL; 893 894 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 895 hwq = blk_mq_unique_tag_to_hwq(tag); 896 qpair = ha->queue_pair_map[hwq]; 897 898 if (qpair) 899 return qla2xxx_mqueuecommand(host, cmd, qpair); 900 } 901 902 if (ha->flags.eeh_busy) { 903 if (ha->flags.pci_channel_io_perm_failure) { 904 ql_dbg(ql_dbg_aer, vha, 0x9010, 905 "PCI Channel IO permanent failure, exiting " 906 "cmd=%p.\n", cmd); 907 cmd->result = DID_NO_CONNECT << 16; 908 } else { 909 ql_dbg(ql_dbg_aer, vha, 0x9011, 910 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 911 cmd->result = DID_REQUEUE << 16; 912 } 913 goto qc24_fail_command; 914 } 915 916 rval = fc_remote_port_chkready(rport); 917 if (rval) { 918 cmd->result = rval; 919 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 920 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 921 cmd, rval); 922 goto qc24_fail_command; 923 } 924 925 if (!vha->flags.difdix_supported && 926 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 927 ql_dbg(ql_dbg_io, vha, 0x3004, 928 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 929 cmd); 930 cmd->result = DID_NO_CONNECT << 16; 931 goto qc24_fail_command; 932 } 933 934 if (!fcport || fcport->deleted) { 935 cmd->result = DID_IMM_RETRY << 16; 936 goto qc24_fail_command; 937 } 938 939 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 940 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 941 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 942 ql_dbg(ql_dbg_io, vha, 0x3005, 943 "Returning DNC, fcport_state=%d loop_state=%d.\n", 944 atomic_read(&fcport->state), 945 atomic_read(&base_vha->loop_state)); 946 cmd->result = DID_NO_CONNECT << 16; 947 goto qc24_fail_command; 948 } 949 goto qc24_target_busy; 950 } 951 952 /* 953 * Return target busy if we've received a non-zero retry_delay_timer 954 * in a FCP_RSP. 955 */ 956 if (fcport->retry_delay_timestamp == 0) { 957 /* retry delay not set */ 958 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 959 fcport->retry_delay_timestamp = 0; 960 else 961 goto qc24_target_busy; 962 963 sp = scsi_cmd_priv(cmd); 964 /* ref: INIT */ 965 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 966 967 sp->u.scmd.cmd = cmd; 968 sp->type = SRB_SCSI_CMD; 969 sp->free = qla2x00_sp_free_dma; 970 sp->done = qla2x00_sp_compl; 971 972 rval = ha->isp_ops->start_scsi(sp); 973 if (rval != QLA_SUCCESS) { 974 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 975 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 976 goto qc24_host_busy_free_sp; 977 } 978 979 return 0; 980 981 qc24_host_busy_free_sp: 982 /* ref: INIT */ 983 kref_put(&sp->cmd_kref, qla2x00_sp_release); 984 985 qc24_target_busy: 986 return SCSI_MLQUEUE_TARGET_BUSY; 987 988 qc24_fail_command: 989 scsi_done(cmd); 990 991 return 0; 992 } 993 994 /* For MQ supported I/O */ 995 int qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)996 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 997 struct qla_qpair *qpair) 998 { 999 scsi_qla_host_t *vha = shost_priv(host); 1000 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1001 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1002 struct qla_hw_data *ha = vha->hw; 1003 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1004 srb_t *sp; 1005 int rval; 1006 1007 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 1008 if (rval) { 1009 cmd->result = rval; 1010 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1011 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1012 cmd, rval); 1013 goto qc24_fail_command; 1014 } 1015 1016 if (!qpair->online) { 1017 ql_dbg(ql_dbg_io, vha, 0x3077, 1018 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1019 cmd->result = DID_NO_CONNECT << 16; 1020 goto qc24_fail_command; 1021 } 1022 1023 if (!fcport || fcport->deleted) { 1024 cmd->result = DID_IMM_RETRY << 16; 1025 goto qc24_fail_command; 1026 } 1027 1028 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1029 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1030 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1031 ql_dbg(ql_dbg_io, vha, 0x3077, 1032 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1033 atomic_read(&fcport->state), 1034 atomic_read(&base_vha->loop_state)); 1035 cmd->result = DID_NO_CONNECT << 16; 1036 goto qc24_fail_command; 1037 } 1038 goto qc24_target_busy; 1039 } 1040 1041 /* 1042 * Return target busy if we've received a non-zero retry_delay_timer 1043 * in a FCP_RSP. 1044 */ 1045 if (fcport->retry_delay_timestamp == 0) { 1046 /* retry delay not set */ 1047 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1048 fcport->retry_delay_timestamp = 0; 1049 else 1050 goto qc24_target_busy; 1051 1052 sp = scsi_cmd_priv(cmd); 1053 /* ref: INIT */ 1054 qla2xxx_init_sp(sp, vha, qpair, fcport); 1055 1056 sp->u.scmd.cmd = cmd; 1057 sp->type = SRB_SCSI_CMD; 1058 sp->free = qla2xxx_qpair_sp_free_dma; 1059 sp->done = qla2xxx_qpair_sp_compl; 1060 1061 rval = ha->isp_ops->start_scsi_mq(sp); 1062 if (rval != QLA_SUCCESS) { 1063 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1064 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1065 goto qc24_host_busy_free_sp; 1066 } 1067 1068 return 0; 1069 1070 qc24_host_busy_free_sp: 1071 /* ref: INIT */ 1072 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1073 1074 qc24_target_busy: 1075 return SCSI_MLQUEUE_TARGET_BUSY; 1076 1077 qc24_fail_command: 1078 scsi_done(cmd); 1079 1080 return 0; 1081 } 1082 1083 /* 1084 * qla2x00_wait_for_hba_online 1085 * Wait till the HBA is online after going through 1086 * <= MAX_RETRIES_OF_ISP_ABORT or 1087 * finally HBA is disabled ie marked offline 1088 * 1089 * Input: 1090 * ha - pointer to host adapter structure 1091 * 1092 * Note: 1093 * Does context switching-Release SPIN_LOCK 1094 * (if any) before calling this routine. 1095 * 1096 * Return: 1097 * Success (Adapter is online) : 0 1098 * Failed (Adapter is offline/disabled) : 1 1099 */ 1100 int qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1101 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1102 { 1103 int return_status; 1104 unsigned long wait_online; 1105 struct qla_hw_data *ha = vha->hw; 1106 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1107 1108 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1109 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1110 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1111 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1112 ha->dpc_active) && time_before(jiffies, wait_online)) { 1113 1114 msleep(1000); 1115 } 1116 if (base_vha->flags.online) 1117 return_status = QLA_SUCCESS; 1118 else 1119 return_status = QLA_FUNCTION_FAILED; 1120 1121 return (return_status); 1122 } 1123 test_fcport_count(scsi_qla_host_t * vha)1124 static inline int test_fcport_count(scsi_qla_host_t *vha) 1125 { 1126 struct qla_hw_data *ha = vha->hw; 1127 unsigned long flags; 1128 int res; 1129 /* Return 0 = sleep, x=wake */ 1130 1131 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1132 ql_dbg(ql_dbg_init, vha, 0x00ec, 1133 "tgt %p, fcport_count=%d\n", 1134 vha, vha->fcport_count); 1135 res = (vha->fcport_count == 0); 1136 if (res) { 1137 struct fc_port *fcport; 1138 1139 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1140 if (fcport->deleted != QLA_SESS_DELETED) { 1141 /* session(s) may not be fully logged in 1142 * (ie fcport_count=0), but session 1143 * deletion thread(s) may be inflight. 1144 */ 1145 1146 res = 0; 1147 break; 1148 } 1149 } 1150 } 1151 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1152 1153 return res; 1154 } 1155 1156 /* 1157 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1158 * it has dependency on UNLOADING flag to stop device discovery 1159 */ 1160 void qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1161 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1162 { 1163 u8 i; 1164 1165 qla2x00_mark_all_devices_lost(vha); 1166 1167 for (i = 0; i < 10; i++) { 1168 if (wait_event_timeout(vha->fcport_waitQ, 1169 test_fcport_count(vha), HZ) > 0) 1170 break; 1171 } 1172 1173 flush_workqueue(vha->hw->wq); 1174 } 1175 1176 /* 1177 * qla2x00_wait_for_hba_ready 1178 * Wait till the HBA is ready before doing driver unload 1179 * 1180 * Input: 1181 * ha - pointer to host adapter structure 1182 * 1183 * Note: 1184 * Does context switching-Release SPIN_LOCK 1185 * (if any) before calling this routine. 1186 * 1187 */ 1188 static void qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1189 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1190 { 1191 struct qla_hw_data *ha = vha->hw; 1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1193 1194 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1195 ha->flags.mbox_busy) || 1196 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1197 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1198 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1199 break; 1200 msleep(1000); 1201 } 1202 } 1203 1204 int qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1205 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1206 { 1207 int return_status; 1208 unsigned long wait_reset; 1209 struct qla_hw_data *ha = vha->hw; 1210 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1211 1212 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1213 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1214 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1215 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1216 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1217 1218 msleep(1000); 1219 1220 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1221 ha->flags.chip_reset_done) 1222 break; 1223 } 1224 if (ha->flags.chip_reset_done) 1225 return_status = QLA_SUCCESS; 1226 else 1227 return_status = QLA_FUNCTION_FAILED; 1228 1229 return return_status; 1230 } 1231 1232 /************************************************************************** 1233 * qla2xxx_eh_abort 1234 * 1235 * Description: 1236 * The abort function will abort the specified command. 1237 * 1238 * Input: 1239 * cmd = Linux SCSI command packet to be aborted. 1240 * 1241 * Returns: 1242 * Either SUCCESS or FAILED. 1243 * 1244 * Note: 1245 * Only return FAILED if command not returned by firmware. 1246 **************************************************************************/ 1247 static int qla2xxx_eh_abort(struct scsi_cmnd * cmd)1248 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1249 { 1250 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1251 DECLARE_COMPLETION_ONSTACK(comp); 1252 srb_t *sp; 1253 int ret; 1254 unsigned int id; 1255 uint64_t lun; 1256 int rval; 1257 struct qla_hw_data *ha = vha->hw; 1258 uint32_t ratov_j; 1259 struct qla_qpair *qpair; 1260 unsigned long flags; 1261 int fast_fail_status = SUCCESS; 1262 1263 if (qla2x00_isp_reg_stat(ha)) { 1264 ql_log(ql_log_info, vha, 0x8042, 1265 "PCI/Register disconnect, exiting.\n"); 1266 qla_pci_set_eeh_busy(vha); 1267 return FAILED; 1268 } 1269 1270 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1271 ret = fc_block_scsi_eh(cmd); 1272 if (ret != 0) 1273 fast_fail_status = ret; 1274 1275 sp = scsi_cmd_priv(cmd); 1276 qpair = sp->qpair; 1277 1278 vha->cmd_timeout_cnt++; 1279 1280 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1281 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1282 1283 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1284 sp->comp = ∁ 1285 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1286 1287 1288 id = cmd->device->id; 1289 lun = cmd->device->lun; 1290 1291 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1292 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1293 vha->host_no, id, lun, sp, cmd, sp->handle); 1294 1295 /* 1296 * Abort will release the original Command/sp from FW. Let the 1297 * original command call scsi_done. In return, he will wakeup 1298 * this sleeping thread. 1299 */ 1300 rval = ha->isp_ops->abort_command(sp); 1301 1302 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1303 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1304 1305 /* Wait for the command completion. */ 1306 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1307 ratov_j = msecs_to_jiffies(ratov_j); 1308 switch (rval) { 1309 case QLA_SUCCESS: 1310 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1311 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1312 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1313 __func__, ha->r_a_tov/10); 1314 ret = FAILED; 1315 } else { 1316 ret = fast_fail_status; 1317 } 1318 break; 1319 default: 1320 ret = FAILED; 1321 break; 1322 } 1323 1324 sp->comp = NULL; 1325 1326 ql_log(ql_log_info, vha, 0x801c, 1327 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1328 vha->host_no, id, lun, ret); 1329 1330 return ret; 1331 } 1332 1333 #define ABORT_POLLING_PERIOD 1000 1334 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1335 1336 /* 1337 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1338 */ 1339 static int __qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1340 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1341 uint64_t l, enum nexus_wait_type type) 1342 { 1343 int cnt, match, status; 1344 unsigned long flags; 1345 scsi_qla_host_t *vha = qpair->vha; 1346 struct req_que *req = qpair->req; 1347 srb_t *sp; 1348 struct scsi_cmnd *cmd; 1349 unsigned long wait_iter = ABORT_WAIT_ITER; 1350 bool found; 1351 struct qla_hw_data *ha = vha->hw; 1352 1353 status = QLA_SUCCESS; 1354 1355 while (wait_iter--) { 1356 found = false; 1357 1358 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1359 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1360 sp = req->outstanding_cmds[cnt]; 1361 if (!sp) 1362 continue; 1363 if (sp->type != SRB_SCSI_CMD) 1364 continue; 1365 if (vha->vp_idx != sp->vha->vp_idx) 1366 continue; 1367 match = 0; 1368 cmd = GET_CMD_SP(sp); 1369 switch (type) { 1370 case WAIT_HOST: 1371 match = 1; 1372 break; 1373 case WAIT_TARGET: 1374 if (sp->fcport) 1375 match = sp->fcport->d_id.b24 == t; 1376 else 1377 match = 0; 1378 break; 1379 case WAIT_LUN: 1380 if (sp->fcport) 1381 match = (sp->fcport->d_id.b24 == t && 1382 cmd->device->lun == l); 1383 else 1384 match = 0; 1385 break; 1386 } 1387 if (!match) 1388 continue; 1389 1390 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1391 1392 if (unlikely(pci_channel_offline(ha->pdev)) || 1393 ha->flags.eeh_busy) { 1394 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1395 "Return:eh_wait.\n"); 1396 return status; 1397 } 1398 1399 /* 1400 * SRB_SCSI_CMD is still in the outstanding_cmds array. 1401 * it means scsi_done has not called. Wait for it to 1402 * clear from outstanding_cmds. 1403 */ 1404 msleep(ABORT_POLLING_PERIOD); 1405 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1406 found = true; 1407 } 1408 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1409 1410 if (!found) 1411 break; 1412 } 1413 1414 if (wait_iter == -1) 1415 status = QLA_FUNCTION_FAILED; 1416 1417 return status; 1418 } 1419 1420 int qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1422 uint64_t l, enum nexus_wait_type type) 1423 { 1424 struct qla_qpair *qpair; 1425 struct qla_hw_data *ha = vha->hw; 1426 int i, status = QLA_SUCCESS; 1427 1428 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1429 type); 1430 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1431 qpair = ha->queue_pair_map[i]; 1432 if (!qpair) 1433 continue; 1434 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1435 type); 1436 } 1437 return status; 1438 } 1439 1440 static char *reset_errors[] = { 1441 "HBA not online", 1442 "HBA not ready", 1443 "Task management failed", 1444 "Waiting for command completions", 1445 }; 1446 1447 static int qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1449 { 1450 struct scsi_device *sdev = cmd->device; 1451 scsi_qla_host_t *vha = shost_priv(sdev->host); 1452 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1453 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1454 struct qla_hw_data *ha = vha->hw; 1455 int err; 1456 1457 if (qla2x00_isp_reg_stat(ha)) { 1458 ql_log(ql_log_info, vha, 0x803e, 1459 "PCI/Register disconnect, exiting.\n"); 1460 qla_pci_set_eeh_busy(vha); 1461 return FAILED; 1462 } 1463 1464 if (!fcport) { 1465 return FAILED; 1466 } 1467 1468 err = fc_block_rport(rport); 1469 if (err != 0) 1470 return err; 1471 1472 if (fcport->deleted) 1473 return FAILED; 1474 1475 ql_log(ql_log_info, vha, 0x8009, 1476 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1477 sdev->id, sdev->lun, cmd); 1478 1479 err = 0; 1480 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1481 ql_log(ql_log_warn, vha, 0x800a, 1482 "Wait for hba online failed for cmd=%p.\n", cmd); 1483 goto eh_reset_failed; 1484 } 1485 err = 2; 1486 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1487 != QLA_SUCCESS) { 1488 ql_log(ql_log_warn, vha, 0x800c, 1489 "do_reset failed for cmd=%p.\n", cmd); 1490 goto eh_reset_failed; 1491 } 1492 err = 3; 1493 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 1494 cmd->device->lun, 1495 WAIT_LUN) != QLA_SUCCESS) { 1496 ql_log(ql_log_warn, vha, 0x800d, 1497 "wait for pending cmds failed for cmd=%p.\n", cmd); 1498 goto eh_reset_failed; 1499 } 1500 1501 ql_log(ql_log_info, vha, 0x800e, 1502 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1503 vha->host_no, sdev->id, sdev->lun, cmd); 1504 1505 return SUCCESS; 1506 1507 eh_reset_failed: 1508 ql_log(ql_log_info, vha, 0x800f, 1509 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1510 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1511 cmd); 1512 vha->reset_cmd_err_cnt++; 1513 return FAILED; 1514 } 1515 1516 static int qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1517 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1518 { 1519 struct scsi_device *sdev = cmd->device; 1520 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1521 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1522 struct qla_hw_data *ha = vha->hw; 1523 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1524 int err; 1525 1526 if (qla2x00_isp_reg_stat(ha)) { 1527 ql_log(ql_log_info, vha, 0x803f, 1528 "PCI/Register disconnect, exiting.\n"); 1529 qla_pci_set_eeh_busy(vha); 1530 return FAILED; 1531 } 1532 1533 if (!fcport) { 1534 return FAILED; 1535 } 1536 1537 err = fc_block_rport(rport); 1538 if (err != 0) 1539 return err; 1540 1541 if (fcport->deleted) 1542 return FAILED; 1543 1544 ql_log(ql_log_info, vha, 0x8009, 1545 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1546 sdev->id, cmd); 1547 1548 err = 0; 1549 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1550 ql_log(ql_log_warn, vha, 0x800a, 1551 "Wait for hba online failed for cmd=%p.\n", cmd); 1552 goto eh_reset_failed; 1553 } 1554 err = 2; 1555 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1556 ql_log(ql_log_warn, vha, 0x800c, 1557 "target_reset failed for cmd=%p.\n", cmd); 1558 goto eh_reset_failed; 1559 } 1560 err = 3; 1561 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0, 1562 WAIT_TARGET) != QLA_SUCCESS) { 1563 ql_log(ql_log_warn, vha, 0x800d, 1564 "wait for pending cmds failed for cmd=%p.\n", cmd); 1565 goto eh_reset_failed; 1566 } 1567 1568 ql_log(ql_log_info, vha, 0x800e, 1569 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1570 vha->host_no, sdev->id, cmd); 1571 1572 return SUCCESS; 1573 1574 eh_reset_failed: 1575 ql_log(ql_log_info, vha, 0x800f, 1576 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1577 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1578 cmd); 1579 vha->reset_cmd_err_cnt++; 1580 return FAILED; 1581 } 1582 1583 /************************************************************************** 1584 * qla2xxx_eh_bus_reset 1585 * 1586 * Description: 1587 * The bus reset function will reset the bus and abort any executing 1588 * commands. 1589 * 1590 * Input: 1591 * cmd = Linux SCSI command packet of the command that cause the 1592 * bus reset. 1593 * 1594 * Returns: 1595 * SUCCESS/FAILURE (defined as macro in scsi.h). 1596 * 1597 **************************************************************************/ 1598 static int qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1599 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1600 { 1601 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1602 int ret = FAILED; 1603 unsigned int id; 1604 uint64_t lun; 1605 struct qla_hw_data *ha = vha->hw; 1606 1607 if (qla2x00_isp_reg_stat(ha)) { 1608 ql_log(ql_log_info, vha, 0x8040, 1609 "PCI/Register disconnect, exiting.\n"); 1610 qla_pci_set_eeh_busy(vha); 1611 return FAILED; 1612 } 1613 1614 id = cmd->device->id; 1615 lun = cmd->device->lun; 1616 1617 if (qla2x00_chip_is_down(vha)) 1618 return ret; 1619 1620 ql_log(ql_log_info, vha, 0x8012, 1621 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1622 1623 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1624 ql_log(ql_log_fatal, vha, 0x8013, 1625 "Wait for hba online failed board disabled.\n"); 1626 goto eh_bus_reset_done; 1627 } 1628 1629 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1630 ret = SUCCESS; 1631 1632 if (ret == FAILED) 1633 goto eh_bus_reset_done; 1634 1635 /* Flush outstanding commands. */ 1636 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1637 QLA_SUCCESS) { 1638 ql_log(ql_log_warn, vha, 0x8014, 1639 "Wait for pending commands failed.\n"); 1640 ret = FAILED; 1641 } 1642 1643 eh_bus_reset_done: 1644 ql_log(ql_log_warn, vha, 0x802b, 1645 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1646 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1647 1648 return ret; 1649 } 1650 1651 /************************************************************************** 1652 * qla2xxx_eh_host_reset 1653 * 1654 * Description: 1655 * The reset function will reset the Adapter. 1656 * 1657 * Input: 1658 * cmd = Linux SCSI command packet of the command that cause the 1659 * adapter reset. 1660 * 1661 * Returns: 1662 * Either SUCCESS or FAILED. 1663 * 1664 * Note: 1665 **************************************************************************/ 1666 static int qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1667 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1668 { 1669 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1670 struct qla_hw_data *ha = vha->hw; 1671 int ret = FAILED; 1672 unsigned int id; 1673 uint64_t lun; 1674 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1675 1676 if (qla2x00_isp_reg_stat(ha)) { 1677 ql_log(ql_log_info, vha, 0x8041, 1678 "PCI/Register disconnect, exiting.\n"); 1679 qla_pci_set_eeh_busy(vha); 1680 return SUCCESS; 1681 } 1682 1683 id = cmd->device->id; 1684 lun = cmd->device->lun; 1685 1686 ql_log(ql_log_info, vha, 0x8018, 1687 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1688 1689 /* 1690 * No point in issuing another reset if one is active. Also do not 1691 * attempt a reset if we are updating flash. 1692 */ 1693 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1694 goto eh_host_reset_lock; 1695 1696 if (vha != base_vha) { 1697 if (qla2x00_vp_abort_isp(vha)) 1698 goto eh_host_reset_lock; 1699 } else { 1700 if (IS_P3P_TYPE(vha->hw)) { 1701 if (!qla82xx_fcoe_ctx_reset(vha)) { 1702 /* Ctx reset success */ 1703 ret = SUCCESS; 1704 goto eh_host_reset_lock; 1705 } 1706 /* fall thru if ctx reset failed */ 1707 } 1708 if (ha->wq) 1709 flush_workqueue(ha->wq); 1710 1711 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1712 if (ha->isp_ops->abort_isp(base_vha)) { 1713 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1714 /* failed. schedule dpc to try */ 1715 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1716 1717 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1718 ql_log(ql_log_warn, vha, 0x802a, 1719 "wait for hba online failed.\n"); 1720 goto eh_host_reset_lock; 1721 } 1722 } 1723 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1724 } 1725 1726 /* Waiting for command to be returned to OS.*/ 1727 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1728 QLA_SUCCESS) 1729 ret = SUCCESS; 1730 1731 eh_host_reset_lock: 1732 ql_log(ql_log_info, vha, 0x8017, 1733 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1734 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1735 1736 return ret; 1737 } 1738 1739 /* 1740 * qla2x00_loop_reset 1741 * Issue loop reset. 1742 * 1743 * Input: 1744 * ha = adapter block pointer. 1745 * 1746 * Returns: 1747 * 0 = success 1748 */ 1749 int qla2x00_loop_reset(scsi_qla_host_t * vha)1750 qla2x00_loop_reset(scsi_qla_host_t *vha) 1751 { 1752 int ret; 1753 struct qla_hw_data *ha = vha->hw; 1754 1755 if (IS_QLAFX00(ha)) 1756 return QLA_SUCCESS; 1757 1758 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1759 atomic_set(&vha->loop_state, LOOP_DOWN); 1760 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1761 qla2x00_mark_all_devices_lost(vha); 1762 ret = qla2x00_full_login_lip(vha); 1763 if (ret != QLA_SUCCESS) { 1764 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1765 "full_login_lip=%d.\n", ret); 1766 } 1767 } 1768 1769 if (ha->flags.enable_lip_reset) { 1770 ret = qla2x00_lip_reset(vha); 1771 if (ret != QLA_SUCCESS) 1772 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1773 "lip_reset failed (%d).\n", ret); 1774 } 1775 1776 /* Issue marker command only when we are going to start the I/O */ 1777 vha->marker_needed = 1; 1778 1779 return QLA_SUCCESS; 1780 } 1781 1782 /* 1783 * The caller must ensure that no completion interrupts will happen 1784 * while this function is in progress. 1785 */ qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1786 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1787 unsigned long *flags) 1788 __releases(qp->qp_lock_ptr) 1789 __acquires(qp->qp_lock_ptr) 1790 { 1791 DECLARE_COMPLETION_ONSTACK(comp); 1792 scsi_qla_host_t *vha = qp->vha; 1793 struct qla_hw_data *ha = vha->hw; 1794 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1795 int rval; 1796 bool ret_cmd; 1797 uint32_t ratov_j; 1798 1799 lockdep_assert_held(qp->qp_lock_ptr); 1800 1801 if (qla2x00_chip_is_down(vha)) { 1802 sp->done(sp, res); 1803 return; 1804 } 1805 1806 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1807 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1808 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1809 !qla2x00_isp_reg_stat(ha))) { 1810 if (sp->comp) { 1811 sp->done(sp, res); 1812 return; 1813 } 1814 1815 sp->comp = ∁ 1816 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1817 1818 rval = ha->isp_ops->abort_command(sp); 1819 /* Wait for command completion. */ 1820 ret_cmd = false; 1821 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1822 ratov_j = msecs_to_jiffies(ratov_j); 1823 switch (rval) { 1824 case QLA_SUCCESS: 1825 if (wait_for_completion_timeout(&comp, ratov_j)) { 1826 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1827 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1828 __func__, ha->r_a_tov/10); 1829 ret_cmd = true; 1830 } 1831 /* else FW return SP to driver */ 1832 break; 1833 default: 1834 ret_cmd = true; 1835 break; 1836 } 1837 1838 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1839 switch (sp->type) { 1840 case SRB_SCSI_CMD: 1841 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1842 sp->done(sp, res); 1843 break; 1844 default: 1845 if (ret_cmd) 1846 sp->done(sp, res); 1847 break; 1848 } 1849 } else { 1850 sp->done(sp, res); 1851 } 1852 } 1853 1854 /* 1855 * The caller must ensure that no completion interrupts will happen 1856 * while this function is in progress. 1857 */ 1858 static void __qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1859 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1860 { 1861 int cnt; 1862 unsigned long flags; 1863 srb_t *sp; 1864 scsi_qla_host_t *vha = qp->vha; 1865 struct qla_hw_data *ha = vha->hw; 1866 struct req_que *req; 1867 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1868 struct qla_tgt_cmd *cmd; 1869 1870 if (!ha->req_q_map) 1871 return; 1872 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1873 req = qp->req; 1874 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1875 sp = req->outstanding_cmds[cnt]; 1876 if (sp) { 1877 if (qla2x00_chip_is_down(vha)) { 1878 req->outstanding_cmds[cnt] = NULL; 1879 sp->done(sp, res); 1880 continue; 1881 } 1882 1883 switch (sp->cmd_type) { 1884 case TYPE_SRB: 1885 qla2x00_abort_srb(qp, sp, res, &flags); 1886 break; 1887 case TYPE_TGT_CMD: 1888 if (!vha->hw->tgt.tgt_ops || !tgt || 1889 qla_ini_mode_enabled(vha)) { 1890 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1891 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1892 vha->dpc_flags); 1893 continue; 1894 } 1895 cmd = (struct qla_tgt_cmd *)sp; 1896 cmd->aborted = 1; 1897 break; 1898 case TYPE_TGT_TMCMD: 1899 /* Skip task management functions. */ 1900 break; 1901 default: 1902 break; 1903 } 1904 req->outstanding_cmds[cnt] = NULL; 1905 } 1906 } 1907 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1908 } 1909 1910 /* 1911 * The caller must ensure that no completion interrupts will happen 1912 * while this function is in progress. 1913 */ 1914 void qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1915 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1916 { 1917 int que; 1918 struct qla_hw_data *ha = vha->hw; 1919 1920 /* Continue only if initialization complete. */ 1921 if (!ha->base_qpair) 1922 return; 1923 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1924 1925 if (!ha->queue_pair_map) 1926 return; 1927 for (que = 0; que < ha->max_qpairs; que++) { 1928 if (!ha->queue_pair_map[que]) 1929 continue; 1930 1931 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1932 } 1933 } 1934 1935 static int qla2xxx_slave_alloc(struct scsi_device * sdev)1936 qla2xxx_slave_alloc(struct scsi_device *sdev) 1937 { 1938 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1939 1940 if (!rport || fc_remote_port_chkready(rport)) 1941 return -ENXIO; 1942 1943 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1944 1945 return 0; 1946 } 1947 1948 static int qla2xxx_slave_configure(struct scsi_device * sdev)1949 qla2xxx_slave_configure(struct scsi_device *sdev) 1950 { 1951 scsi_qla_host_t *vha = shost_priv(sdev->host); 1952 struct req_que *req = vha->req; 1953 1954 if (IS_T10_PI_CAPABLE(vha->hw)) 1955 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1956 1957 scsi_change_queue_depth(sdev, req->max_q_depth); 1958 return 0; 1959 } 1960 1961 static void qla2xxx_slave_destroy(struct scsi_device * sdev)1962 qla2xxx_slave_destroy(struct scsi_device *sdev) 1963 { 1964 sdev->hostdata = NULL; 1965 } 1966 1967 /** 1968 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1969 * @ha: HA context 1970 * 1971 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1972 * supported addressing method. 1973 */ 1974 static void qla2x00_config_dma_addressing(struct qla_hw_data * ha)1975 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1976 { 1977 /* Assume a 32bit DMA mask. */ 1978 ha->flags.enable_64bit_addressing = 0; 1979 1980 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1981 /* Any upper-dword bits set? */ 1982 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1983 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1984 /* Ok, a 64bit DMA mask is applicable. */ 1985 ha->flags.enable_64bit_addressing = 1; 1986 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1987 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1988 return; 1989 } 1990 } 1991 1992 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1993 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1994 } 1995 1996 static void qla2x00_enable_intrs(struct qla_hw_data * ha)1997 qla2x00_enable_intrs(struct qla_hw_data *ha) 1998 { 1999 unsigned long flags = 0; 2000 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2001 2002 spin_lock_irqsave(&ha->hardware_lock, flags); 2003 ha->interrupts_on = 1; 2004 /* enable risc and host interrupts */ 2005 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 2006 rd_reg_word(®->ictrl); 2007 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2008 2009 } 2010 2011 static void qla2x00_disable_intrs(struct qla_hw_data * ha)2012 qla2x00_disable_intrs(struct qla_hw_data *ha) 2013 { 2014 unsigned long flags = 0; 2015 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2016 2017 spin_lock_irqsave(&ha->hardware_lock, flags); 2018 ha->interrupts_on = 0; 2019 /* disable risc and host interrupts */ 2020 wrt_reg_word(®->ictrl, 0); 2021 rd_reg_word(®->ictrl); 2022 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2023 } 2024 2025 static void qla24xx_enable_intrs(struct qla_hw_data * ha)2026 qla24xx_enable_intrs(struct qla_hw_data *ha) 2027 { 2028 unsigned long flags = 0; 2029 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2030 2031 spin_lock_irqsave(&ha->hardware_lock, flags); 2032 ha->interrupts_on = 1; 2033 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2034 rd_reg_dword(®->ictrl); 2035 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2036 } 2037 2038 static void qla24xx_disable_intrs(struct qla_hw_data * ha)2039 qla24xx_disable_intrs(struct qla_hw_data *ha) 2040 { 2041 unsigned long flags = 0; 2042 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2043 2044 if (IS_NOPOLLING_TYPE(ha)) 2045 return; 2046 spin_lock_irqsave(&ha->hardware_lock, flags); 2047 ha->interrupts_on = 0; 2048 wrt_reg_dword(®->ictrl, 0); 2049 rd_reg_dword(®->ictrl); 2050 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2051 } 2052 2053 static int qla2x00_iospace_config(struct qla_hw_data * ha)2054 qla2x00_iospace_config(struct qla_hw_data *ha) 2055 { 2056 resource_size_t pio; 2057 uint16_t msix; 2058 2059 if (pci_request_selected_regions(ha->pdev, ha->bars, 2060 QLA2XXX_DRIVER_NAME)) { 2061 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2062 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2063 pci_name(ha->pdev)); 2064 goto iospace_error_exit; 2065 } 2066 if (!(ha->bars & 1)) 2067 goto skip_pio; 2068 2069 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2070 pio = pci_resource_start(ha->pdev, 0); 2071 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2072 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2073 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2074 "Invalid pci I/O region size (%s).\n", 2075 pci_name(ha->pdev)); 2076 pio = 0; 2077 } 2078 } else { 2079 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2080 "Region #0 no a PIO resource (%s).\n", 2081 pci_name(ha->pdev)); 2082 pio = 0; 2083 } 2084 ha->pio_address = pio; 2085 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2086 "PIO address=%llu.\n", 2087 (unsigned long long)ha->pio_address); 2088 2089 skip_pio: 2090 /* Use MMIO operations for all accesses. */ 2091 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2092 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2093 "Region #1 not an MMIO resource (%s), aborting.\n", 2094 pci_name(ha->pdev)); 2095 goto iospace_error_exit; 2096 } 2097 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2098 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2099 "Invalid PCI mem region size (%s), aborting.\n", 2100 pci_name(ha->pdev)); 2101 goto iospace_error_exit; 2102 } 2103 2104 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2105 if (!ha->iobase) { 2106 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2107 "Cannot remap MMIO (%s), aborting.\n", 2108 pci_name(ha->pdev)); 2109 goto iospace_error_exit; 2110 } 2111 2112 /* Determine queue resources */ 2113 ha->max_req_queues = ha->max_rsp_queues = 1; 2114 ha->msix_count = QLA_BASE_VECTORS; 2115 2116 /* Check if FW supports MQ or not */ 2117 if (!(ha->fw_attributes & BIT_6)) 2118 goto mqiobase_exit; 2119 2120 if (!ql2xmqsupport || !ql2xnvmeenable || 2121 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2122 goto mqiobase_exit; 2123 2124 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2125 pci_resource_len(ha->pdev, 3)); 2126 if (ha->mqiobase) { 2127 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2128 "MQIO Base=%p.\n", ha->mqiobase); 2129 /* Read MSIX vector size of the board */ 2130 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2131 ha->msix_count = msix + 1; 2132 /* Max queues are bounded by available msix vectors */ 2133 /* MB interrupt uses 1 vector */ 2134 ha->max_req_queues = ha->msix_count - 1; 2135 ha->max_rsp_queues = ha->max_req_queues; 2136 /* Queue pairs is the max value minus the base queue pair */ 2137 ha->max_qpairs = ha->max_rsp_queues - 1; 2138 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2139 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2140 2141 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2142 "MSI-X vector count: %d.\n", ha->msix_count); 2143 } else 2144 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2145 "BAR 3 not enabled.\n"); 2146 2147 mqiobase_exit: 2148 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2149 "MSIX Count: %d.\n", ha->msix_count); 2150 return (0); 2151 2152 iospace_error_exit: 2153 return (-ENOMEM); 2154 } 2155 2156 2157 static int qla83xx_iospace_config(struct qla_hw_data * ha)2158 qla83xx_iospace_config(struct qla_hw_data *ha) 2159 { 2160 uint16_t msix; 2161 2162 if (pci_request_selected_regions(ha->pdev, ha->bars, 2163 QLA2XXX_DRIVER_NAME)) { 2164 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2165 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2166 pci_name(ha->pdev)); 2167 2168 goto iospace_error_exit; 2169 } 2170 2171 /* Use MMIO operations for all accesses. */ 2172 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2173 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2174 "Invalid pci I/O region size (%s).\n", 2175 pci_name(ha->pdev)); 2176 goto iospace_error_exit; 2177 } 2178 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2179 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2180 "Invalid PCI mem region size (%s), aborting\n", 2181 pci_name(ha->pdev)); 2182 goto iospace_error_exit; 2183 } 2184 2185 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2186 if (!ha->iobase) { 2187 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2188 "Cannot remap MMIO (%s), aborting.\n", 2189 pci_name(ha->pdev)); 2190 goto iospace_error_exit; 2191 } 2192 2193 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2194 /* 83XX 26XX always use MQ type access for queues 2195 * - mbar 2, a.k.a region 4 */ 2196 ha->max_req_queues = ha->max_rsp_queues = 1; 2197 ha->msix_count = QLA_BASE_VECTORS; 2198 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2199 pci_resource_len(ha->pdev, 4)); 2200 2201 if (!ha->mqiobase) { 2202 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2203 "BAR2/region4 not enabled\n"); 2204 goto mqiobase_exit; 2205 } 2206 2207 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2208 pci_resource_len(ha->pdev, 2)); 2209 if (ha->msixbase) { 2210 /* Read MSIX vector size of the board */ 2211 pci_read_config_word(ha->pdev, 2212 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2213 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2214 /* 2215 * By default, driver uses at least two msix vectors 2216 * (default & rspq) 2217 */ 2218 if (ql2xmqsupport || ql2xnvmeenable) { 2219 /* MB interrupt uses 1 vector */ 2220 ha->max_req_queues = ha->msix_count - 1; 2221 2222 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2223 if (QLA_TGT_MODE_ENABLED()) 2224 ha->max_req_queues--; 2225 2226 ha->max_rsp_queues = ha->max_req_queues; 2227 2228 /* Queue pairs is the max value minus 2229 * the base queue pair */ 2230 ha->max_qpairs = ha->max_req_queues - 1; 2231 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2232 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2233 } 2234 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2235 "MSI-X vector count: %d.\n", ha->msix_count); 2236 } else 2237 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2238 "BAR 1 not enabled.\n"); 2239 2240 mqiobase_exit: 2241 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2242 "MSIX Count: %d.\n", ha->msix_count); 2243 return 0; 2244 2245 iospace_error_exit: 2246 return -ENOMEM; 2247 } 2248 2249 static struct isp_operations qla2100_isp_ops = { 2250 .pci_config = qla2100_pci_config, 2251 .reset_chip = qla2x00_reset_chip, 2252 .chip_diag = qla2x00_chip_diag, 2253 .config_rings = qla2x00_config_rings, 2254 .reset_adapter = qla2x00_reset_adapter, 2255 .nvram_config = qla2x00_nvram_config, 2256 .update_fw_options = qla2x00_update_fw_options, 2257 .load_risc = qla2x00_load_risc, 2258 .pci_info_str = qla2x00_pci_info_str, 2259 .fw_version_str = qla2x00_fw_version_str, 2260 .intr_handler = qla2100_intr_handler, 2261 .enable_intrs = qla2x00_enable_intrs, 2262 .disable_intrs = qla2x00_disable_intrs, 2263 .abort_command = qla2x00_abort_command, 2264 .target_reset = qla2x00_abort_target, 2265 .lun_reset = qla2x00_lun_reset, 2266 .fabric_login = qla2x00_login_fabric, 2267 .fabric_logout = qla2x00_fabric_logout, 2268 .calc_req_entries = qla2x00_calc_iocbs_32, 2269 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2270 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2271 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2272 .read_nvram = qla2x00_read_nvram_data, 2273 .write_nvram = qla2x00_write_nvram_data, 2274 .fw_dump = qla2100_fw_dump, 2275 .beacon_on = NULL, 2276 .beacon_off = NULL, 2277 .beacon_blink = NULL, 2278 .read_optrom = qla2x00_read_optrom_data, 2279 .write_optrom = qla2x00_write_optrom_data, 2280 .get_flash_version = qla2x00_get_flash_version, 2281 .start_scsi = qla2x00_start_scsi, 2282 .start_scsi_mq = NULL, 2283 .abort_isp = qla2x00_abort_isp, 2284 .iospace_config = qla2x00_iospace_config, 2285 .initialize_adapter = qla2x00_initialize_adapter, 2286 }; 2287 2288 static struct isp_operations qla2300_isp_ops = { 2289 .pci_config = qla2300_pci_config, 2290 .reset_chip = qla2x00_reset_chip, 2291 .chip_diag = qla2x00_chip_diag, 2292 .config_rings = qla2x00_config_rings, 2293 .reset_adapter = qla2x00_reset_adapter, 2294 .nvram_config = qla2x00_nvram_config, 2295 .update_fw_options = qla2x00_update_fw_options, 2296 .load_risc = qla2x00_load_risc, 2297 .pci_info_str = qla2x00_pci_info_str, 2298 .fw_version_str = qla2x00_fw_version_str, 2299 .intr_handler = qla2300_intr_handler, 2300 .enable_intrs = qla2x00_enable_intrs, 2301 .disable_intrs = qla2x00_disable_intrs, 2302 .abort_command = qla2x00_abort_command, 2303 .target_reset = qla2x00_abort_target, 2304 .lun_reset = qla2x00_lun_reset, 2305 .fabric_login = qla2x00_login_fabric, 2306 .fabric_logout = qla2x00_fabric_logout, 2307 .calc_req_entries = qla2x00_calc_iocbs_32, 2308 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2309 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2310 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2311 .read_nvram = qla2x00_read_nvram_data, 2312 .write_nvram = qla2x00_write_nvram_data, 2313 .fw_dump = qla2300_fw_dump, 2314 .beacon_on = qla2x00_beacon_on, 2315 .beacon_off = qla2x00_beacon_off, 2316 .beacon_blink = qla2x00_beacon_blink, 2317 .read_optrom = qla2x00_read_optrom_data, 2318 .write_optrom = qla2x00_write_optrom_data, 2319 .get_flash_version = qla2x00_get_flash_version, 2320 .start_scsi = qla2x00_start_scsi, 2321 .start_scsi_mq = NULL, 2322 .abort_isp = qla2x00_abort_isp, 2323 .iospace_config = qla2x00_iospace_config, 2324 .initialize_adapter = qla2x00_initialize_adapter, 2325 }; 2326 2327 static struct isp_operations qla24xx_isp_ops = { 2328 .pci_config = qla24xx_pci_config, 2329 .reset_chip = qla24xx_reset_chip, 2330 .chip_diag = qla24xx_chip_diag, 2331 .config_rings = qla24xx_config_rings, 2332 .reset_adapter = qla24xx_reset_adapter, 2333 .nvram_config = qla24xx_nvram_config, 2334 .update_fw_options = qla24xx_update_fw_options, 2335 .load_risc = qla24xx_load_risc, 2336 .pci_info_str = qla24xx_pci_info_str, 2337 .fw_version_str = qla24xx_fw_version_str, 2338 .intr_handler = qla24xx_intr_handler, 2339 .enable_intrs = qla24xx_enable_intrs, 2340 .disable_intrs = qla24xx_disable_intrs, 2341 .abort_command = qla24xx_abort_command, 2342 .target_reset = qla24xx_abort_target, 2343 .lun_reset = qla24xx_lun_reset, 2344 .fabric_login = qla24xx_login_fabric, 2345 .fabric_logout = qla24xx_fabric_logout, 2346 .calc_req_entries = NULL, 2347 .build_iocbs = NULL, 2348 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2349 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2350 .read_nvram = qla24xx_read_nvram_data, 2351 .write_nvram = qla24xx_write_nvram_data, 2352 .fw_dump = qla24xx_fw_dump, 2353 .beacon_on = qla24xx_beacon_on, 2354 .beacon_off = qla24xx_beacon_off, 2355 .beacon_blink = qla24xx_beacon_blink, 2356 .read_optrom = qla24xx_read_optrom_data, 2357 .write_optrom = qla24xx_write_optrom_data, 2358 .get_flash_version = qla24xx_get_flash_version, 2359 .start_scsi = qla24xx_start_scsi, 2360 .start_scsi_mq = NULL, 2361 .abort_isp = qla2x00_abort_isp, 2362 .iospace_config = qla2x00_iospace_config, 2363 .initialize_adapter = qla2x00_initialize_adapter, 2364 }; 2365 2366 static struct isp_operations qla25xx_isp_ops = { 2367 .pci_config = qla25xx_pci_config, 2368 .reset_chip = qla24xx_reset_chip, 2369 .chip_diag = qla24xx_chip_diag, 2370 .config_rings = qla24xx_config_rings, 2371 .reset_adapter = qla24xx_reset_adapter, 2372 .nvram_config = qla24xx_nvram_config, 2373 .update_fw_options = qla24xx_update_fw_options, 2374 .load_risc = qla24xx_load_risc, 2375 .pci_info_str = qla24xx_pci_info_str, 2376 .fw_version_str = qla24xx_fw_version_str, 2377 .intr_handler = qla24xx_intr_handler, 2378 .enable_intrs = qla24xx_enable_intrs, 2379 .disable_intrs = qla24xx_disable_intrs, 2380 .abort_command = qla24xx_abort_command, 2381 .target_reset = qla24xx_abort_target, 2382 .lun_reset = qla24xx_lun_reset, 2383 .fabric_login = qla24xx_login_fabric, 2384 .fabric_logout = qla24xx_fabric_logout, 2385 .calc_req_entries = NULL, 2386 .build_iocbs = NULL, 2387 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2388 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2389 .read_nvram = qla25xx_read_nvram_data, 2390 .write_nvram = qla25xx_write_nvram_data, 2391 .fw_dump = qla25xx_fw_dump, 2392 .beacon_on = qla24xx_beacon_on, 2393 .beacon_off = qla24xx_beacon_off, 2394 .beacon_blink = qla24xx_beacon_blink, 2395 .read_optrom = qla25xx_read_optrom_data, 2396 .write_optrom = qla24xx_write_optrom_data, 2397 .get_flash_version = qla24xx_get_flash_version, 2398 .start_scsi = qla24xx_dif_start_scsi, 2399 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2400 .abort_isp = qla2x00_abort_isp, 2401 .iospace_config = qla2x00_iospace_config, 2402 .initialize_adapter = qla2x00_initialize_adapter, 2403 }; 2404 2405 static struct isp_operations qla81xx_isp_ops = { 2406 .pci_config = qla25xx_pci_config, 2407 .reset_chip = qla24xx_reset_chip, 2408 .chip_diag = qla24xx_chip_diag, 2409 .config_rings = qla24xx_config_rings, 2410 .reset_adapter = qla24xx_reset_adapter, 2411 .nvram_config = qla81xx_nvram_config, 2412 .update_fw_options = qla24xx_update_fw_options, 2413 .load_risc = qla81xx_load_risc, 2414 .pci_info_str = qla24xx_pci_info_str, 2415 .fw_version_str = qla24xx_fw_version_str, 2416 .intr_handler = qla24xx_intr_handler, 2417 .enable_intrs = qla24xx_enable_intrs, 2418 .disable_intrs = qla24xx_disable_intrs, 2419 .abort_command = qla24xx_abort_command, 2420 .target_reset = qla24xx_abort_target, 2421 .lun_reset = qla24xx_lun_reset, 2422 .fabric_login = qla24xx_login_fabric, 2423 .fabric_logout = qla24xx_fabric_logout, 2424 .calc_req_entries = NULL, 2425 .build_iocbs = NULL, 2426 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2427 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2428 .read_nvram = NULL, 2429 .write_nvram = NULL, 2430 .fw_dump = qla81xx_fw_dump, 2431 .beacon_on = qla24xx_beacon_on, 2432 .beacon_off = qla24xx_beacon_off, 2433 .beacon_blink = qla83xx_beacon_blink, 2434 .read_optrom = qla25xx_read_optrom_data, 2435 .write_optrom = qla24xx_write_optrom_data, 2436 .get_flash_version = qla24xx_get_flash_version, 2437 .start_scsi = qla24xx_dif_start_scsi, 2438 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2439 .abort_isp = qla2x00_abort_isp, 2440 .iospace_config = qla2x00_iospace_config, 2441 .initialize_adapter = qla2x00_initialize_adapter, 2442 }; 2443 2444 static struct isp_operations qla82xx_isp_ops = { 2445 .pci_config = qla82xx_pci_config, 2446 .reset_chip = qla82xx_reset_chip, 2447 .chip_diag = qla24xx_chip_diag, 2448 .config_rings = qla82xx_config_rings, 2449 .reset_adapter = qla24xx_reset_adapter, 2450 .nvram_config = qla81xx_nvram_config, 2451 .update_fw_options = qla24xx_update_fw_options, 2452 .load_risc = qla82xx_load_risc, 2453 .pci_info_str = qla24xx_pci_info_str, 2454 .fw_version_str = qla24xx_fw_version_str, 2455 .intr_handler = qla82xx_intr_handler, 2456 .enable_intrs = qla82xx_enable_intrs, 2457 .disable_intrs = qla82xx_disable_intrs, 2458 .abort_command = qla24xx_abort_command, 2459 .target_reset = qla24xx_abort_target, 2460 .lun_reset = qla24xx_lun_reset, 2461 .fabric_login = qla24xx_login_fabric, 2462 .fabric_logout = qla24xx_fabric_logout, 2463 .calc_req_entries = NULL, 2464 .build_iocbs = NULL, 2465 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2466 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2467 .read_nvram = qla24xx_read_nvram_data, 2468 .write_nvram = qla24xx_write_nvram_data, 2469 .fw_dump = qla82xx_fw_dump, 2470 .beacon_on = qla82xx_beacon_on, 2471 .beacon_off = qla82xx_beacon_off, 2472 .beacon_blink = NULL, 2473 .read_optrom = qla82xx_read_optrom_data, 2474 .write_optrom = qla82xx_write_optrom_data, 2475 .get_flash_version = qla82xx_get_flash_version, 2476 .start_scsi = qla82xx_start_scsi, 2477 .start_scsi_mq = NULL, 2478 .abort_isp = qla82xx_abort_isp, 2479 .iospace_config = qla82xx_iospace_config, 2480 .initialize_adapter = qla2x00_initialize_adapter, 2481 }; 2482 2483 static struct isp_operations qla8044_isp_ops = { 2484 .pci_config = qla82xx_pci_config, 2485 .reset_chip = qla82xx_reset_chip, 2486 .chip_diag = qla24xx_chip_diag, 2487 .config_rings = qla82xx_config_rings, 2488 .reset_adapter = qla24xx_reset_adapter, 2489 .nvram_config = qla81xx_nvram_config, 2490 .update_fw_options = qla24xx_update_fw_options, 2491 .load_risc = qla82xx_load_risc, 2492 .pci_info_str = qla24xx_pci_info_str, 2493 .fw_version_str = qla24xx_fw_version_str, 2494 .intr_handler = qla8044_intr_handler, 2495 .enable_intrs = qla82xx_enable_intrs, 2496 .disable_intrs = qla82xx_disable_intrs, 2497 .abort_command = qla24xx_abort_command, 2498 .target_reset = qla24xx_abort_target, 2499 .lun_reset = qla24xx_lun_reset, 2500 .fabric_login = qla24xx_login_fabric, 2501 .fabric_logout = qla24xx_fabric_logout, 2502 .calc_req_entries = NULL, 2503 .build_iocbs = NULL, 2504 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2505 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2506 .read_nvram = NULL, 2507 .write_nvram = NULL, 2508 .fw_dump = qla8044_fw_dump, 2509 .beacon_on = qla82xx_beacon_on, 2510 .beacon_off = qla82xx_beacon_off, 2511 .beacon_blink = NULL, 2512 .read_optrom = qla8044_read_optrom_data, 2513 .write_optrom = qla8044_write_optrom_data, 2514 .get_flash_version = qla82xx_get_flash_version, 2515 .start_scsi = qla82xx_start_scsi, 2516 .start_scsi_mq = NULL, 2517 .abort_isp = qla8044_abort_isp, 2518 .iospace_config = qla82xx_iospace_config, 2519 .initialize_adapter = qla2x00_initialize_adapter, 2520 }; 2521 2522 static struct isp_operations qla83xx_isp_ops = { 2523 .pci_config = qla25xx_pci_config, 2524 .reset_chip = qla24xx_reset_chip, 2525 .chip_diag = qla24xx_chip_diag, 2526 .config_rings = qla24xx_config_rings, 2527 .reset_adapter = qla24xx_reset_adapter, 2528 .nvram_config = qla81xx_nvram_config, 2529 .update_fw_options = qla24xx_update_fw_options, 2530 .load_risc = qla81xx_load_risc, 2531 .pci_info_str = qla24xx_pci_info_str, 2532 .fw_version_str = qla24xx_fw_version_str, 2533 .intr_handler = qla24xx_intr_handler, 2534 .enable_intrs = qla24xx_enable_intrs, 2535 .disable_intrs = qla24xx_disable_intrs, 2536 .abort_command = qla24xx_abort_command, 2537 .target_reset = qla24xx_abort_target, 2538 .lun_reset = qla24xx_lun_reset, 2539 .fabric_login = qla24xx_login_fabric, 2540 .fabric_logout = qla24xx_fabric_logout, 2541 .calc_req_entries = NULL, 2542 .build_iocbs = NULL, 2543 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2544 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2545 .read_nvram = NULL, 2546 .write_nvram = NULL, 2547 .fw_dump = qla83xx_fw_dump, 2548 .beacon_on = qla24xx_beacon_on, 2549 .beacon_off = qla24xx_beacon_off, 2550 .beacon_blink = qla83xx_beacon_blink, 2551 .read_optrom = qla25xx_read_optrom_data, 2552 .write_optrom = qla24xx_write_optrom_data, 2553 .get_flash_version = qla24xx_get_flash_version, 2554 .start_scsi = qla24xx_dif_start_scsi, 2555 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2556 .abort_isp = qla2x00_abort_isp, 2557 .iospace_config = qla83xx_iospace_config, 2558 .initialize_adapter = qla2x00_initialize_adapter, 2559 }; 2560 2561 static struct isp_operations qlafx00_isp_ops = { 2562 .pci_config = qlafx00_pci_config, 2563 .reset_chip = qlafx00_soft_reset, 2564 .chip_diag = qlafx00_chip_diag, 2565 .config_rings = qlafx00_config_rings, 2566 .reset_adapter = qlafx00_soft_reset, 2567 .nvram_config = NULL, 2568 .update_fw_options = NULL, 2569 .load_risc = NULL, 2570 .pci_info_str = qlafx00_pci_info_str, 2571 .fw_version_str = qlafx00_fw_version_str, 2572 .intr_handler = qlafx00_intr_handler, 2573 .enable_intrs = qlafx00_enable_intrs, 2574 .disable_intrs = qlafx00_disable_intrs, 2575 .abort_command = qla24xx_async_abort_command, 2576 .target_reset = qlafx00_abort_target, 2577 .lun_reset = qlafx00_lun_reset, 2578 .fabric_login = NULL, 2579 .fabric_logout = NULL, 2580 .calc_req_entries = NULL, 2581 .build_iocbs = NULL, 2582 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2583 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2584 .read_nvram = qla24xx_read_nvram_data, 2585 .write_nvram = qla24xx_write_nvram_data, 2586 .fw_dump = NULL, 2587 .beacon_on = qla24xx_beacon_on, 2588 .beacon_off = qla24xx_beacon_off, 2589 .beacon_blink = NULL, 2590 .read_optrom = qla24xx_read_optrom_data, 2591 .write_optrom = qla24xx_write_optrom_data, 2592 .get_flash_version = qla24xx_get_flash_version, 2593 .start_scsi = qlafx00_start_scsi, 2594 .start_scsi_mq = NULL, 2595 .abort_isp = qlafx00_abort_isp, 2596 .iospace_config = qlafx00_iospace_config, 2597 .initialize_adapter = qlafx00_initialize_adapter, 2598 }; 2599 2600 static struct isp_operations qla27xx_isp_ops = { 2601 .pci_config = qla25xx_pci_config, 2602 .reset_chip = qla24xx_reset_chip, 2603 .chip_diag = qla24xx_chip_diag, 2604 .config_rings = qla24xx_config_rings, 2605 .reset_adapter = qla24xx_reset_adapter, 2606 .nvram_config = qla81xx_nvram_config, 2607 .update_fw_options = qla24xx_update_fw_options, 2608 .load_risc = qla81xx_load_risc, 2609 .pci_info_str = qla24xx_pci_info_str, 2610 .fw_version_str = qla24xx_fw_version_str, 2611 .intr_handler = qla24xx_intr_handler, 2612 .enable_intrs = qla24xx_enable_intrs, 2613 .disable_intrs = qla24xx_disable_intrs, 2614 .abort_command = qla24xx_abort_command, 2615 .target_reset = qla24xx_abort_target, 2616 .lun_reset = qla24xx_lun_reset, 2617 .fabric_login = qla24xx_login_fabric, 2618 .fabric_logout = qla24xx_fabric_logout, 2619 .calc_req_entries = NULL, 2620 .build_iocbs = NULL, 2621 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2622 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2623 .read_nvram = NULL, 2624 .write_nvram = NULL, 2625 .fw_dump = qla27xx_fwdump, 2626 .mpi_fw_dump = qla27xx_mpi_fwdump, 2627 .beacon_on = qla24xx_beacon_on, 2628 .beacon_off = qla24xx_beacon_off, 2629 .beacon_blink = qla83xx_beacon_blink, 2630 .read_optrom = qla25xx_read_optrom_data, 2631 .write_optrom = qla24xx_write_optrom_data, 2632 .get_flash_version = qla24xx_get_flash_version, 2633 .start_scsi = qla24xx_dif_start_scsi, 2634 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2635 .abort_isp = qla2x00_abort_isp, 2636 .iospace_config = qla83xx_iospace_config, 2637 .initialize_adapter = qla2x00_initialize_adapter, 2638 }; 2639 2640 static inline void qla2x00_set_isp_flags(struct qla_hw_data * ha)2641 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2642 { 2643 ha->device_type = DT_EXTENDED_IDS; 2644 switch (ha->pdev->device) { 2645 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2646 ha->isp_type |= DT_ISP2100; 2647 ha->device_type &= ~DT_EXTENDED_IDS; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2651 ha->isp_type |= DT_ISP2200; 2652 ha->device_type &= ~DT_EXTENDED_IDS; 2653 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2654 break; 2655 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2656 ha->isp_type |= DT_ISP2300; 2657 ha->device_type |= DT_ZIO_SUPPORTED; 2658 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2659 break; 2660 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2661 ha->isp_type |= DT_ISP2312; 2662 ha->device_type |= DT_ZIO_SUPPORTED; 2663 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2664 break; 2665 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2666 ha->isp_type |= DT_ISP2322; 2667 ha->device_type |= DT_ZIO_SUPPORTED; 2668 if (ha->pdev->subsystem_vendor == 0x1028 && 2669 ha->pdev->subsystem_device == 0x0170) 2670 ha->device_type |= DT_OEM_001; 2671 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2672 break; 2673 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2674 ha->isp_type |= DT_ISP6312; 2675 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2676 break; 2677 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2678 ha->isp_type |= DT_ISP6322; 2679 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2680 break; 2681 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2682 ha->isp_type |= DT_ISP2422; 2683 ha->device_type |= DT_ZIO_SUPPORTED; 2684 ha->device_type |= DT_FWI2; 2685 ha->device_type |= DT_IIDMA; 2686 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2687 break; 2688 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2689 ha->isp_type |= DT_ISP2432; 2690 ha->device_type |= DT_ZIO_SUPPORTED; 2691 ha->device_type |= DT_FWI2; 2692 ha->device_type |= DT_IIDMA; 2693 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2694 break; 2695 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2696 ha->isp_type |= DT_ISP8432; 2697 ha->device_type |= DT_ZIO_SUPPORTED; 2698 ha->device_type |= DT_FWI2; 2699 ha->device_type |= DT_IIDMA; 2700 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2701 break; 2702 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2703 ha->isp_type |= DT_ISP5422; 2704 ha->device_type |= DT_FWI2; 2705 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2706 break; 2707 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2708 ha->isp_type |= DT_ISP5432; 2709 ha->device_type |= DT_FWI2; 2710 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2711 break; 2712 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2713 ha->isp_type |= DT_ISP2532; 2714 ha->device_type |= DT_ZIO_SUPPORTED; 2715 ha->device_type |= DT_FWI2; 2716 ha->device_type |= DT_IIDMA; 2717 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2718 break; 2719 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2720 ha->isp_type |= DT_ISP8001; 2721 ha->device_type |= DT_ZIO_SUPPORTED; 2722 ha->device_type |= DT_FWI2; 2723 ha->device_type |= DT_IIDMA; 2724 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2725 break; 2726 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2727 ha->isp_type |= DT_ISP8021; 2728 ha->device_type |= DT_ZIO_SUPPORTED; 2729 ha->device_type |= DT_FWI2; 2730 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2731 /* Initialize 82XX ISP flags */ 2732 qla82xx_init_flags(ha); 2733 break; 2734 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2735 ha->isp_type |= DT_ISP8044; 2736 ha->device_type |= DT_ZIO_SUPPORTED; 2737 ha->device_type |= DT_FWI2; 2738 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2739 /* Initialize 82XX ISP flags */ 2740 qla82xx_init_flags(ha); 2741 break; 2742 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2743 ha->isp_type |= DT_ISP2031; 2744 ha->device_type |= DT_ZIO_SUPPORTED; 2745 ha->device_type |= DT_FWI2; 2746 ha->device_type |= DT_IIDMA; 2747 ha->device_type |= DT_T10_PI; 2748 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2749 break; 2750 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2751 ha->isp_type |= DT_ISP8031; 2752 ha->device_type |= DT_ZIO_SUPPORTED; 2753 ha->device_type |= DT_FWI2; 2754 ha->device_type |= DT_IIDMA; 2755 ha->device_type |= DT_T10_PI; 2756 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2757 break; 2758 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2759 ha->isp_type |= DT_ISPFX00; 2760 break; 2761 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2762 ha->isp_type |= DT_ISP2071; 2763 ha->device_type |= DT_ZIO_SUPPORTED; 2764 ha->device_type |= DT_FWI2; 2765 ha->device_type |= DT_IIDMA; 2766 ha->device_type |= DT_T10_PI; 2767 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2768 break; 2769 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2770 ha->isp_type |= DT_ISP2271; 2771 ha->device_type |= DT_ZIO_SUPPORTED; 2772 ha->device_type |= DT_FWI2; 2773 ha->device_type |= DT_IIDMA; 2774 ha->device_type |= DT_T10_PI; 2775 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2776 break; 2777 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2778 ha->isp_type |= DT_ISP2261; 2779 ha->device_type |= DT_ZIO_SUPPORTED; 2780 ha->device_type |= DT_FWI2; 2781 ha->device_type |= DT_IIDMA; 2782 ha->device_type |= DT_T10_PI; 2783 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2784 break; 2785 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2786 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2787 ha->isp_type |= DT_ISP2081; 2788 ha->device_type |= DT_ZIO_SUPPORTED; 2789 ha->device_type |= DT_FWI2; 2790 ha->device_type |= DT_IIDMA; 2791 ha->device_type |= DT_T10_PI; 2792 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2793 break; 2794 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2795 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2796 ha->isp_type |= DT_ISP2281; 2797 ha->device_type |= DT_ZIO_SUPPORTED; 2798 ha->device_type |= DT_FWI2; 2799 ha->device_type |= DT_IIDMA; 2800 ha->device_type |= DT_T10_PI; 2801 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2802 break; 2803 } 2804 2805 if (IS_QLA82XX(ha)) 2806 ha->port_no = ha->portnum & 1; 2807 else { 2808 /* Get adapter physical port no from interrupt pin register. */ 2809 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2810 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2811 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2812 ha->port_no--; 2813 else 2814 ha->port_no = !(ha->port_no & 1); 2815 } 2816 2817 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2818 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2819 ha->device_type, ha->port_no, ha->fw_srisc_address); 2820 } 2821 2822 static void qla2xxx_scan_start(struct Scsi_Host * shost)2823 qla2xxx_scan_start(struct Scsi_Host *shost) 2824 { 2825 scsi_qla_host_t *vha = shost_priv(shost); 2826 2827 if (vha->hw->flags.running_gold_fw) 2828 return; 2829 2830 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2831 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2832 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2833 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2834 } 2835 2836 static int qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2837 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2838 { 2839 scsi_qla_host_t *vha = shost_priv(shost); 2840 2841 if (test_bit(UNLOADING, &vha->dpc_flags)) 2842 return 1; 2843 if (!vha->host) 2844 return 1; 2845 if (time > vha->hw->loop_reset_delay * HZ) 2846 return 1; 2847 2848 return atomic_read(&vha->loop_state) == LOOP_READY; 2849 } 2850 qla_heartbeat_work_fn(struct work_struct * work)2851 static void qla_heartbeat_work_fn(struct work_struct *work) 2852 { 2853 struct qla_hw_data *ha = container_of(work, 2854 struct qla_hw_data, heartbeat_work); 2855 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2856 2857 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2858 qla_no_op_mb(base_vha); 2859 } 2860 qla2x00_iocb_work_fn(struct work_struct * work)2861 static void qla2x00_iocb_work_fn(struct work_struct *work) 2862 { 2863 struct scsi_qla_host *vha = container_of(work, 2864 struct scsi_qla_host, iocb_work); 2865 struct qla_hw_data *ha = vha->hw; 2866 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2867 int i = 2; 2868 unsigned long flags; 2869 2870 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2871 return; 2872 2873 while (!list_empty(&vha->work_list) && i > 0) { 2874 qla2x00_do_work(vha); 2875 i--; 2876 } 2877 2878 spin_lock_irqsave(&vha->work_lock, flags); 2879 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2880 spin_unlock_irqrestore(&vha->work_lock, flags); 2881 } 2882 2883 static void qla_trace_init(void)2884 qla_trace_init(void) 2885 { 2886 qla_trc_array = trace_array_get_by_name("qla2xxx"); 2887 if (!qla_trc_array) { 2888 ql_log(ql_log_fatal, NULL, 0x0001, 2889 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2890 return; 2891 } 2892 2893 QLA_TRACE_ENABLE(qla_trc_array); 2894 } 2895 2896 static void qla_trace_uninit(void)2897 qla_trace_uninit(void) 2898 { 2899 if (!qla_trc_array) 2900 return; 2901 trace_array_put(qla_trc_array); 2902 } 2903 2904 /* 2905 * PCI driver interface 2906 */ 2907 static int qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2908 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2909 { 2910 int ret = -ENODEV; 2911 struct Scsi_Host *host; 2912 scsi_qla_host_t *base_vha = NULL; 2913 struct qla_hw_data *ha; 2914 char pci_info[30]; 2915 char fw_str[30], wq_name[30]; 2916 struct scsi_host_template *sht; 2917 int bars, mem_only = 0; 2918 uint16_t req_length = 0, rsp_length = 0; 2919 struct req_que *req = NULL; 2920 struct rsp_que *rsp = NULL; 2921 int i; 2922 2923 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2924 sht = &qla2xxx_driver_template; 2925 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2940 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2941 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2942 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2943 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2944 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2945 mem_only = 1; 2946 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2947 "Mem only adapter.\n"); 2948 } 2949 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2950 "Bars=%d.\n", bars); 2951 2952 if (mem_only) { 2953 if (pci_enable_device_mem(pdev)) 2954 return ret; 2955 } else { 2956 if (pci_enable_device(pdev)) 2957 return ret; 2958 } 2959 2960 if (is_kdump_kernel()) { 2961 ql2xmqsupport = 0; 2962 ql2xallocfwdump = 0; 2963 } 2964 2965 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2966 if (!ha) { 2967 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2968 "Unable to allocate memory for ha.\n"); 2969 goto disable_device; 2970 } 2971 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2972 "Memory allocated for ha=%p.\n", ha); 2973 ha->pdev = pdev; 2974 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2975 spin_lock_init(&ha->tgt.q_full_lock); 2976 spin_lock_init(&ha->tgt.sess_lock); 2977 spin_lock_init(&ha->tgt.atio_lock); 2978 2979 spin_lock_init(&ha->sadb_lock); 2980 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2981 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2982 2983 spin_lock_init(&ha->sadb_fp_lock); 2984 2985 if (qla_edif_sadb_build_free_pool(ha)) { 2986 kfree(ha); 2987 goto disable_device; 2988 } 2989 2990 atomic_set(&ha->nvme_active_aen_cnt, 0); 2991 2992 /* Clear our data area */ 2993 ha->bars = bars; 2994 ha->mem_only = mem_only; 2995 spin_lock_init(&ha->hardware_lock); 2996 spin_lock_init(&ha->vport_slock); 2997 mutex_init(&ha->selflogin_lock); 2998 mutex_init(&ha->optrom_mutex); 2999 3000 /* Set ISP-type information. */ 3001 qla2x00_set_isp_flags(ha); 3002 3003 /* Set EEH reset type to fundamental if required by hba */ 3004 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 3005 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3006 pdev->needs_freset = 1; 3007 3008 ha->prev_topology = 0; 3009 ha->init_cb_size = sizeof(init_cb_t); 3010 ha->link_data_rate = PORT_SPEED_UNKNOWN; 3011 ha->optrom_size = OPTROM_SIZE_2300; 3012 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3013 atomic_set(&ha->num_pend_mbx_stage1, 0); 3014 atomic_set(&ha->num_pend_mbx_stage2, 0); 3015 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3016 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3017 INIT_LIST_HEAD(&ha->tmf_pending); 3018 INIT_LIST_HEAD(&ha->tmf_active); 3019 3020 /* Assign ISP specific operations. */ 3021 if (IS_QLA2100(ha)) { 3022 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3023 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3024 req_length = REQUEST_ENTRY_CNT_2100; 3025 rsp_length = RESPONSE_ENTRY_CNT_2100; 3026 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3027 ha->gid_list_info_size = 4; 3028 ha->flash_conf_off = ~0; 3029 ha->flash_data_off = ~0; 3030 ha->nvram_conf_off = ~0; 3031 ha->nvram_data_off = ~0; 3032 ha->isp_ops = &qla2100_isp_ops; 3033 } else if (IS_QLA2200(ha)) { 3034 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3035 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3036 req_length = REQUEST_ENTRY_CNT_2200; 3037 rsp_length = RESPONSE_ENTRY_CNT_2100; 3038 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3039 ha->gid_list_info_size = 4; 3040 ha->flash_conf_off = ~0; 3041 ha->flash_data_off = ~0; 3042 ha->nvram_conf_off = ~0; 3043 ha->nvram_data_off = ~0; 3044 ha->isp_ops = &qla2100_isp_ops; 3045 } else if (IS_QLA23XX(ha)) { 3046 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3047 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3048 req_length = REQUEST_ENTRY_CNT_2200; 3049 rsp_length = RESPONSE_ENTRY_CNT_2300; 3050 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3051 ha->gid_list_info_size = 6; 3052 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3053 ha->optrom_size = OPTROM_SIZE_2322; 3054 ha->flash_conf_off = ~0; 3055 ha->flash_data_off = ~0; 3056 ha->nvram_conf_off = ~0; 3057 ha->nvram_data_off = ~0; 3058 ha->isp_ops = &qla2300_isp_ops; 3059 } else if (IS_QLA24XX_TYPE(ha)) { 3060 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3061 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3062 req_length = REQUEST_ENTRY_CNT_24XX; 3063 rsp_length = RESPONSE_ENTRY_CNT_2300; 3064 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3065 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3066 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3067 ha->gid_list_info_size = 8; 3068 ha->optrom_size = OPTROM_SIZE_24XX; 3069 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3070 ha->isp_ops = &qla24xx_isp_ops; 3071 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3072 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3073 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3074 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3075 } else if (IS_QLA25XX(ha)) { 3076 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3077 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3078 req_length = REQUEST_ENTRY_CNT_24XX; 3079 rsp_length = RESPONSE_ENTRY_CNT_2300; 3080 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3081 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3082 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3083 ha->gid_list_info_size = 8; 3084 ha->optrom_size = OPTROM_SIZE_25XX; 3085 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3086 ha->isp_ops = &qla25xx_isp_ops; 3087 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3088 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3089 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3090 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3091 } else if (IS_QLA81XX(ha)) { 3092 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3093 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3094 req_length = REQUEST_ENTRY_CNT_24XX; 3095 rsp_length = RESPONSE_ENTRY_CNT_2300; 3096 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3097 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3098 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3099 ha->gid_list_info_size = 8; 3100 ha->optrom_size = OPTROM_SIZE_81XX; 3101 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3102 ha->isp_ops = &qla81xx_isp_ops; 3103 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3104 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3105 ha->nvram_conf_off = ~0; 3106 ha->nvram_data_off = ~0; 3107 } else if (IS_QLA82XX(ha)) { 3108 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3109 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3110 req_length = REQUEST_ENTRY_CNT_82XX; 3111 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3112 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3113 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3114 ha->gid_list_info_size = 8; 3115 ha->optrom_size = OPTROM_SIZE_82XX; 3116 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3117 ha->isp_ops = &qla82xx_isp_ops; 3118 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3119 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3120 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3121 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3122 } else if (IS_QLA8044(ha)) { 3123 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3124 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3125 req_length = REQUEST_ENTRY_CNT_82XX; 3126 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3127 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3128 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3129 ha->gid_list_info_size = 8; 3130 ha->optrom_size = OPTROM_SIZE_83XX; 3131 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3132 ha->isp_ops = &qla8044_isp_ops; 3133 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3134 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3135 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3136 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3137 } else if (IS_QLA83XX(ha)) { 3138 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3139 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3140 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3141 req_length = REQUEST_ENTRY_CNT_83XX; 3142 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3143 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3144 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3145 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3146 ha->gid_list_info_size = 8; 3147 ha->optrom_size = OPTROM_SIZE_83XX; 3148 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3149 ha->isp_ops = &qla83xx_isp_ops; 3150 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3151 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3152 ha->nvram_conf_off = ~0; 3153 ha->nvram_data_off = ~0; 3154 } else if (IS_QLAFX00(ha)) { 3155 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3156 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3157 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3158 req_length = REQUEST_ENTRY_CNT_FX00; 3159 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3160 ha->isp_ops = &qlafx00_isp_ops; 3161 ha->port_down_retry_count = 30; /* default value */ 3162 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3163 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3164 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3165 ha->mr.fw_hbt_en = 1; 3166 ha->mr.host_info_resend = false; 3167 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3168 } else if (IS_QLA27XX(ha)) { 3169 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3170 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3171 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3172 req_length = REQUEST_ENTRY_CNT_83XX; 3173 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3174 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3175 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3176 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3177 ha->gid_list_info_size = 8; 3178 ha->optrom_size = OPTROM_SIZE_83XX; 3179 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3180 ha->isp_ops = &qla27xx_isp_ops; 3181 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3182 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3183 ha->nvram_conf_off = ~0; 3184 ha->nvram_data_off = ~0; 3185 } else if (IS_QLA28XX(ha)) { 3186 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3187 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3188 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3189 req_length = REQUEST_ENTRY_CNT_83XX; 3190 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3191 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3192 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3193 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3194 ha->gid_list_info_size = 8; 3195 ha->optrom_size = OPTROM_SIZE_28XX; 3196 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3197 ha->isp_ops = &qla27xx_isp_ops; 3198 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3199 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3200 ha->nvram_conf_off = ~0; 3201 ha->nvram_data_off = ~0; 3202 } 3203 3204 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3205 "mbx_count=%d, req_length=%d, " 3206 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3207 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3208 "max_fibre_devices=%d.\n", 3209 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3210 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3211 ha->nvram_npiv_size, ha->max_fibre_devices); 3212 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3213 "isp_ops=%p, flash_conf_off=%d, " 3214 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3215 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3216 ha->nvram_conf_off, ha->nvram_data_off); 3217 3218 /* Configure PCI I/O space */ 3219 ret = ha->isp_ops->iospace_config(ha); 3220 if (ret) 3221 goto iospace_config_failed; 3222 3223 ql_log_pci(ql_log_info, pdev, 0x001d, 3224 "Found an ISP%04X irq %d iobase 0x%p.\n", 3225 pdev->device, pdev->irq, ha->iobase); 3226 mutex_init(&ha->vport_lock); 3227 mutex_init(&ha->mq_lock); 3228 init_completion(&ha->mbx_cmd_comp); 3229 complete(&ha->mbx_cmd_comp); 3230 init_completion(&ha->mbx_intr_comp); 3231 init_completion(&ha->dcbx_comp); 3232 init_completion(&ha->lb_portup_comp); 3233 3234 set_bit(0, (unsigned long *) ha->vp_idx_map); 3235 3236 qla2x00_config_dma_addressing(ha); 3237 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3238 "64 Bit addressing is %s.\n", 3239 ha->flags.enable_64bit_addressing ? "enable" : 3240 "disable"); 3241 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3242 if (ret) { 3243 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3244 "Failed to allocate memory for adapter, aborting.\n"); 3245 3246 goto probe_hw_failed; 3247 } 3248 3249 req->max_q_depth = MAX_Q_DEPTH; 3250 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3251 req->max_q_depth = ql2xmaxqdepth; 3252 3253 3254 base_vha = qla2x00_create_host(sht, ha); 3255 if (!base_vha) { 3256 ret = -ENOMEM; 3257 goto probe_hw_failed; 3258 } 3259 3260 pci_set_drvdata(pdev, base_vha); 3261 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3262 3263 host = base_vha->host; 3264 base_vha->req = req; 3265 if (IS_QLA2XXX_MIDTYPE(ha)) 3266 base_vha->mgmt_svr_loop_id = 3267 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3268 else 3269 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3270 base_vha->vp_idx; 3271 3272 /* Setup fcport template structure. */ 3273 ha->mr.fcport.vha = base_vha; 3274 ha->mr.fcport.port_type = FCT_UNKNOWN; 3275 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3276 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3277 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3278 ha->mr.fcport.scan_state = 1; 3279 3280 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3281 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3282 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3283 3284 /* Set the SG table size based on ISP type */ 3285 if (!IS_FWI2_CAPABLE(ha)) { 3286 if (IS_QLA2100(ha)) 3287 host->sg_tablesize = 32; 3288 } else { 3289 if (!IS_QLA82XX(ha)) 3290 host->sg_tablesize = QLA_SG_ALL; 3291 } 3292 host->max_id = ha->max_fibre_devices; 3293 host->cmd_per_lun = 3; 3294 host->unique_id = host->host_no; 3295 3296 if (ql2xenabledif && ql2xenabledif != 2) { 3297 ql_log(ql_log_warn, base_vha, 0x302d, 3298 "Invalid value for ql2xenabledif, resetting it to default (2)\n"); 3299 ql2xenabledif = 2; 3300 } 3301 3302 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3303 host->max_cmd_len = 32; 3304 else 3305 host->max_cmd_len = MAX_CMDSZ; 3306 host->max_channel = MAX_BUSES - 1; 3307 /* Older HBAs support only 16-bit LUNs */ 3308 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3309 ql2xmaxlun > 0xffff) 3310 host->max_lun = 0xffff; 3311 else 3312 host->max_lun = ql2xmaxlun; 3313 host->transportt = qla2xxx_transport_template; 3314 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3315 3316 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3317 "max_id=%d this_id=%d " 3318 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3319 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3320 host->this_id, host->cmd_per_lun, host->unique_id, 3321 host->max_cmd_len, host->max_channel, host->max_lun, 3322 host->transportt, sht->vendor_id); 3323 3324 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3325 3326 /* Set up the irqs */ 3327 ret = qla2x00_request_irqs(ha, rsp); 3328 if (ret) 3329 goto probe_failed; 3330 3331 /* Alloc arrays of request and response ring ptrs */ 3332 ret = qla2x00_alloc_queues(ha, req, rsp); 3333 if (ret) { 3334 ql_log(ql_log_fatal, base_vha, 0x003d, 3335 "Failed to allocate memory for queue pointers..." 3336 "aborting.\n"); 3337 ret = -ENODEV; 3338 goto probe_failed; 3339 } 3340 3341 if (ha->mqenable) { 3342 /* number of hardware queues supported by blk/scsi-mq*/ 3343 host->nr_hw_queues = ha->max_qpairs; 3344 3345 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3346 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3347 } else { 3348 if (ql2xnvmeenable) { 3349 host->nr_hw_queues = ha->max_qpairs; 3350 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3351 "FC-NVMe support is enabled, HW queues=%d\n", 3352 host->nr_hw_queues); 3353 } else { 3354 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3355 "blk/scsi-mq disabled.\n"); 3356 } 3357 } 3358 3359 qlt_probe_one_stage1(base_vha, ha); 3360 3361 pci_save_state(pdev); 3362 3363 /* Assign back pointers */ 3364 rsp->req = req; 3365 req->rsp = rsp; 3366 3367 if (IS_QLAFX00(ha)) { 3368 ha->rsp_q_map[0] = rsp; 3369 ha->req_q_map[0] = req; 3370 set_bit(0, ha->req_qid_map); 3371 set_bit(0, ha->rsp_qid_map); 3372 } 3373 3374 /* FWI2-capable only. */ 3375 req->req_q_in = &ha->iobase->isp24.req_q_in; 3376 req->req_q_out = &ha->iobase->isp24.req_q_out; 3377 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3378 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3379 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3380 IS_QLA28XX(ha)) { 3381 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3382 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3383 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3384 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3385 } 3386 3387 if (IS_QLAFX00(ha)) { 3388 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3389 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3390 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3391 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3392 } 3393 3394 if (IS_P3P_TYPE(ha)) { 3395 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3396 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3397 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3398 } 3399 3400 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3401 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3402 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3403 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3404 "req->req_q_in=%p req->req_q_out=%p " 3405 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3406 req->req_q_in, req->req_q_out, 3407 rsp->rsp_q_in, rsp->rsp_q_out); 3408 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3409 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3410 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3411 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3412 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3413 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3414 3415 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3416 if (unlikely(!ha->wq)) { 3417 ret = -ENOMEM; 3418 goto probe_failed; 3419 } 3420 3421 if (ha->isp_ops->initialize_adapter(base_vha)) { 3422 ql_log(ql_log_fatal, base_vha, 0x00d6, 3423 "Failed to initialize adapter - Adapter flags %x.\n", 3424 base_vha->device_flags); 3425 3426 if (IS_QLA82XX(ha)) { 3427 qla82xx_idc_lock(ha); 3428 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3429 QLA8XXX_DEV_FAILED); 3430 qla82xx_idc_unlock(ha); 3431 ql_log(ql_log_fatal, base_vha, 0x00d7, 3432 "HW State: FAILED.\n"); 3433 } else if (IS_QLA8044(ha)) { 3434 qla8044_idc_lock(ha); 3435 qla8044_wr_direct(base_vha, 3436 QLA8044_CRB_DEV_STATE_INDEX, 3437 QLA8XXX_DEV_FAILED); 3438 qla8044_idc_unlock(ha); 3439 ql_log(ql_log_fatal, base_vha, 0x0150, 3440 "HW State: FAILED.\n"); 3441 } 3442 3443 ret = -ENODEV; 3444 goto probe_failed; 3445 } 3446 3447 if (IS_QLAFX00(ha)) 3448 host->can_queue = QLAFX00_MAX_CANQUEUE; 3449 else 3450 host->can_queue = req->num_outstanding_cmds - 10; 3451 3452 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3453 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3454 host->can_queue, base_vha->req, 3455 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3456 3457 /* Check if FW supports MQ or not for ISP25xx */ 3458 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3459 ha->mqenable = 0; 3460 3461 if (ha->mqenable) { 3462 bool startit = false; 3463 3464 if (QLA_TGT_MODE_ENABLED()) 3465 startit = false; 3466 3467 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3468 startit = true; 3469 3470 /* Create start of day qpairs for Block MQ */ 3471 for (i = 0; i < ha->max_qpairs; i++) 3472 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3473 } 3474 qla_init_iocb_limit(base_vha); 3475 3476 if (ha->flags.running_gold_fw) 3477 goto skip_dpc; 3478 3479 /* 3480 * Startup the kernel thread for this host adapter 3481 */ 3482 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3483 "%s_dpc", base_vha->host_str); 3484 if (IS_ERR(ha->dpc_thread)) { 3485 ql_log(ql_log_fatal, base_vha, 0x00ed, 3486 "Failed to start DPC thread.\n"); 3487 ret = PTR_ERR(ha->dpc_thread); 3488 ha->dpc_thread = NULL; 3489 goto probe_failed; 3490 } 3491 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3492 "DPC thread started successfully.\n"); 3493 3494 /* 3495 * If we're not coming up in initiator mode, we might sit for 3496 * a while without waking up the dpc thread, which leads to a 3497 * stuck process warning. So just kick the dpc once here and 3498 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3499 */ 3500 qla2xxx_wake_dpc(base_vha); 3501 3502 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3503 3504 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3505 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3506 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3507 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3508 3509 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3510 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3511 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3512 INIT_WORK(&ha->idc_state_handler, 3513 qla83xx_idc_state_handler_work); 3514 INIT_WORK(&ha->nic_core_unrecoverable, 3515 qla83xx_nic_core_unrecoverable_work); 3516 } 3517 3518 skip_dpc: 3519 list_add_tail(&base_vha->list, &ha->vp_list); 3520 base_vha->host->irq = ha->pdev->irq; 3521 3522 /* Initialized the timer */ 3523 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3524 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3525 "Started qla2x00_timer with " 3526 "interval=%d.\n", WATCH_INTERVAL); 3527 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3528 "Detected hba at address=%p.\n", 3529 ha); 3530 3531 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3532 if (ha->fw_attributes & BIT_4) { 3533 int prot = 0, guard; 3534 3535 base_vha->flags.difdix_supported = 1; 3536 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3537 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3538 if (ql2xprotmask) 3539 scsi_host_set_prot(host, ql2xprotmask); 3540 else 3541 scsi_host_set_prot(host, 3542 prot | SHOST_DIF_TYPE1_PROTECTION 3543 | SHOST_DIF_TYPE2_PROTECTION 3544 | SHOST_DIF_TYPE3_PROTECTION 3545 | SHOST_DIX_TYPE1_PROTECTION 3546 | SHOST_DIX_TYPE2_PROTECTION 3547 | SHOST_DIX_TYPE3_PROTECTION); 3548 3549 guard = SHOST_DIX_GUARD_CRC; 3550 3551 if (IS_PI_IPGUARD_CAPABLE(ha) && 3552 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3553 guard |= SHOST_DIX_GUARD_IP; 3554 3555 if (ql2xprotguard) 3556 scsi_host_set_guard(host, ql2xprotguard); 3557 else 3558 scsi_host_set_guard(host, guard); 3559 } else 3560 base_vha->flags.difdix_supported = 0; 3561 } 3562 3563 ha->isp_ops->enable_intrs(ha); 3564 3565 if (IS_QLAFX00(ha)) { 3566 ret = qlafx00_fx_disc(base_vha, 3567 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3568 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3569 QLA_SG_ALL : 128; 3570 } 3571 3572 ret = scsi_add_host(host, &pdev->dev); 3573 if (ret) 3574 goto probe_failed; 3575 3576 base_vha->flags.init_done = 1; 3577 base_vha->flags.online = 1; 3578 ha->prev_minidump_failed = 0; 3579 3580 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3581 "Init done and hba is online.\n"); 3582 3583 if (qla_ini_mode_enabled(base_vha) || 3584 qla_dual_mode_enabled(base_vha)) 3585 scsi_scan_host(host); 3586 else 3587 ql_log(ql_log_info, base_vha, 0x0122, 3588 "skipping scsi_scan_host() for non-initiator port\n"); 3589 3590 qla2x00_alloc_sysfs_attr(base_vha); 3591 3592 if (IS_QLAFX00(ha)) { 3593 ret = qlafx00_fx_disc(base_vha, 3594 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3595 3596 /* Register system information */ 3597 ret = qlafx00_fx_disc(base_vha, 3598 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3599 } 3600 3601 qla2x00_init_host_attr(base_vha); 3602 3603 qla2x00_dfs_setup(base_vha); 3604 3605 ql_log(ql_log_info, base_vha, 0x00fb, 3606 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3607 ql_log(ql_log_info, base_vha, 0x00fc, 3608 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3609 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3610 sizeof(pci_info)), 3611 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3612 base_vha->host_no, 3613 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3614 3615 qlt_add_target(ha, base_vha); 3616 3617 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3618 3619 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3620 return -ENODEV; 3621 3622 return 0; 3623 3624 probe_failed: 3625 qla_enode_stop(base_vha); 3626 qla_edb_stop(base_vha); 3627 vfree(base_vha->scan.l); 3628 if (base_vha->gnl.l) { 3629 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3630 base_vha->gnl.l, base_vha->gnl.ldma); 3631 base_vha->gnl.l = NULL; 3632 } 3633 3634 if (base_vha->timer_active) 3635 qla2x00_stop_timer(base_vha); 3636 base_vha->flags.online = 0; 3637 if (ha->dpc_thread) { 3638 struct task_struct *t = ha->dpc_thread; 3639 3640 ha->dpc_thread = NULL; 3641 kthread_stop(t); 3642 } 3643 3644 qla2x00_free_device(base_vha); 3645 scsi_host_put(base_vha->host); 3646 /* 3647 * Need to NULL out local req/rsp after 3648 * qla2x00_free_device => qla2x00_free_queues frees 3649 * what these are pointing to. Or else we'll 3650 * fall over below in qla2x00_free_req/rsp_que. 3651 */ 3652 req = NULL; 3653 rsp = NULL; 3654 3655 probe_hw_failed: 3656 qla2x00_mem_free(ha); 3657 qla2x00_free_req_que(ha, req); 3658 qla2x00_free_rsp_que(ha, rsp); 3659 qla2x00_clear_drv_active(ha); 3660 3661 iospace_config_failed: 3662 if (IS_P3P_TYPE(ha)) { 3663 if (!ha->nx_pcibase) 3664 iounmap((device_reg_t *)ha->nx_pcibase); 3665 if (!ql2xdbwr) 3666 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3667 } else { 3668 if (ha->iobase) 3669 iounmap(ha->iobase); 3670 if (ha->cregbase) 3671 iounmap(ha->cregbase); 3672 } 3673 pci_release_selected_regions(ha->pdev, ha->bars); 3674 kfree(ha); 3675 3676 disable_device: 3677 pci_disable_device(pdev); 3678 return ret; 3679 } 3680 __qla_set_remove_flag(scsi_qla_host_t * base_vha)3681 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3682 { 3683 scsi_qla_host_t *vp; 3684 unsigned long flags; 3685 struct qla_hw_data *ha; 3686 3687 if (!base_vha) 3688 return; 3689 3690 ha = base_vha->hw; 3691 3692 spin_lock_irqsave(&ha->vport_slock, flags); 3693 list_for_each_entry(vp, &ha->vp_list, list) 3694 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3695 3696 /* 3697 * Indicate device removal to prevent future board_disable 3698 * and wait until any pending board_disable has completed. 3699 */ 3700 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3701 spin_unlock_irqrestore(&ha->vport_slock, flags); 3702 } 3703 3704 static void qla2x00_shutdown(struct pci_dev * pdev)3705 qla2x00_shutdown(struct pci_dev *pdev) 3706 { 3707 scsi_qla_host_t *vha; 3708 struct qla_hw_data *ha; 3709 3710 vha = pci_get_drvdata(pdev); 3711 ha = vha->hw; 3712 3713 ql_log(ql_log_info, vha, 0xfffa, 3714 "Adapter shutdown\n"); 3715 3716 /* 3717 * Prevent future board_disable and wait 3718 * until any pending board_disable has completed. 3719 */ 3720 __qla_set_remove_flag(vha); 3721 cancel_work_sync(&ha->board_disable); 3722 3723 if (!atomic_read(&pdev->enable_cnt)) 3724 return; 3725 3726 /* Notify ISPFX00 firmware */ 3727 if (IS_QLAFX00(ha)) 3728 qlafx00_driver_shutdown(vha, 20); 3729 3730 /* Turn-off FCE trace */ 3731 if (ha->flags.fce_enabled) { 3732 qla2x00_disable_fce_trace(vha, NULL, NULL); 3733 ha->flags.fce_enabled = 0; 3734 } 3735 3736 /* Turn-off EFT trace */ 3737 if (ha->eft) 3738 qla2x00_disable_eft_trace(vha); 3739 3740 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3741 IS_QLA28XX(ha)) { 3742 if (ha->flags.fw_started) 3743 qla2x00_abort_isp_cleanup(vha); 3744 } else { 3745 /* Stop currently executing firmware. */ 3746 qla2x00_try_to_stop_firmware(vha); 3747 } 3748 3749 /* Disable timer */ 3750 if (vha->timer_active) 3751 qla2x00_stop_timer(vha); 3752 3753 /* Turn adapter off line */ 3754 vha->flags.online = 0; 3755 3756 /* turn-off interrupts on the card */ 3757 if (ha->interrupts_on) { 3758 vha->flags.init_done = 0; 3759 ha->isp_ops->disable_intrs(ha); 3760 } 3761 3762 qla2x00_free_irqs(vha); 3763 3764 qla2x00_free_fw_dump(ha); 3765 3766 pci_disable_device(pdev); 3767 ql_log(ql_log_info, vha, 0xfffe, 3768 "Adapter shutdown successfully.\n"); 3769 } 3770 3771 /* Deletes all the virtual ports for a given ha */ 3772 static void qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3773 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3774 { 3775 scsi_qla_host_t *vha; 3776 unsigned long flags; 3777 3778 mutex_lock(&ha->vport_lock); 3779 while (ha->cur_vport_count) { 3780 spin_lock_irqsave(&ha->vport_slock, flags); 3781 3782 BUG_ON(base_vha->list.next == &ha->vp_list); 3783 /* This assumes first entry in ha->vp_list is always base vha */ 3784 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3785 scsi_host_get(vha->host); 3786 3787 spin_unlock_irqrestore(&ha->vport_slock, flags); 3788 mutex_unlock(&ha->vport_lock); 3789 3790 qla_nvme_delete(vha); 3791 3792 fc_vport_terminate(vha->fc_vport); 3793 scsi_host_put(vha->host); 3794 3795 mutex_lock(&ha->vport_lock); 3796 } 3797 mutex_unlock(&ha->vport_lock); 3798 } 3799 3800 /* Stops all deferred work threads */ 3801 static void qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3802 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3803 { 3804 /* Cancel all work and destroy DPC workqueues */ 3805 if (ha->dpc_lp_wq) { 3806 cancel_work_sync(&ha->idc_aen); 3807 destroy_workqueue(ha->dpc_lp_wq); 3808 ha->dpc_lp_wq = NULL; 3809 } 3810 3811 if (ha->dpc_hp_wq) { 3812 cancel_work_sync(&ha->nic_core_reset); 3813 cancel_work_sync(&ha->idc_state_handler); 3814 cancel_work_sync(&ha->nic_core_unrecoverable); 3815 destroy_workqueue(ha->dpc_hp_wq); 3816 ha->dpc_hp_wq = NULL; 3817 } 3818 3819 /* Kill the kernel thread for this host */ 3820 if (ha->dpc_thread) { 3821 struct task_struct *t = ha->dpc_thread; 3822 3823 /* 3824 * qla2xxx_wake_dpc checks for ->dpc_thread 3825 * so we need to zero it out. 3826 */ 3827 ha->dpc_thread = NULL; 3828 kthread_stop(t); 3829 } 3830 } 3831 3832 static void qla2x00_unmap_iobases(struct qla_hw_data * ha)3833 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3834 { 3835 if (IS_QLA82XX(ha)) { 3836 3837 iounmap((device_reg_t *)ha->nx_pcibase); 3838 if (!ql2xdbwr) 3839 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3840 } else { 3841 if (ha->iobase) 3842 iounmap(ha->iobase); 3843 3844 if (ha->cregbase) 3845 iounmap(ha->cregbase); 3846 3847 if (ha->mqiobase) 3848 iounmap(ha->mqiobase); 3849 3850 if (ha->msixbase) 3851 iounmap(ha->msixbase); 3852 } 3853 } 3854 3855 static void qla2x00_clear_drv_active(struct qla_hw_data * ha)3856 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3857 { 3858 if (IS_QLA8044(ha)) { 3859 qla8044_idc_lock(ha); 3860 qla8044_clear_drv_active(ha); 3861 qla8044_idc_unlock(ha); 3862 } else if (IS_QLA82XX(ha)) { 3863 qla82xx_idc_lock(ha); 3864 qla82xx_clear_drv_active(ha); 3865 qla82xx_idc_unlock(ha); 3866 } 3867 } 3868 3869 static void qla2x00_remove_one(struct pci_dev * pdev)3870 qla2x00_remove_one(struct pci_dev *pdev) 3871 { 3872 scsi_qla_host_t *base_vha; 3873 struct qla_hw_data *ha; 3874 3875 base_vha = pci_get_drvdata(pdev); 3876 ha = base_vha->hw; 3877 ql_log(ql_log_info, base_vha, 0xb079, 3878 "Removing driver\n"); 3879 __qla_set_remove_flag(base_vha); 3880 cancel_work_sync(&ha->board_disable); 3881 3882 /* 3883 * If the PCI device is disabled then there was a PCI-disconnect and 3884 * qla2x00_disable_board_on_pci_error has taken care of most of the 3885 * resources. 3886 */ 3887 if (!atomic_read(&pdev->enable_cnt)) { 3888 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3889 base_vha->gnl.l, base_vha->gnl.ldma); 3890 base_vha->gnl.l = NULL; 3891 scsi_host_put(base_vha->host); 3892 kfree(ha); 3893 pci_set_drvdata(pdev, NULL); 3894 return; 3895 } 3896 qla2x00_wait_for_hba_ready(base_vha); 3897 3898 /* 3899 * if UNLOADING flag is already set, then continue unload, 3900 * where it was set first. 3901 */ 3902 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3903 return; 3904 3905 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3906 IS_QLA28XX(ha)) { 3907 if (ha->flags.fw_started) 3908 qla2x00_abort_isp_cleanup(base_vha); 3909 } else if (!IS_QLAFX00(ha)) { 3910 if (IS_QLA8031(ha)) { 3911 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3912 "Clearing fcoe driver presence.\n"); 3913 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3914 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3915 "Error while clearing DRV-Presence.\n"); 3916 } 3917 3918 qla2x00_try_to_stop_firmware(base_vha); 3919 } 3920 3921 qla2x00_wait_for_sess_deletion(base_vha); 3922 3923 qla_nvme_delete(base_vha); 3924 3925 dma_free_coherent(&ha->pdev->dev, 3926 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3927 3928 base_vha->gnl.l = NULL; 3929 qla_enode_stop(base_vha); 3930 qla_edb_stop(base_vha); 3931 3932 vfree(base_vha->scan.l); 3933 3934 if (IS_QLAFX00(ha)) 3935 qlafx00_driver_shutdown(base_vha, 20); 3936 3937 qla2x00_delete_all_vps(ha, base_vha); 3938 3939 qla2x00_dfs_remove(base_vha); 3940 3941 qla84xx_put_chip(base_vha); 3942 3943 /* Disable timer */ 3944 if (base_vha->timer_active) 3945 qla2x00_stop_timer(base_vha); 3946 3947 base_vha->flags.online = 0; 3948 3949 /* free DMA memory */ 3950 if (ha->exlogin_buf) 3951 qla2x00_free_exlogin_buffer(ha); 3952 3953 /* free DMA memory */ 3954 if (ha->exchoffld_buf) 3955 qla2x00_free_exchoffld_buffer(ha); 3956 3957 qla2x00_destroy_deferred_work(ha); 3958 3959 qlt_remove_target(ha, base_vha); 3960 3961 qla2x00_free_sysfs_attr(base_vha, true); 3962 3963 fc_remove_host(base_vha->host); 3964 3965 scsi_remove_host(base_vha->host); 3966 3967 qla2x00_free_device(base_vha); 3968 3969 qla2x00_clear_drv_active(ha); 3970 3971 scsi_host_put(base_vha->host); 3972 3973 qla2x00_unmap_iobases(ha); 3974 3975 pci_release_selected_regions(ha->pdev, ha->bars); 3976 kfree(ha); 3977 3978 pci_disable_device(pdev); 3979 } 3980 3981 static inline void qla24xx_free_purex_list(struct purex_list * list)3982 qla24xx_free_purex_list(struct purex_list *list) 3983 { 3984 struct purex_item *item, *next; 3985 ulong flags; 3986 3987 spin_lock_irqsave(&list->lock, flags); 3988 list_for_each_entry_safe(item, next, &list->head, list) { 3989 list_del(&item->list); 3990 if (item == &item->vha->default_item) 3991 continue; 3992 kfree(item); 3993 } 3994 spin_unlock_irqrestore(&list->lock, flags); 3995 } 3996 3997 static void qla2x00_free_device(scsi_qla_host_t * vha)3998 qla2x00_free_device(scsi_qla_host_t *vha) 3999 { 4000 struct qla_hw_data *ha = vha->hw; 4001 4002 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 4003 4004 /* Disable timer */ 4005 if (vha->timer_active) 4006 qla2x00_stop_timer(vha); 4007 4008 qla25xx_delete_queues(vha); 4009 vha->flags.online = 0; 4010 4011 /* turn-off interrupts on the card */ 4012 if (ha->interrupts_on) { 4013 vha->flags.init_done = 0; 4014 ha->isp_ops->disable_intrs(ha); 4015 } 4016 4017 qla2x00_free_fcports(vha); 4018 4019 qla2x00_free_irqs(vha); 4020 4021 /* Flush the work queue and remove it */ 4022 if (ha->wq) { 4023 destroy_workqueue(ha->wq); 4024 ha->wq = NULL; 4025 } 4026 4027 4028 qla24xx_free_purex_list(&vha->purex_list); 4029 4030 qla2x00_mem_free(ha); 4031 4032 qla82xx_md_free(vha); 4033 4034 qla_edif_sadb_release_free_pool(ha); 4035 qla_edif_sadb_release(ha); 4036 4037 qla2x00_free_queues(ha); 4038 } 4039 qla2x00_free_fcports(struct scsi_qla_host * vha)4040 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4041 { 4042 fc_port_t *fcport, *tfcport; 4043 4044 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4045 qla2x00_free_fcport(fcport); 4046 } 4047 4048 static inline void qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)4049 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4050 { 4051 int now; 4052 4053 if (!fcport->rport) 4054 return; 4055 4056 if (fcport->rport) { 4057 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4058 "%s %8phN. rport %p roles %x\n", 4059 __func__, fcport->port_name, fcport->rport, 4060 fcport->rport->roles); 4061 fc_remote_port_delete(fcport->rport); 4062 } 4063 qlt_do_generation_tick(vha, &now); 4064 } 4065 4066 /* 4067 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4068 * 4069 * Input: ha = adapter block pointer. fcport = port structure pointer. 4070 * 4071 * Return: None. 4072 * 4073 * Context: 4074 */ qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4075 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4076 int do_login) 4077 { 4078 if (IS_QLAFX00(vha->hw)) { 4079 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4080 qla2x00_schedule_rport_del(vha, fcport); 4081 return; 4082 } 4083 4084 if (atomic_read(&fcport->state) == FCS_ONLINE && 4085 vha->vp_idx == fcport->vha->vp_idx) { 4086 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4087 qla2x00_schedule_rport_del(vha, fcport); 4088 } 4089 4090 /* 4091 * We may need to retry the login, so don't change the state of the 4092 * port but do the retries. 4093 */ 4094 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4095 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4096 4097 if (!do_login) 4098 return; 4099 4100 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4101 } 4102 4103 void qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4104 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4105 { 4106 fc_port_t *fcport; 4107 4108 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4109 "Mark all dev lost\n"); 4110 4111 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4112 if (ql2xfc2target && 4113 fcport->loop_id != FC_NO_LOOP_ID && 4114 (fcport->flags & FCF_FCP2_DEVICE) && 4115 fcport->port_type == FCT_TARGET && 4116 !qla2x00_reset_active(vha)) { 4117 ql_dbg(ql_dbg_disc, vha, 0x211a, 4118 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4119 fcport->flags, fcport->port_type, 4120 fcport->d_id.b24, fcport->port_name); 4121 continue; 4122 } 4123 fcport->scan_state = 0; 4124 qlt_schedule_sess_for_deletion(fcport); 4125 } 4126 } 4127 qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4128 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4129 { 4130 int i; 4131 4132 if (IS_FWI2_CAPABLE(ha)) 4133 return; 4134 4135 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4136 set_bit(i, ha->loop_id_map); 4137 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4138 set_bit(BROADCAST, ha->loop_id_map); 4139 } 4140 4141 /* 4142 * qla2x00_mem_alloc 4143 * Allocates adapter memory. 4144 * 4145 * Returns: 4146 * 0 = success. 4147 * !0 = failure. 4148 */ 4149 static int qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4150 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4151 struct req_que **req, struct rsp_que **rsp) 4152 { 4153 char name[16]; 4154 int rc; 4155 4156 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4157 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4158 if (!ha->vp_map) 4159 goto fail; 4160 } 4161 4162 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4163 &ha->init_cb_dma, GFP_KERNEL); 4164 if (!ha->init_cb) 4165 goto fail_free_vp_map; 4166 4167 rc = btree_init32(&ha->host_map); 4168 if (rc) 4169 goto fail_free_init_cb; 4170 4171 if (qlt_mem_alloc(ha) < 0) 4172 goto fail_free_btree; 4173 4174 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4175 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4176 if (!ha->gid_list) 4177 goto fail_free_tgt_mem; 4178 4179 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4180 if (!ha->srb_mempool) 4181 goto fail_free_gid_list; 4182 4183 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4184 /* Allocate cache for CT6 Ctx. */ 4185 if (!ctx_cachep) { 4186 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4187 sizeof(struct ct6_dsd), 0, 4188 SLAB_HWCACHE_ALIGN, NULL); 4189 if (!ctx_cachep) 4190 goto fail_free_srb_mempool; 4191 } 4192 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4193 ctx_cachep); 4194 if (!ha->ctx_mempool) 4195 goto fail_free_srb_mempool; 4196 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4197 "ctx_cachep=%p ctx_mempool=%p.\n", 4198 ctx_cachep, ha->ctx_mempool); 4199 } 4200 4201 /* Get memory for cached NVRAM */ 4202 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4203 if (!ha->nvram) 4204 goto fail_free_ctx_mempool; 4205 4206 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4207 ha->pdev->device); 4208 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4209 DMA_POOL_SIZE, 8, 0); 4210 if (!ha->s_dma_pool) 4211 goto fail_free_nvram; 4212 4213 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4214 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4215 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4216 4217 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4218 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4219 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4220 if (!ha->dl_dma_pool) { 4221 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4222 "Failed to allocate memory for dl_dma_pool.\n"); 4223 goto fail_s_dma_pool; 4224 } 4225 4226 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4227 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4228 if (!ha->fcp_cmnd_dma_pool) { 4229 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4230 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4231 goto fail_dl_dma_pool; 4232 } 4233 4234 if (ql2xenabledif) { 4235 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4236 struct dsd_dma *dsd, *nxt; 4237 uint i; 4238 /* Creata a DMA pool of buffers for DIF bundling */ 4239 ha->dif_bundl_pool = dma_pool_create(name, 4240 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4241 if (!ha->dif_bundl_pool) { 4242 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4243 "%s: failed create dif_bundl_pool\n", 4244 __func__); 4245 goto fail_dif_bundl_dma_pool; 4246 } 4247 4248 INIT_LIST_HEAD(&ha->pool.good.head); 4249 INIT_LIST_HEAD(&ha->pool.unusable.head); 4250 ha->pool.good.count = 0; 4251 ha->pool.unusable.count = 0; 4252 for (i = 0; i < 128; i++) { 4253 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4254 if (!dsd) { 4255 ql_dbg_pci(ql_dbg_init, ha->pdev, 4256 0xe0ee, "%s: failed alloc dsd\n", 4257 __func__); 4258 return -ENOMEM; 4259 } 4260 ha->dif_bundle_kallocs++; 4261 4262 dsd->dsd_addr = dma_pool_alloc( 4263 ha->dif_bundl_pool, GFP_ATOMIC, 4264 &dsd->dsd_list_dma); 4265 if (!dsd->dsd_addr) { 4266 ql_dbg_pci(ql_dbg_init, ha->pdev, 4267 0xe0ee, 4268 "%s: failed alloc ->dsd_addr\n", 4269 __func__); 4270 kfree(dsd); 4271 ha->dif_bundle_kallocs--; 4272 continue; 4273 } 4274 ha->dif_bundle_dma_allocs++; 4275 4276 /* 4277 * if DMA buffer crosses 4G boundary, 4278 * put it on bad list 4279 */ 4280 if (MSD(dsd->dsd_list_dma) ^ 4281 MSD(dsd->dsd_list_dma + bufsize)) { 4282 list_add_tail(&dsd->list, 4283 &ha->pool.unusable.head); 4284 ha->pool.unusable.count++; 4285 } else { 4286 list_add_tail(&dsd->list, 4287 &ha->pool.good.head); 4288 ha->pool.good.count++; 4289 } 4290 } 4291 4292 /* return the good ones back to the pool */ 4293 list_for_each_entry_safe(dsd, nxt, 4294 &ha->pool.good.head, list) { 4295 list_del(&dsd->list); 4296 dma_pool_free(ha->dif_bundl_pool, 4297 dsd->dsd_addr, dsd->dsd_list_dma); 4298 ha->dif_bundle_dma_allocs--; 4299 kfree(dsd); 4300 ha->dif_bundle_kallocs--; 4301 } 4302 4303 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4304 "%s: dif dma pool (good=%u unusable=%u)\n", 4305 __func__, ha->pool.good.count, 4306 ha->pool.unusable.count); 4307 } 4308 4309 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4310 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4311 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4312 ha->dif_bundl_pool); 4313 } 4314 4315 /* Allocate memory for SNS commands */ 4316 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4317 /* Get consistent memory allocated for SNS commands */ 4318 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4319 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4320 if (!ha->sns_cmd) 4321 goto fail_dma_pool; 4322 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4323 "sns_cmd: %p.\n", ha->sns_cmd); 4324 } else { 4325 /* Get consistent memory allocated for MS IOCB */ 4326 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4327 &ha->ms_iocb_dma); 4328 if (!ha->ms_iocb) 4329 goto fail_dma_pool; 4330 /* Get consistent memory allocated for CT SNS commands */ 4331 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4332 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4333 if (!ha->ct_sns) 4334 goto fail_free_ms_iocb; 4335 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4336 "ms_iocb=%p ct_sns=%p.\n", 4337 ha->ms_iocb, ha->ct_sns); 4338 } 4339 4340 /* Allocate memory for request ring */ 4341 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4342 if (!*req) { 4343 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4344 "Failed to allocate memory for req.\n"); 4345 goto fail_req; 4346 } 4347 (*req)->length = req_len; 4348 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4349 ((*req)->length + 1) * sizeof(request_t), 4350 &(*req)->dma, GFP_KERNEL); 4351 if (!(*req)->ring) { 4352 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4353 "Failed to allocate memory for req_ring.\n"); 4354 goto fail_req_ring; 4355 } 4356 /* Allocate memory for response ring */ 4357 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4358 if (!*rsp) { 4359 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4360 "Failed to allocate memory for rsp.\n"); 4361 goto fail_rsp; 4362 } 4363 (*rsp)->hw = ha; 4364 (*rsp)->length = rsp_len; 4365 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4366 ((*rsp)->length + 1) * sizeof(response_t), 4367 &(*rsp)->dma, GFP_KERNEL); 4368 if (!(*rsp)->ring) { 4369 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4370 "Failed to allocate memory for rsp_ring.\n"); 4371 goto fail_rsp_ring; 4372 } 4373 (*req)->rsp = *rsp; 4374 (*rsp)->req = *req; 4375 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4376 "req=%p req->length=%d req->ring=%p rsp=%p " 4377 "rsp->length=%d rsp->ring=%p.\n", 4378 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4379 (*rsp)->ring); 4380 /* Allocate memory for NVRAM data for vports */ 4381 if (ha->nvram_npiv_size) { 4382 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4383 sizeof(struct qla_npiv_entry), 4384 GFP_KERNEL); 4385 if (!ha->npiv_info) { 4386 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4387 "Failed to allocate memory for npiv_info.\n"); 4388 goto fail_npiv_info; 4389 } 4390 } else 4391 ha->npiv_info = NULL; 4392 4393 /* Get consistent memory allocated for EX-INIT-CB. */ 4394 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4395 IS_QLA28XX(ha)) { 4396 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4397 &ha->ex_init_cb_dma); 4398 if (!ha->ex_init_cb) 4399 goto fail_ex_init_cb; 4400 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4401 "ex_init_cb=%p.\n", ha->ex_init_cb); 4402 } 4403 4404 /* Get consistent memory allocated for Special Features-CB. */ 4405 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4406 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4407 &ha->sf_init_cb_dma); 4408 if (!ha->sf_init_cb) 4409 goto fail_sf_init_cb; 4410 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4411 "sf_init_cb=%p.\n", ha->sf_init_cb); 4412 } 4413 4414 4415 /* Get consistent memory allocated for Async Port-Database. */ 4416 if (!IS_FWI2_CAPABLE(ha)) { 4417 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4418 &ha->async_pd_dma); 4419 if (!ha->async_pd) 4420 goto fail_async_pd; 4421 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4422 "async_pd=%p.\n", ha->async_pd); 4423 } 4424 4425 INIT_LIST_HEAD(&ha->vp_list); 4426 4427 /* Allocate memory for our loop_id bitmap */ 4428 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4429 sizeof(long), 4430 GFP_KERNEL); 4431 if (!ha->loop_id_map) 4432 goto fail_loop_id_map; 4433 else { 4434 qla2x00_set_reserved_loop_ids(ha); 4435 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4436 "loop_id_map=%p.\n", ha->loop_id_map); 4437 } 4438 4439 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4440 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4441 if (!ha->sfp_data) { 4442 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4443 "Unable to allocate memory for SFP read-data.\n"); 4444 goto fail_sfp_data; 4445 } 4446 4447 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4448 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4449 GFP_KERNEL); 4450 if (!ha->flt) { 4451 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4452 "Unable to allocate memory for FLT.\n"); 4453 goto fail_flt_buffer; 4454 } 4455 4456 /* allocate the purex dma pool */ 4457 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4458 ELS_MAX_PAYLOAD, 8, 0); 4459 4460 if (!ha->purex_dma_pool) { 4461 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4462 "Unable to allocate purex_dma_pool.\n"); 4463 goto fail_flt; 4464 } 4465 4466 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4467 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4468 ha->elsrej.size, 4469 &ha->elsrej.cdma, 4470 GFP_KERNEL); 4471 if (!ha->elsrej.c) { 4472 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4473 "Alloc failed for els reject cmd.\n"); 4474 goto fail_elsrej; 4475 } 4476 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4477 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4478 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4479 4480 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt); 4481 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size, 4482 &ha->lsrjt.cdma, GFP_KERNEL); 4483 if (!ha->lsrjt.c) { 4484 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4485 "Alloc failed for nvme fc reject cmd.\n"); 4486 goto fail_lsrjt; 4487 } 4488 4489 return 0; 4490 4491 fail_lsrjt: 4492 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4493 ha->elsrej.c, ha->elsrej.cdma); 4494 fail_elsrej: 4495 dma_pool_destroy(ha->purex_dma_pool); 4496 fail_flt: 4497 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4498 ha->flt, ha->flt_dma); 4499 4500 fail_flt_buffer: 4501 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4502 ha->sfp_data, ha->sfp_data_dma); 4503 fail_sfp_data: 4504 kfree(ha->loop_id_map); 4505 fail_loop_id_map: 4506 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4507 fail_async_pd: 4508 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4509 fail_sf_init_cb: 4510 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4511 fail_ex_init_cb: 4512 kfree(ha->npiv_info); 4513 fail_npiv_info: 4514 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4515 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4516 (*rsp)->ring = NULL; 4517 (*rsp)->dma = 0; 4518 fail_rsp_ring: 4519 kfree(*rsp); 4520 *rsp = NULL; 4521 fail_rsp: 4522 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4523 sizeof(request_t), (*req)->ring, (*req)->dma); 4524 (*req)->ring = NULL; 4525 (*req)->dma = 0; 4526 fail_req_ring: 4527 kfree(*req); 4528 *req = NULL; 4529 fail_req: 4530 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4531 ha->ct_sns, ha->ct_sns_dma); 4532 ha->ct_sns = NULL; 4533 ha->ct_sns_dma = 0; 4534 fail_free_ms_iocb: 4535 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4536 ha->ms_iocb = NULL; 4537 ha->ms_iocb_dma = 0; 4538 4539 if (ha->sns_cmd) 4540 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4541 ha->sns_cmd, ha->sns_cmd_dma); 4542 fail_dma_pool: 4543 if (ql2xenabledif) { 4544 struct dsd_dma *dsd, *nxt; 4545 4546 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4547 list) { 4548 list_del(&dsd->list); 4549 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4550 dsd->dsd_list_dma); 4551 ha->dif_bundle_dma_allocs--; 4552 kfree(dsd); 4553 ha->dif_bundle_kallocs--; 4554 ha->pool.unusable.count--; 4555 } 4556 dma_pool_destroy(ha->dif_bundl_pool); 4557 ha->dif_bundl_pool = NULL; 4558 } 4559 4560 fail_dif_bundl_dma_pool: 4561 if (IS_QLA82XX(ha) || ql2xenabledif) { 4562 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4563 ha->fcp_cmnd_dma_pool = NULL; 4564 } 4565 fail_dl_dma_pool: 4566 if (IS_QLA82XX(ha) || ql2xenabledif) { 4567 dma_pool_destroy(ha->dl_dma_pool); 4568 ha->dl_dma_pool = NULL; 4569 } 4570 fail_s_dma_pool: 4571 dma_pool_destroy(ha->s_dma_pool); 4572 ha->s_dma_pool = NULL; 4573 fail_free_nvram: 4574 kfree(ha->nvram); 4575 ha->nvram = NULL; 4576 fail_free_ctx_mempool: 4577 mempool_destroy(ha->ctx_mempool); 4578 ha->ctx_mempool = NULL; 4579 fail_free_srb_mempool: 4580 mempool_destroy(ha->srb_mempool); 4581 ha->srb_mempool = NULL; 4582 fail_free_gid_list: 4583 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4584 ha->gid_list, 4585 ha->gid_list_dma); 4586 ha->gid_list = NULL; 4587 ha->gid_list_dma = 0; 4588 fail_free_tgt_mem: 4589 qlt_mem_free(ha); 4590 fail_free_btree: 4591 btree_destroy32(&ha->host_map); 4592 fail_free_init_cb: 4593 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4594 ha->init_cb_dma); 4595 ha->init_cb = NULL; 4596 ha->init_cb_dma = 0; 4597 fail_free_vp_map: 4598 kfree(ha->vp_map); 4599 ha->vp_map = NULL; 4600 fail: 4601 ql_log(ql_log_fatal, NULL, 0x0030, 4602 "Memory allocation failure.\n"); 4603 return -ENOMEM; 4604 } 4605 4606 int qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4607 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4608 { 4609 int rval; 4610 uint16_t size, max_cnt; 4611 uint32_t temp; 4612 struct qla_hw_data *ha = vha->hw; 4613 4614 /* Return if we don't need to alloacate any extended logins */ 4615 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4616 return QLA_SUCCESS; 4617 4618 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4619 return QLA_SUCCESS; 4620 4621 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4622 max_cnt = 0; 4623 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4624 if (rval != QLA_SUCCESS) { 4625 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4626 "Failed to get exlogin status.\n"); 4627 return rval; 4628 } 4629 4630 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4631 temp *= size; 4632 4633 if (temp != ha->exlogin_size) { 4634 qla2x00_free_exlogin_buffer(ha); 4635 ha->exlogin_size = temp; 4636 4637 ql_log(ql_log_info, vha, 0xd024, 4638 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4639 max_cnt, size, temp); 4640 4641 ql_log(ql_log_info, vha, 0xd025, 4642 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4643 4644 /* Get consistent memory for extended logins */ 4645 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4646 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4647 if (!ha->exlogin_buf) { 4648 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4649 "Failed to allocate memory for exlogin_buf_dma.\n"); 4650 return -ENOMEM; 4651 } 4652 } 4653 4654 /* Now configure the dma buffer */ 4655 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4656 if (rval) { 4657 ql_log(ql_log_fatal, vha, 0xd033, 4658 "Setup extended login buffer ****FAILED****.\n"); 4659 qla2x00_free_exlogin_buffer(ha); 4660 } 4661 4662 return rval; 4663 } 4664 4665 /* 4666 * qla2x00_free_exlogin_buffer 4667 * 4668 * Input: 4669 * ha = adapter block pointer 4670 */ 4671 void qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4672 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4673 { 4674 if (ha->exlogin_buf) { 4675 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4676 ha->exlogin_buf, ha->exlogin_buf_dma); 4677 ha->exlogin_buf = NULL; 4678 ha->exlogin_size = 0; 4679 } 4680 } 4681 4682 static void qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4683 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4684 { 4685 u32 temp; 4686 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb; 4687 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4688 4689 if (max_cnt > vha->hw->max_exchg) 4690 max_cnt = vha->hw->max_exchg; 4691 4692 if (qla_ini_mode_enabled(vha)) { 4693 if (vha->ql2xiniexchg > max_cnt) 4694 vha->ql2xiniexchg = max_cnt; 4695 4696 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4697 *ret_cnt = vha->ql2xiniexchg; 4698 4699 } else if (qla_tgt_mode_enabled(vha)) { 4700 if (vha->ql2xexchoffld > max_cnt) { 4701 vha->ql2xexchoffld = max_cnt; 4702 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4703 } 4704 4705 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4706 *ret_cnt = vha->ql2xexchoffld; 4707 } else if (qla_dual_mode_enabled(vha)) { 4708 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4709 if (temp > max_cnt) { 4710 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4711 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4712 temp = max_cnt; 4713 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4714 } 4715 4716 if (temp > FW_DEF_EXCHANGES_CNT) 4717 *ret_cnt = temp; 4718 } 4719 } 4720 4721 int qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4722 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4723 { 4724 int rval; 4725 u16 size, max_cnt; 4726 u32 actual_cnt, totsz; 4727 struct qla_hw_data *ha = vha->hw; 4728 4729 if (!ha->flags.exchoffld_enabled) 4730 return QLA_SUCCESS; 4731 4732 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4733 return QLA_SUCCESS; 4734 4735 max_cnt = 0; 4736 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4737 if (rval != QLA_SUCCESS) { 4738 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4739 "Failed to get exlogin status.\n"); 4740 return rval; 4741 } 4742 4743 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4744 ql_log(ql_log_info, vha, 0xd014, 4745 "Actual exchange offload count: %d.\n", actual_cnt); 4746 4747 totsz = actual_cnt * size; 4748 4749 if (totsz != ha->exchoffld_size) { 4750 qla2x00_free_exchoffld_buffer(ha); 4751 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4752 ha->exchoffld_size = 0; 4753 ha->flags.exchoffld_enabled = 0; 4754 return QLA_SUCCESS; 4755 } 4756 4757 ha->exchoffld_size = totsz; 4758 4759 ql_log(ql_log_info, vha, 0xd016, 4760 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4761 max_cnt, actual_cnt, size, totsz); 4762 4763 ql_log(ql_log_info, vha, 0xd017, 4764 "Exchange Buffers requested size = 0x%x\n", 4765 ha->exchoffld_size); 4766 4767 /* Get consistent memory for extended logins */ 4768 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4769 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4770 if (!ha->exchoffld_buf) { 4771 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4772 "Failed to allocate memory for Exchange Offload.\n"); 4773 4774 if (ha->max_exchg > 4775 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4776 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4777 } else if (ha->max_exchg > 4778 (FW_DEF_EXCHANGES_CNT + 512)) { 4779 ha->max_exchg -= 512; 4780 } else { 4781 ha->flags.exchoffld_enabled = 0; 4782 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4783 "Disabling Exchange offload due to lack of memory\n"); 4784 } 4785 ha->exchoffld_size = 0; 4786 4787 return -ENOMEM; 4788 } 4789 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4790 /* pathological case */ 4791 qla2x00_free_exchoffld_buffer(ha); 4792 ha->exchoffld_size = 0; 4793 ha->flags.exchoffld_enabled = 0; 4794 ql_log(ql_log_info, vha, 0xd016, 4795 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4796 ha->exchoffld_size, actual_cnt, size, totsz); 4797 return 0; 4798 } 4799 4800 /* Now configure the dma buffer */ 4801 rval = qla_set_exchoffld_mem_cfg(vha); 4802 if (rval) { 4803 ql_log(ql_log_fatal, vha, 0xd02e, 4804 "Setup exchange offload buffer ****FAILED****.\n"); 4805 qla2x00_free_exchoffld_buffer(ha); 4806 } else { 4807 /* re-adjust number of target exchange */ 4808 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4809 4810 if (qla_ini_mode_enabled(vha)) 4811 icb->exchange_count = 0; 4812 else 4813 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4814 } 4815 4816 return rval; 4817 } 4818 4819 /* 4820 * qla2x00_free_exchoffld_buffer 4821 * 4822 * Input: 4823 * ha = adapter block pointer 4824 */ 4825 void qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4826 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4827 { 4828 if (ha->exchoffld_buf) { 4829 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4830 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4831 ha->exchoffld_buf = NULL; 4832 ha->exchoffld_size = 0; 4833 } 4834 } 4835 4836 /* 4837 * qla2x00_free_fw_dump 4838 * Frees fw dump stuff. 4839 * 4840 * Input: 4841 * ha = adapter block pointer 4842 */ 4843 static void qla2x00_free_fw_dump(struct qla_hw_data * ha)4844 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4845 { 4846 struct fwdt *fwdt = ha->fwdt; 4847 uint j; 4848 4849 if (ha->fce) 4850 dma_free_coherent(&ha->pdev->dev, 4851 FCE_SIZE, ha->fce, ha->fce_dma); 4852 4853 if (ha->eft) 4854 dma_free_coherent(&ha->pdev->dev, 4855 EFT_SIZE, ha->eft, ha->eft_dma); 4856 4857 vfree(ha->fw_dump); 4858 4859 ha->fce = NULL; 4860 ha->fce_dma = 0; 4861 ha->flags.fce_enabled = 0; 4862 ha->eft = NULL; 4863 ha->eft_dma = 0; 4864 ha->fw_dumped = false; 4865 ha->fw_dump_cap_flags = 0; 4866 ha->fw_dump_reading = 0; 4867 ha->fw_dump = NULL; 4868 ha->fw_dump_len = 0; 4869 4870 for (j = 0; j < 2; j++, fwdt++) { 4871 vfree(fwdt->template); 4872 fwdt->template = NULL; 4873 fwdt->length = 0; 4874 } 4875 } 4876 4877 /* 4878 * qla2x00_mem_free 4879 * Frees all adapter allocated memory. 4880 * 4881 * Input: 4882 * ha = adapter block pointer. 4883 */ 4884 static void qla2x00_mem_free(struct qla_hw_data * ha)4885 qla2x00_mem_free(struct qla_hw_data *ha) 4886 { 4887 qla2x00_free_fw_dump(ha); 4888 4889 if (ha->mctp_dump) 4890 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4891 ha->mctp_dump_dma); 4892 ha->mctp_dump = NULL; 4893 4894 mempool_destroy(ha->srb_mempool); 4895 ha->srb_mempool = NULL; 4896 4897 if (ha->dcbx_tlv) 4898 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4899 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4900 ha->dcbx_tlv = NULL; 4901 4902 if (ha->xgmac_data) 4903 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4904 ha->xgmac_data, ha->xgmac_data_dma); 4905 ha->xgmac_data = NULL; 4906 4907 if (ha->sns_cmd) 4908 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4909 ha->sns_cmd, ha->sns_cmd_dma); 4910 ha->sns_cmd = NULL; 4911 ha->sns_cmd_dma = 0; 4912 4913 if (ha->ct_sns) 4914 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4915 ha->ct_sns, ha->ct_sns_dma); 4916 ha->ct_sns = NULL; 4917 ha->ct_sns_dma = 0; 4918 4919 if (ha->sfp_data) 4920 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4921 ha->sfp_data_dma); 4922 ha->sfp_data = NULL; 4923 4924 if (ha->flt) 4925 dma_free_coherent(&ha->pdev->dev, 4926 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4927 ha->flt, ha->flt_dma); 4928 ha->flt = NULL; 4929 ha->flt_dma = 0; 4930 4931 if (ha->ms_iocb) 4932 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4933 ha->ms_iocb = NULL; 4934 ha->ms_iocb_dma = 0; 4935 4936 if (ha->sf_init_cb) 4937 dma_pool_free(ha->s_dma_pool, 4938 ha->sf_init_cb, ha->sf_init_cb_dma); 4939 4940 if (ha->ex_init_cb) 4941 dma_pool_free(ha->s_dma_pool, 4942 ha->ex_init_cb, ha->ex_init_cb_dma); 4943 ha->ex_init_cb = NULL; 4944 ha->ex_init_cb_dma = 0; 4945 4946 if (ha->async_pd) 4947 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4948 ha->async_pd = NULL; 4949 ha->async_pd_dma = 0; 4950 4951 dma_pool_destroy(ha->s_dma_pool); 4952 ha->s_dma_pool = NULL; 4953 4954 if (ha->gid_list) 4955 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4956 ha->gid_list, ha->gid_list_dma); 4957 ha->gid_list = NULL; 4958 ha->gid_list_dma = 0; 4959 4960 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) { 4961 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4962 4963 /* clean up allocated prev pool */ 4964 list_for_each_entry_safe(dsd_ptr, tdsd_ptr, 4965 &ha->base_qpair->dsd_list, list) { 4966 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr, 4967 dsd_ptr->dsd_list_dma); 4968 list_del(&dsd_ptr->list); 4969 kfree(dsd_ptr); 4970 } 4971 } 4972 4973 dma_pool_destroy(ha->dl_dma_pool); 4974 ha->dl_dma_pool = NULL; 4975 4976 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4977 ha->fcp_cmnd_dma_pool = NULL; 4978 4979 mempool_destroy(ha->ctx_mempool); 4980 ha->ctx_mempool = NULL; 4981 4982 if (ql2xenabledif && ha->dif_bundl_pool) { 4983 struct dsd_dma *dsd, *nxt; 4984 4985 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4986 list) { 4987 list_del(&dsd->list); 4988 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4989 dsd->dsd_list_dma); 4990 ha->dif_bundle_dma_allocs--; 4991 kfree(dsd); 4992 ha->dif_bundle_kallocs--; 4993 ha->pool.unusable.count--; 4994 } 4995 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4996 list_del(&dsd->list); 4997 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4998 dsd->dsd_list_dma); 4999 ha->dif_bundle_dma_allocs--; 5000 kfree(dsd); 5001 ha->dif_bundle_kallocs--; 5002 } 5003 } 5004 5005 dma_pool_destroy(ha->dif_bundl_pool); 5006 ha->dif_bundl_pool = NULL; 5007 5008 qlt_mem_free(ha); 5009 qla_remove_hostmap(ha); 5010 5011 if (ha->init_cb) 5012 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 5013 ha->init_cb, ha->init_cb_dma); 5014 5015 dma_pool_destroy(ha->purex_dma_pool); 5016 ha->purex_dma_pool = NULL; 5017 5018 if (ha->elsrej.c) { 5019 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 5020 ha->elsrej.c, ha->elsrej.cdma); 5021 ha->elsrej.c = NULL; 5022 } 5023 5024 if (ha->lsrjt.c) { 5025 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c, 5026 ha->lsrjt.cdma); 5027 ha->lsrjt.c = NULL; 5028 } 5029 5030 ha->init_cb = NULL; 5031 ha->init_cb_dma = 0; 5032 5033 vfree(ha->optrom_buffer); 5034 ha->optrom_buffer = NULL; 5035 kfree(ha->nvram); 5036 ha->nvram = NULL; 5037 kfree(ha->npiv_info); 5038 ha->npiv_info = NULL; 5039 kfree(ha->swl); 5040 ha->swl = NULL; 5041 kfree(ha->loop_id_map); 5042 ha->sf_init_cb = NULL; 5043 ha->sf_init_cb_dma = 0; 5044 ha->loop_id_map = NULL; 5045 5046 kfree(ha->vp_map); 5047 ha->vp_map = NULL; 5048 } 5049 qla2x00_create_host(const struct scsi_host_template * sht,struct qla_hw_data * ha)5050 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht, 5051 struct qla_hw_data *ha) 5052 { 5053 struct Scsi_Host *host; 5054 struct scsi_qla_host *vha = NULL; 5055 5056 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5057 if (!host) { 5058 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5059 "Failed to allocate host from the scsi layer, aborting.\n"); 5060 return NULL; 5061 } 5062 5063 /* Clear our data area */ 5064 vha = shost_priv(host); 5065 memset(vha, 0, sizeof(scsi_qla_host_t)); 5066 5067 vha->host = host; 5068 vha->host_no = host->host_no; 5069 vha->hw = ha; 5070 5071 vha->qlini_mode = ql2x_ini_mode; 5072 vha->ql2xexchoffld = ql2xexchoffld; 5073 vha->ql2xiniexchg = ql2xiniexchg; 5074 5075 INIT_LIST_HEAD(&vha->vp_fcports); 5076 INIT_LIST_HEAD(&vha->work_list); 5077 INIT_LIST_HEAD(&vha->list); 5078 INIT_LIST_HEAD(&vha->qla_cmd_list); 5079 INIT_LIST_HEAD(&vha->logo_list); 5080 INIT_LIST_HEAD(&vha->plogi_ack_list); 5081 INIT_LIST_HEAD(&vha->qp_list); 5082 INIT_LIST_HEAD(&vha->gnl.fcports); 5083 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5084 5085 INIT_LIST_HEAD(&vha->purex_list.head); 5086 spin_lock_init(&vha->purex_list.lock); 5087 5088 spin_lock_init(&vha->work_lock); 5089 spin_lock_init(&vha->cmd_list_lock); 5090 init_waitqueue_head(&vha->fcport_waitQ); 5091 init_waitqueue_head(&vha->vref_waitq); 5092 qla_enode_init(vha); 5093 qla_edb_init(vha); 5094 5095 5096 vha->gnl.size = sizeof(struct get_name_list_extended) * 5097 (ha->max_loop_id + 1); 5098 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5099 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5100 if (!vha->gnl.l) { 5101 ql_log(ql_log_fatal, vha, 0xd04a, 5102 "Alloc failed for name list.\n"); 5103 scsi_host_put(vha->host); 5104 return NULL; 5105 } 5106 5107 /* todo: what about ext login? */ 5108 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5109 vha->scan.l = vmalloc(vha->scan.size); 5110 if (!vha->scan.l) { 5111 ql_log(ql_log_fatal, vha, 0xd04a, 5112 "Alloc failed for scan database.\n"); 5113 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5114 vha->gnl.l, vha->gnl.ldma); 5115 vha->gnl.l = NULL; 5116 scsi_host_put(vha->host); 5117 return NULL; 5118 } 5119 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5120 5121 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu", 5122 QLA2XXX_DRIVER_NAME, vha->host_no); 5123 ql_dbg(ql_dbg_init, vha, 0x0041, 5124 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5125 vha->host, vha->hw, vha, 5126 dev_name(&(ha->pdev->dev))); 5127 5128 return vha; 5129 } 5130 5131 struct qla_work_evt * qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5132 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5133 { 5134 struct qla_work_evt *e; 5135 5136 if (test_bit(UNLOADING, &vha->dpc_flags)) 5137 return NULL; 5138 5139 if (qla_vha_mark_busy(vha)) 5140 return NULL; 5141 5142 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5143 if (!e) { 5144 QLA_VHA_MARK_NOT_BUSY(vha); 5145 return NULL; 5146 } 5147 5148 INIT_LIST_HEAD(&e->list); 5149 e->type = type; 5150 e->flags = QLA_EVT_FLAG_FREE; 5151 return e; 5152 } 5153 5154 int qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5155 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5156 { 5157 unsigned long flags; 5158 bool q = false; 5159 5160 spin_lock_irqsave(&vha->work_lock, flags); 5161 list_add_tail(&e->list, &vha->work_list); 5162 5163 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5164 q = true; 5165 5166 spin_unlock_irqrestore(&vha->work_lock, flags); 5167 5168 if (q) 5169 queue_work(vha->hw->wq, &vha->iocb_work); 5170 5171 return QLA_SUCCESS; 5172 } 5173 5174 int qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5175 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5176 u32 data) 5177 { 5178 struct qla_work_evt *e; 5179 5180 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5181 if (!e) 5182 return QLA_FUNCTION_FAILED; 5183 5184 e->u.aen.code = code; 5185 e->u.aen.data = data; 5186 return qla2x00_post_work(vha, e); 5187 } 5188 5189 int qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5190 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5191 { 5192 struct qla_work_evt *e; 5193 5194 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5195 if (!e) 5196 return QLA_FUNCTION_FAILED; 5197 5198 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5199 return qla2x00_post_work(vha, e); 5200 } 5201 5202 #define qla2x00_post_async_work(name, type) \ 5203 int qla2x00_post_async_##name##_work( \ 5204 struct scsi_qla_host *vha, \ 5205 fc_port_t *fcport, uint16_t *data) \ 5206 { \ 5207 struct qla_work_evt *e; \ 5208 \ 5209 e = qla2x00_alloc_work(vha, type); \ 5210 if (!e) \ 5211 return QLA_FUNCTION_FAILED; \ 5212 \ 5213 e->u.logio.fcport = fcport; \ 5214 if (data) { \ 5215 e->u.logio.data[0] = data[0]; \ 5216 e->u.logio.data[1] = data[1]; \ 5217 } \ 5218 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5219 return qla2x00_post_work(vha, e); \ 5220 } 5221 5222 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5223 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5224 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5225 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5226 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5227 5228 int qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5229 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5230 { 5231 struct qla_work_evt *e; 5232 5233 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5234 if (!e) 5235 return QLA_FUNCTION_FAILED; 5236 5237 e->u.uevent.code = code; 5238 return qla2x00_post_work(vha, e); 5239 } 5240 5241 static void qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5242 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5243 { 5244 char event_string[40]; 5245 char *envp[] = { event_string, NULL }; 5246 5247 switch (code) { 5248 case QLA_UEVENT_CODE_FW_DUMP: 5249 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5250 vha->host_no); 5251 break; 5252 default: 5253 /* do nothing */ 5254 break; 5255 } 5256 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5257 } 5258 5259 int qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5260 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5261 uint32_t *data, int cnt) 5262 { 5263 struct qla_work_evt *e; 5264 5265 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5266 if (!e) 5267 return QLA_FUNCTION_FAILED; 5268 5269 e->u.aenfx.evtcode = evtcode; 5270 e->u.aenfx.count = cnt; 5271 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5272 return qla2x00_post_work(vha, e); 5273 } 5274 qla24xx_sched_upd_fcport(fc_port_t * fcport)5275 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5276 { 5277 unsigned long flags; 5278 5279 if (IS_SW_RESV_ADDR(fcport->d_id)) 5280 return; 5281 5282 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5283 if (fcport->disc_state == DSC_UPD_FCPORT) { 5284 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5285 return; 5286 } 5287 fcport->jiffies_at_registration = jiffies; 5288 fcport->sec_since_registration = 0; 5289 fcport->next_disc_state = DSC_DELETED; 5290 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5291 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5292 5293 queue_work(system_unbound_wq, &fcport->reg_work); 5294 } 5295 5296 static qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5297 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5298 { 5299 unsigned long flags; 5300 fc_port_t *fcport = NULL, *tfcp; 5301 struct qlt_plogi_ack_t *pla = 5302 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5303 uint8_t free_fcport = 0; 5304 5305 ql_dbg(ql_dbg_disc, vha, 0xffff, 5306 "%s %d %8phC enter\n", 5307 __func__, __LINE__, e->u.new_sess.port_name); 5308 5309 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5310 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5311 if (fcport) { 5312 fcport->d_id = e->u.new_sess.id; 5313 if (pla) { 5314 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5315 memcpy(fcport->node_name, 5316 pla->iocb.u.isp24.u.plogi.node_name, 5317 WWN_SIZE); 5318 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5319 /* we took an extra ref_count to prevent PLOGI ACK when 5320 * fcport/sess has not been created. 5321 */ 5322 pla->ref_count--; 5323 } 5324 } else { 5325 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5326 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5327 if (fcport) { 5328 fcport->d_id = e->u.new_sess.id; 5329 fcport->flags |= FCF_FABRIC_DEVICE; 5330 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5331 fcport->tgt_short_link_down_cnt = 0; 5332 5333 memcpy(fcport->port_name, e->u.new_sess.port_name, 5334 WWN_SIZE); 5335 5336 fcport->fc4_type = e->u.new_sess.fc4_type; 5337 if (NVME_PRIORITY(vha->hw, fcport)) 5338 fcport->do_prli_nvme = 1; 5339 else 5340 fcport->do_prli_nvme = 0; 5341 5342 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5343 fcport->dm_login_expire = jiffies + 5344 QLA_N2N_WAIT_TIME * HZ; 5345 fcport->fc4_type = FS_FC4TYPE_FCP; 5346 fcport->n2n_flag = 1; 5347 if (vha->flags.nvme_enabled) 5348 fcport->fc4_type |= FS_FC4TYPE_NVME; 5349 } 5350 5351 } else { 5352 ql_dbg(ql_dbg_disc, vha, 0xffff, 5353 "%s %8phC mem alloc fail.\n", 5354 __func__, e->u.new_sess.port_name); 5355 5356 if (pla) { 5357 list_del(&pla->list); 5358 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5359 } 5360 return; 5361 } 5362 5363 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5364 /* search again to make sure no one else got ahead */ 5365 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5366 e->u.new_sess.port_name, 1); 5367 if (tfcp) { 5368 /* should rarily happen */ 5369 ql_dbg(ql_dbg_disc, vha, 0xffff, 5370 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5371 __func__, tfcp->port_name, tfcp->disc_state, 5372 tfcp->fw_login_state); 5373 5374 free_fcport = 1; 5375 } else { 5376 list_add_tail(&fcport->list, &vha->vp_fcports); 5377 5378 } 5379 if (pla) { 5380 qlt_plogi_ack_link(vha, pla, fcport, 5381 QLT_PLOGI_LINK_SAME_WWN); 5382 pla->ref_count--; 5383 } 5384 } 5385 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5386 5387 if (fcport) { 5388 fcport->id_changed = 1; 5389 fcport->scan_state = QLA_FCPORT_FOUND; 5390 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5391 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5392 5393 if (pla) { 5394 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5395 u16 wd3_lo; 5396 5397 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5398 fcport->local = 0; 5399 fcport->loop_id = 5400 le16_to_cpu( 5401 pla->iocb.u.isp24.nport_handle); 5402 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5403 wd3_lo = 5404 le16_to_cpu( 5405 pla->iocb.u.isp24.u.prli.wd3_lo); 5406 5407 if (wd3_lo & BIT_7) 5408 fcport->conf_compl_supported = 1; 5409 5410 if ((wd3_lo & BIT_4) == 0) 5411 fcport->port_type = FCT_INITIATOR; 5412 else 5413 fcport->port_type = FCT_TARGET; 5414 } 5415 qlt_plogi_ack_unref(vha, pla); 5416 } else { 5417 fc_port_t *dfcp = NULL; 5418 5419 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5420 tfcp = qla2x00_find_fcport_by_nportid(vha, 5421 &e->u.new_sess.id, 1); 5422 if (tfcp && (tfcp != fcport)) { 5423 /* 5424 * We have a conflict fcport with same NportID. 5425 */ 5426 ql_dbg(ql_dbg_disc, vha, 0xffff, 5427 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5428 __func__, tfcp->port_name, tfcp->disc_state, 5429 tfcp->fw_login_state); 5430 5431 switch (tfcp->disc_state) { 5432 case DSC_DELETED: 5433 break; 5434 case DSC_DELETE_PEND: 5435 fcport->login_pause = 1; 5436 tfcp->conflict = fcport; 5437 break; 5438 default: 5439 fcport->login_pause = 1; 5440 tfcp->conflict = fcport; 5441 dfcp = tfcp; 5442 break; 5443 } 5444 } 5445 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5446 if (dfcp) 5447 qlt_schedule_sess_for_deletion(tfcp); 5448 5449 if (N2N_TOPO(vha->hw)) { 5450 fcport->flags &= ~FCF_FABRIC_DEVICE; 5451 fcport->keep_nport_handle = 1; 5452 if (vha->flags.nvme_enabled) { 5453 fcport->fc4_type = 5454 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5455 fcport->n2n_flag = 1; 5456 } 5457 fcport->fw_login_state = 0; 5458 5459 schedule_delayed_work(&vha->scan.scan_work, 5); 5460 } else { 5461 qla24xx_fcport_handle_login(vha, fcport); 5462 } 5463 } 5464 } 5465 5466 if (free_fcport) { 5467 qla2x00_free_fcport(fcport); 5468 if (pla) { 5469 list_del(&pla->list); 5470 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5471 } 5472 } 5473 } 5474 qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5475 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5476 { 5477 struct srb *sp = e->u.iosb.sp; 5478 int rval; 5479 5480 rval = qla2x00_start_sp(sp); 5481 if (rval != QLA_SUCCESS) { 5482 ql_dbg(ql_dbg_disc, vha, 0x2043, 5483 "%s: %s: Re-issue IOCB failed (%d).\n", 5484 __func__, sp->name, rval); 5485 qla24xx_sp_unmap(vha, sp); 5486 } 5487 } 5488 5489 void qla2x00_do_work(struct scsi_qla_host * vha)5490 qla2x00_do_work(struct scsi_qla_host *vha) 5491 { 5492 struct qla_work_evt *e, *tmp; 5493 unsigned long flags; 5494 LIST_HEAD(work); 5495 int rc; 5496 5497 spin_lock_irqsave(&vha->work_lock, flags); 5498 list_splice_init(&vha->work_list, &work); 5499 spin_unlock_irqrestore(&vha->work_lock, flags); 5500 5501 list_for_each_entry_safe(e, tmp, &work, list) { 5502 rc = QLA_SUCCESS; 5503 switch (e->type) { 5504 case QLA_EVT_AEN: 5505 fc_host_post_event(vha->host, fc_get_event_number(), 5506 e->u.aen.code, e->u.aen.data); 5507 break; 5508 case QLA_EVT_IDC_ACK: 5509 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5510 break; 5511 case QLA_EVT_ASYNC_LOGIN: 5512 qla2x00_async_login(vha, e->u.logio.fcport, 5513 e->u.logio.data); 5514 break; 5515 case QLA_EVT_ASYNC_LOGOUT: 5516 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5517 break; 5518 case QLA_EVT_ASYNC_ADISC: 5519 qla2x00_async_adisc(vha, e->u.logio.fcport, 5520 e->u.logio.data); 5521 break; 5522 case QLA_EVT_UEVENT: 5523 qla2x00_uevent_emit(vha, e->u.uevent.code); 5524 break; 5525 case QLA_EVT_AENFX: 5526 qlafx00_process_aen(vha, e); 5527 break; 5528 case QLA_EVT_UNMAP: 5529 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5530 break; 5531 case QLA_EVT_RELOGIN: 5532 qla2x00_relogin(vha); 5533 break; 5534 case QLA_EVT_NEW_SESS: 5535 qla24xx_create_new_sess(vha, e); 5536 break; 5537 case QLA_EVT_GPDB: 5538 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5539 e->u.fcport.opt); 5540 break; 5541 case QLA_EVT_PRLI: 5542 qla24xx_async_prli(vha, e->u.fcport.fcport); 5543 break; 5544 case QLA_EVT_GPSC: 5545 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5546 break; 5547 case QLA_EVT_GNL: 5548 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5549 break; 5550 case QLA_EVT_NACK: 5551 qla24xx_do_nack_work(vha, e); 5552 break; 5553 case QLA_EVT_ASYNC_PRLO: 5554 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5555 break; 5556 case QLA_EVT_ASYNC_PRLO_DONE: 5557 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5558 e->u.logio.data); 5559 break; 5560 case QLA_EVT_SCAN_CMD: 5561 qla_fab_async_scan(vha, e->u.iosb.sp); 5562 break; 5563 case QLA_EVT_SCAN_FINISH: 5564 qla_fab_scan_finish(vha, e->u.iosb.sp); 5565 break; 5566 case QLA_EVT_GFPNID: 5567 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5568 break; 5569 case QLA_EVT_SP_RETRY: 5570 qla_sp_retry(vha, e); 5571 break; 5572 case QLA_EVT_IIDMA: 5573 qla_do_iidma_work(vha, e->u.fcport.fcport); 5574 break; 5575 case QLA_EVT_ELS_PLOGI: 5576 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5577 e->u.fcport.fcport); 5578 break; 5579 case QLA_EVT_SA_REPLACE: 5580 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5581 break; 5582 } 5583 5584 if (rc == EAGAIN) { 5585 /* put 'work' at head of 'vha->work_list' */ 5586 spin_lock_irqsave(&vha->work_lock, flags); 5587 list_splice(&work, &vha->work_list); 5588 spin_unlock_irqrestore(&vha->work_lock, flags); 5589 break; 5590 } 5591 list_del_init(&e->list); 5592 if (e->flags & QLA_EVT_FLAG_FREE) 5593 kfree(e); 5594 5595 /* For each work completed decrement vha ref count */ 5596 QLA_VHA_MARK_NOT_BUSY(vha); 5597 } 5598 } 5599 qla24xx_post_relogin_work(struct scsi_qla_host * vha)5600 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5601 { 5602 struct qla_work_evt *e; 5603 5604 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5605 5606 if (!e) { 5607 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5608 return QLA_FUNCTION_FAILED; 5609 } 5610 5611 return qla2x00_post_work(vha, e); 5612 } 5613 5614 /* Relogins all the fcports of a vport 5615 * Context: dpc thread 5616 */ qla2x00_relogin(struct scsi_qla_host * vha)5617 void qla2x00_relogin(struct scsi_qla_host *vha) 5618 { 5619 fc_port_t *fcport; 5620 int status, relogin_needed = 0; 5621 struct event_arg ea; 5622 5623 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5624 /* 5625 * If the port is not ONLINE then try to login 5626 * to it if we haven't run out of retries. 5627 */ 5628 if (atomic_read(&fcport->state) != FCS_ONLINE && 5629 fcport->login_retry) { 5630 if (fcport->scan_state != QLA_FCPORT_FOUND || 5631 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5632 fcport->disc_state == DSC_LOGIN_COMPLETE) 5633 continue; 5634 5635 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5636 fcport->disc_state == DSC_DELETE_PEND) { 5637 relogin_needed = 1; 5638 } else { 5639 if (vha->hw->current_topology != ISP_CFG_NL) { 5640 memset(&ea, 0, sizeof(ea)); 5641 ea.fcport = fcport; 5642 qla24xx_handle_relogin_event(vha, &ea); 5643 } else if (vha->hw->current_topology == 5644 ISP_CFG_NL && 5645 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5646 (void)qla24xx_fcport_handle_login(vha, 5647 fcport); 5648 } else if (vha->hw->current_topology == 5649 ISP_CFG_NL) { 5650 fcport->login_retry--; 5651 status = 5652 qla2x00_local_device_login(vha, 5653 fcport); 5654 if (status == QLA_SUCCESS) { 5655 fcport->old_loop_id = 5656 fcport->loop_id; 5657 ql_dbg(ql_dbg_disc, vha, 0x2003, 5658 "Port login OK: logged in ID 0x%x.\n", 5659 fcport->loop_id); 5660 qla2x00_update_fcport 5661 (vha, fcport); 5662 } else if (status == 1) { 5663 set_bit(RELOGIN_NEEDED, 5664 &vha->dpc_flags); 5665 /* retry the login again */ 5666 ql_dbg(ql_dbg_disc, vha, 0x2007, 5667 "Retrying %d login again loop_id 0x%x.\n", 5668 fcport->login_retry, 5669 fcport->loop_id); 5670 } else { 5671 fcport->login_retry = 0; 5672 } 5673 5674 if (fcport->login_retry == 0 && 5675 status != QLA_SUCCESS) 5676 qla2x00_clear_loop_id(fcport); 5677 } 5678 } 5679 } 5680 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5681 break; 5682 } 5683 5684 if (relogin_needed) 5685 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5686 5687 ql_dbg(ql_dbg_disc, vha, 0x400e, 5688 "Relogin end.\n"); 5689 } 5690 5691 /* Schedule work on any of the dpc-workqueues */ 5692 void qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5693 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5694 { 5695 struct qla_hw_data *ha = base_vha->hw; 5696 5697 switch (work_code) { 5698 case MBA_IDC_AEN: /* 0x8200 */ 5699 if (ha->dpc_lp_wq) 5700 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5701 break; 5702 5703 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5704 if (!ha->flags.nic_core_reset_hdlr_active) { 5705 if (ha->dpc_hp_wq) 5706 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5707 } else 5708 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5709 "NIC Core reset is already active. Skip " 5710 "scheduling it again.\n"); 5711 break; 5712 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5713 if (ha->dpc_hp_wq) 5714 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5715 break; 5716 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5717 if (ha->dpc_hp_wq) 5718 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5719 break; 5720 default: 5721 ql_log(ql_log_warn, base_vha, 0xb05f, 5722 "Unknown work-code=0x%x.\n", work_code); 5723 } 5724 5725 return; 5726 } 5727 5728 /* Work: Perform NIC Core Unrecoverable state handling */ 5729 void qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5730 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5731 { 5732 struct qla_hw_data *ha = 5733 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5734 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5735 uint32_t dev_state = 0; 5736 5737 qla83xx_idc_lock(base_vha, 0); 5738 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5739 qla83xx_reset_ownership(base_vha); 5740 if (ha->flags.nic_core_reset_owner) { 5741 ha->flags.nic_core_reset_owner = 0; 5742 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5743 QLA8XXX_DEV_FAILED); 5744 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5745 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5746 } 5747 qla83xx_idc_unlock(base_vha, 0); 5748 } 5749 5750 /* Work: Execute IDC state handler */ 5751 void qla83xx_idc_state_handler_work(struct work_struct * work)5752 qla83xx_idc_state_handler_work(struct work_struct *work) 5753 { 5754 struct qla_hw_data *ha = 5755 container_of(work, struct qla_hw_data, idc_state_handler); 5756 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5757 uint32_t dev_state = 0; 5758 5759 qla83xx_idc_lock(base_vha, 0); 5760 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5761 if (dev_state == QLA8XXX_DEV_FAILED || 5762 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5763 qla83xx_idc_state_handler(base_vha); 5764 qla83xx_idc_unlock(base_vha, 0); 5765 } 5766 5767 static int qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5768 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5769 { 5770 int rval = QLA_SUCCESS; 5771 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5772 uint32_t heart_beat_counter1, heart_beat_counter2; 5773 5774 do { 5775 if (time_after(jiffies, heart_beat_wait)) { 5776 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5777 "Nic Core f/w is not alive.\n"); 5778 rval = QLA_FUNCTION_FAILED; 5779 break; 5780 } 5781 5782 qla83xx_idc_lock(base_vha, 0); 5783 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5784 &heart_beat_counter1); 5785 qla83xx_idc_unlock(base_vha, 0); 5786 msleep(100); 5787 qla83xx_idc_lock(base_vha, 0); 5788 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5789 &heart_beat_counter2); 5790 qla83xx_idc_unlock(base_vha, 0); 5791 } while (heart_beat_counter1 == heart_beat_counter2); 5792 5793 return rval; 5794 } 5795 5796 /* Work: Perform NIC Core Reset handling */ 5797 void qla83xx_nic_core_reset_work(struct work_struct * work)5798 qla83xx_nic_core_reset_work(struct work_struct *work) 5799 { 5800 struct qla_hw_data *ha = 5801 container_of(work, struct qla_hw_data, nic_core_reset); 5802 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5803 uint32_t dev_state = 0; 5804 5805 if (IS_QLA2031(ha)) { 5806 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5807 ql_log(ql_log_warn, base_vha, 0xb081, 5808 "Failed to dump mctp\n"); 5809 return; 5810 } 5811 5812 if (!ha->flags.nic_core_reset_hdlr_active) { 5813 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5814 qla83xx_idc_lock(base_vha, 0); 5815 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5816 &dev_state); 5817 qla83xx_idc_unlock(base_vha, 0); 5818 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5819 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5820 "Nic Core f/w is alive.\n"); 5821 return; 5822 } 5823 } 5824 5825 ha->flags.nic_core_reset_hdlr_active = 1; 5826 if (qla83xx_nic_core_reset(base_vha)) { 5827 /* NIC Core reset failed. */ 5828 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5829 "NIC Core reset failed.\n"); 5830 } 5831 ha->flags.nic_core_reset_hdlr_active = 0; 5832 } 5833 } 5834 5835 /* Work: Handle 8200 IDC aens */ 5836 void qla83xx_service_idc_aen(struct work_struct * work)5837 qla83xx_service_idc_aen(struct work_struct *work) 5838 { 5839 struct qla_hw_data *ha = 5840 container_of(work, struct qla_hw_data, idc_aen); 5841 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5842 uint32_t dev_state, idc_control; 5843 5844 qla83xx_idc_lock(base_vha, 0); 5845 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5846 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5847 qla83xx_idc_unlock(base_vha, 0); 5848 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5849 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5850 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5851 "Application requested NIC Core Reset.\n"); 5852 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5853 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5854 QLA_SUCCESS) { 5855 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5856 "Other protocol driver requested NIC Core Reset.\n"); 5857 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5858 } 5859 } else if (dev_state == QLA8XXX_DEV_FAILED || 5860 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5861 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5862 } 5863 } 5864 5865 /* 5866 * Control the frequency of IDC lock retries 5867 */ 5868 #define QLA83XX_WAIT_LOGIC_MS 100 5869 5870 static int qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5871 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5872 { 5873 int rval; 5874 uint32_t data; 5875 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5876 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5877 struct qla_hw_data *ha = base_vha->hw; 5878 5879 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5880 "Trying force recovery of the IDC lock.\n"); 5881 5882 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5883 if (rval) 5884 return rval; 5885 5886 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5887 return QLA_SUCCESS; 5888 } else { 5889 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5890 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5891 data); 5892 if (rval) 5893 return rval; 5894 5895 msleep(200); 5896 5897 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5898 &data); 5899 if (rval) 5900 return rval; 5901 5902 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5903 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5904 ~(idc_lck_rcvry_stage_mask)); 5905 rval = qla83xx_wr_reg(base_vha, 5906 QLA83XX_IDC_LOCK_RECOVERY, data); 5907 if (rval) 5908 return rval; 5909 5910 /* Forcefully perform IDC UnLock */ 5911 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5912 &data); 5913 if (rval) 5914 return rval; 5915 /* Clear lock-id by setting 0xff */ 5916 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5917 0xff); 5918 if (rval) 5919 return rval; 5920 /* Clear lock-recovery by setting 0x0 */ 5921 rval = qla83xx_wr_reg(base_vha, 5922 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5923 if (rval) 5924 return rval; 5925 } else 5926 return QLA_SUCCESS; 5927 } 5928 5929 return rval; 5930 } 5931 5932 static int qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5933 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5934 { 5935 int rval = QLA_SUCCESS; 5936 uint32_t o_drv_lockid, n_drv_lockid; 5937 unsigned long lock_recovery_timeout; 5938 5939 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5940 retry_lockid: 5941 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5942 if (rval) 5943 goto exit; 5944 5945 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5946 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5947 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5948 return QLA_SUCCESS; 5949 else 5950 return QLA_FUNCTION_FAILED; 5951 } 5952 5953 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5954 if (rval) 5955 goto exit; 5956 5957 if (o_drv_lockid == n_drv_lockid) { 5958 msleep(QLA83XX_WAIT_LOGIC_MS); 5959 goto retry_lockid; 5960 } else 5961 return QLA_SUCCESS; 5962 5963 exit: 5964 return rval; 5965 } 5966 5967 /* 5968 * Context: task, can sleep 5969 */ 5970 void qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5971 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5972 { 5973 uint32_t data; 5974 uint32_t lock_owner; 5975 struct qla_hw_data *ha = base_vha->hw; 5976 5977 might_sleep(); 5978 5979 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5980 retry_lock: 5981 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5982 == QLA_SUCCESS) { 5983 if (data) { 5984 /* Setting lock-id to our function-number */ 5985 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5986 ha->portnum); 5987 } else { 5988 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5989 &lock_owner); 5990 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5991 "Failed to acquire IDC lock, acquired by %d, " 5992 "retrying...\n", lock_owner); 5993 5994 /* Retry/Perform IDC-Lock recovery */ 5995 if (qla83xx_idc_lock_recovery(base_vha) 5996 == QLA_SUCCESS) { 5997 msleep(QLA83XX_WAIT_LOGIC_MS); 5998 goto retry_lock; 5999 } else 6000 ql_log(ql_log_warn, base_vha, 0xb075, 6001 "IDC Lock recovery FAILED.\n"); 6002 } 6003 6004 } 6005 6006 return; 6007 } 6008 6009 static bool qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)6010 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 6011 struct purex_entry_24xx *purex) 6012 { 6013 char fwstr[16]; 6014 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 6015 struct port_database_24xx *pdb; 6016 6017 /* Domain Controller is always logged-out. */ 6018 /* if RDP request is not from Domain Controller: */ 6019 if (sid != 0xfffc01) 6020 return false; 6021 6022 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 6023 6024 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 6025 if (!pdb) { 6026 ql_dbg(ql_dbg_init, vha, 0x0181, 6027 "%s: Failed allocate pdb\n", __func__); 6028 } else if (qla24xx_get_port_database(vha, 6029 le16_to_cpu(purex->nport_handle), pdb)) { 6030 ql_dbg(ql_dbg_init, vha, 0x0181, 6031 "%s: Failed get pdb sid=%x\n", __func__, sid); 6032 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6033 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6034 ql_dbg(ql_dbg_init, vha, 0x0181, 6035 "%s: Port not logged in sid=%#x\n", __func__, sid); 6036 } else { 6037 /* RDP request is from logged in port */ 6038 kfree(pdb); 6039 return false; 6040 } 6041 kfree(pdb); 6042 6043 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6044 fwstr[strcspn(fwstr, " ")] = 0; 6045 /* if FW version allows RDP response length upto 2048 bytes: */ 6046 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6047 return false; 6048 6049 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6050 6051 /* RDP response length is to be reduced to maximum 256 bytes */ 6052 return true; 6053 } 6054 6055 /* 6056 * Function Name: qla24xx_process_purex_iocb 6057 * 6058 * Description: 6059 * Prepare a RDP response and send to Fabric switch 6060 * 6061 * PARAMETERS: 6062 * vha: SCSI qla host 6063 * purex: RDP request received by HBA 6064 */ qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)6065 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6066 struct purex_item *item) 6067 { 6068 struct qla_hw_data *ha = vha->hw; 6069 struct purex_entry_24xx *purex = 6070 (struct purex_entry_24xx *)&item->iocb; 6071 dma_addr_t rsp_els_dma; 6072 dma_addr_t rsp_payload_dma; 6073 dma_addr_t stat_dma; 6074 dma_addr_t sfp_dma; 6075 struct els_entry_24xx *rsp_els = NULL; 6076 struct rdp_rsp_payload *rsp_payload = NULL; 6077 struct link_statistics *stat = NULL; 6078 uint8_t *sfp = NULL; 6079 uint16_t sfp_flags = 0; 6080 uint rsp_payload_length = sizeof(*rsp_payload); 6081 int rval; 6082 6083 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6084 "%s: Enter\n", __func__); 6085 6086 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6087 "-------- ELS REQ -------\n"); 6088 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6089 purex, sizeof(*purex)); 6090 6091 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6092 rsp_payload_length = 6093 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6094 ql_dbg(ql_dbg_init, vha, 0x0181, 6095 "Reducing RSP payload length to %u bytes...\n", 6096 rsp_payload_length); 6097 } 6098 6099 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6100 &rsp_els_dma, GFP_KERNEL); 6101 if (!rsp_els) { 6102 ql_log(ql_log_warn, vha, 0x0183, 6103 "Failed allocate dma buffer ELS RSP.\n"); 6104 goto dealloc; 6105 } 6106 6107 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6108 &rsp_payload_dma, GFP_KERNEL); 6109 if (!rsp_payload) { 6110 ql_log(ql_log_warn, vha, 0x0184, 6111 "Failed allocate dma buffer ELS RSP payload.\n"); 6112 goto dealloc; 6113 } 6114 6115 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6116 &sfp_dma, GFP_KERNEL); 6117 6118 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6119 &stat_dma, GFP_KERNEL); 6120 6121 /* Prepare Response IOCB */ 6122 rsp_els->entry_type = ELS_IOCB_TYPE; 6123 rsp_els->entry_count = 1; 6124 rsp_els->sys_define = 0; 6125 rsp_els->entry_status = 0; 6126 rsp_els->handle = 0; 6127 rsp_els->nport_handle = purex->nport_handle; 6128 rsp_els->tx_dsd_count = cpu_to_le16(1); 6129 rsp_els->vp_index = purex->vp_idx; 6130 rsp_els->sof_type = EST_SOFI3; 6131 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6132 rsp_els->rx_dsd_count = 0; 6133 rsp_els->opcode = purex->els_frame_payload[0]; 6134 6135 rsp_els->d_id[0] = purex->s_id[0]; 6136 rsp_els->d_id[1] = purex->s_id[1]; 6137 rsp_els->d_id[2] = purex->s_id[2]; 6138 6139 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6140 rsp_els->rx_byte_count = 0; 6141 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6142 6143 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6144 rsp_els->tx_len = rsp_els->tx_byte_count; 6145 6146 rsp_els->rx_address = 0; 6147 rsp_els->rx_len = 0; 6148 6149 /* Prepare Response Payload */ 6150 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6151 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6152 sizeof(rsp_payload->hdr)); 6153 6154 /* Link service Request Info Descriptor */ 6155 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6156 rsp_payload->ls_req_info_desc.desc_len = 6157 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6158 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6159 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6160 6161 /* Link service Request Info Descriptor 2 */ 6162 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6163 rsp_payload->ls_req_info_desc2.desc_len = 6164 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6165 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6166 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6167 6168 6169 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6170 rsp_payload->sfp_diag_desc.desc_len = 6171 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6172 6173 if (sfp) { 6174 /* SFP Flags */ 6175 memset(sfp, 0, SFP_RTDI_LEN); 6176 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6177 if (!rval) { 6178 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6179 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6180 sfp_flags |= BIT_0; /* short wave */ 6181 else if (sfp[0] & BIT_1) 6182 sfp_flags |= BIT_1; /* long wave 1310nm */ 6183 else if (sfp[1] & BIT_4) 6184 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6185 } 6186 6187 /* SFP Type */ 6188 memset(sfp, 0, SFP_RTDI_LEN); 6189 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6190 if (!rval) { 6191 sfp_flags |= BIT_4; /* optical */ 6192 if (sfp[0] == 0x3) 6193 sfp_flags |= BIT_6; /* sfp+ */ 6194 } 6195 6196 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6197 6198 /* SFP Diagnostics */ 6199 memset(sfp, 0, SFP_RTDI_LEN); 6200 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6201 if (!rval) { 6202 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6203 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6204 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6205 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6206 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6207 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6208 } 6209 } 6210 6211 /* Port Speed Descriptor */ 6212 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6213 rsp_payload->port_speed_desc.desc_len = 6214 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6215 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6216 qla25xx_fdmi_port_speed_capability(ha)); 6217 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6218 qla25xx_fdmi_port_speed_currently(ha)); 6219 6220 /* Link Error Status Descriptor */ 6221 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6222 rsp_payload->ls_err_desc.desc_len = 6223 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6224 6225 if (stat) { 6226 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6227 if (!rval) { 6228 rsp_payload->ls_err_desc.link_fail_cnt = 6229 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6230 rsp_payload->ls_err_desc.loss_sync_cnt = 6231 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6232 rsp_payload->ls_err_desc.loss_sig_cnt = 6233 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6234 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6235 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6236 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6237 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6238 rsp_payload->ls_err_desc.inval_crc_cnt = 6239 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6240 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6241 } 6242 } 6243 6244 /* Portname Descriptor */ 6245 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6246 rsp_payload->port_name_diag_desc.desc_len = 6247 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6248 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6249 vha->node_name, 6250 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6251 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6252 vha->port_name, 6253 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6254 6255 /* F-Port Portname Descriptor */ 6256 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6257 rsp_payload->port_name_direct_desc.desc_len = 6258 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6259 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6260 vha->fabric_node_name, 6261 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6262 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6263 vha->fabric_port_name, 6264 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6265 6266 /* Bufer Credit Descriptor */ 6267 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6268 rsp_payload->buffer_credit_desc.desc_len = 6269 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6270 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6271 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6272 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6273 6274 if (ha->flags.plogi_template_valid) { 6275 uint32_t tmp = 6276 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6277 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6278 } 6279 6280 if (rsp_payload_length < sizeof(*rsp_payload)) 6281 goto send; 6282 6283 /* Optical Element Descriptor, Temperature */ 6284 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6285 rsp_payload->optical_elmt_desc[0].desc_len = 6286 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6287 /* Optical Element Descriptor, Voltage */ 6288 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6289 rsp_payload->optical_elmt_desc[1].desc_len = 6290 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6291 /* Optical Element Descriptor, Tx Bias Current */ 6292 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6293 rsp_payload->optical_elmt_desc[2].desc_len = 6294 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6295 /* Optical Element Descriptor, Tx Power */ 6296 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6297 rsp_payload->optical_elmt_desc[3].desc_len = 6298 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6299 /* Optical Element Descriptor, Rx Power */ 6300 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6301 rsp_payload->optical_elmt_desc[4].desc_len = 6302 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6303 6304 if (sfp) { 6305 memset(sfp, 0, SFP_RTDI_LEN); 6306 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6307 if (!rval) { 6308 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6309 6310 /* Optical Element Descriptor, Temperature */ 6311 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6312 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6313 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6314 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6315 rsp_payload->optical_elmt_desc[0].element_flags = 6316 cpu_to_be32(1 << 28); 6317 6318 /* Optical Element Descriptor, Voltage */ 6319 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6320 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6321 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6322 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6323 rsp_payload->optical_elmt_desc[1].element_flags = 6324 cpu_to_be32(2 << 28); 6325 6326 /* Optical Element Descriptor, Tx Bias Current */ 6327 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6328 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6329 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6330 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6331 rsp_payload->optical_elmt_desc[2].element_flags = 6332 cpu_to_be32(3 << 28); 6333 6334 /* Optical Element Descriptor, Tx Power */ 6335 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6336 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6337 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6338 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6339 rsp_payload->optical_elmt_desc[3].element_flags = 6340 cpu_to_be32(4 << 28); 6341 6342 /* Optical Element Descriptor, Rx Power */ 6343 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6344 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6345 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6346 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6347 rsp_payload->optical_elmt_desc[4].element_flags = 6348 cpu_to_be32(5 << 28); 6349 } 6350 6351 memset(sfp, 0, SFP_RTDI_LEN); 6352 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6353 if (!rval) { 6354 /* Temperature high/low alarm/warning */ 6355 rsp_payload->optical_elmt_desc[0].element_flags |= 6356 cpu_to_be32( 6357 (sfp[0] >> 7 & 1) << 3 | 6358 (sfp[0] >> 6 & 1) << 2 | 6359 (sfp[4] >> 7 & 1) << 1 | 6360 (sfp[4] >> 6 & 1) << 0); 6361 6362 /* Voltage high/low alarm/warning */ 6363 rsp_payload->optical_elmt_desc[1].element_flags |= 6364 cpu_to_be32( 6365 (sfp[0] >> 5 & 1) << 3 | 6366 (sfp[0] >> 4 & 1) << 2 | 6367 (sfp[4] >> 5 & 1) << 1 | 6368 (sfp[4] >> 4 & 1) << 0); 6369 6370 /* Tx Bias Current high/low alarm/warning */ 6371 rsp_payload->optical_elmt_desc[2].element_flags |= 6372 cpu_to_be32( 6373 (sfp[0] >> 3 & 1) << 3 | 6374 (sfp[0] >> 2 & 1) << 2 | 6375 (sfp[4] >> 3 & 1) << 1 | 6376 (sfp[4] >> 2 & 1) << 0); 6377 6378 /* Tx Power high/low alarm/warning */ 6379 rsp_payload->optical_elmt_desc[3].element_flags |= 6380 cpu_to_be32( 6381 (sfp[0] >> 1 & 1) << 3 | 6382 (sfp[0] >> 0 & 1) << 2 | 6383 (sfp[4] >> 1 & 1) << 1 | 6384 (sfp[4] >> 0 & 1) << 0); 6385 6386 /* Rx Power high/low alarm/warning */ 6387 rsp_payload->optical_elmt_desc[4].element_flags |= 6388 cpu_to_be32( 6389 (sfp[1] >> 7 & 1) << 3 | 6390 (sfp[1] >> 6 & 1) << 2 | 6391 (sfp[5] >> 7 & 1) << 1 | 6392 (sfp[5] >> 6 & 1) << 0); 6393 } 6394 } 6395 6396 /* Optical Product Data Descriptor */ 6397 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6398 rsp_payload->optical_prod_desc.desc_len = 6399 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6400 6401 if (sfp) { 6402 memset(sfp, 0, SFP_RTDI_LEN); 6403 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6404 if (!rval) { 6405 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6406 sfp + 0, 6407 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6408 memcpy(rsp_payload->optical_prod_desc.part_number, 6409 sfp + 20, 6410 sizeof(rsp_payload->optical_prod_desc.part_number)); 6411 memcpy(rsp_payload->optical_prod_desc.revision, 6412 sfp + 36, 6413 sizeof(rsp_payload->optical_prod_desc.revision)); 6414 memcpy(rsp_payload->optical_prod_desc.serial_number, 6415 sfp + 48, 6416 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6417 } 6418 6419 memset(sfp, 0, SFP_RTDI_LEN); 6420 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6421 if (!rval) { 6422 memcpy(rsp_payload->optical_prod_desc.date, 6423 sfp + 0, 6424 sizeof(rsp_payload->optical_prod_desc.date)); 6425 } 6426 } 6427 6428 send: 6429 ql_dbg(ql_dbg_init, vha, 0x0183, 6430 "Sending ELS Response to RDP Request...\n"); 6431 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6432 "-------- ELS RSP -------\n"); 6433 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6434 rsp_els, sizeof(*rsp_els)); 6435 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6436 "-------- ELS RSP PAYLOAD -------\n"); 6437 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6438 rsp_payload, rsp_payload_length); 6439 6440 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6441 6442 if (rval) { 6443 ql_log(ql_log_warn, vha, 0x0188, 6444 "%s: iocb failed to execute -> %x\n", __func__, rval); 6445 } else if (rsp_els->comp_status) { 6446 ql_log(ql_log_warn, vha, 0x0189, 6447 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6448 __func__, rsp_els->comp_status, 6449 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6450 } else { 6451 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6452 } 6453 6454 dealloc: 6455 if (stat) 6456 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6457 stat, stat_dma); 6458 if (sfp) 6459 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6460 sfp, sfp_dma); 6461 if (rsp_payload) 6462 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6463 rsp_payload, rsp_payload_dma); 6464 if (rsp_els) 6465 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6466 rsp_els, rsp_els_dma); 6467 } 6468 6469 void qla24xx_free_purex_item(struct purex_item * item)6470 qla24xx_free_purex_item(struct purex_item *item) 6471 { 6472 if (item == &item->vha->default_item) 6473 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6474 else 6475 kfree(item); 6476 } 6477 qla24xx_process_purex_list(struct purex_list * list)6478 void qla24xx_process_purex_list(struct purex_list *list) 6479 { 6480 struct list_head head = LIST_HEAD_INIT(head); 6481 struct purex_item *item, *next; 6482 ulong flags; 6483 6484 spin_lock_irqsave(&list->lock, flags); 6485 list_splice_init(&list->head, &head); 6486 spin_unlock_irqrestore(&list->lock, flags); 6487 6488 list_for_each_entry_safe(item, next, &head, list) { 6489 list_del(&item->list); 6490 item->process_item(item->vha, item); 6491 qla24xx_free_purex_item(item); 6492 } 6493 } 6494 6495 /* 6496 * Context: task, can sleep 6497 */ 6498 void qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6499 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6500 { 6501 #if 0 6502 uint16_t options = (requester_id << 15) | BIT_7; 6503 #endif 6504 uint16_t retry; 6505 uint32_t data; 6506 struct qla_hw_data *ha = base_vha->hw; 6507 6508 might_sleep(); 6509 6510 /* IDC-unlock implementation using driver-unlock/lock-id 6511 * remote registers 6512 */ 6513 retry = 0; 6514 retry_unlock: 6515 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6516 == QLA_SUCCESS) { 6517 if (data == ha->portnum) { 6518 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6519 /* Clearing lock-id by setting 0xff */ 6520 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6521 } else if (retry < 10) { 6522 /* SV: XXX: IDC unlock retrying needed here? */ 6523 6524 /* Retry for IDC-unlock */ 6525 msleep(QLA83XX_WAIT_LOGIC_MS); 6526 retry++; 6527 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6528 "Failed to release IDC lock, retrying=%d\n", retry); 6529 goto retry_unlock; 6530 } 6531 } else if (retry < 10) { 6532 /* Retry for IDC-unlock */ 6533 msleep(QLA83XX_WAIT_LOGIC_MS); 6534 retry++; 6535 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6536 "Failed to read drv-lockid, retrying=%d\n", retry); 6537 goto retry_unlock; 6538 } 6539 6540 return; 6541 6542 #if 0 6543 /* XXX: IDC-unlock implementation using access-control mbx */ 6544 retry = 0; 6545 retry_unlock2: 6546 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6547 if (retry < 10) { 6548 /* Retry for IDC-unlock */ 6549 msleep(QLA83XX_WAIT_LOGIC_MS); 6550 retry++; 6551 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6552 "Failed to release IDC lock, retrying=%d\n", retry); 6553 goto retry_unlock2; 6554 } 6555 } 6556 6557 return; 6558 #endif 6559 } 6560 6561 int __qla83xx_set_drv_presence(scsi_qla_host_t * vha)6562 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6563 { 6564 int rval = QLA_SUCCESS; 6565 struct qla_hw_data *ha = vha->hw; 6566 uint32_t drv_presence; 6567 6568 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6569 if (rval == QLA_SUCCESS) { 6570 drv_presence |= (1 << ha->portnum); 6571 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6572 drv_presence); 6573 } 6574 6575 return rval; 6576 } 6577 6578 int qla83xx_set_drv_presence(scsi_qla_host_t * vha)6579 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6580 { 6581 int rval = QLA_SUCCESS; 6582 6583 qla83xx_idc_lock(vha, 0); 6584 rval = __qla83xx_set_drv_presence(vha); 6585 qla83xx_idc_unlock(vha, 0); 6586 6587 return rval; 6588 } 6589 6590 int __qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6591 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6592 { 6593 int rval = QLA_SUCCESS; 6594 struct qla_hw_data *ha = vha->hw; 6595 uint32_t drv_presence; 6596 6597 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6598 if (rval == QLA_SUCCESS) { 6599 drv_presence &= ~(1 << ha->portnum); 6600 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6601 drv_presence); 6602 } 6603 6604 return rval; 6605 } 6606 6607 int qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6608 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6609 { 6610 int rval = QLA_SUCCESS; 6611 6612 qla83xx_idc_lock(vha, 0); 6613 rval = __qla83xx_clear_drv_presence(vha); 6614 qla83xx_idc_unlock(vha, 0); 6615 6616 return rval; 6617 } 6618 6619 static void qla83xx_need_reset_handler(scsi_qla_host_t * vha)6620 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6621 { 6622 struct qla_hw_data *ha = vha->hw; 6623 uint32_t drv_ack, drv_presence; 6624 unsigned long ack_timeout; 6625 6626 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6627 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6628 while (1) { 6629 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6630 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6631 if ((drv_ack & drv_presence) == drv_presence) 6632 break; 6633 6634 if (time_after_eq(jiffies, ack_timeout)) { 6635 ql_log(ql_log_warn, vha, 0xb067, 6636 "RESET ACK TIMEOUT! drv_presence=0x%x " 6637 "drv_ack=0x%x\n", drv_presence, drv_ack); 6638 /* 6639 * The function(s) which did not ack in time are forced 6640 * to withdraw any further participation in the IDC 6641 * reset. 6642 */ 6643 if (drv_ack != drv_presence) 6644 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6645 drv_ack); 6646 break; 6647 } 6648 6649 qla83xx_idc_unlock(vha, 0); 6650 msleep(1000); 6651 qla83xx_idc_lock(vha, 0); 6652 } 6653 6654 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6655 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6656 } 6657 6658 static int qla83xx_device_bootstrap(scsi_qla_host_t * vha)6659 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6660 { 6661 int rval = QLA_SUCCESS; 6662 uint32_t idc_control; 6663 6664 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6665 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6666 6667 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6668 __qla83xx_get_idc_control(vha, &idc_control); 6669 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6670 __qla83xx_set_idc_control(vha, 0); 6671 6672 qla83xx_idc_unlock(vha, 0); 6673 rval = qla83xx_restart_nic_firmware(vha); 6674 qla83xx_idc_lock(vha, 0); 6675 6676 if (rval != QLA_SUCCESS) { 6677 ql_log(ql_log_fatal, vha, 0xb06a, 6678 "Failed to restart NIC f/w.\n"); 6679 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6680 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6681 } else { 6682 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6683 "Success in restarting nic f/w.\n"); 6684 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6685 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6686 } 6687 6688 return rval; 6689 } 6690 6691 /* Assumes idc_lock always held on entry */ 6692 int qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6693 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6694 { 6695 struct qla_hw_data *ha = base_vha->hw; 6696 int rval = QLA_SUCCESS; 6697 unsigned long dev_init_timeout; 6698 uint32_t dev_state; 6699 6700 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6701 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6702 6703 while (1) { 6704 6705 if (time_after_eq(jiffies, dev_init_timeout)) { 6706 ql_log(ql_log_warn, base_vha, 0xb06e, 6707 "Initialization TIMEOUT!\n"); 6708 /* Init timeout. Disable further NIC Core 6709 * communication. 6710 */ 6711 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6712 QLA8XXX_DEV_FAILED); 6713 ql_log(ql_log_info, base_vha, 0xb06f, 6714 "HW State: FAILED.\n"); 6715 } 6716 6717 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6718 switch (dev_state) { 6719 case QLA8XXX_DEV_READY: 6720 if (ha->flags.nic_core_reset_owner) 6721 qla83xx_idc_audit(base_vha, 6722 IDC_AUDIT_COMPLETION); 6723 ha->flags.nic_core_reset_owner = 0; 6724 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6725 "Reset_owner reset by 0x%x.\n", 6726 ha->portnum); 6727 goto exit; 6728 case QLA8XXX_DEV_COLD: 6729 if (ha->flags.nic_core_reset_owner) 6730 rval = qla83xx_device_bootstrap(base_vha); 6731 else { 6732 /* Wait for AEN to change device-state */ 6733 qla83xx_idc_unlock(base_vha, 0); 6734 msleep(1000); 6735 qla83xx_idc_lock(base_vha, 0); 6736 } 6737 break; 6738 case QLA8XXX_DEV_INITIALIZING: 6739 /* Wait for AEN to change device-state */ 6740 qla83xx_idc_unlock(base_vha, 0); 6741 msleep(1000); 6742 qla83xx_idc_lock(base_vha, 0); 6743 break; 6744 case QLA8XXX_DEV_NEED_RESET: 6745 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6746 qla83xx_need_reset_handler(base_vha); 6747 else { 6748 /* Wait for AEN to change device-state */ 6749 qla83xx_idc_unlock(base_vha, 0); 6750 msleep(1000); 6751 qla83xx_idc_lock(base_vha, 0); 6752 } 6753 /* reset timeout value after need reset handler */ 6754 dev_init_timeout = jiffies + 6755 (ha->fcoe_dev_init_timeout * HZ); 6756 break; 6757 case QLA8XXX_DEV_NEED_QUIESCENT: 6758 /* XXX: DEBUG for now */ 6759 qla83xx_idc_unlock(base_vha, 0); 6760 msleep(1000); 6761 qla83xx_idc_lock(base_vha, 0); 6762 break; 6763 case QLA8XXX_DEV_QUIESCENT: 6764 /* XXX: DEBUG for now */ 6765 if (ha->flags.quiesce_owner) 6766 goto exit; 6767 6768 qla83xx_idc_unlock(base_vha, 0); 6769 msleep(1000); 6770 qla83xx_idc_lock(base_vha, 0); 6771 dev_init_timeout = jiffies + 6772 (ha->fcoe_dev_init_timeout * HZ); 6773 break; 6774 case QLA8XXX_DEV_FAILED: 6775 if (ha->flags.nic_core_reset_owner) 6776 qla83xx_idc_audit(base_vha, 6777 IDC_AUDIT_COMPLETION); 6778 ha->flags.nic_core_reset_owner = 0; 6779 __qla83xx_clear_drv_presence(base_vha); 6780 qla83xx_idc_unlock(base_vha, 0); 6781 qla8xxx_dev_failed_handler(base_vha); 6782 rval = QLA_FUNCTION_FAILED; 6783 qla83xx_idc_lock(base_vha, 0); 6784 goto exit; 6785 case QLA8XXX_BAD_VALUE: 6786 qla83xx_idc_unlock(base_vha, 0); 6787 msleep(1000); 6788 qla83xx_idc_lock(base_vha, 0); 6789 break; 6790 default: 6791 ql_log(ql_log_warn, base_vha, 0xb071, 6792 "Unknown Device State: %x.\n", dev_state); 6793 qla83xx_idc_unlock(base_vha, 0); 6794 qla8xxx_dev_failed_handler(base_vha); 6795 rval = QLA_FUNCTION_FAILED; 6796 qla83xx_idc_lock(base_vha, 0); 6797 goto exit; 6798 } 6799 } 6800 6801 exit: 6802 return rval; 6803 } 6804 6805 void qla2x00_disable_board_on_pci_error(struct work_struct * work)6806 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6807 { 6808 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6809 board_disable); 6810 struct pci_dev *pdev = ha->pdev; 6811 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6812 6813 ql_log(ql_log_warn, base_vha, 0x015b, 6814 "Disabling adapter.\n"); 6815 6816 if (!atomic_read(&pdev->enable_cnt)) { 6817 ql_log(ql_log_info, base_vha, 0xfffc, 6818 "PCI device disabled, no action req for PCI error=%lx\n", 6819 base_vha->pci_flags); 6820 return; 6821 } 6822 6823 /* 6824 * if UNLOADING flag is already set, then continue unload, 6825 * where it was set first. 6826 */ 6827 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6828 return; 6829 6830 qla2x00_wait_for_sess_deletion(base_vha); 6831 6832 qla2x00_delete_all_vps(ha, base_vha); 6833 6834 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6835 6836 qla2x00_dfs_remove(base_vha); 6837 6838 qla84xx_put_chip(base_vha); 6839 6840 if (base_vha->timer_active) 6841 qla2x00_stop_timer(base_vha); 6842 6843 base_vha->flags.online = 0; 6844 6845 qla2x00_destroy_deferred_work(ha); 6846 6847 /* 6848 * Do not try to stop beacon blink as it will issue a mailbox 6849 * command. 6850 */ 6851 qla2x00_free_sysfs_attr(base_vha, false); 6852 6853 fc_remove_host(base_vha->host); 6854 6855 scsi_remove_host(base_vha->host); 6856 6857 base_vha->flags.init_done = 0; 6858 qla25xx_delete_queues(base_vha); 6859 qla2x00_free_fcports(base_vha); 6860 qla2x00_free_irqs(base_vha); 6861 qla2x00_mem_free(ha); 6862 qla82xx_md_free(base_vha); 6863 qla2x00_free_queues(ha); 6864 6865 qla2x00_unmap_iobases(ha); 6866 6867 pci_release_selected_regions(ha->pdev, ha->bars); 6868 pci_disable_device(pdev); 6869 6870 /* 6871 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6872 */ 6873 } 6874 6875 /************************************************************************** 6876 * qla2x00_do_dpc 6877 * This kernel thread is a task that is schedule by the interrupt handler 6878 * to perform the background processing for interrupts. 6879 * 6880 * Notes: 6881 * This task always run in the context of a kernel thread. It 6882 * is kick-off by the driver's detect code and starts up 6883 * up one per adapter. It immediately goes to sleep and waits for 6884 * some fibre event. When either the interrupt handler or 6885 * the timer routine detects a event it will one of the task 6886 * bits then wake us up. 6887 **************************************************************************/ 6888 static int qla2x00_do_dpc(void * data)6889 qla2x00_do_dpc(void *data) 6890 { 6891 scsi_qla_host_t *base_vha; 6892 struct qla_hw_data *ha; 6893 uint32_t online; 6894 struct qla_qpair *qpair; 6895 6896 ha = (struct qla_hw_data *)data; 6897 base_vha = pci_get_drvdata(ha->pdev); 6898 6899 set_user_nice(current, MIN_NICE); 6900 6901 set_current_state(TASK_INTERRUPTIBLE); 6902 while (1) { 6903 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6904 "DPC handler sleeping.\n"); 6905 6906 schedule(); 6907 6908 if (kthread_should_stop()) 6909 break; 6910 6911 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6912 qla_pci_set_eeh_busy(base_vha); 6913 6914 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6915 goto end_loop; 6916 6917 if (ha->flags.eeh_busy) { 6918 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6919 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6920 goto end_loop; 6921 } 6922 6923 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6924 /* don't do any work. Wait to be terminated by kthread_stop */ 6925 goto end_loop; 6926 6927 ha->dpc_active = 1; 6928 6929 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6930 "DPC handler waking up, dpc_flags=0x%lx.\n", 6931 base_vha->dpc_flags); 6932 6933 if (IS_P3P_TYPE(ha)) { 6934 if (IS_QLA8044(ha)) { 6935 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6936 &base_vha->dpc_flags)) { 6937 qla8044_idc_lock(ha); 6938 qla8044_wr_direct(base_vha, 6939 QLA8044_CRB_DEV_STATE_INDEX, 6940 QLA8XXX_DEV_FAILED); 6941 qla8044_idc_unlock(ha); 6942 ql_log(ql_log_info, base_vha, 0x4004, 6943 "HW State: FAILED.\n"); 6944 qla8044_device_state_handler(base_vha); 6945 continue; 6946 } 6947 6948 } else { 6949 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6950 &base_vha->dpc_flags)) { 6951 qla82xx_idc_lock(ha); 6952 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6953 QLA8XXX_DEV_FAILED); 6954 qla82xx_idc_unlock(ha); 6955 ql_log(ql_log_info, base_vha, 0x0151, 6956 "HW State: FAILED.\n"); 6957 qla82xx_device_state_handler(base_vha); 6958 continue; 6959 } 6960 } 6961 6962 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6963 &base_vha->dpc_flags)) { 6964 6965 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6966 "FCoE context reset scheduled.\n"); 6967 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6968 &base_vha->dpc_flags))) { 6969 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6970 /* FCoE-ctx reset failed. 6971 * Escalate to chip-reset 6972 */ 6973 set_bit(ISP_ABORT_NEEDED, 6974 &base_vha->dpc_flags); 6975 } 6976 clear_bit(ABORT_ISP_ACTIVE, 6977 &base_vha->dpc_flags); 6978 } 6979 6980 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6981 "FCoE context reset end.\n"); 6982 } 6983 } else if (IS_QLAFX00(ha)) { 6984 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6985 &base_vha->dpc_flags)) { 6986 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6987 "Firmware Reset Recovery\n"); 6988 if (qlafx00_reset_initialize(base_vha)) { 6989 /* Failed. Abort isp later. */ 6990 if (!test_bit(UNLOADING, 6991 &base_vha->dpc_flags)) { 6992 set_bit(ISP_UNRECOVERABLE, 6993 &base_vha->dpc_flags); 6994 ql_dbg(ql_dbg_dpc, base_vha, 6995 0x4021, 6996 "Reset Recovery Failed\n"); 6997 } 6998 } 6999 } 7000 7001 if (test_and_clear_bit(FX00_TARGET_SCAN, 7002 &base_vha->dpc_flags)) { 7003 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 7004 "ISPFx00 Target Scan scheduled\n"); 7005 if (qlafx00_rescan_isp(base_vha)) { 7006 if (!test_bit(UNLOADING, 7007 &base_vha->dpc_flags)) 7008 set_bit(ISP_UNRECOVERABLE, 7009 &base_vha->dpc_flags); 7010 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 7011 "ISPFx00 Target Scan Failed\n"); 7012 } 7013 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 7014 "ISPFx00 Target Scan End\n"); 7015 } 7016 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 7017 &base_vha->dpc_flags)) { 7018 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 7019 "ISPFx00 Host Info resend scheduled\n"); 7020 qlafx00_fx_disc(base_vha, 7021 &base_vha->hw->mr.fcport, 7022 FXDISC_REG_HOST_INFO); 7023 } 7024 } 7025 7026 if (test_and_clear_bit(DETECT_SFP_CHANGE, 7027 &base_vha->dpc_flags)) { 7028 /* Semantic: 7029 * - NO-OP -- await next ISP-ABORT. Preferred method 7030 * to minimize disruptions that will occur 7031 * when a forced chip-reset occurs. 7032 * - Force -- ISP-ABORT scheduled. 7033 */ 7034 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7035 } 7036 7037 if (test_and_clear_bit 7038 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7039 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7040 bool do_reset = true; 7041 7042 switch (base_vha->qlini_mode) { 7043 case QLA2XXX_INI_MODE_ENABLED: 7044 break; 7045 case QLA2XXX_INI_MODE_DISABLED: 7046 if (!qla_tgt_mode_enabled(base_vha) && 7047 !ha->flags.fw_started) 7048 do_reset = false; 7049 break; 7050 case QLA2XXX_INI_MODE_DUAL: 7051 if (!qla_dual_mode_enabled(base_vha) && 7052 !ha->flags.fw_started) 7053 do_reset = false; 7054 break; 7055 default: 7056 break; 7057 } 7058 7059 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7060 &base_vha->dpc_flags))) { 7061 base_vha->flags.online = 1; 7062 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7063 "ISP abort scheduled.\n"); 7064 if (ha->isp_ops->abort_isp(base_vha)) { 7065 /* failed. retry later */ 7066 set_bit(ISP_ABORT_NEEDED, 7067 &base_vha->dpc_flags); 7068 } 7069 clear_bit(ABORT_ISP_ACTIVE, 7070 &base_vha->dpc_flags); 7071 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7072 "ISP abort end.\n"); 7073 } 7074 } 7075 7076 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7077 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7078 qla24xx_process_purex_list 7079 (&base_vha->purex_list); 7080 clear_bit(PROCESS_PUREX_IOCB, 7081 &base_vha->dpc_flags); 7082 } 7083 } 7084 7085 if (IS_QLAFX00(ha)) 7086 goto loop_resync_check; 7087 7088 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7089 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7090 "Quiescence mode scheduled.\n"); 7091 if (IS_P3P_TYPE(ha)) { 7092 if (IS_QLA82XX(ha)) 7093 qla82xx_device_state_handler(base_vha); 7094 if (IS_QLA8044(ha)) 7095 qla8044_device_state_handler(base_vha); 7096 clear_bit(ISP_QUIESCE_NEEDED, 7097 &base_vha->dpc_flags); 7098 if (!ha->flags.quiesce_owner) { 7099 qla2x00_perform_loop_resync(base_vha); 7100 if (IS_QLA82XX(ha)) { 7101 qla82xx_idc_lock(ha); 7102 qla82xx_clear_qsnt_ready( 7103 base_vha); 7104 qla82xx_idc_unlock(ha); 7105 } else if (IS_QLA8044(ha)) { 7106 qla8044_idc_lock(ha); 7107 qla8044_clear_qsnt_ready( 7108 base_vha); 7109 qla8044_idc_unlock(ha); 7110 } 7111 } 7112 } else { 7113 clear_bit(ISP_QUIESCE_NEEDED, 7114 &base_vha->dpc_flags); 7115 qla2x00_quiesce_io(base_vha); 7116 } 7117 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7118 "Quiescence mode end.\n"); 7119 } 7120 7121 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7122 &base_vha->dpc_flags) && 7123 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7124 7125 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7126 "Reset marker scheduled.\n"); 7127 qla2x00_rst_aen(base_vha); 7128 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7129 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7130 "Reset marker end.\n"); 7131 } 7132 7133 /* Retry each device up to login retry count */ 7134 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7135 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7136 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7137 7138 if (!base_vha->relogin_jif || 7139 time_after_eq(jiffies, base_vha->relogin_jif)) { 7140 base_vha->relogin_jif = jiffies + HZ; 7141 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7142 7143 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7144 "Relogin scheduled.\n"); 7145 qla24xx_post_relogin_work(base_vha); 7146 } 7147 } 7148 loop_resync_check: 7149 if (!qla2x00_reset_active(base_vha) && 7150 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7151 &base_vha->dpc_flags)) { 7152 /* 7153 * Allow abort_isp to complete before moving on to scanning. 7154 */ 7155 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7156 "Loop resync scheduled.\n"); 7157 7158 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7159 &base_vha->dpc_flags))) { 7160 7161 qla2x00_loop_resync(base_vha); 7162 7163 clear_bit(LOOP_RESYNC_ACTIVE, 7164 &base_vha->dpc_flags); 7165 } 7166 7167 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7168 "Loop resync end.\n"); 7169 } 7170 7171 if (IS_QLAFX00(ha)) 7172 goto intr_on_check; 7173 7174 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7175 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7176 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7177 qla2xxx_flash_npiv_conf(base_vha); 7178 } 7179 7180 intr_on_check: 7181 if (!ha->interrupts_on) 7182 ha->isp_ops->enable_intrs(ha); 7183 7184 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7185 &base_vha->dpc_flags)) { 7186 if (ha->beacon_blink_led == 1) 7187 ha->isp_ops->beacon_blink(base_vha); 7188 } 7189 7190 /* qpair online check */ 7191 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7192 &base_vha->dpc_flags)) { 7193 if (ha->flags.eeh_busy || 7194 ha->flags.pci_channel_io_perm_failure) 7195 online = 0; 7196 else 7197 online = 1; 7198 7199 mutex_lock(&ha->mq_lock); 7200 list_for_each_entry(qpair, &base_vha->qp_list, 7201 qp_list_elem) 7202 qpair->online = online; 7203 mutex_unlock(&ha->mq_lock); 7204 } 7205 7206 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7207 &base_vha->dpc_flags)) { 7208 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7209 7210 if (threshold > ha->orig_fw_xcb_count) 7211 threshold = ha->orig_fw_xcb_count; 7212 7213 ql_log(ql_log_info, base_vha, 0xffffff, 7214 "SET ZIO Activity exchange threshold to %d.\n", 7215 threshold); 7216 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7217 ql_log(ql_log_info, base_vha, 0xffffff, 7218 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7219 threshold); 7220 } 7221 } 7222 7223 if (!IS_QLAFX00(ha)) 7224 qla2x00_do_dpc_all_vps(base_vha); 7225 7226 if (test_and_clear_bit(N2N_LINK_RESET, 7227 &base_vha->dpc_flags)) { 7228 qla2x00_lip_reset(base_vha); 7229 } 7230 7231 ha->dpc_active = 0; 7232 end_loop: 7233 set_current_state(TASK_INTERRUPTIBLE); 7234 } /* End of while(1) */ 7235 __set_current_state(TASK_RUNNING); 7236 7237 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7238 "DPC handler exiting.\n"); 7239 7240 /* 7241 * Make sure that nobody tries to wake us up again. 7242 */ 7243 ha->dpc_active = 0; 7244 7245 return 0; 7246 } 7247 7248 void qla2xxx_wake_dpc(struct scsi_qla_host * vha)7249 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7250 { 7251 struct qla_hw_data *ha = vha->hw; 7252 struct task_struct *t = ha->dpc_thread; 7253 7254 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7255 wake_up_process(t); 7256 } 7257 7258 /* 7259 * qla2x00_rst_aen 7260 * Processes asynchronous reset. 7261 * 7262 * Input: 7263 * ha = adapter block pointer. 7264 */ 7265 static void qla2x00_rst_aen(scsi_qla_host_t * vha)7266 qla2x00_rst_aen(scsi_qla_host_t *vha) 7267 { 7268 if (vha->flags.online && !vha->flags.reset_active && 7269 !atomic_read(&vha->loop_down_timer) && 7270 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7271 do { 7272 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7273 7274 /* 7275 * Issue marker command only when we are going to start 7276 * the I/O. 7277 */ 7278 vha->marker_needed = 1; 7279 } while (!atomic_read(&vha->loop_down_timer) && 7280 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7281 } 7282 } 7283 qla_do_heartbeat(struct scsi_qla_host * vha)7284 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7285 { 7286 struct qla_hw_data *ha = vha->hw; 7287 u32 cmpl_cnt; 7288 u16 i; 7289 bool do_heartbeat = false; 7290 7291 /* 7292 * Allow do_heartbeat only if we don’t have any active interrupts, 7293 * but there are still IOs outstanding with firmware. 7294 */ 7295 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7296 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7297 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7298 do_heartbeat = true; 7299 goto skip; 7300 } 7301 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7302 7303 for (i = 0; i < ha->max_qpairs; i++) { 7304 if (ha->queue_pair_map[i]) { 7305 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7306 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7307 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7308 do_heartbeat = true; 7309 break; 7310 } 7311 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7312 } 7313 } 7314 7315 skip: 7316 return do_heartbeat; 7317 } 7318 qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7319 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7320 { 7321 struct qla_hw_data *ha = vha->hw; 7322 7323 if (vha->vp_idx) 7324 return; 7325 7326 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7327 return; 7328 7329 /* 7330 * dpc thread cannot run if heartbeat is running at the same time. 7331 * We also do not want to starve heartbeat task. Therefore, do 7332 * heartbeat task at least once every 5 seconds. 7333 */ 7334 if (dpc_started && 7335 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7336 return; 7337 7338 if (qla_do_heartbeat(vha)) { 7339 ha->last_heartbeat_run_jiffies = jiffies; 7340 queue_work(ha->wq, &ha->heartbeat_work); 7341 } 7342 } 7343 qla_wind_down_chip(scsi_qla_host_t * vha)7344 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7345 { 7346 struct qla_hw_data *ha = vha->hw; 7347 7348 if (!ha->flags.eeh_busy) 7349 return; 7350 if (ha->pci_error_state) 7351 /* system is trying to recover */ 7352 return; 7353 7354 /* 7355 * Current system is not handling PCIE error. At this point, this is 7356 * best effort to wind down the adapter. 7357 */ 7358 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7359 !ha->flags.eeh_flush) { 7360 ql_log(ql_log_info, vha, 0x9009, 7361 "PCI Error detected, attempting to reset hardware.\n"); 7362 7363 ha->isp_ops->reset_chip(vha); 7364 ha->isp_ops->disable_intrs(ha); 7365 7366 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7367 ha->eeh_jif = jiffies; 7368 7369 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7370 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7371 pci_clear_master(ha->pdev); 7372 7373 /* flush all command */ 7374 qla2x00_abort_isp_cleanup(vha); 7375 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7376 7377 ql_log(ql_log_info, vha, 0x900a, 7378 "PCI Error handling complete, all IOs aborted.\n"); 7379 } 7380 } 7381 7382 /************************************************************************** 7383 * qla2x00_timer 7384 * 7385 * Description: 7386 * One second timer 7387 * 7388 * Context: Interrupt 7389 ***************************************************************************/ 7390 void qla2x00_timer(struct timer_list * t)7391 qla2x00_timer(struct timer_list *t) 7392 { 7393 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7394 unsigned long cpu_flags = 0; 7395 int start_dpc = 0; 7396 int index; 7397 srb_t *sp; 7398 uint16_t w; 7399 struct qla_hw_data *ha = vha->hw; 7400 struct req_que *req; 7401 unsigned long flags; 7402 fc_port_t *fcport = NULL; 7403 7404 if (ha->flags.eeh_busy) { 7405 qla_wind_down_chip(vha); 7406 7407 ql_dbg(ql_dbg_timer, vha, 0x6000, 7408 "EEH = %d, restarting timer.\n", 7409 ha->flags.eeh_busy); 7410 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7411 return; 7412 } 7413 7414 /* 7415 * Hardware read to raise pending EEH errors during mailbox waits. If 7416 * the read returns -1 then disable the board. 7417 */ 7418 if (!pci_channel_offline(ha->pdev)) { 7419 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7420 qla2x00_check_reg16_for_disconnect(vha, w); 7421 } 7422 7423 /* Make sure qla82xx_watchdog is run only for physical port */ 7424 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7425 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7426 start_dpc++; 7427 if (IS_QLA82XX(ha)) 7428 qla82xx_watchdog(vha); 7429 else if (IS_QLA8044(ha)) 7430 qla8044_watchdog(vha); 7431 } 7432 7433 if (!vha->vp_idx && IS_QLAFX00(ha)) 7434 qlafx00_timer_routine(vha); 7435 7436 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7437 vha->link_down_time++; 7438 7439 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7440 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7441 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7442 fcport->tgt_link_down_time++; 7443 } 7444 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7445 7446 /* Loop down handler. */ 7447 if (atomic_read(&vha->loop_down_timer) > 0 && 7448 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7449 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7450 && vha->flags.online) { 7451 7452 if (atomic_read(&vha->loop_down_timer) == 7453 vha->loop_down_abort_time) { 7454 7455 ql_log(ql_log_info, vha, 0x6008, 7456 "Loop down - aborting the queues before time expires.\n"); 7457 7458 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7459 atomic_set(&vha->loop_state, LOOP_DEAD); 7460 7461 /* 7462 * Schedule an ISP abort to return any FCP2-device 7463 * commands. 7464 */ 7465 /* NPIV - scan physical port only */ 7466 if (!vha->vp_idx) { 7467 spin_lock_irqsave(&ha->hardware_lock, 7468 cpu_flags); 7469 req = ha->req_q_map[0]; 7470 for (index = 1; 7471 index < req->num_outstanding_cmds; 7472 index++) { 7473 fc_port_t *sfcp; 7474 7475 sp = req->outstanding_cmds[index]; 7476 if (!sp) 7477 continue; 7478 if (sp->cmd_type != TYPE_SRB) 7479 continue; 7480 if (sp->type != SRB_SCSI_CMD) 7481 continue; 7482 sfcp = sp->fcport; 7483 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7484 continue; 7485 7486 if (IS_QLA82XX(ha)) 7487 set_bit(FCOE_CTX_RESET_NEEDED, 7488 &vha->dpc_flags); 7489 else 7490 set_bit(ISP_ABORT_NEEDED, 7491 &vha->dpc_flags); 7492 break; 7493 } 7494 spin_unlock_irqrestore(&ha->hardware_lock, 7495 cpu_flags); 7496 } 7497 start_dpc++; 7498 } 7499 7500 /* if the loop has been down for 4 minutes, reinit adapter */ 7501 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7502 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7503 ql_log(ql_log_warn, vha, 0x6009, 7504 "Loop down - aborting ISP.\n"); 7505 7506 if (IS_QLA82XX(ha)) 7507 set_bit(FCOE_CTX_RESET_NEEDED, 7508 &vha->dpc_flags); 7509 else 7510 set_bit(ISP_ABORT_NEEDED, 7511 &vha->dpc_flags); 7512 } 7513 } 7514 ql_dbg(ql_dbg_timer, vha, 0x600a, 7515 "Loop down - seconds remaining %d.\n", 7516 atomic_read(&vha->loop_down_timer)); 7517 } 7518 /* Check if beacon LED needs to be blinked for physical host only */ 7519 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7520 /* There is no beacon_blink function for ISP82xx */ 7521 if (!IS_P3P_TYPE(ha)) { 7522 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7523 start_dpc++; 7524 } 7525 } 7526 7527 /* check if edif running */ 7528 if (vha->hw->flags.edif_enabled) 7529 qla_edif_timer(vha); 7530 7531 /* Process any deferred work. */ 7532 if (!list_empty(&vha->work_list)) { 7533 unsigned long flags; 7534 bool q = false; 7535 7536 spin_lock_irqsave(&vha->work_lock, flags); 7537 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7538 q = true; 7539 spin_unlock_irqrestore(&vha->work_lock, flags); 7540 if (q) 7541 queue_work(vha->hw->wq, &vha->iocb_work); 7542 } 7543 7544 /* 7545 * FC-NVME 7546 * see if the active AEN count has changed from what was last reported. 7547 */ 7548 index = atomic_read(&ha->nvme_active_aen_cnt); 7549 if (!vha->vp_idx && 7550 (index != ha->nvme_last_rptd_aen) && 7551 ha->zio_mode == QLA_ZIO_MODE_6 && 7552 !ha->flags.host_shutting_down) { 7553 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7554 ql_log(ql_log_info, vha, 0x3002, 7555 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7556 ha->nvme_last_rptd_aen); 7557 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7558 start_dpc++; 7559 } 7560 7561 if (!vha->vp_idx && 7562 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7563 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7564 ql_log(ql_log_info, vha, 0x3002, 7565 "Sched: Set ZIO exchange threshold to %d.\n", 7566 ha->last_zio_threshold); 7567 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7568 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7569 start_dpc++; 7570 } 7571 qla_adjust_buf(vha); 7572 7573 /* borrowing w to signify dpc will run */ 7574 w = 0; 7575 /* Schedule the DPC routine if needed */ 7576 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7577 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7578 start_dpc || 7579 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7580 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7581 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7582 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7583 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7584 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7585 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7586 ql_dbg(ql_dbg_timer, vha, 0x600b, 7587 "isp_abort_needed=%d loop_resync_needed=%d " 7588 "start_dpc=%d reset_marker_needed=%d", 7589 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7590 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7591 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7592 ql_dbg(ql_dbg_timer, vha, 0x600c, 7593 "beacon_blink_needed=%d isp_unrecoverable=%d " 7594 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7595 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7596 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7597 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7598 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7599 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7600 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7601 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7602 qla2xxx_wake_dpc(vha); 7603 w = 1; 7604 } 7605 7606 qla_heart_beat(vha, w); 7607 7608 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7609 } 7610 7611 /* Firmware interface routines. */ 7612 7613 #define FW_ISP21XX 0 7614 #define FW_ISP22XX 1 7615 #define FW_ISP2300 2 7616 #define FW_ISP2322 3 7617 #define FW_ISP24XX 4 7618 #define FW_ISP25XX 5 7619 #define FW_ISP81XX 6 7620 #define FW_ISP82XX 7 7621 #define FW_ISP2031 8 7622 #define FW_ISP8031 9 7623 #define FW_ISP27XX 10 7624 #define FW_ISP28XX 11 7625 7626 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7627 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7628 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7629 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7630 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7631 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7632 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7633 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7634 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7635 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7636 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7637 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7638 7639 7640 static DEFINE_MUTEX(qla_fw_lock); 7641 7642 static struct fw_blob qla_fw_blobs[] = { 7643 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7644 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7645 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7646 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7647 { .name = FW_FILE_ISP24XX, }, 7648 { .name = FW_FILE_ISP25XX, }, 7649 { .name = FW_FILE_ISP81XX, }, 7650 { .name = FW_FILE_ISP82XX, }, 7651 { .name = FW_FILE_ISP2031, }, 7652 { .name = FW_FILE_ISP8031, }, 7653 { .name = FW_FILE_ISP27XX, }, 7654 { .name = FW_FILE_ISP28XX, }, 7655 { .name = NULL, }, 7656 }; 7657 7658 struct fw_blob * qla2x00_request_firmware(scsi_qla_host_t * vha)7659 qla2x00_request_firmware(scsi_qla_host_t *vha) 7660 { 7661 struct qla_hw_data *ha = vha->hw; 7662 struct fw_blob *blob; 7663 7664 if (IS_QLA2100(ha)) { 7665 blob = &qla_fw_blobs[FW_ISP21XX]; 7666 } else if (IS_QLA2200(ha)) { 7667 blob = &qla_fw_blobs[FW_ISP22XX]; 7668 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7669 blob = &qla_fw_blobs[FW_ISP2300]; 7670 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7671 blob = &qla_fw_blobs[FW_ISP2322]; 7672 } else if (IS_QLA24XX_TYPE(ha)) { 7673 blob = &qla_fw_blobs[FW_ISP24XX]; 7674 } else if (IS_QLA25XX(ha)) { 7675 blob = &qla_fw_blobs[FW_ISP25XX]; 7676 } else if (IS_QLA81XX(ha)) { 7677 blob = &qla_fw_blobs[FW_ISP81XX]; 7678 } else if (IS_QLA82XX(ha)) { 7679 blob = &qla_fw_blobs[FW_ISP82XX]; 7680 } else if (IS_QLA2031(ha)) { 7681 blob = &qla_fw_blobs[FW_ISP2031]; 7682 } else if (IS_QLA8031(ha)) { 7683 blob = &qla_fw_blobs[FW_ISP8031]; 7684 } else if (IS_QLA27XX(ha)) { 7685 blob = &qla_fw_blobs[FW_ISP27XX]; 7686 } else if (IS_QLA28XX(ha)) { 7687 blob = &qla_fw_blobs[FW_ISP28XX]; 7688 } else { 7689 return NULL; 7690 } 7691 7692 if (!blob->name) 7693 return NULL; 7694 7695 mutex_lock(&qla_fw_lock); 7696 if (blob->fw) 7697 goto out; 7698 7699 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7700 ql_log(ql_log_warn, vha, 0x0063, 7701 "Failed to load firmware image (%s).\n", blob->name); 7702 blob->fw = NULL; 7703 blob = NULL; 7704 } 7705 7706 out: 7707 mutex_unlock(&qla_fw_lock); 7708 return blob; 7709 } 7710 7711 static void qla2x00_release_firmware(void)7712 qla2x00_release_firmware(void) 7713 { 7714 struct fw_blob *blob; 7715 7716 mutex_lock(&qla_fw_lock); 7717 for (blob = qla_fw_blobs; blob->name; blob++) 7718 release_firmware(blob->fw); 7719 mutex_unlock(&qla_fw_lock); 7720 } 7721 qla_pci_error_cleanup(scsi_qla_host_t * vha)7722 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7723 { 7724 struct qla_hw_data *ha = vha->hw; 7725 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7726 struct qla_qpair *qpair = NULL; 7727 struct scsi_qla_host *vp, *tvp; 7728 fc_port_t *fcport; 7729 int i; 7730 unsigned long flags; 7731 7732 ql_dbg(ql_dbg_aer, vha, 0x9000, 7733 "%s\n", __func__); 7734 ha->chip_reset++; 7735 7736 ha->base_qpair->chip_reset = ha->chip_reset; 7737 for (i = 0; i < ha->max_qpairs; i++) { 7738 if (ha->queue_pair_map[i]) 7739 ha->queue_pair_map[i]->chip_reset = 7740 ha->base_qpair->chip_reset; 7741 } 7742 7743 /* 7744 * purge mailbox might take a while. Slot Reset/chip reset 7745 * will take care of the purge 7746 */ 7747 7748 mutex_lock(&ha->mq_lock); 7749 ha->base_qpair->online = 0; 7750 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7751 qpair->online = 0; 7752 wmb(); 7753 mutex_unlock(&ha->mq_lock); 7754 7755 qla2x00_mark_all_devices_lost(vha); 7756 7757 spin_lock_irqsave(&ha->vport_slock, flags); 7758 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7759 atomic_inc(&vp->vref_count); 7760 spin_unlock_irqrestore(&ha->vport_slock, flags); 7761 qla2x00_mark_all_devices_lost(vp); 7762 spin_lock_irqsave(&ha->vport_slock, flags); 7763 atomic_dec(&vp->vref_count); 7764 } 7765 spin_unlock_irqrestore(&ha->vport_slock, flags); 7766 7767 /* Clear all async request states across all VPs. */ 7768 list_for_each_entry(fcport, &vha->vp_fcports, list) 7769 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7770 7771 spin_lock_irqsave(&ha->vport_slock, flags); 7772 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7773 atomic_inc(&vp->vref_count); 7774 spin_unlock_irqrestore(&ha->vport_slock, flags); 7775 list_for_each_entry(fcport, &vp->vp_fcports, list) 7776 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7777 spin_lock_irqsave(&ha->vport_slock, flags); 7778 atomic_dec(&vp->vref_count); 7779 } 7780 spin_unlock_irqrestore(&ha->vport_slock, flags); 7781 } 7782 7783 7784 static pci_ers_result_t qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7785 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7786 { 7787 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7788 struct qla_hw_data *ha = vha->hw; 7789 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7790 7791 ql_log(ql_log_warn, vha, 0x9000, 7792 "PCI error detected, state %x.\n", state); 7793 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7794 7795 if (!atomic_read(&pdev->enable_cnt)) { 7796 ql_log(ql_log_info, vha, 0xffff, 7797 "PCI device is disabled,state %x\n", state); 7798 ret = PCI_ERS_RESULT_NEED_RESET; 7799 goto out; 7800 } 7801 7802 switch (state) { 7803 case pci_channel_io_normal: 7804 qla_pci_set_eeh_busy(vha); 7805 if (ql2xmqsupport || ql2xnvmeenable) { 7806 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7807 qla2xxx_wake_dpc(vha); 7808 } 7809 ret = PCI_ERS_RESULT_CAN_RECOVER; 7810 break; 7811 case pci_channel_io_frozen: 7812 qla_pci_set_eeh_busy(vha); 7813 ret = PCI_ERS_RESULT_NEED_RESET; 7814 break; 7815 case pci_channel_io_perm_failure: 7816 ha->flags.pci_channel_io_perm_failure = 1; 7817 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7818 if (ql2xmqsupport || ql2xnvmeenable) { 7819 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7820 qla2xxx_wake_dpc(vha); 7821 } 7822 ret = PCI_ERS_RESULT_DISCONNECT; 7823 } 7824 out: 7825 ql_dbg(ql_dbg_aer, vha, 0x600d, 7826 "PCI error detected returning [%x].\n", ret); 7827 return ret; 7828 } 7829 7830 static pci_ers_result_t qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7831 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7832 { 7833 int risc_paused = 0; 7834 uint32_t stat; 7835 unsigned long flags; 7836 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7837 struct qla_hw_data *ha = base_vha->hw; 7838 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7839 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7840 7841 ql_log(ql_log_warn, base_vha, 0x9000, 7842 "mmio enabled\n"); 7843 7844 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7845 7846 if (IS_QLA82XX(ha)) 7847 return PCI_ERS_RESULT_RECOVERED; 7848 7849 if (qla2x00_isp_reg_stat(ha)) { 7850 ql_log(ql_log_info, base_vha, 0x803f, 7851 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7852 goto out; 7853 } 7854 7855 spin_lock_irqsave(&ha->hardware_lock, flags); 7856 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7857 stat = rd_reg_word(®->hccr); 7858 if (stat & HCCR_RISC_PAUSE) 7859 risc_paused = 1; 7860 } else if (IS_QLA23XX(ha)) { 7861 stat = rd_reg_dword(®->u.isp2300.host_status); 7862 if (stat & HSR_RISC_PAUSED) 7863 risc_paused = 1; 7864 } else if (IS_FWI2_CAPABLE(ha)) { 7865 stat = rd_reg_dword(®24->host_status); 7866 if (stat & HSRX_RISC_PAUSED) 7867 risc_paused = 1; 7868 } 7869 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7870 7871 if (risc_paused) { 7872 ql_log(ql_log_info, base_vha, 0x9003, 7873 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7874 qla2xxx_dump_fw(base_vha); 7875 } 7876 out: 7877 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7878 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7879 "mmio enabled returning.\n"); 7880 return PCI_ERS_RESULT_NEED_RESET; 7881 } 7882 7883 static pci_ers_result_t qla2xxx_pci_slot_reset(struct pci_dev * pdev)7884 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7885 { 7886 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7887 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7888 struct qla_hw_data *ha = base_vha->hw; 7889 int rc; 7890 struct qla_qpair *qpair = NULL; 7891 7892 ql_log(ql_log_warn, base_vha, 0x9004, 7893 "Slot Reset.\n"); 7894 7895 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7896 /* Workaround: qla2xxx driver which access hardware earlier 7897 * needs error state to be pci_channel_io_online. 7898 * Otherwise mailbox command timesout. 7899 */ 7900 pdev->error_state = pci_channel_io_normal; 7901 7902 pci_restore_state(pdev); 7903 7904 /* pci_restore_state() clears the saved_state flag of the device 7905 * save restored state which resets saved_state flag 7906 */ 7907 pci_save_state(pdev); 7908 7909 if (ha->mem_only) 7910 rc = pci_enable_device_mem(pdev); 7911 else 7912 rc = pci_enable_device(pdev); 7913 7914 if (rc) { 7915 ql_log(ql_log_warn, base_vha, 0x9005, 7916 "Can't re-enable PCI device after reset.\n"); 7917 goto exit_slot_reset; 7918 } 7919 7920 7921 if (ha->isp_ops->pci_config(base_vha)) 7922 goto exit_slot_reset; 7923 7924 mutex_lock(&ha->mq_lock); 7925 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7926 qpair->online = 1; 7927 mutex_unlock(&ha->mq_lock); 7928 7929 ha->flags.eeh_busy = 0; 7930 base_vha->flags.online = 1; 7931 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7932 ha->isp_ops->abort_isp(base_vha); 7933 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7934 7935 if (qla2x00_isp_reg_stat(ha)) { 7936 ha->flags.eeh_busy = 1; 7937 qla_pci_error_cleanup(base_vha); 7938 ql_log(ql_log_warn, base_vha, 0x9005, 7939 "Device unable to recover from PCI error.\n"); 7940 } else { 7941 ret = PCI_ERS_RESULT_RECOVERED; 7942 } 7943 7944 exit_slot_reset: 7945 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7946 "Slot Reset returning %x.\n", ret); 7947 7948 return ret; 7949 } 7950 7951 static void qla2xxx_pci_resume(struct pci_dev * pdev)7952 qla2xxx_pci_resume(struct pci_dev *pdev) 7953 { 7954 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7955 struct qla_hw_data *ha = base_vha->hw; 7956 int ret; 7957 7958 ql_log(ql_log_warn, base_vha, 0x900f, 7959 "Pci Resume.\n"); 7960 7961 7962 ret = qla2x00_wait_for_hba_online(base_vha); 7963 if (ret != QLA_SUCCESS) { 7964 ql_log(ql_log_fatal, base_vha, 0x9002, 7965 "The device failed to resume I/O from slot/link_reset.\n"); 7966 } 7967 ha->pci_error_state = QLA_PCI_RESUME; 7968 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7969 "Pci Resume returning.\n"); 7970 } 7971 qla_pci_set_eeh_busy(struct scsi_qla_host * vha)7972 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7973 { 7974 struct qla_hw_data *ha = vha->hw; 7975 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7976 bool do_cleanup = false; 7977 unsigned long flags; 7978 7979 if (ha->flags.eeh_busy) 7980 return; 7981 7982 spin_lock_irqsave(&base_vha->work_lock, flags); 7983 if (!ha->flags.eeh_busy) { 7984 ha->eeh_jif = jiffies; 7985 ha->flags.eeh_flush = 0; 7986 7987 ha->flags.eeh_busy = 1; 7988 do_cleanup = true; 7989 } 7990 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7991 7992 if (do_cleanup) 7993 qla_pci_error_cleanup(base_vha); 7994 } 7995 7996 /* 7997 * this routine will schedule a task to pause IO from interrupt context 7998 * if caller sees a PCIE error event (register read = 0xf's) 7999 */ qla_schedule_eeh_work(struct scsi_qla_host * vha)8000 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 8001 { 8002 struct qla_hw_data *ha = vha->hw; 8003 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 8004 8005 if (ha->flags.eeh_busy) 8006 return; 8007 8008 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 8009 qla2xxx_wake_dpc(base_vha); 8010 } 8011 8012 static void qla_pci_reset_prepare(struct pci_dev * pdev)8013 qla_pci_reset_prepare(struct pci_dev *pdev) 8014 { 8015 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8016 struct qla_hw_data *ha = base_vha->hw; 8017 struct qla_qpair *qpair; 8018 8019 ql_log(ql_log_warn, base_vha, 0xffff, 8020 "%s.\n", __func__); 8021 8022 /* 8023 * PCI FLR/function reset is about to reset the 8024 * slot. Stop the chip to stop all DMA access. 8025 * It is assumed that pci_reset_done will be called 8026 * after FLR to resume Chip operation. 8027 */ 8028 ha->flags.eeh_busy = 1; 8029 mutex_lock(&ha->mq_lock); 8030 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8031 qpair->online = 0; 8032 mutex_unlock(&ha->mq_lock); 8033 8034 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8035 qla2x00_abort_isp_cleanup(base_vha); 8036 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8037 } 8038 8039 static void qla_pci_reset_done(struct pci_dev * pdev)8040 qla_pci_reset_done(struct pci_dev *pdev) 8041 { 8042 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8043 struct qla_hw_data *ha = base_vha->hw; 8044 struct qla_qpair *qpair; 8045 8046 ql_log(ql_log_warn, base_vha, 0xffff, 8047 "%s.\n", __func__); 8048 8049 /* 8050 * FLR just completed by PCI layer. Resume adapter 8051 */ 8052 ha->flags.eeh_busy = 0; 8053 mutex_lock(&ha->mq_lock); 8054 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8055 qpair->online = 1; 8056 mutex_unlock(&ha->mq_lock); 8057 8058 base_vha->flags.online = 1; 8059 ha->isp_ops->abort_isp(base_vha); 8060 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8061 } 8062 qla2xxx_map_queues(struct Scsi_Host * shost)8063 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8064 { 8065 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8066 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8067 8068 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8069 blk_mq_map_queues(qmap); 8070 else 8071 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 8072 } 8073 8074 struct scsi_host_template qla2xxx_driver_template = { 8075 .module = THIS_MODULE, 8076 .name = QLA2XXX_DRIVER_NAME, 8077 .queuecommand = qla2xxx_queuecommand, 8078 8079 .eh_timed_out = fc_eh_timed_out, 8080 .eh_abort_handler = qla2xxx_eh_abort, 8081 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8082 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8083 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8084 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8085 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8086 8087 .slave_configure = qla2xxx_slave_configure, 8088 8089 .slave_alloc = qla2xxx_slave_alloc, 8090 .slave_destroy = qla2xxx_slave_destroy, 8091 .scan_finished = qla2xxx_scan_finished, 8092 .scan_start = qla2xxx_scan_start, 8093 .change_queue_depth = scsi_change_queue_depth, 8094 .map_queues = qla2xxx_map_queues, 8095 .this_id = -1, 8096 .cmd_per_lun = 3, 8097 .sg_tablesize = SG_ALL, 8098 8099 .max_sectors = 0xFFFF, 8100 .shost_groups = qla2x00_host_groups, 8101 8102 .supported_mode = MODE_INITIATOR, 8103 .track_queue_depth = 1, 8104 .cmd_size = sizeof(srb_t), 8105 }; 8106 8107 static const struct pci_error_handlers qla2xxx_err_handler = { 8108 .error_detected = qla2xxx_pci_error_detected, 8109 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8110 .slot_reset = qla2xxx_pci_slot_reset, 8111 .resume = qla2xxx_pci_resume, 8112 .reset_prepare = qla_pci_reset_prepare, 8113 .reset_done = qla_pci_reset_done, 8114 }; 8115 8116 static struct pci_device_id qla2xxx_pci_tbl[] = { 8117 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8118 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8119 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8120 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8121 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8122 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8123 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8124 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8125 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8126 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8127 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8128 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8129 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8130 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8131 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8132 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8133 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8134 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8135 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8136 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8137 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8138 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8139 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8140 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8141 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8142 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8143 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8144 { 0 }, 8145 }; 8146 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8147 8148 static struct pci_driver qla2xxx_pci_driver = { 8149 .name = QLA2XXX_DRIVER_NAME, 8150 .driver = { 8151 .owner = THIS_MODULE, 8152 }, 8153 .id_table = qla2xxx_pci_tbl, 8154 .probe = qla2x00_probe_one, 8155 .remove = qla2x00_remove_one, 8156 .shutdown = qla2x00_shutdown, 8157 .err_handler = &qla2xxx_err_handler, 8158 }; 8159 8160 static const struct file_operations apidev_fops = { 8161 .owner = THIS_MODULE, 8162 .llseek = noop_llseek, 8163 }; 8164 8165 /** 8166 * qla2x00_module_init - Module initialization. 8167 **/ 8168 static int __init qla2x00_module_init(void)8169 qla2x00_module_init(void) 8170 { 8171 int ret = 0; 8172 8173 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8174 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8175 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8176 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8177 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8178 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8179 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8180 BUILD_BUG_ON(sizeof(request_t) != 64); 8181 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8182 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8183 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8184 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8185 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8186 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8187 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8188 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8189 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8190 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8191 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8192 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8193 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8194 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8195 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8196 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8197 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8198 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8199 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8200 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8201 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8202 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8203 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8204 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8205 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8206 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8207 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8208 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8209 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8210 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8211 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8212 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8213 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8214 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8215 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8216 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8217 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8218 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8219 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8220 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8221 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8222 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8223 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8224 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8225 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8226 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8227 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8228 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8229 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8230 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8231 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8232 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8233 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8234 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8235 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8236 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8237 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8238 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8239 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8240 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8241 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8242 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8243 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8244 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8245 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8246 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8247 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8248 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8249 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8250 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8251 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8252 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8253 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8254 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8255 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8256 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8257 8258 qla_trace_init(); 8259 8260 /* Allocate cache for SRBs. */ 8261 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8262 SLAB_HWCACHE_ALIGN, NULL); 8263 if (srb_cachep == NULL) { 8264 ql_log(ql_log_fatal, NULL, 0x0001, 8265 "Unable to allocate SRB cache...Failing load!.\n"); 8266 return -ENOMEM; 8267 } 8268 8269 /* Initialize target kmem_cache and mem_pools */ 8270 ret = qlt_init(); 8271 if (ret < 0) { 8272 goto destroy_cache; 8273 } else if (ret > 0) { 8274 /* 8275 * If initiator mode is explictly disabled by qlt_init(), 8276 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8277 * performing scsi_scan_target() during LOOP UP event. 8278 */ 8279 qla2xxx_transport_functions.disable_target_scan = 1; 8280 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8281 } 8282 8283 /* Derive version string. */ 8284 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8285 if (ql2xextended_error_logging) 8286 strcat(qla2x00_version_str, "-debug"); 8287 if (ql2xextended_error_logging == 1) 8288 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8289 8290 qla2xxx_transport_template = 8291 fc_attach_transport(&qla2xxx_transport_functions); 8292 if (!qla2xxx_transport_template) { 8293 ql_log(ql_log_fatal, NULL, 0x0002, 8294 "fc_attach_transport failed...Failing load!.\n"); 8295 ret = -ENODEV; 8296 goto qlt_exit; 8297 } 8298 8299 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8300 if (apidev_major < 0) { 8301 ql_log(ql_log_fatal, NULL, 0x0003, 8302 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8303 } 8304 8305 qla2xxx_transport_vport_template = 8306 fc_attach_transport(&qla2xxx_transport_vport_functions); 8307 if (!qla2xxx_transport_vport_template) { 8308 ql_log(ql_log_fatal, NULL, 0x0004, 8309 "fc_attach_transport vport failed...Failing load!.\n"); 8310 ret = -ENODEV; 8311 goto unreg_chrdev; 8312 } 8313 ql_log(ql_log_info, NULL, 0x0005, 8314 "QLogic Fibre Channel HBA Driver: %s.\n", 8315 qla2x00_version_str); 8316 ret = pci_register_driver(&qla2xxx_pci_driver); 8317 if (ret) { 8318 ql_log(ql_log_fatal, NULL, 0x0006, 8319 "pci_register_driver failed...ret=%d Failing load!.\n", 8320 ret); 8321 goto release_vport_transport; 8322 } 8323 return ret; 8324 8325 release_vport_transport: 8326 fc_release_transport(qla2xxx_transport_vport_template); 8327 8328 unreg_chrdev: 8329 if (apidev_major >= 0) 8330 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8331 fc_release_transport(qla2xxx_transport_template); 8332 8333 qlt_exit: 8334 qlt_exit(); 8335 8336 destroy_cache: 8337 kmem_cache_destroy(srb_cachep); 8338 8339 qla_trace_uninit(); 8340 return ret; 8341 } 8342 8343 /** 8344 * qla2x00_module_exit - Module cleanup. 8345 **/ 8346 static void __exit qla2x00_module_exit(void)8347 qla2x00_module_exit(void) 8348 { 8349 pci_unregister_driver(&qla2xxx_pci_driver); 8350 qla2x00_release_firmware(); 8351 kmem_cache_destroy(ctx_cachep); 8352 fc_release_transport(qla2xxx_transport_vport_template); 8353 if (apidev_major >= 0) 8354 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8355 fc_release_transport(qla2xxx_transport_template); 8356 qlt_exit(); 8357 kmem_cache_destroy(srb_cachep); 8358 qla_trace_uninit(); 8359 } 8360 8361 module_init(qla2x00_module_init); 8362 module_exit(qla2x00_module_exit); 8363 8364 MODULE_AUTHOR("QLogic Corporation"); 8365 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8366 MODULE_LICENSE("GPL"); 8367 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8368 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8369 MODULE_FIRMWARE(FW_FILE_ISP2300); 8370 MODULE_FIRMWARE(FW_FILE_ISP2322); 8371 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8372 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8373