xref: /openbmc/linux/sound/soc/codecs/rt5682s.h (revision 8793bee7)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * rt5682s.h  --  RT5682I-VS ALSA SoC audio driver
4  *
5  * Copyright 2021 Realtek Microelectronics
6  * Author: Derek Fang <derek.fang@realtek.com>
7  */
8 
9 #ifndef __RT5682S_H__
10 #define __RT5682S_H__
11 
12 #include <sound/rt5682s.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/clk-provider.h>
18 
19 
20 /* Info */
21 #define RT5682S_RESET				0x0000
22 #define RT5682S_VERSION_ID			0x00fd
23 #define RT5682S_VENDOR_ID			0x00fe
24 #define RT5682S_DEVICE_ID			0x00ff
25 /*  I/O - Output */
26 #define RT5682S_HP_CTRL_1			0x0002
27 #define RT5682S_HP_CTRL_2			0x0003
28 #define RT5682S_HPL_GAIN			0x0005
29 #define RT5682S_HPR_GAIN			0x0006
30 
31 #define RT5682S_I2C_CTRL			0x0008
32 
33 /* I/O - Input */
34 #define RT5682S_CBJ_BST_CTRL			0x000b
35 #define RT5682S_CBJ_DET_CTRL			0x000f
36 #define RT5682S_CBJ_CTRL_1			0x0010
37 #define RT5682S_CBJ_CTRL_2			0x0011
38 #define RT5682S_CBJ_CTRL_3			0x0012
39 #define RT5682S_CBJ_CTRL_4			0x0013
40 #define RT5682S_CBJ_CTRL_5			0x0014
41 #define RT5682S_CBJ_CTRL_6			0x0015
42 #define RT5682S_CBJ_CTRL_7			0x0016
43 #define RT5682S_CBJ_CTRL_8			0x0017
44 /* I/O - ADC/DAC/DMIC */
45 #define RT5682S_DAC1_DIG_VOL			0x0019
46 #define RT5682S_STO1_ADC_DIG_VOL		0x001c
47 #define RT5682S_STO1_ADC_BOOST			0x001f
48 #define RT5682S_HP_IMP_GAIN_1			0x0022
49 #define RT5682S_HP_IMP_GAIN_2			0x0023
50 /* Mixer - D-D */
51 #define RT5682S_SIDETONE_CTRL			0x0024
52 #define RT5682S_STO1_ADC_MIXER			0x0026
53 #define RT5682S_AD_DA_MIXER			0x0029
54 #define RT5682S_STO1_DAC_MIXER			0x002a
55 #define RT5682S_A_DAC1_MUX			0x002b
56 #define RT5682S_DIG_INF2_DATA			0x0030
57 /* Mixer - ADC */
58 #define RT5682S_REC_MIXER			0x003c
59 #define RT5682S_CAL_REC				0x0044
60 /* HP Analog Offset Control */
61 #define RT5682S_HP_ANA_OST_CTRL_1		0x004b
62 #define RT5682S_HP_ANA_OST_CTRL_2		0x004c
63 #define RT5682S_HP_ANA_OST_CTRL_3		0x004d
64 /* Power */
65 #define RT5682S_PWR_DIG_1			0x0061
66 #define RT5682S_PWR_DIG_2			0x0062
67 #define RT5682S_PWR_ANLG_1			0x0063
68 #define RT5682S_PWR_ANLG_2			0x0064
69 #define RT5682S_PWR_ANLG_3			0x0065
70 #define RT5682S_PWR_MIXER			0x0066
71 
72 #define RT5682S_MB_CTRL				0x0067
73 #define RT5682S_CLK_GATE_TCON_1			0x0068
74 #define RT5682S_CLK_GATE_TCON_2			0x0069
75 #define RT5682S_CLK_GATE_TCON_3			0x006a
76 /* Clock Detect */
77 #define RT5682S_CLK_DET				0x006b
78 /* Filter Auto Reset */
79 #define RT5682S_RESET_LPF_CTRL			0x006c
80 #define RT5682S_RESET_HPF_CTRL			0x006d
81 /* DMIC */
82 #define RT5682S_DMIC_CTRL_1			0x006e
83 #define RT5682S_LPF_AD_DMIC			0x006f
84 /* Format - ADC/DAC */
85 #define RT5682S_I2S1_SDP			0x0070
86 #define RT5682S_I2S2_SDP			0x0071
87 #define RT5682S_ADDA_CLK_1			0x0073
88 #define RT5682S_ADDA_CLK_2			0x0074
89 #define RT5682S_I2S1_F_DIV_CTRL_1		0x0075
90 #define RT5682S_I2S1_F_DIV_CTRL_2		0x0076
91 /* Format - TDM Control */
92 #define RT5682S_TDM_CTRL			0x0079
93 #define RT5682S_TDM_ADDA_CTRL_1			0x007a
94 #define RT5682S_TDM_ADDA_CTRL_2			0x007b
95 #define RT5682S_DATA_SEL_CTRL_1			0x007c
96 #define RT5682S_TDM_TCON_CTRL_1			0x007e
97 #define RT5682S_TDM_TCON_CTRL_2			0x007f
98 /* Function - Analog */
99 #define RT5682S_GLB_CLK				0x0080
100 #define RT5682S_PLL_TRACK_1			0x0083
101 #define RT5682S_PLL_TRACK_2			0x0084
102 #define RT5682S_PLL_TRACK_3			0x0085
103 #define RT5682S_PLL_TRACK_4			0x0086
104 #define RT5682S_PLL_TRACK_5			0x0087
105 #define RT5682S_PLL_TRACK_6			0x0088
106 #define RT5682S_PLL_TRACK_11			0x008c
107 #define RT5682S_DEPOP_1				0x008e
108 #define RT5682S_HP_CHARGE_PUMP_1		0x008f
109 #define RT5682S_HP_CHARGE_PUMP_2		0x0091
110 #define RT5682S_HP_CHARGE_PUMP_3		0x0092
111 #define RT5682S_MICBIAS_1			0x0093
112 #define RT5682S_MICBIAS_2			0x0094
113 #define RT5682S_MICBIAS_3			0x0095
114 
115 #define RT5682S_PLL_TRACK_12			0x0096
116 #define RT5682S_PLL_TRACK_14			0x0097
117 #define RT5682S_PLL_CTRL_1			0x0098
118 #define RT5682S_PLL_CTRL_2			0x0099
119 #define RT5682S_PLL_CTRL_3			0x009a
120 #define RT5682S_PLL_CTRL_4			0x009b
121 #define RT5682S_PLL_CTRL_5			0x009c
122 #define RT5682S_PLL_CTRL_6			0x009d
123 #define RT5682S_PLL_CTRL_7			0x009e
124 
125 #define RT5682S_RC_CLK_CTRL			0x009f
126 #define RT5682S_I2S2_M_CLK_CTRL_1		0x00a0
127 #define RT5682S_I2S2_F_DIV_CTRL_1		0x00a3
128 #define RT5682S_I2S2_F_DIV_CTRL_2		0x00a4
129 
130 #define RT5682S_IRQ_CTRL_1			0x00b6
131 #define RT5682S_IRQ_CTRL_2			0x00b7
132 #define RT5682S_IRQ_CTRL_3			0x00b8
133 #define RT5682S_IRQ_CTRL_4			0x00b9
134 #define RT5682S_INT_ST_1			0x00be
135 #define RT5682S_GPIO_CTRL_1			0x00c0
136 #define RT5682S_GPIO_CTRL_2			0x00c1
137 #define RT5682S_GPIO_ST				0x00c2
138 #define RT5682S_HP_AMP_DET_CTRL_1		0x00d0
139 #define RT5682S_MID_HP_AMP_DET			0x00d2
140 #define RT5682S_LOW_HP_AMP_DET			0x00d3
141 #define RT5682S_DELAY_BUF_CTRL			0x00d4
142 #define RT5682S_SV_ZCD_1			0x00d9
143 #define RT5682S_SV_ZCD_2			0x00da
144 #define RT5682S_IL_CMD_1			0x00db
145 #define RT5682S_IL_CMD_2			0x00dc
146 #define RT5682S_IL_CMD_3			0x00dd
147 #define RT5682S_IL_CMD_4			0x00de
148 #define RT5682S_IL_CMD_5			0x00df
149 #define RT5682S_IL_CMD_6			0x00e0
150 #define RT5682S_4BTN_IL_CMD_1			0x00e2
151 #define RT5682S_4BTN_IL_CMD_2			0x00e3
152 #define RT5682S_4BTN_IL_CMD_3			0x00e4
153 #define RT5682S_4BTN_IL_CMD_4			0x00e5
154 #define RT5682S_4BTN_IL_CMD_5			0x00e6
155 #define RT5682S_4BTN_IL_CMD_6			0x00e7
156 #define RT5682S_4BTN_IL_CMD_7			0x00e8
157 
158 #define RT5682S_ADC_STO1_HP_CTRL_1		0x00ea
159 #define RT5682S_ADC_STO1_HP_CTRL_2		0x00eb
160 #define RT5682S_AJD1_CTRL			0x00f0
161 #define RT5682S_JD_CTRL_1			0x00f6
162 /* General Control */
163 #define RT5682S_DUMMY_1				0x00fa
164 #define RT5682S_DUMMY_2				0x00fb
165 #define RT5682S_DUMMY_3				0x00fc
166 
167 #define RT5682S_DAC_ADC_DIG_VOL1		0x0100
168 #define RT5682S_BIAS_CUR_CTRL_2			0x010b
169 #define RT5682S_BIAS_CUR_CTRL_3			0x010c
170 #define RT5682S_BIAS_CUR_CTRL_4			0x010d
171 #define RT5682S_BIAS_CUR_CTRL_5			0x010e
172 #define RT5682S_BIAS_CUR_CTRL_6			0x010f
173 #define RT5682S_BIAS_CUR_CTRL_7			0x0110
174 #define RT5682S_BIAS_CUR_CTRL_8			0x0111
175 #define RT5682S_BIAS_CUR_CTRL_9			0x0112
176 #define RT5682S_BIAS_CUR_CTRL_10		0x0113
177 #define RT5682S_VREF_REC_OP_FB_CAP_CTRL_1	0x0117
178 #define RT5682S_VREF_REC_OP_FB_CAP_CTRL_2	0x0118
179 #define RT5682S_CHARGE_PUMP_1			0x0125
180 #define RT5682S_DIG_IN_CTRL_1			0x0132
181 #define RT5682S_PAD_DRIVING_CTRL		0x0136
182 #define RT5682S_CHOP_DAC_1			0x0139
183 #define RT5682S_CHOP_DAC_2			0x013a
184 #define RT5682S_CHOP_ADC			0x013b
185 #define RT5682S_CALIB_ADC_CTRL			0x013c
186 #define RT5682S_VOL_TEST			0x013f
187 #define RT5682S_SPKVDD_DET_ST			0x0142
188 #define RT5682S_TEST_MODE_CTRL_1		0x0145
189 #define RT5682S_TEST_MODE_CTRL_2		0x0146
190 #define RT5682S_TEST_MODE_CTRL_3		0x0147
191 #define RT5682S_TEST_MODE_CTRL_4		0x0148
192 #define RT5682S_PLL_INTERNAL_1			0x0156
193 #define RT5682S_PLL_INTERNAL_2			0x0157
194 #define RT5682S_PLL_INTERNAL_3			0x0158
195 #define RT5682S_PLL_INTERNAL_4			0x0159
196 #define RT5682S_STO_NG2_CTRL_1			0x0160
197 #define RT5682S_STO_NG2_CTRL_2			0x0161
198 #define RT5682S_STO_NG2_CTRL_3			0x0162
199 #define RT5682S_STO_NG2_CTRL_4			0x0163
200 #define RT5682S_STO_NG2_CTRL_5			0x0164
201 #define RT5682S_STO_NG2_CTRL_6			0x0165
202 #define RT5682S_STO_NG2_CTRL_7			0x0166
203 #define RT5682S_STO_NG2_CTRL_8			0x0167
204 #define RT5682S_STO_NG2_CTRL_9			0x0168
205 #define RT5682S_STO_NG2_CTRL_10			0x0169
206 #define RT5682S_STO1_DAC_SIL_DET		0x0190
207 #define RT5682S_SIL_PSV_CTRL1			0x0194
208 #define RT5682S_SIL_PSV_CTRL2			0x0195
209 #define RT5682S_SIL_PSV_CTRL3			0x0197
210 #define RT5682S_SIL_PSV_CTRL4			0x0198
211 #define RT5682S_SIL_PSV_CTRL5			0x0199
212 #define RT5682S_HP_IMP_SENS_CTRL_1		0x01ac
213 #define RT5682S_HP_IMP_SENS_CTRL_2		0x01ad
214 #define RT5682S_HP_IMP_SENS_CTRL_3		0x01ae
215 #define RT5682S_HP_IMP_SENS_CTRL_4		0x01af
216 #define RT5682S_HP_IMP_SENS_CTRL_5		0x01b0
217 #define RT5682S_HP_IMP_SENS_CTRL_6		0x01b1
218 #define RT5682S_HP_IMP_SENS_CTRL_7		0x01b2
219 #define RT5682S_HP_IMP_SENS_CTRL_8		0x01b3
220 #define RT5682S_HP_IMP_SENS_CTRL_9		0x01b4
221 #define RT5682S_HP_IMP_SENS_CTRL_10		0x01b5
222 #define RT5682S_HP_IMP_SENS_CTRL_11		0x01b6
223 #define RT5682S_HP_IMP_SENS_CTRL_12		0x01b7
224 #define RT5682S_HP_IMP_SENS_CTRL_13		0x01b8
225 #define RT5682S_HP_IMP_SENS_CTRL_14		0x01b9
226 #define RT5682S_HP_IMP_SENS_CTRL_15		0x01ba
227 #define RT5682S_HP_IMP_SENS_CTRL_16		0x01bb
228 #define RT5682S_HP_IMP_SENS_CTRL_17		0x01bc
229 #define RT5682S_HP_IMP_SENS_CTRL_18		0x01bd
230 #define RT5682S_HP_IMP_SENS_CTRL_19		0x01be
231 #define RT5682S_HP_IMP_SENS_CTRL_20		0x01bf
232 #define RT5682S_HP_IMP_SENS_CTRL_21		0x01c0
233 #define RT5682S_HP_IMP_SENS_CTRL_22		0x01c1
234 #define RT5682S_HP_IMP_SENS_CTRL_23		0x01c2
235 #define RT5682S_HP_IMP_SENS_CTRL_24		0x01c3
236 #define RT5682S_HP_IMP_SENS_CTRL_25		0x01c4
237 #define RT5682S_HP_IMP_SENS_CTRL_26		0x01c5
238 #define RT5682S_HP_IMP_SENS_CTRL_27		0x01c6
239 #define RT5682S_HP_IMP_SENS_CTRL_28		0x01c7
240 #define RT5682S_HP_IMP_SENS_CTRL_29		0x01c8
241 #define RT5682S_HP_IMP_SENS_CTRL_30		0x01c9
242 #define RT5682S_HP_IMP_SENS_CTRL_31		0x01ca
243 #define RT5682S_HP_IMP_SENS_CTRL_32		0x01cb
244 #define RT5682S_HP_IMP_SENS_CTRL_33		0x01cc
245 #define RT5682S_HP_IMP_SENS_CTRL_34		0x01cd
246 #define RT5682S_HP_IMP_SENS_CTRL_35		0x01ce
247 #define RT5682S_HP_IMP_SENS_CTRL_36		0x01cf
248 #define RT5682S_HP_IMP_SENS_CTRL_37		0x01d0
249 #define RT5682S_HP_IMP_SENS_CTRL_38		0x01d1
250 #define RT5682S_HP_IMP_SENS_CTRL_39		0x01d2
251 #define RT5682S_HP_IMP_SENS_CTRL_40		0x01d3
252 #define RT5682S_HP_IMP_SENS_CTRL_41		0x01d4
253 #define RT5682S_HP_IMP_SENS_CTRL_42		0x01d5
254 #define RT5682S_HP_IMP_SENS_CTRL_43		0x01d6
255 #define RT5682S_HP_IMP_SENS_CTRL_44		0x01d7
256 #define RT5682S_HP_IMP_SENS_CTRL_45		0x01d8
257 #define RT5682S_HP_IMP_SENS_CTRL_46		0x01d9
258 #define RT5682S_HP_LOGIC_CTRL_1			0x01da
259 #define RT5682S_HP_LOGIC_CTRL_2			0x01db
260 #define RT5682S_HP_LOGIC_CTRL_3			0x01dc
261 #define RT5682S_HP_CALIB_CTRL_1			0x01de
262 #define RT5682S_HP_CALIB_CTRL_2			0x01df
263 #define RT5682S_HP_CALIB_CTRL_3			0x01e0
264 #define RT5682S_HP_CALIB_CTRL_4			0x01e1
265 #define RT5682S_HP_CALIB_CTRL_5			0x01e2
266 #define RT5682S_HP_CALIB_CTRL_6			0x01e3
267 #define RT5682S_HP_CALIB_CTRL_7			0x01e4
268 #define RT5682S_HP_CALIB_CTRL_8			0x01e5
269 #define RT5682S_HP_CALIB_CTRL_9			0x01e6
270 #define RT5682S_HP_CALIB_CTRL_10		0x01e7
271 #define RT5682S_HP_CALIB_CTRL_11		0x01e8
272 #define RT5682S_HP_CALIB_ST_1			0x01ea
273 #define RT5682S_HP_CALIB_ST_2			0x01eb
274 #define RT5682S_HP_CALIB_ST_3			0x01ec
275 #define RT5682S_HP_CALIB_ST_4			0x01ed
276 #define RT5682S_HP_CALIB_ST_5			0x01ee
277 #define RT5682S_HP_CALIB_ST_6			0x01ef
278 #define RT5682S_HP_CALIB_ST_7			0x01f0
279 #define RT5682S_HP_CALIB_ST_8			0x01f1
280 #define RT5682S_HP_CALIB_ST_9			0x01f2
281 #define RT5682S_HP_CALIB_ST_10			0x01f3
282 #define RT5682S_HP_CALIB_ST_11			0x01f4
283 #define RT5682S_SAR_IL_CMD_1			0x0210
284 #define RT5682S_SAR_IL_CMD_2			0x0211
285 #define RT5682S_SAR_IL_CMD_3			0x0212
286 #define RT5682S_SAR_IL_CMD_4			0x0213
287 #define RT5682S_SAR_IL_CMD_5			0x0214
288 #define RT5682S_SAR_IL_CMD_6			0x0215
289 #define RT5682S_SAR_IL_CMD_7			0x0216
290 #define RT5682S_SAR_IL_CMD_8			0x0217
291 #define RT5682S_SAR_IL_CMD_9			0x0218
292 #define RT5682S_SAR_IL_CMD_10			0x0219
293 #define RT5682S_SAR_IL_CMD_11			0x021a
294 #define RT5682S_SAR_IL_CMD_12			0x021b
295 #define RT5682S_SAR_IL_CMD_13			0x021c
296 #define RT5682S_SAR_IL_CMD_14			0x021d
297 #define RT5682S_DUMMY_4				0x02fa
298 #define RT5682S_DUMMY_5				0x02fb
299 #define RT5682S_DUMMY_6				0x02fc
300 #define RT5682S_VERSION_ID_HIDE			0x03fe
301 #define RT5682S_VERSION_ID_CUS			0x03ff
302 #define RT5682S_SCAN_CTL			0x0500
303 #define RT5682S_HP_AMP_DET			0x0600
304 #define RT5682S_BIAS_CUR_CTRL_11		0x0610
305 #define RT5682S_BIAS_CUR_CTRL_12		0x0611
306 #define RT5682S_BIAS_CUR_CTRL_13		0x0620
307 #define RT5682S_BIAS_CUR_CTRL_14		0x0621
308 #define RT5682S_BIAS_CUR_CTRL_15		0x0630
309 #define RT5682S_BIAS_CUR_CTRL_16		0x0631
310 #define RT5682S_BIAS_CUR_CTRL_17		0x0640
311 #define RT5682S_BIAS_CUR_CTRL_18		0x0641
312 #define RT5682S_I2C_TRANS_CTRL			0x07fa
313 #define RT5682S_DUMMY_7				0x08fa
314 #define RT5682S_DUMMY_8				0x08fb
315 #define RT5682S_DMIC_FLOAT_DET			0x0d00
316 #define RT5682S_HA_CMP_OP_1			0x1100
317 #define RT5682S_HA_CMP_OP_2			0x1101
318 #define RT5682S_HA_CMP_OP_3			0x1102
319 #define RT5682S_HA_CMP_OP_4			0x1103
320 #define RT5682S_HA_CMP_OP_5			0x1104
321 #define RT5682S_HA_CMP_OP_6			0x1105
322 #define RT5682S_HA_CMP_OP_7			0x1106
323 #define RT5682S_HA_CMP_OP_8			0x1107
324 #define RT5682S_HA_CMP_OP_9			0x1108
325 #define RT5682S_HA_CMP_OP_10			0x1109
326 #define RT5682S_HA_CMP_OP_11			0x110a
327 #define RT5682S_HA_CMP_OP_12			0x110b
328 #define RT5682S_HA_CMP_OP_13			0x110c
329 #define RT5682S_HA_CMP_OP_14			0x1111
330 #define RT5682S_HA_CMP_OP_15			0x1112
331 #define RT5682S_HA_CMP_OP_16			0x1113
332 #define RT5682S_HA_CMP_OP_17			0x1114
333 #define RT5682S_HA_CMP_OP_18			0x1115
334 #define RT5682S_HA_CMP_OP_19			0x1116
335 #define RT5682S_HA_CMP_OP_20			0x1117
336 #define RT5682S_HA_CMP_OP_21			0x1118
337 #define RT5682S_HA_CMP_OP_22			0x1119
338 #define RT5682S_HA_CMP_OP_23			0x111a
339 #define RT5682S_HA_CMP_OP_24			0x111b
340 #define RT5682S_HA_CMP_OP_25			0x111c
341 #define RT5682S_NEW_CBJ_DET_CTL_1		0x1401
342 #define RT5682S_NEW_CBJ_DET_CTL_2		0x1402
343 #define RT5682S_NEW_CBJ_DET_CTL_3		0x1403
344 #define RT5682S_NEW_CBJ_DET_CTL_4		0x1404
345 #define RT5682S_NEW_CBJ_DET_CTL_5		0x1406
346 #define RT5682S_NEW_CBJ_DET_CTL_6		0x1407
347 #define RT5682S_NEW_CBJ_DET_CTL_7		0x1408
348 #define RT5682S_NEW_CBJ_DET_CTL_8		0x1409
349 #define RT5682S_NEW_CBJ_DET_CTL_9		0x140a
350 #define RT5682S_NEW_CBJ_DET_CTL_10		0x140b
351 #define RT5682S_NEW_CBJ_DET_CTL_11		0x140c
352 #define RT5682S_NEW_CBJ_DET_CTL_12		0x140d
353 #define RT5682S_NEW_CBJ_DET_CTL_13		0x140e
354 #define RT5682S_NEW_CBJ_DET_CTL_14		0x140f
355 #define RT5682S_NEW_CBJ_DET_CTL_15		0x1410
356 #define RT5682S_NEW_CBJ_DET_CTL_16		0x1411
357 #define RT5682S_DA_FILTER_1			0x1801
358 #define RT5682S_DA_FILTER_2			0x1802
359 #define RT5682S_DA_FILTER_3			0x1803
360 #define RT5682S_DA_FILTER_4			0x1804
361 #define RT5682S_DA_FILTER_5			0x1805
362 #define RT5682S_CLK_SW_TEST_1			0x2c00
363 #define RT5682S_CLK_SW_TEST_2			0x3400
364 #define RT5682S_CLK_SW_TEST_3			0x3404
365 #define RT5682S_CLK_SW_TEST_4			0x3405
366 #define RT5682S_CLK_SW_TEST_5			0x3406
367 #define RT5682S_CLK_SW_TEST_6			0x3407
368 #define RT5682S_CLK_SW_TEST_7			0x3408
369 #define RT5682S_CLK_SW_TEST_8			0x3409
370 #define RT5682S_CLK_SW_TEST_9			0x340a
371 #define RT5682S_CLK_SW_TEST_10			0x340b
372 #define RT5682S_CLK_SW_TEST_11			0x340c
373 #define RT5682S_CLK_SW_TEST_12			0x340d
374 #define RT5682S_CLK_SW_TEST_13			0x340e
375 #define RT5682S_CLK_SW_TEST_14			0x340f
376 #define RT5682S_EFUSE_MANU_WRITE_1		0x3410
377 #define RT5682S_EFUSE_MANU_WRITE_2		0x3411
378 #define RT5682S_EFUSE_MANU_WRITE_3		0x3412
379 #define RT5682S_EFUSE_MANU_WRITE_4		0x3413
380 #define RT5682S_EFUSE_MANU_WRITE_5		0x3414
381 #define RT5682S_EFUSE_MANU_WRITE_6		0x3415
382 #define RT5682S_EFUSE_READ_1			0x3424
383 #define RT5682S_EFUSE_READ_2			0x3425
384 #define RT5682S_EFUSE_READ_3			0x3426
385 #define RT5682S_EFUSE_READ_4			0x3427
386 #define RT5682S_EFUSE_READ_5			0x3428
387 #define RT5682S_EFUSE_READ_6			0x3429
388 #define RT5682S_EFUSE_READ_7			0x342a
389 #define RT5682S_EFUSE_READ_8			0x342b
390 #define RT5682S_EFUSE_READ_9			0x342c
391 #define RT5682S_EFUSE_READ_10			0x342d
392 #define RT5682S_EFUSE_READ_11			0x342e
393 #define RT5682S_EFUSE_READ_12			0x342f
394 #define RT5682S_EFUSE_READ_13			0x3430
395 #define RT5682S_EFUSE_READ_14			0x3431
396 #define RT5682S_EFUSE_READ_15			0x3432
397 #define RT5682S_EFUSE_READ_16			0x3433
398 #define RT5682S_EFUSE_READ_17			0x3434
399 #define RT5682S_EFUSE_READ_18			0x3435
400 #define RT5682S_EFUSE_TIMING_CTL_1		0x3440
401 #define RT5682S_EFUSE_TIMING_CTL_2		0x3441
402 #define RT5682S_PILOT_DIG_CTL_1			0x3500
403 #define RT5682S_PILOT_DIG_CTL_2			0x3501
404 #define RT5682S_HP_AMP_DET_CTL_1		0x3b00
405 #define RT5682S_HP_AMP_DET_CTL_2		0x3b01
406 #define RT5682S_HP_AMP_DET_CTL_3		0x3b02
407 #define RT5682S_HP_AMP_DET_CTL_4		0x3b03
408 
409 #define RT5682S_MAX_REG				(RT5682S_HP_AMP_DET_CTL_4)
410 
411 /* global definition */
412 #define RT5682S_L_MUTE				(0x1 << 15)
413 #define RT5682S_L_MUTE_SFT			15
414 #define RT5682S_R_MUTE				(0x1 << 7)
415 #define RT5682S_R_MUTE_SFT			7
416 #define RT5682S_L_VOL_SFT			8
417 #define RT5682S_R_VOL_SFT			0
418 #define RT5682S_CLK_SRC_MCLK			(0x0)
419 #define RT5682S_CLK_SRC_PLL1			(0x1)
420 #define RT5682S_CLK_SRC_PLL2			(0x2)
421 #define RT5682S_CLK_SRC_RCCLK			(0x4) /* 25M */
422 
423 
424 /* Headphone Amp Control 2 (0x0003) */
425 #define RT5682S_HPO_L_PATH_MASK			(0x1 << 14)
426 #define RT5682S_HPO_L_PATH_EN			(0x1 << 14)
427 #define RT5682S_HPO_L_PATH_DIS			(0x0 << 14)
428 #define RT5682S_HPO_R_PATH_MASK			(0x1 << 13)
429 #define RT5682S_HPO_R_PATH_EN			(0x1 << 13)
430 #define RT5682S_HPO_R_PATH_DIS			(0x0 << 13)
431 #define RT5682S_HPO_SEL_IP_EN_SW		(0x1)
432 #define RT5682S_HPO_IP_EN_GATING		(0x1)
433 #define RT5682S_HPO_IP_NO_GATING		(0x0)
434 
435 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
436 #define RT5682S_G_HP				(0xf << 8)
437 #define RT5682S_G_HP_SFT			8
438 #define RT5682S_G_STO_DA_DMIX			(0xf)
439 #define RT5682S_G_STO_DA_SFT			0
440 
441 /* Embeeded Jack and Type Detection Control 2 (0x0010) */
442 #define RT5682S_EMB_JD_MASK			(0x1 << 15)
443 #define RT5682S_EMB_JD_EN			(0x1 << 15)
444 #define RT5682S_EMB_JD_EN_SFT			15
445 #define RT5682S_EMB_JD_RST			(0x1 << 14)
446 #define RT5682S_JD_MODE				(0x1 << 13)
447 #define RT5682S_JD_MODE_SFT			13
448 #define RT5682S_DET_TYPE			(0x1 << 12)
449 #define RT5682S_DET_TYPE_SFT			12
450 #define RT5682S_POLA_EXT_JD_MASK		(0x1 << 11)
451 #define RT5682S_POLA_EXT_JD_LOW			(0x1 << 11)
452 #define RT5682S_POLA_EXT_JD_HIGH		(0x0 << 11)
453 #define RT5682S_SEL_FAST_OFF_MASK		(0x3 << 9)
454 #define RT5682S_SEL_FAST_OFF_SFT		9
455 #define RT5682S_POL_FAST_OFF_MASK		(0x1 << 8)
456 #define RT5682S_POL_FAST_OFF_HIGH		(0x1 << 8)
457 #define RT5682S_POL_FAST_OFF_LOW		(0x0 << 8)
458 #define RT5682S_FAST_OFF_MASK			(0x1 << 7)
459 #define RT5682S_FAST_OFF_EN			(0x1 << 7)
460 #define RT5682S_FAST_OFF_DIS			(0x0 << 7)
461 #define RT5682S_VREF_POW_MASK			(0x1 << 6)
462 #define RT5682S_VREF_POW_FSM			(0x0 << 6)
463 #define RT5682S_VREF_POW_REG			(0x1 << 6)
464 #define RT5682S_MB1_PATH_BIT			5
465 #define RT5682S_MB1_PATH_MASK			(0x1 << 5)
466 #define RT5682S_CTRL_MB1_REG			(0x1 << 5)
467 #define RT5682S_CTRL_MB1_FSM			(0x0 << 5)
468 #define RT5682S_MB2_PATH_BIT			4
469 #define RT5682S_MB2_PATH_MASK			(0x1 << 4)
470 #define RT5682S_CTRL_MB2_REG			(0x1 << 4)
471 #define RT5682S_CTRL_MB2_FSM			(0x0 << 4)
472 #define RT5682S_TRIG_JD_MASK			(0x1 << 3)
473 #define RT5682S_TRIG_JD_HIGH			(0x1 << 3)
474 #define RT5682S_TRIG_JD_LOW			(0x0 << 3)
475 #define RT5682S_MIC_CAP_MASK			(0x1 << 1)
476 #define RT5682S_MIC_CAP_HS			(0x1 << 1)
477 #define RT5682S_MIC_CAP_HP			(0x0 << 1)
478 #define RT5682S_MIC_CAP_SRC_MASK		(0x1)
479 #define RT5682S_MIC_CAP_SRC_REG			(0x1)
480 #define RT5682S_MIC_CAP_SRC_ANA			(0x0)
481 
482 /* Embeeded Jack and Type Detection Control 3 (0x0011) */
483 #define RT5682S_SEL_CBJ_TYPE_SLOW		(0x1 << 15)
484 #define RT5682S_SEL_CBJ_TYPE_NORM		(0x0 << 15)
485 #define RT5682S_SEL_CBJ_TYPE_MASK		(0x1 << 15)
486 #define RT5682S_POW_BG_MB1_MASK			(0x1 << 13)
487 #define RT5682S_POW_BG_MB1_REG			(0x1 << 13)
488 #define RT5682S_POW_BG_MB1_FSM			(0x0 << 13)
489 #define RT5682S_POW_BG_MB2_MASK			(0x1 << 12)
490 #define RT5682S_POW_BG_MB2_REG			(0x1 << 12)
491 #define RT5682S_POW_BG_MB2_FSM			(0x0 << 12)
492 #define RT5682S_EXT_JD_SRC			(0x7 << 4)
493 #define RT5682S_EXT_JD_SRC_SFT			4
494 #define RT5682S_EXT_JD_SRC_GPIO_JD1		(0x0 << 4)
495 #define RT5682S_EXT_JD_SRC_GPIO_JD2		(0x1 << 4)
496 #define RT5682S_EXT_JD_SRC_JDH			(0x2 << 4)
497 #define RT5682S_EXT_JD_SRC_JDL			(0x3 << 4)
498 #define RT5682S_EXT_JD_SRC_MANUAL		(0x4 << 4)
499 #define RT5682S_JACK_TYPE_MASK			(0x3)
500 
501 /* Combo Jack and Type Detection Control 4 (0x0012) */
502 #define RT5682S_CBJ_IN_BUF_MASK			(0x1 << 7)
503 #define RT5682S_CBJ_IN_BUF_EN			(0x1 << 7)
504 #define RT5682S_CBJ_IN_BUF_DIS			(0x0 << 7)
505 #define RT5682S_CBJ_IN_BUF_BIT			7
506 
507 /* Combo Jack and Type Detection Control 5 (0x0013) */
508 #define RT5682S_SEL_SHT_MID_TON_MASK		(0x3 << 12)
509 #define RT5682S_SEL_SHT_MID_TON_2		(0x0 << 12)
510 #define RT5682S_SEL_SHT_MID_TON_3		(0x1 << 12)
511 #define RT5682S_CBJ_JD_TEST_MASK		(0x1 << 6)
512 #define RT5682S_CBJ_JD_TEST_NORM		(0x0 << 6)
513 #define RT5682S_CBJ_JD_TEST_MODE		(0x1 << 6)
514 
515 /* Combo Jack and Type Detection Control 6 (0x0014) */
516 #define RT5682S_JD_FAST_OFF_SRC_MASK		(0x7 << 8)
517 #define RT5682S_JD_FAST_OFF_SRC_JDH		(0x6 << 8)
518 #define RT5682S_JD_FAST_OFF_SRC_GPIO6		(0x5 << 8)
519 #define RT5682S_JD_FAST_OFF_SRC_GPIO5		(0x4 << 8)
520 #define RT5682S_JD_FAST_OFF_SRC_GPIO4		(0x3 << 8)
521 #define RT5682S_JD_FAST_OFF_SRC_GPIO3		(0x2 << 8)
522 #define RT5682S_JD_FAST_OFF_SRC_GPIO2		(0x1 << 8)
523 #define RT5682S_JD_FAST_OFF_SRC_GPIO1		(0x0 << 8)
524 
525 /* DAC1 Digital Volume (0x0019) */
526 #define RT5682S_DAC_L1_VOL_MASK			(0xff << 8)
527 #define RT5682S_DAC_L1_VOL_SFT			8
528 #define RT5682S_DAC_R1_VOL_MASK			(0xff)
529 #define RT5682S_DAC_R1_VOL_SFT			0
530 
531 /* ADC Digital Volume Control (0x001c) */
532 #define RT5682S_ADC_L_VOL_MASK			(0x7f << 8)
533 #define RT5682S_ADC_L_VOL_SFT			8
534 #define RT5682S_ADC_R_VOL_MASK			(0x7f)
535 #define RT5682S_ADC_R_VOL_SFT			0
536 
537 /* Stereo1 ADC Boost Gain Control (0x001f) */
538 #define RT5682S_STO1_ADC_L_BST_MASK		(0x3 << 14)
539 #define RT5682S_STO1_ADC_L_BST_SFT		14
540 #define RT5682S_STO1_ADC_R_BST_MASK		(0x3 << 12)
541 #define RT5682S_STO1_ADC_R_BST_SFT		12
542 
543 /* Sidetone Control (0x0024) */
544 #define RT5682S_ST_SRC_SEL			(0x1 << 8)
545 #define RT5682S_ST_SRC_SFT			8
546 #define RT5682S_ST_EN_MASK			(0x1 << 6)
547 #define RT5682S_ST_DIS				(0x0 << 6)
548 #define RT5682S_ST_EN				(0x1 << 6)
549 #define RT5682S_ST_EN_SFT			6
550 
551 /* Stereo1 ADC Mixer Control (0x0026) */
552 #define RT5682S_M_STO1_ADC_L1			(0x1 << 15)
553 #define RT5682S_M_STO1_ADC_L1_SFT		15
554 #define RT5682S_M_STO1_ADC_L2			(0x1 << 14)
555 #define RT5682S_M_STO1_ADC_L2_SFT		14
556 #define RT5682S_STO1_ADC1L_SRC_MASK		(0x1 << 13)
557 #define RT5682S_STO1_ADC1L_SRC_SFT		13
558 #define RT5682S_STO1_ADC1_SRC_ADC		(0x1 << 13)
559 #define RT5682S_STO1_ADC1_SRC_DACMIX		(0x0 << 13)
560 #define RT5682S_STO1_ADC2L_SRC_MASK		(0x1 << 12)
561 #define RT5682S_STO1_ADC2L_SRC_SFT		12
562 #define RT5682S_STO1_ADCL_SRC_MASK		(0x3 << 10)
563 #define RT5682S_STO1_ADCL_SRC_SFT		10
564 #define RT5682S_M_STO1_ADC_R1			(0x1 << 7)
565 #define RT5682S_M_STO1_ADC_R1_SFT		7
566 #define RT5682S_M_STO1_ADC_R2			(0x1 << 6)
567 #define RT5682S_M_STO1_ADC_R2_SFT		6
568 #define RT5682S_STO1_ADC1R_SRC_MASK		(0x1 << 5)
569 #define RT5682S_STO1_ADC1R_SRC_SFT		5
570 #define RT5682S_STO1_ADC2R_SRC_MASK		(0x1 << 4)
571 #define RT5682S_STO1_ADC2R_SRC_SFT		4
572 #define RT5682S_STO1_ADCR_SRC_MASK		(0x3 << 2)
573 #define RT5682S_STO1_ADCR_SRC_SFT		2
574 
575 /* ADC Mixer to DAC Mixer Control (0x0029) */
576 #define RT5682S_M_ADCMIX_L			(0x1 << 15)
577 #define RT5682S_M_ADCMIX_L_SFT			15
578 #define RT5682S_M_DAC1_L			(0x1 << 14)
579 #define RT5682S_M_DAC1_L_SFT			14
580 #define RT5682S_M_ADCMIX_R			(0x1 << 7)
581 #define RT5682S_M_ADCMIX_R_SFT			7
582 #define RT5682S_M_DAC1_R			(0x1 << 6)
583 #define RT5682S_M_DAC1_R_SFT			6
584 
585 /* Stereo1 DAC Mixer Control (0x002a) */
586 #define RT5682S_M_DAC_L1_STO_L			(0x1 << 15)
587 #define RT5682S_M_DAC_L1_STO_L_SFT		15
588 #define RT5682S_G_DAC_L1_STO_L_MASK		(0x1 << 14)
589 #define RT5682S_G_DAC_L1_STO_L_SFT		14
590 #define RT5682S_M_DAC_R1_STO_L			(0x1 << 13)
591 #define RT5682S_M_DAC_R1_STO_L_SFT		13
592 #define RT5682S_G_DAC_R1_STO_L_MASK		(0x1 << 12)
593 #define RT5682S_G_DAC_R1_STO_L_SFT		12
594 #define RT5682S_M_DAC_L1_STO_R			(0x1 << 7)
595 #define RT5682S_M_DAC_L1_STO_R_SFT		7
596 #define RT5682S_G_DAC_L1_STO_R_MASK		(0x1 << 6)
597 #define RT5682S_G_DAC_L1_STO_R_SFT		6
598 #define RT5682S_M_DAC_R1_STO_R			(0x1 << 5)
599 #define RT5682S_M_DAC_R1_STO_R_SFT		5
600 #define RT5682S_G_DAC_R1_STO_R_MASK		(0x1 << 4)
601 #define RT5682S_G_DAC_R1_STO_R_SFT		4
602 
603 /* Analog DAC1 Input Source Control (0x002b) */
604 #define RT5682S_M_ST_STO_L			(0x1 << 9)
605 #define RT5682S_M_ST_STO_L_SFT			9
606 #define RT5682S_M_ST_STO_R			(0x1 << 8)
607 #define RT5682S_M_ST_STO_R_SFT			8
608 #define RT5682S_DAC_L1_SRC_MASK			(0x1 << 4)
609 #define RT5682S_A_DACL1_SFT			4
610 #define RT5682S_DAC_R1_SRC_MASK			(0x1)
611 #define RT5682S_A_DACR1_SFT			0
612 
613 /* Digital Interface Data Control (0x0030) */
614 #define RT5682S_IF2_DAC_SEL_MASK		(0x3 << 2)
615 #define RT5682S_IF2_DAC_SEL_SFT			2
616 #define RT5682S_IF2_ADC_SEL_MASK		(0x3 << 0)
617 #define RT5682S_IF2_ADC_SEL_SFT			0
618 
619 /* REC Left/Right Mixer Control 2 (0x003c) */
620 #define RT5682S_BST_CBJ_MASK			(0x3f << 8)
621 #define RT5682S_BST_CBJ_SFT			8
622 #define RT5682S_M_CBJ_RM1_L			(0x1 << 7)
623 #define RT5682S_M_CBJ_RM1_L_SFT			7
624 #define RT5682S_M_CBJ_RM1_R			(0x1 << 6)
625 #define RT5682S_M_CBJ_RM1_R_SFT			6
626 
627 /* REC Left/Right Mixer Calibration Control(0x0044) */
628 #define RT5682S_PWR_RM1_R_BIT			8
629 #define RT5682S_PWR_RM1_L_BIT			0
630 
631 /* Power Management for Digital 1 (0x0061) */
632 #define RT5682S_PWR_I2S1			(0x1 << 15)
633 #define RT5682S_PWR_I2S1_BIT			15
634 #define RT5682S_PWR_I2S2			(0x1 << 14)
635 #define RT5682S_PWR_I2S2_BIT			14
636 #define RT5682S_PRE_CHR_DAC_L1			(0x1 << 13)
637 #define RT5682S_PRE_CHR_DAC_L1_BIT		13
638 #define RT5682S_PRE_CHR_DAC_R1			(0x1 << 12)
639 #define RT5682S_PRE_CHR_DAC_R1_BIT		12
640 #define RT5682S_PWR_DAC_L1			(0x1 << 11)
641 #define RT5682S_PWR_DAC_L1_BIT			11
642 #define RT5682S_PWR_DAC_R1			(0x1 << 10)
643 #define RT5682S_PWR_DAC_R1_BIT			10
644 #define RT5682S_PWR_LDO				(0x1 << 8)
645 #define RT5682S_PWR_LDO_BIT			8
646 #define RT5682S_PWR_D2S_L			(0x1 << 7)
647 #define RT5682S_PWR_D2S_L_BIT			7
648 #define RT5682S_PWR_D2S_R			(0x1 << 6)
649 #define RT5682S_PWR_D2S_R_BIT			6
650 #define RT5682S_PWR_ADC_L1			(0x1 << 4)
651 #define RT5682S_PWR_ADC_L1_BIT			4
652 #define RT5682S_PWR_ADC_R1			(0x1 << 3)
653 #define RT5682S_PWR_ADC_R1_BIT			3
654 #define RT5682S_EFUSE_SW_EN			(0x1 << 2)
655 #define RT5682S_EFUSE_SW_DIS			(0x0 << 2)
656 #define RT5682S_PWR_EFUSE			(0x1 << 1)
657 #define RT5682S_PWR_EFUSE_BIT			1
658 #define RT5682S_DIG_GATE_CTRL			(0x1 << 0)
659 #define RT5682S_DIG_GATE_CTRL_SFT		0
660 
661 /* Power Management for Digital 2 (0x0062) */
662 #define RT5682S_PWR_ADC_S1F			(0x1 << 15)
663 #define RT5682S_PWR_ADC_S1F_BIT			15
664 #define RT5682S_PWR_DAC_S1F			(0x1 << 10)
665 #define RT5682S_PWR_DAC_S1F_BIT			10
666 #define RT5682S_DLDO_I_LIMIT_MASK		(0x1 << 7)
667 #define RT5682S_DLDO_I_LIMIT_EN			(0x1 << 7)
668 #define RT5682S_DLDO_I_LIMIT_DIS		(0x0 << 7)
669 #define RT5682S_DLDO_I_BIAS_SEL_4		(0x1 << 6)
670 #define RT5682S_DLDO_I_BIAS_SEL_0		(0x0 << 6)
671 #define RT5682S_DLDO_REG_TEST_1			(0x1 << 5)
672 #define RT5682S_DLDO_REG_TEST_0			(0x0 << 5)
673 #define RT5682S_DLDO_SRC_REG			(0x1 << 4)
674 #define RT5682S_DLDO_SRC_EFUSE			(0x0 << 4)
675 
676 /* Power Management for Analog 1 (0x0063) */
677 #define RT5682S_PWR_VREF1			(0x1 << 15)
678 #define RT5682S_PWR_VREF1_BIT			15
679 #define RT5682S_PWR_FV1				(0x1 << 14)
680 #define RT5682S_PWR_FV1_BIT			14
681 #define RT5682S_PWR_VREF2			(0x1 << 13)
682 #define RT5682S_PWR_VREF2_BIT			13
683 #define RT5682S_PWR_FV2				(0x1 << 12)
684 #define RT5682S_PWR_FV2_BIT			12
685 #define RT5682S_LDO1_DBG_MASK			(0x3 << 10)
686 #define RT5682S_PWR_MB				(0x1 << 9)
687 #define RT5682S_PWR_MB_BIT			9
688 #define RT5682S_PWR_BG				(0x1 << 7)
689 #define RT5682S_PWR_BG_BIT			7
690 #define RT5682S_LDO1_BYPASS_MASK		(0x1 << 6)
691 #define RT5682S_LDO1_BYPASS			(0x1 << 6)
692 #define RT5682S_LDO1_NOT_BYPASS			(0x0 << 6)
693 
694 /* Power Management for Analog 2 (0x0064) */
695 #define RT5682S_PWR_MCLK0_WD			(0x1 << 15)
696 #define RT5682S_PWR_MCLK0_WD_BIT		15
697 #define RT5682S_PWR_MCLK1_WD			(0x1 << 14)
698 #define RT5682S_PWR_MCLK1_WD_BIT		14
699 #define RT5682S_RST_MCLK0			(0x1 << 13)
700 #define RT5682S_RST_MCLK0_BIT			13
701 #define RT5682S_RST_MCLK1			(0x1 << 12)
702 #define RT5682S_RST_MCLK1_BIT			12
703 #define RT5682S_PWR_MB1				(0x1 << 11)
704 #define RT5682S_PWR_MB1_PWR_DOWN		(0x0 << 11)
705 #define RT5682S_PWR_MB1_BIT			11
706 #define RT5682S_PWR_MB2				(0x1 << 10)
707 #define RT5682S_PWR_MB2_PWR_DOWN		(0x0 << 10)
708 #define RT5682S_PWR_MB2_BIT			10
709 #define RT5682S_PWR_JD_MASK			(0x1 << 0)
710 #define RT5682S_PWR_JD_ENABLE			(0x1 << 0)
711 #define RT5682S_PWR_JD_DISABLE			(0x0 << 0)
712 
713 /* Power Management for Analog 3 (0x0065) */
714 #define RT5682S_PWR_LDO_PLLA			(0x1 << 15)
715 #define RT5682S_PWR_LDO_PLLA_BIT		15
716 #define RT5682S_PWR_LDO_PLLB			(0x1 << 14)
717 #define RT5682S_PWR_LDO_PLLB_BIT		14
718 #define RT5682S_PWR_BIAS_PLLA			(0x1 << 13)
719 #define RT5682S_PWR_BIAS_PLLA_BIT		13
720 #define RT5682S_PWR_BIAS_PLLB			(0x1 << 12)
721 #define RT5682S_PWR_BIAS_PLLB_BIT		12
722 #define RT5682S_PWR_CBJ				(0x1 << 9)
723 #define RT5682S_PWR_CBJ_BIT			9
724 #define RT5682S_RSTB_PLLB			(0x1 << 7)
725 #define RT5682S_RSTB_PLLB_BIT			7
726 #define RT5682S_RSTB_PLLA			(0x1 << 6)
727 #define RT5682S_RSTB_PLLA_BIT			6
728 #define RT5682S_PWR_PLLB			(0x1 << 5)
729 #define RT5682S_PWR_PLLB_BIT			5
730 #define RT5682S_PWR_PLLA			(0x1 << 4)
731 #define RT5682S_PWR_PLLA_BIT			4
732 #define RT5682S_PWR_LDO_MB2			(0x1 << 2)
733 #define RT5682S_PWR_LDO_MB2_BIT			2
734 #define RT5682S_PWR_LDO_MB1			(0x1 << 1)
735 #define RT5682S_PWR_LDO_MB1_BIT			1
736 #define RT5682S_PWR_BGLDO			(0x1 << 0)
737 #define RT5682S_PWR_BGLDO_BIT			0
738 
739 /* Power Management for Mixer (0x0066) */
740 #define RT5682S_PWR_CLK_COMP_8FS		(0x1 << 15)
741 #define RT5682S_PWR_CLK_COMP_8FS_BIT		15
742 #define RT5682S_DBG_BGLDO_MASK			(0x3 << 12)
743 #define RT5682S_DBG_BGLDO_SFT			12
744 #define RT5682S_DBG_BGLDO_MB1_MASK		(0x3 << 10)
745 #define RT5682S_DBG_BGLDO_MB1_SFT		10
746 #define RT5682S_DBG_BGLDO_MB2_MASK		(0x3 << 8)
747 #define RT5682S_DBG_BGLDO_MB2_SFT		8
748 #define RT5682S_DLDO_BGLDO_MASK			(0x3 << 6)
749 #define RT5682S_DLDO_BGLDO_MB2_SFT		6
750 #define RT5682S_PWR_STO1_DAC_L			(0x1 << 5)
751 #define RT5682S_PWR_STO1_DAC_L_BIT		5
752 #define RT5682S_PWR_STO1_DAC_R			(0x1 << 4)
753 #define RT5682S_PWR_STO1_DAC_R_BIT		4
754 #define RT5682S_DVO_BGLDO_MB1_MASK		(0x3 << 2)
755 #define RT5682S_DVO_BGLDO_MB1_SFT		2
756 #define RT5682S_DVO_BGLDO_MB2_MASK		(0x3 << 0)
757 
758 /* MCLK and System Clock Detection Control (0x006b) */
759 #define RT5682S_SYS_CLK_DET			(0x1 << 15)
760 #define RT5682S_SYS_CLK_DET_SFT			15
761 #define RT5682S_PLL1_CLK_DET			(0x1 << 14)
762 #define RT5682S_PLL1_CLK_DET_SFT		14
763 
764 /* Digital Microphone Control 1 (0x006e) */
765 #define RT5682S_DMIC_1_EN_MASK			(0x1 << 15)
766 #define RT5682S_DMIC_1_EN_SFT			15
767 #define RT5682S_DMIC_1_DIS			(0x0 << 15)
768 #define RT5682S_DMIC_1_EN			(0x1 << 15)
769 #define RT5682S_FIFO_CLK_DIV_MASK		(0x7 << 12)
770 #define RT5682S_FIFO_CLK_DIV_2			(0x1 << 12)
771 #define RT5682S_DMIC_1_DP_MASK			(0x3 << 4)
772 #define RT5682S_DMIC_1_DP_SFT			4
773 #define RT5682S_DMIC_1_DP_GPIO2			(0x0 << 4)
774 #define RT5682S_DMIC_1_DP_GPIO5			(0x1 << 4)
775 #define RT5682S_DMIC_CLK_MASK			(0xf << 0)
776 #define RT5682S_DMIC_CLK_SFT			0
777 
778 /* I2S1 Audio Serial Data Port Control (0x0070) */
779 #define RT5682S_SEL_ADCDAT_MASK			(0x1 << 15)
780 #define RT5682S_SEL_ADCDAT_OUT			(0x0 << 15)
781 #define RT5682S_SEL_ADCDAT_IN			(0x1 << 15)
782 #define RT5682S_SEL_ADCDAT_SFT			15
783 #define RT5682S_I2S1_TX_CHL_MASK		(0x7 << 12)
784 #define RT5682S_I2S1_TX_CHL_SFT			12
785 #define RT5682S_I2S1_TX_CHL_16			(0x0 << 12)
786 #define RT5682S_I2S1_TX_CHL_20			(0x1 << 12)
787 #define RT5682S_I2S1_TX_CHL_24			(0x2 << 12)
788 #define RT5682S_I2S1_TX_CHL_32			(0x3 << 12)
789 #define RT5682S_I2S1_TX_CHL_8			(0x4 << 12)
790 #define RT5682S_I2S1_RX_CHL_MASK		(0x7 << 8)
791 #define RT5682S_I2S1_RX_CHL_SFT			8
792 #define RT5682S_I2S1_RX_CHL_16			(0x0 << 8)
793 #define RT5682S_I2S1_RX_CHL_20			(0x1 << 8)
794 #define RT5682S_I2S1_RX_CHL_24			(0x2 << 8)
795 #define RT5682S_I2S1_RX_CHL_32			(0x3 << 8)
796 #define RT5682S_I2S1_RX_CHL_8			(0x4 << 8)
797 #define RT5682S_I2S1_MONO_MASK			(0x1 << 7)
798 #define RT5682S_I2S1_MONO_EN			(0x1 << 7)
799 #define RT5682S_I2S1_MONO_DIS			(0x0 << 7)
800 #define RT5682S_I2S1_DL_MASK			(0x7 << 4)
801 #define RT5682S_I2S1_DL_SFT			4
802 #define RT5682S_I2S1_DL_16			(0x0 << 4)
803 #define RT5682S_I2S1_DL_20			(0x1 << 4)
804 #define RT5682S_I2S1_DL_24			(0x2 << 4)
805 #define RT5682S_I2S1_DL_32			(0x3 << 4)
806 #define RT5682S_I2S1_DL_8			(0x4 << 4)
807 
808 /* I2S1/2 Audio Serial Data Port Control (0x0071) */
809 #define RT5682S_I2S2_MS_MASK			(0x1 << 15)
810 #define RT5682S_I2S2_MS_SFT			15
811 #define RT5682S_I2S2_MS_M			(0x0 << 15)
812 #define RT5682S_I2S2_MS_S			(0x1 << 15)
813 #define RT5682S_I2S2_PIN_CFG_MASK		(0x1 << 14)
814 #define RT5682S_I2S2_PIN_CFG_SFT		14
815 #define RT5682S_I2S2_OUT_MASK			(0x1 << 9)
816 #define RT5682S_I2S2_OUT_SFT			9
817 #define RT5682S_I2S2_OUT_UM			(0x0 << 9)
818 #define RT5682S_I2S2_OUT_M			(0x1 << 9)
819 #define RT5682S_I2S_BP_MASK			(0x1 << 8)
820 #define RT5682S_I2S_BP_SFT			8
821 #define RT5682S_I2S_BP_NOR			(0x0 << 8)
822 #define RT5682S_I2S_BP_INV			(0x1 << 8)
823 #define RT5682S_I2S2_MONO_MASK			(0x1 << 7)
824 #define RT5682S_I2S2_MONO_EN			(0x1 << 7)
825 #define RT5682S_I2S2_MONO_DIS			(0x0 << 7)
826 #define RT5682S_I2S2_DL_MASK			(0x7 << 4)
827 #define RT5682S_I2S2_DL_SFT			4
828 #define RT5682S_I2S2_DL_8			(0x0 << 4)
829 #define RT5682S_I2S2_DL_16			(0x1 << 4)
830 #define RT5682S_I2S2_DL_20			(0x2 << 4)
831 #define RT5682S_I2S2_DL_24			(0x3 << 4)
832 #define RT5682S_I2S2_DL_32			(0x4 << 4)
833 #define RT5682S_I2S_DF_MASK			(0x7)
834 #define RT5682S_I2S_DF_SFT			0
835 #define RT5682S_I2S_DF_I2S			(0x0)
836 #define RT5682S_I2S_DF_LEFT			(0x1)
837 #define RT5682S_I2S_DF_PCM_A			(0x2)
838 #define RT5682S_I2S_DF_PCM_B			(0x3)
839 #define RT5682S_I2S_DF_PCM_A_N			(0x6)
840 #define RT5682S_I2S_DF_PCM_B_N			(0x7)
841 
842 /* ADC/DAC Clock Control 1 (0x0073) */
843 #define RT5682S_ADC_OSR_MASK			(0xf << 12)
844 #define RT5682S_ADC_OSR_SFT			12
845 #define RT5682S_ADC_OSR_D_1			(0x0 << 12)
846 #define RT5682S_ADC_OSR_D_2			(0x1 << 12)
847 #define RT5682S_ADC_OSR_D_4			(0x2 << 12)
848 #define RT5682S_ADC_OSR_D_6			(0x3 << 12)
849 #define RT5682S_ADC_OSR_D_8			(0x4 << 12)
850 #define RT5682S_ADC_OSR_D_12			(0x5 << 12)
851 #define RT5682S_ADC_OSR_D_16			(0x6 << 12)
852 #define RT5682S_ADC_OSR_D_24			(0x7 << 12)
853 #define RT5682S_ADC_OSR_D_32			(0x8 << 12)
854 #define RT5682S_ADC_OSR_D_48			(0x9 << 12)
855 #define RT5682S_I2S_M_D_MASK			(0xf << 8)
856 #define RT5682S_I2S_M_D_SFT			8
857 #define RT5682S_I2S_M_D_1			(0x0 << 8)
858 #define RT5682S_I2S_M_D_2			(0x1 << 8)
859 #define RT5682S_I2S_M_D_3			(0x2 << 8)
860 #define RT5682S_I2S_M_D_4			(0x3 << 8)
861 #define RT5682S_I2S_M_D_6			(0x4 << 8)
862 #define RT5682S_I2S_M_D_8			(0x5 << 8)
863 #define RT5682S_I2S_M_D_12			(0x6 << 8)
864 #define RT5682S_I2S_M_D_16			(0x7 << 8)
865 #define RT5682S_I2S_M_D_24			(0x8 << 8)
866 #define RT5682S_I2S_M_D_32			(0x9 << 8)
867 #define RT5682S_I2S_M_D_48			(0x10 << 8)
868 #define RT5682S_I2S_M_CLK_SRC_MASK		(0x7 << 4)
869 #define RT5682S_I2S_M_CLK_SRC_SFT		4
870 #define RT5682S_DAC_OSR_MASK			(0xf << 0)
871 #define RT5682S_DAC_OSR_SFT			0
872 #define RT5682S_DAC_OSR_D_1			(0x0 << 0)
873 #define RT5682S_DAC_OSR_D_2			(0x1 << 0)
874 #define RT5682S_DAC_OSR_D_4			(0x2 << 0)
875 #define RT5682S_DAC_OSR_D_6			(0x3 << 0)
876 #define RT5682S_DAC_OSR_D_8			(0x4 << 0)
877 #define RT5682S_DAC_OSR_D_12			(0x5 << 0)
878 #define RT5682S_DAC_OSR_D_16			(0x6 << 0)
879 #define RT5682S_DAC_OSR_D_24			(0x7 << 0)
880 #define RT5682S_DAC_OSR_D_32			(0x8 << 0)
881 #define RT5682S_DAC_OSR_D_48			(0x9 << 0)
882 
883 /* ADC/DAC Clock Control 2 (0x0074) */
884 #define RT5682S_I2S2_BCLK_MS2_MASK		(0x1 << 11)
885 #define RT5682S_I2S2_BCLK_MS2_SFT		11
886 #define RT5682S_I2S2_BCLK_MS2_32		(0x0 << 11)
887 #define RT5682S_I2S2_BCLK_MS2_64		(0x1 << 11)
888 
889 
890 /* TDM control 1 (0x0079) */
891 #define RT5682S_TDM_TX_CH_MASK			(0x3 << 12)
892 #define RT5682S_TDM_TX_CH_2			(0x0 << 12)
893 #define RT5682S_TDM_TX_CH_4			(0x1 << 12)
894 #define RT5682S_TDM_TX_CH_6			(0x2 << 12)
895 #define RT5682S_TDM_TX_CH_8			(0x3 << 12)
896 #define RT5682S_TDM_RX_CH_MASK			(0x3 << 8)
897 #define RT5682S_TDM_RX_CH_2			(0x0 << 8)
898 #define RT5682S_TDM_RX_CH_4			(0x1 << 8)
899 #define RT5682S_TDM_RX_CH_6			(0x2 << 8)
900 #define RT5682S_TDM_RX_CH_8			(0x3 << 8)
901 #define RT5682S_TDM_ADC_LCA_MASK		(0x7 << 4)
902 #define RT5682S_TDM_ADC_LCA_SFT			4
903 #define RT5682S_TDM_ADC_DL_MASK			(0x3 << 0)
904 #define RT5682S_TDM_ADC_DL_SFT			0
905 
906 /* TDM control 2 (0x007a) */
907 #define RT5682S_IF1_ADC1_SEL_SFT		14
908 #define RT5682S_IF1_ADC2_SEL_SFT		12
909 #define RT5682S_IF1_ADC3_SEL_SFT		10
910 #define RT5682S_IF1_ADC4_SEL_SFT		8
911 #define RT5682S_TDM_ADC_SEL_SFT			3
912 
913 /* TDM control 3 (0x007b) */
914 #define RT5682S_TDM_EN				(0x1 << 7)
915 
916 /* TDM/I2S control (0x007e) */
917 #define RT5682S_TDM_S_BP_MASK			(0x1 << 15)
918 #define RT5682S_TDM_S_BP_SFT			15
919 #define RT5682S_TDM_S_BP_NOR			(0x0 << 15)
920 #define RT5682S_TDM_S_BP_INV			(0x1 << 15)
921 #define RT5682S_TDM_S_LP_MASK			(0x1 << 14)
922 #define RT5682S_TDM_S_LP_SFT			14
923 #define RT5682S_TDM_S_LP_NOR			(0x0 << 14)
924 #define RT5682S_TDM_S_LP_INV			(0x1 << 14)
925 #define RT5682S_TDM_DF_MASK			(0x7 << 11)
926 #define RT5682S_TDM_DF_SFT			11
927 #define RT5682S_TDM_DF_I2S			(0x0 << 11)
928 #define RT5682S_TDM_DF_LEFT			(0x1 << 11)
929 #define RT5682S_TDM_DF_PCM_A			(0x2 << 11)
930 #define RT5682S_TDM_DF_PCM_B			(0x3 << 11)
931 #define RT5682S_TDM_DF_PCM_A_N			(0x6 << 11)
932 #define RT5682S_TDM_DF_PCM_B_N			(0x7 << 11)
933 #define RT5682S_TDM_BCLK_MS1_MASK		(0x3 << 8)
934 #define RT5682S_TDM_BCLK_MS1_SFT		8
935 #define RT5682S_TDM_BCLK_MS1_32			(0x0 << 8)
936 #define RT5682S_TDM_BCLK_MS1_64			(0x1 << 8)
937 #define RT5682S_TDM_BCLK_MS1_128		(0x2 << 8)
938 #define RT5682S_TDM_BCLK_MS1_256		(0x3 << 8)
939 #define RT5682S_TDM_BCLK_MS1_16			(0x4 << 8)
940 #define RT5682S_TDM_CL_MASK			(0x3 << 4)
941 #define RT5682S_TDM_CL_16			(0x0 << 4)
942 #define RT5682S_TDM_CL_20			(0x1 << 4)
943 #define RT5682S_TDM_CL_24			(0x2 << 4)
944 #define RT5682S_TDM_CL_32			(0x3 << 4)
945 #define RT5682S_TDM_M_BP_MASK			(0x1 << 2)
946 #define RT5682S_TDM_M_BP_SFT			2
947 #define RT5682S_TDM_M_BP_NOR			(0x0 << 2)
948 #define RT5682S_TDM_M_BP_INV			(0x1 << 2)
949 #define RT5682S_TDM_M_LP_MASK			(0x1 << 1)
950 #define RT5682S_TDM_M_LP_SFT			1
951 #define RT5682S_TDM_M_LP_NOR			(0x0 << 1)
952 #define RT5682S_TDM_M_LP_INV			(0x1 << 1)
953 #define RT5682S_TDM_MS_MASK			(0x1 << 0)
954 #define RT5682S_TDM_MS_SFT			0
955 #define RT5682S_TDM_MS_S			(0x0 << 0)
956 #define RT5682S_TDM_MS_M			(0x1 << 0)
957 
958 /* Global Clock Control (0x0080) */
959 #define RT5682S_SCLK_SRC_MASK			(0x7 << 13)
960 #define RT5682S_SCLK_SRC_SFT			13
961 #define RT5682S_PLL_SRC_MASK			(0x3 << 8)
962 #define RT5682S_PLL_SRC_SFT			8
963 #define RT5682S_PLL_SRC_MCLK			(0x0 << 8)
964 #define RT5682S_PLL_SRC_BCLK1			(0x1 << 8)
965 #define RT5682S_PLL_SRC_RC			(0x3 << 8)
966 
967 /* PLL tracking mode 1 (0x0083) */
968 #define RT5682S_DA_ASRC_MASK			(0x1 << 13)
969 #define RT5682S_DA_ASRC_SFT			13
970 #define RT5682S_DAC_STO1_ASRC_MASK		(0x1 << 12)
971 #define RT5682S_DAC_STO1_ASRC_SFT		12
972 #define RT5682S_AD_ASRC_MASK			(0x1 << 8)
973 #define RT5682S_AD_ASRC_SFT			8
974 #define RT5682S_AD_ASRC_SEL_MASK		(0x1 << 4)
975 #define RT5682S_AD_ASRC_SEL_SFT			4
976 #define RT5682S_DMIC_ASRC_MASK			(0x1 << 3)
977 #define RT5682S_DMIC_ASRC_SFT			3
978 #define RT5682S_ADC_STO1_ASRC_MASK		(0x1 << 2)
979 #define RT5682S_ADC_STO1_ASRC_SFT		2
980 #define RT5682S_DA_ASRC_SEL_MASK		(0x1 << 0)
981 #define RT5682S_DA_ASRC_SEL_SFT			0
982 
983 /* PLL tracking mode 2 3 (0x0084)(0x0085)*/
984 #define RT5682S_FILTER_CLK_SEL_MASK		(0x7 << 12)
985 #define RT5682S_FILTER_CLK_SEL_SFT		12
986 #define RT5682S_FILTER_CLK_DIV_MASK		(0xf << 8)
987 #define RT5682S_FILTER_CLK_DIV_SFT		8
988 
989 /* ASRC Control 4 (0x0086) */
990 #define RT5682S_ASRCIN_FTK_N1_MASK		(0x3 << 14)
991 #define RT5682S_ASRCIN_FTK_N1_SFT		14
992 #define RT5682S_ASRCIN_FTK_N2_MASK		(0x3 << 12)
993 #define RT5682S_ASRCIN_FTK_N2_SFT		12
994 #define RT5682S_ASRCIN_FTK_M1_MASK		(0x7 << 8)
995 #define RT5682S_ASRCIN_FTK_M1_SFT		8
996 #define RT5682S_ASRCIN_FTK_M2_MASK		(0x7 << 4)
997 #define RT5682S_ASRCIN_FTK_M2_SFT		4
998 
999 /* ASRC Control 11 (0x008c) */
1000 #define RT5682S_ASRCIN_AUTO_CLKOUT_MASK		(0x1 << 5)
1001 #define RT5682S_ASRCIN_AUTO_CLKOUT_EN		(0x1 << 5)
1002 #define RT5682S_ASRCIN_AUTO_CLKOUT_DIS		(0x0 << 5)
1003 #define RT5682S_ASRCIN_AUTO_RST_MASK		(0x1 << 4)
1004 #define RT5682S_ASRCIN_AUTO_RST_EN		(0x1 << 4)
1005 #define RT5682S_ASRCIN_AUTO_RST_DIS		(0x0 << 4)
1006 #define RT5682S_SEL_LRCK_DET_MASK		(0x3)
1007 #define RT5682S_SEL_LRCK_DET_DIV8		(0x3)
1008 #define RT5682S_SEL_LRCK_DET_DIV4		(0x2)
1009 #define RT5682S_SEL_LRCK_DET_DIV2		(0x1)
1010 #define RT5682S_SEL_LRCK_DET_DIV1		(0x0)
1011 
1012 /* Depop Mode Control 1 (0x008e) */
1013 #define RT5682S_OUT_HP_L_EN			(0x1 << 6)
1014 #define RT5682S_OUT_HP_R_EN			(0x1 << 5)
1015 #define RT5682S_LDO_PUMP_EN			(0x1 << 4)
1016 #define RT5682S_LDO_PUMP_EN_SFT			4
1017 #define RT5682S_PUMP_EN				(0x1 << 3)
1018 #define RT5682S_PUMP_EN_SFT			3
1019 #define RT5682S_CAPLESS_L_EN			(0x1 << 1)
1020 #define RT5682S_CAPLESS_L_EN_SFT		1
1021 #define RT5682S_CAPLESS_R_EN			(0x1 << 0)
1022 #define RT5682S_CAPLESS_R_EN_SFT		0
1023 
1024 /* Depop Mode Control 2 (0x8f) */
1025 #define RT5682S_RAMP_MASK			(0x1 << 12)
1026 #define RT5682S_RAMP_SFT			12
1027 #define RT5682S_RAMP_DIS			(0x0 << 12)
1028 #define RT5682S_RAMP_EN				(0x1 << 12)
1029 #define RT5682S_BPS_MASK			(0x1 << 11)
1030 #define RT5682S_BPS_SFT				11
1031 #define RT5682S_BPS_DIS				(0x0 << 11)
1032 #define RT5682S_BPS_EN				(0x1 << 11)
1033 #define RT5682S_FAST_UPDN_MASK			(0x1 << 10)
1034 #define RT5682S_FAST_UPDN_SFT			10
1035 #define RT5682S_FAST_UPDN_DIS			(0x0 << 10)
1036 #define RT5682S_FAST_UPDN_EN			(0x1 << 10)
1037 #define RT5682S_VLO_MASK			(0x1 << 7)
1038 #define RT5682S_VLO_SFT				7
1039 #define RT5682S_VLO_3V				(0x0 << 7)
1040 #define RT5682S_VLO_33V				(0x1 << 7)
1041 
1042 /* HPOUT charge pump 1 (0x0091) */
1043 #define RT5682S_OSW_L_MASK			(0x1 << 11)
1044 #define RT5682S_OSW_L_SFT			11
1045 #define RT5682S_OSW_L_DIS			(0x0 << 11)
1046 #define RT5682S_OSW_L_EN			(0x1 << 11)
1047 #define RT5682S_OSW_R_MASK			(0x1 << 10)
1048 #define RT5682S_OSW_R_SFT			10
1049 #define RT5682S_OSW_R_DIS			(0x0 << 10)
1050 #define RT5682S_OSW_R_EN			(0x1 << 10)
1051 #define RT5682S_PM_HP_MASK			(0x3 << 8)
1052 #define RT5682S_PM_HP_SFT			8
1053 #define RT5682S_PM_HP_LV			(0x0 << 8)
1054 #define RT5682S_PM_HP_MV			(0x1 << 8)
1055 #define RT5682S_PM_HP_HV			(0x2 << 8)
1056 
1057 /* Micbias Control1 (0x93) */
1058 #define RT5682S_MIC1_OV_MASK			(0x3 << 14)
1059 #define RT5682S_MIC1_OV_SFT			14
1060 #define RT5682S_MIC1_OV_2V7			(0x0 << 14)
1061 #define RT5682S_MIC1_OV_2V4			(0x1 << 14)
1062 #define RT5682S_MIC1_OV_2V25			(0x3 << 14)
1063 #define RT5682S_MIC1_OV_1V8			(0x4 << 14)
1064 #define RT5682S_MIC2_OV_MASK			(0x3 << 8)
1065 #define RT5682S_MIC2_OV_SFT			8
1066 #define RT5682S_MIC2_OV_2V7			(0x0 << 8)
1067 #define RT5682S_MIC2_OV_2V4			(0x1 << 8)
1068 #define RT5682S_MIC2_OV_2V25			(0x3 << 8)
1069 #define RT5682S_MIC2_OV_1V8			(0x4 << 8)
1070 
1071 /* Micbias Control2 (0x0094) */
1072 #define RT5682S_PWR_CLK25M_MASK			(0x1 << 9)
1073 #define RT5682S_PWR_CLK25M_SFT			9
1074 #define RT5682S_PWR_CLK25M_PD			(0x0 << 9)
1075 #define RT5682S_PWR_CLK25M_PU			(0x1 << 9)
1076 #define RT5682S_PWR_CLK1M_MASK			(0x1 << 8)
1077 #define RT5682S_PWR_CLK1M_SFT			8
1078 #define RT5682S_PWR_CLK1M_PD			(0x0 << 8)
1079 #define RT5682S_PWR_CLK1M_PU			(0x1 << 8)
1080 
1081 /* PLL M/N/K Code Control 1 (0x0098) */
1082 #define RT5682S_PLLA_N_MASK			(0x1ff << 0)
1083 
1084 /* PLL M/N/K Code Control 2 (0x0099) */
1085 #define RT5682S_PLLA_M_MASK			(0x1f << 8)
1086 #define RT5682S_PLLA_M_SFT			8
1087 #define RT5682S_PLLA_K_MASK			(0x1f << 0)
1088 
1089 /* PLL M/N/K Code Control 3 (0x009a) */
1090 #define RT5682S_PLLB_N_MASK			(0x3ff << 0)
1091 
1092 /* PLL M/N/K Code Control 4 (0x009b) */
1093 #define RT5682S_PLLB_M_MASK			(0x1f << 8)
1094 #define RT5682S_PLLB_M_SFT			8
1095 #define RT5682S_PLLB_K_MASK			(0x1f << 0)
1096 
1097 /* PLL M/N/K Code Control 6 (0x009d) */
1098 #define RT5682S_PLLB_SEL_PS_MASK		(0x1 << 13)
1099 #define RT5682S_PLLB_SEL_PS_SFT			13
1100 #define RT5682S_PLLB_BYP_PS_MASK		(0x1 << 12)
1101 #define RT5682S_PLLB_BYP_PS_SFT			12
1102 #define RT5682S_PLLB_M_BP_MASK			(0x1 << 11)
1103 #define RT5682S_PLLB_M_BP_SFT			11
1104 #define RT5682S_PLLB_K_BP_MASK			(0x1 << 10)
1105 #define RT5682S_PLLB_K_BP_SFT			10
1106 #define RT5682S_PLLA_M_BP_MASK			(0x1 << 7)
1107 #define RT5682S_PLLA_M_BP_SFT			7
1108 #define RT5682S_PLLA_K_BP_MASK			(0x1 << 6)
1109 #define RT5682S_PLLA_K_BP_SFT			6
1110 
1111 /* PLL M/N/K Code Control 7 (0x009e) */
1112 #define RT5682S_PLLB_SRC_MASK			(0x1)
1113 #define RT5682S_PLLB_SRC_DFIN			(0x1)
1114 #define RT5682S_PLLB_SRC_PLLA			(0x0)
1115 
1116 /* RC Clock Control (0x009f) */
1117 #define RT5682S_POW_IRQ				(0x1 << 15)
1118 #define RT5682S_POW_JDH				(0x1 << 14)
1119 
1120 /* I2S2 Master Mode Clock Control 1 (0x00a0) */
1121 #define RT5682S_I2S2_M_CLK_SRC_MASK		(0x7 << 4)
1122 #define RT5682S_I2S2_M_CLK_SRC_SFT		4
1123 #define RT5682S_I2S2_M_D_MASK			(0xf << 0)
1124 #define RT5682S_I2S2_M_D_1			(0x0)
1125 #define RT5682S_I2S2_M_D_2			(0x1)
1126 #define RT5682S_I2S2_M_D_3			(0x2)
1127 #define RT5682S_I2S2_M_D_4			(0x3)
1128 #define RT5682S_I2S2_M_D_6			(0x4)
1129 #define RT5682S_I2S2_M_D_8			(0x5)
1130 #define RT5682S_I2S2_M_D_12			(0x6)
1131 #define RT5682S_I2S2_M_D_16			(0x7)
1132 #define RT5682S_I2S2_M_D_24			(0x8)
1133 #define RT5682S_I2S2_M_D_32			(0x9)
1134 #define RT5682S_I2S2_M_D_48			(0xa)
1135 #define RT5682S_I2S2_M_D_SFT			0
1136 
1137 /* IRQ Control 1 (0x00b6) */
1138 #define RT5682S_JD1_PULSE_EN_MASK		(0x1 << 10)
1139 #define RT5682S_JD1_PULSE_EN_SFT		10
1140 #define RT5682S_JD1_PULSE_DIS			(0x0 << 10)
1141 #define RT5682S_JD1_PULSE_EN			(0x1 << 10)
1142 
1143 /* IRQ Control 2 (0x00b7) */
1144 #define RT5682S_JD1_EN_MASK			(0x1 << 15)
1145 #define RT5682S_JD1_EN_SFT			15
1146 #define RT5682S_JD1_DIS				(0x0 << 15)
1147 #define RT5682S_JD1_EN				(0x1 << 15)
1148 #define RT5682S_JD1_POL_MASK			(0x1 << 13)
1149 #define RT5682S_JD1_POL_NOR			(0x0 << 13)
1150 #define RT5682S_JD1_POL_INV			(0x1 << 13)
1151 #define RT5682S_JD1_IRQ_MASK			(0x1 << 10)
1152 #define RT5682S_JD1_IRQ_LEV			(0x0 << 10)
1153 #define RT5682S_JD1_IRQ_PUL			(0x1 << 10)
1154 
1155 /* IRQ Control 3 (0x00b8) */
1156 #define RT5682S_IL_IRQ_MASK			(0x1 << 7)
1157 #define RT5682S_IL_IRQ_DIS			(0x0 << 7)
1158 #define RT5682S_IL_IRQ_EN			(0x1 << 7)
1159 #define RT5682S_IL_IRQ_TYPE_MASK		(0x1 << 4)
1160 #define RT5682S_IL_IRQ_LEV			(0x0 << 4)
1161 #define RT5682S_IL_IRQ_PUL			(0x1 << 4)
1162 
1163 /* GPIO Control 1 (0x00c0) */
1164 #define RT5682S_GP1_PIN_MASK			(0x3 << 14)
1165 #define RT5682S_GP1_PIN_SFT			14
1166 #define RT5682S_GP1_PIN_GPIO1			(0x0 << 14)
1167 #define RT5682S_GP1_PIN_IRQ			(0x1 << 14)
1168 #define RT5682S_GP1_PIN_DMIC_CLK		(0x2 << 14)
1169 #define RT5682S_GP2_PIN_MASK			(0x3 << 12)
1170 #define RT5682S_GP2_PIN_SFT			12
1171 #define RT5682S_GP2_PIN_GPIO2			(0x0 << 12)
1172 #define RT5682S_GP2_PIN_LRCK2			(0x1 << 12)
1173 #define RT5682S_GP2_PIN_DMIC_SDA		(0x2 << 12)
1174 #define RT5682S_GP3_PIN_MASK			(0x3 << 10)
1175 #define RT5682S_GP3_PIN_SFT			10
1176 #define RT5682S_GP3_PIN_GPIO3			(0x0 << 10)
1177 #define RT5682S_GP3_PIN_BCLK2			(0x1 << 10)
1178 #define RT5682S_GP3_PIN_DMIC_CLK		(0x2 << 10)
1179 #define RT5682S_GP4_PIN_MASK			(0x3 << 8)
1180 #define RT5682S_GP4_PIN_SFT			8
1181 #define RT5682S_GP4_PIN_GPIO4			(0x0 << 8)
1182 #define RT5682S_GP4_PIN_ADCDAT1			(0x1 << 8)
1183 #define RT5682S_GP4_PIN_DMIC_CLK		(0x2 << 8)
1184 #define RT5682S_GP4_PIN_ADCDAT2			(0x3 << 8)
1185 #define RT5682S_GP5_PIN_MASK			(0x3 << 6)
1186 #define RT5682S_GP5_PIN_SFT			6
1187 #define RT5682S_GP5_PIN_GPIO5			(0x0 << 6)
1188 #define RT5682S_GP5_PIN_DACDAT1			(0x1 << 6)
1189 #define RT5682S_GP5_PIN_DMIC_SDA		(0x2 << 6)
1190 #define RT5682S_GP6_PIN_MASK			(0x1 << 5)
1191 #define RT5682S_GP6_PIN_SFT			5
1192 #define RT5682S_GP6_PIN_GPIO6			(0x0 << 5)
1193 #define RT5682S_GP6_PIN_LRCK1			(0x1 << 5)
1194 
1195 /* GPIO Control 2 (0x00c1)*/
1196 #define RT5682S_GP1_PF_MASK			(0x1 << 15)
1197 #define RT5682S_GP1_PF_IN			(0x0 << 15)
1198 #define RT5682S_GP1_PF_OUT			(0x1 << 15)
1199 #define RT5682S_GP1_OUT_MASK			(0x1 << 14)
1200 #define RT5682S_GP1_OUT_L			(0x0 << 14)
1201 #define RT5682S_GP1_OUT_H			(0x1 << 14)
1202 #define RT5682S_GP2_PF_MASK			(0x1 << 13)
1203 #define RT5682S_GP2_PF_IN			(0x0 << 13)
1204 #define RT5682S_GP2_PF_OUT			(0x1 << 13)
1205 #define RT5682S_GP2_OUT_MASK			(0x1 << 12)
1206 #define RT5682S_GP2_OUT_L			(0x0 << 12)
1207 #define RT5682S_GP2_OUT_H			(0x1 << 12)
1208 #define RT5682S_GP3_PF_MASK			(0x1 << 11)
1209 #define RT5682S_GP3_PF_IN			(0x0 << 11)
1210 #define RT5682S_GP3_PF_OUT			(0x1 << 11)
1211 #define RT5682S_GP3_OUT_MASK			(0x1 << 10)
1212 #define RT5682S_GP3_OUT_L			(0x0 << 10)
1213 #define RT5682S_GP3_OUT_H			(0x1 << 10)
1214 #define RT5682S_GP4_PF_MASK			(0x1 << 9)
1215 #define RT5682S_GP4_PF_IN			(0x0 << 9)
1216 #define RT5682S_GP4_PF_OUT			(0x1 << 9)
1217 #define RT5682S_GP4_OUT_MASK			(0x1 << 8)
1218 #define RT5682S_GP4_OUT_L			(0x0 << 8)
1219 #define RT5682S_GP4_OUT_H			(0x1 << 8)
1220 #define RT5682S_GP5_PF_MASK			(0x1 << 7)
1221 #define RT5682S_GP5_PF_IN			(0x0 << 7)
1222 #define RT5682S_GP5_PF_OUT			(0x1 << 7)
1223 #define RT5682S_GP5_OUT_MASK			(0x1 << 6)
1224 #define RT5682S_GP5_OUT_L			(0x0 << 6)
1225 #define RT5682S_GP5_OUT_H			(0x1 << 6)
1226 #define RT5682S_GP6_PF_MASK			(0x1 << 5)
1227 #define RT5682S_GP6_PF_IN			(0x0 << 5)
1228 #define RT5682S_GP6_PF_OUT			(0x1 << 5)
1229 #define RT5682S_GP6_OUT_MASK			(0x1 << 4)
1230 #define RT5682S_GP6_OUT_L			(0x0 << 4)
1231 #define RT5682S_GP6_OUT_H			(0x1 << 4)
1232 
1233 /* GPIO Status (0x00c2) */
1234 #define RT5682S_GP6_ST				(0x1 << 6)
1235 #define RT5682S_GP5_ST				(0x1 << 5)
1236 #define RT5682S_GP4_ST				(0x1 << 4)
1237 #define RT5682S_GP3_ST				(0x1 << 3)
1238 #define RT5682S_GP2_ST				(0x1 << 2)
1239 #define RT5682S_GP1_ST				(0x1 << 1)
1240 
1241 /* Soft volume and zero cross control 1 (0x00d9) */
1242 #define RT5682S_ZCD_MASK			(0x1 << 10)
1243 #define RT5682S_ZCD_SFT				10
1244 #define RT5682S_ZCD_PD				(0x0 << 10)
1245 #define RT5682S_ZCD_PU				(0x1 << 10)
1246 
1247 /* 4 Button Inline Command Control 2 (0x00e3) */
1248 #define RT5682S_4BTN_IL_MASK			(0x1 << 15)
1249 #define RT5682S_4BTN_IL_EN			(0x1 << 15)
1250 #define RT5682S_4BTN_IL_DIS			(0x0 << 15)
1251 #define RT5682S_4BTN_IL_RST_MASK		(0x1 << 14)
1252 #define RT5682S_4BTN_IL_NOR			(0x1 << 14)
1253 #define RT5682S_4BTN_IL_RST			(0x0 << 14)
1254 
1255 /* 4 Button Inline Command Control 3~6 (0x00e5~0x00e8) */
1256 #define RT5682S_4BTN_IL_HOLD_WIN_MASK		(0x7f << 8)
1257 #define RT5682S_4BTN_IL_HOLD_WIN_SFT		8
1258 #define RT5682S_4BTN_IL_CLICK_WIN_MASK		(0x7f)
1259 #define RT5682S_4BTN_IL_CLICK_WIN_SFT		0
1260 
1261 /* Analog JD Control (0x00f0) */
1262 #define RT5682S_JDH_RS_MASK			(0x1 << 4)
1263 #define RT5682S_JDH_NO_PLUG			(0x1 << 4)
1264 #define RT5682S_JDH_PLUG			(0x0 << 4)
1265 
1266 /* Charge Pump Internal Register1 (0x0125) */
1267 #define RT5682S_CP_CLK_HP_MASK			(0x3 << 4)
1268 #define RT5682S_CP_CLK_HP_100KHZ		(0x0 << 4)
1269 #define RT5682S_CP_CLK_HP_200KHZ		(0x1 << 4)
1270 #define RT5682S_CP_CLK_HP_300KHZ		(0x2 << 4)
1271 #define RT5682S_CP_CLK_HP_600KHZ		(0x3 << 4)
1272 
1273 /* Pad Driving Control (0x0136) */
1274 #define RT5682S_PAD_DRV_GP1_MASK		(0x1 << 14)
1275 #define RT5682S_PAD_DRV_GP1_HIGH		(0x1 << 14)
1276 #define RT5682S_PAD_DRV_GP1_LOW			(0x0 << 14)
1277 #define RT5682S_PAD_DRV_GP2_MASK		(0x1 << 12)
1278 #define RT5682S_PAD_DRV_GP2_HIGH		(0x1 << 12)
1279 #define RT5682S_PAD_DRV_GP2_LOW			(0x0 << 12)
1280 #define RT5682S_PAD_DRV_GP3_MASK		(0x1 << 10)
1281 #define RT5682S_PAD_DRV_GP3_HIGH		(0x1 << 10)
1282 #define RT5682S_PAD_DRV_GP3_LOW			(0x0 << 10)
1283 #define RT5682S_PAD_DRV_GP4_MASK		(0x1 << 8)
1284 #define RT5682S_PAD_DRV_GP4_HIGH		(0x1 << 8)
1285 #define RT5682S_PAD_DRV_GP4_LOW			(0x0 << 8)
1286 #define RT5682S_PAD_DRV_GP5_MASK		(0x1 << 6)
1287 #define RT5682S_PAD_DRV_GP5_HIGH		(0x1 << 6)
1288 #define RT5682S_PAD_DRV_GP5_LOW			(0x0 << 6)
1289 #define RT5682S_PAD_DRV_GP6_MASK		(0x1 << 4)
1290 #define RT5682S_PAD_DRV_GP6_HIGH		(0x1 << 4)
1291 #define RT5682S_PAD_DRV_GP6_LOW			(0x0 << 4)
1292 
1293 /* Chopper and Clock control for DAC (0x013a)*/
1294 #define RT5682S_CKXEN_DAC1_MASK			(0x1 << 13)
1295 #define RT5682S_CKXEN_DAC1_SFT			13
1296 #define RT5682S_CKGEN_DAC1_MASK			(0x1 << 12)
1297 #define RT5682S_CKGEN_DAC1_SFT			12
1298 
1299 /* Chopper and Clock control for ADC (0x013b)*/
1300 #define RT5682S_CKXEN_ADC1_MASK			(0x1 << 13)
1301 #define RT5682S_CKXEN_ADC1_SFT			13
1302 #define RT5682S_CKGEN_ADC1_MASK			(0x1 << 12)
1303 #define RT5682S_CKGEN_ADC1_SFT			12
1304 
1305 /* Volume test (0x013f)*/
1306 #define RT5682S_SEL_CLK_VOL_MASK		(0x1 << 15)
1307 #define RT5682S_SEL_CLK_VOL_EN			(0x1 << 15)
1308 #define RT5682S_SEL_CLK_VOL_DIS			(0x0 << 15)
1309 
1310 /* Test Mode Control 1 (0x0145) */
1311 #define RT5682S_AD2DA_LB_MASK			(0x1 << 10)
1312 #define RT5682S_AD2DA_LB_SFT			10
1313 
1314 /* Stereo Noise Gate Control 1 (0x0160) */
1315 #define RT5682S_NG2_EN_MASK			(0x1 << 15)
1316 #define RT5682S_NG2_EN				(0x1 << 15)
1317 #define RT5682S_NG2_DIS				(0x0 << 15)
1318 
1319 /* Stereo1 DAC Silence Detection Control (0x0190) */
1320 #define RT5682S_DEB_STO_DAC_MASK		(0x7 << 4)
1321 #define RT5682S_DEB_80_MS			(0x0 << 4)
1322 
1323 /* HP Behavior Logic Control 2 (0x01db) */
1324 #define RT5682S_HP_SIG_SRC_MASK			(0x3)
1325 #define RT5682S_HP_SIG_SRC_1BIT_CTL		(0x3)
1326 #define RT5682S_HP_SIG_SRC_REG			(0x2)
1327 #define RT5682S_HP_SIG_SRC_IMPE_REG		(0x1)
1328 #define RT5682S_HP_SIG_SRC_DC_CALI		(0x0)
1329 
1330 /* SAR ADC Inline Command Control 1 (0x0210) */
1331 #define RT5682S_SAR_BUTDET_MASK			(0x1 << 15)
1332 #define RT5682S_SAR_BUTDET_EN			(0x1 << 15)
1333 #define RT5682S_SAR_BUTDET_DIS			(0x0 << 15)
1334 #define RT5682S_SAR_BUTDET_POW_MASK		(0x1 << 14)
1335 #define RT5682S_SAR_BUTDET_POW_SAV		(0x1 << 14)
1336 #define RT5682S_SAR_BUTDET_POW_NORM		(0x0 << 14)
1337 #define RT5682S_SAR_BUTDET_RST_MASK		(0x1 << 13)
1338 #define RT5682S_SAR_BUTDET_RST_NORM		(0x1 << 13)
1339 #define RT5682S_SAR_BUTDET_RST			(0x0 << 13)
1340 #define RT5682S_SAR_POW_MASK			(0x1 << 12)
1341 #define RT5682S_SAR_POW_EN			(0x1 << 12)
1342 #define RT5682S_SAR_POW_DIS			(0x0 << 12)
1343 #define RT5682S_SAR_RST_MASK			(0x1 << 11)
1344 #define RT5682S_SAR_RST_NORMAL			(0x1 << 11)
1345 #define RT5682S_SAR_RST				(0x0 << 11)
1346 #define RT5682S_SAR_BYPASS_MASK			(0x1 << 10)
1347 #define RT5682S_SAR_BYPASS_EN			(0x1 << 10)
1348 #define RT5682S_SAR_BYPASS_DIS			(0x0 << 10)
1349 #define RT5682S_SAR_SEL_MB1_2_MASK		(0x3 << 8)
1350 #define RT5682S_SAR_SEL_MB1_2_SFT		8
1351 #define RT5682S_SAR_SEL_MODE_MASK		(0x1 << 7)
1352 #define RT5682S_SAR_SEL_MODE_CMP		(0x1 << 7)
1353 #define RT5682S_SAR_SEL_MODE_ADC		(0x0 << 7)
1354 #define RT5682S_SAR_SEL_MB1_2_CTL_MASK		(0x1 << 5)
1355 #define RT5682S_SAR_SEL_MB1_2_AUTO		(0x1 << 5)
1356 #define RT5682S_SAR_SEL_MB1_2_MANU		(0x0 << 5)
1357 #define RT5682S_SAR_SEL_SIGNAL_MASK		(0x1 << 4)
1358 #define RT5682S_SAR_SEL_SIGNAL_AUTO		(0x1 << 4)
1359 #define RT5682S_SAR_SEL_SIGNAL_MANU		(0x0 << 4)
1360 
1361 /* SAR ADC Inline Command Control 2 (0x0211) */
1362 #define RT5682S_SAR_ADC_PSV_MASK		(0x1 << 4)
1363 #define RT5682S_SAR_ADC_PSV_ENTRY		(0x1 << 4)
1364 
1365 
1366 /* SAR ADC Inline Command Control 13 (0x021c) */
1367 #define RT5682S_SAR_SOUR_MASK			(0x3f)
1368 #define RT5682S_SAR_SOUR_BTN			(0x3f)
1369 #define RT5682S_SAR_SOUR_TYPE			(0x0)
1370 
1371 /* Headphone Amp Detection Control 1 (0x3b00) */
1372 #define RT5682S_CP_SW_SIZE_MASK			(0x7 << 4)
1373 #define RT5682S_CP_SW_SIZE_L			(0x4 << 4)
1374 #define RT5682S_CP_SW_SIZE_M			(0x2 << 4)
1375 #define RT5682S_CP_SW_SIZE_S			(0x1 << 4)
1376 
1377 #define RT5682S_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1378 #define RT5682S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1379 		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1380 
1381 /* System Clock Source */
1382 enum {
1383 	RT5682S_SCLK_S_MCLK,
1384 	RT5682S_SCLK_S_PLL1,
1385 	RT5682S_SCLK_S_PLL2,
1386 	RT5682S_SCLK_S_RCCLK,
1387 };
1388 
1389 /* PLL Source */
1390 enum {
1391 	RT5682S_PLL_S_MCLK,
1392 	RT5682S_PLL_S_BCLK1,
1393 	RT5682S_PLL_S_BCLK2,
1394 	RT5682S_PLL_S_RCCLK,
1395 };
1396 
1397 enum {
1398 	RT5682S_PLL1,
1399 	RT5682S_PLL2,
1400 	RT5682S_PLLS,
1401 };
1402 
1403 enum {
1404 	RT5682S_AIF1,
1405 	RT5682S_AIF2,
1406 	RT5682S_AIFS
1407 };
1408 
1409 /* filter mask */
1410 enum {
1411 	RT5682S_DA_STEREO1_FILTER = 0x1,
1412 	RT5682S_AD_STEREO1_FILTER = (0x1 << 1),
1413 };
1414 
1415 enum {
1416 	RT5682S_CLK_SEL_SYS,
1417 	RT5682S_CLK_SEL_I2S1_ASRC,
1418 	RT5682S_CLK_SEL_I2S2_ASRC,
1419 };
1420 
1421 enum {
1422 	USE_PLLA,
1423 	USE_PLLB,
1424 	USE_PLLAB,
1425 };
1426 
1427 struct pll_calc_map {
1428 	unsigned int freq_in;
1429 	unsigned int freq_out;
1430 	int m;
1431 	int n;
1432 	int k;
1433 	bool m_bp;
1434 	bool k_bp;
1435 	bool byp_ps;
1436 	bool sel_ps;
1437 };
1438 
1439 enum {
1440 	RT5682S_SUPPLY_AVDD,
1441 	RT5682S_SUPPLY_MICVDD,
1442 	RT5682S_SUPPLY_DBVDD,
1443 	RT5682S_SUPPLY_LDO1_IN,
1444 	RT5682S_NUM_SUPPLIES,
1445 };
1446 
1447 struct rt5682s_priv {
1448 	struct snd_soc_component *component;
1449 	struct rt5682s_platform_data pdata;
1450 	struct gpio_desc *ldo1_en;
1451 	struct regmap *regmap;
1452 	struct snd_soc_jack *hs_jack;
1453 	struct regulator_bulk_data supplies[RT5682S_NUM_SUPPLIES];
1454 	struct delayed_work jack_detect_work;
1455 	struct delayed_work jd_check_work;
1456 	struct mutex calibrate_mutex;
1457 	struct mutex sar_mutex;
1458 	struct mutex wclk_mutex;
1459 
1460 #ifdef CONFIG_COMMON_CLK
1461 	struct clk_hw dai_clks_hw[RT5682S_DAI_NUM_CLKS];
1462 	struct clk *mclk;
1463 #endif
1464 
1465 	int sysclk;
1466 	int sysclk_src;
1467 	int lrck[RT5682S_AIFS];
1468 	int bclk[RT5682S_AIFS];
1469 	int master[RT5682S_AIFS];
1470 
1471 	int pll_src[RT5682S_PLLS];
1472 	int pll_in[RT5682S_PLLS];
1473 	int pll_out[RT5682S_PLLS];
1474 	int pll_comb;
1475 
1476 	int jack_type;
1477 	unsigned int irq;
1478 	int irq_work_delay_time;
1479 	int wclk_enabled;
1480 };
1481 
1482 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
1483 		unsigned int filter_mask, unsigned int clk_src);
1484 
1485 #endif /* __RT5682S_H__ */
1486