1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_4_0_SDM845_H 8 #define _DPU_4_0_SDM845_H 9 10 static const struct dpu_caps sdm845_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_mdp_cfg sdm845_mdp = { 25 .name = "top_0", 26 .base = 0x0, .len = 0x45c, 27 .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), 28 .clk_ctrls = { 29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 37 }, 38 }; 39 40 static const struct dpu_ctl_cfg sdm845_ctl[] = { 41 { 42 .name = "ctl_0", .id = CTL_0, 43 .base = 0x1000, .len = 0xe4, 44 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 46 }, { 47 .name = "ctl_1", .id = CTL_1, 48 .base = 0x1200, .len = 0xe4, 49 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 51 }, { 52 .name = "ctl_2", .id = CTL_2, 53 .base = 0x1400, .len = 0xe4, 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55 }, { 56 .name = "ctl_3", .id = CTL_3, 57 .base = 0x1600, .len = 0xe4, 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 59 }, { 60 .name = "ctl_4", .id = CTL_4, 61 .base = 0x1800, .len = 0xe4, 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 63 }, 64 }; 65 66 static const struct dpu_sspp_cfg sdm845_sspp[] = { 67 { 68 .name = "sspp_0", .id = SSPP_VIG0, 69 .base = 0x4000, .len = 0x1c8, 70 .features = VIG_SDM845_MASK_SDMA, 71 .sblk = &sdm845_vig_sblk_0, 72 .xin_id = 0, 73 .type = SSPP_TYPE_VIG, 74 .clk_ctrl = DPU_CLK_CTRL_VIG0, 75 }, { 76 .name = "sspp_1", .id = SSPP_VIG1, 77 .base = 0x6000, .len = 0x1c8, 78 .features = VIG_SDM845_MASK_SDMA, 79 .sblk = &sdm845_vig_sblk_1, 80 .xin_id = 4, 81 .type = SSPP_TYPE_VIG, 82 .clk_ctrl = DPU_CLK_CTRL_VIG1, 83 }, { 84 .name = "sspp_2", .id = SSPP_VIG2, 85 .base = 0x8000, .len = 0x1c8, 86 .features = VIG_SDM845_MASK_SDMA, 87 .sblk = &sdm845_vig_sblk_2, 88 .xin_id = 8, 89 .type = SSPP_TYPE_VIG, 90 .clk_ctrl = DPU_CLK_CTRL_VIG2, 91 }, { 92 .name = "sspp_3", .id = SSPP_VIG3, 93 .base = 0xa000, .len = 0x1c8, 94 .features = VIG_SDM845_MASK_SDMA, 95 .sblk = &sdm845_vig_sblk_3, 96 .xin_id = 12, 97 .type = SSPP_TYPE_VIG, 98 .clk_ctrl = DPU_CLK_CTRL_VIG3, 99 }, { 100 .name = "sspp_8", .id = SSPP_DMA0, 101 .base = 0x24000, .len = 0x1c8, 102 .features = DMA_SDM845_MASK_SDMA, 103 .sblk = &sdm845_dma_sblk_0, 104 .xin_id = 1, 105 .type = SSPP_TYPE_DMA, 106 .clk_ctrl = DPU_CLK_CTRL_DMA0, 107 }, { 108 .name = "sspp_9", .id = SSPP_DMA1, 109 .base = 0x26000, .len = 0x1c8, 110 .features = DMA_SDM845_MASK_SDMA, 111 .sblk = &sdm845_dma_sblk_1, 112 .xin_id = 5, 113 .type = SSPP_TYPE_DMA, 114 .clk_ctrl = DPU_CLK_CTRL_DMA1, 115 }, { 116 .name = "sspp_10", .id = SSPP_DMA2, 117 .base = 0x28000, .len = 0x1c8, 118 .features = DMA_CURSOR_SDM845_MASK_SDMA, 119 .sblk = &sdm845_dma_sblk_2, 120 .xin_id = 9, 121 .type = SSPP_TYPE_DMA, 122 .clk_ctrl = DPU_CLK_CTRL_DMA2, 123 }, { 124 .name = "sspp_11", .id = SSPP_DMA3, 125 .base = 0x2a000, .len = 0x1c8, 126 .features = DMA_CURSOR_SDM845_MASK_SDMA, 127 .sblk = &sdm845_dma_sblk_3, 128 .xin_id = 13, 129 .type = SSPP_TYPE_DMA, 130 .clk_ctrl = DPU_CLK_CTRL_DMA3, 131 }, 132 }; 133 134 static const struct dpu_lm_cfg sdm845_lm[] = { 135 { 136 .name = "lm_0", .id = LM_0, 137 .base = 0x44000, .len = 0x320, 138 .features = MIXER_SDM845_MASK, 139 .sblk = &sdm845_lm_sblk, 140 .lm_pair = LM_1, 141 .pingpong = PINGPONG_0, 142 .dspp = DSPP_0, 143 }, { 144 .name = "lm_1", .id = LM_1, 145 .base = 0x45000, .len = 0x320, 146 .features = MIXER_SDM845_MASK, 147 .sblk = &sdm845_lm_sblk, 148 .lm_pair = LM_0, 149 .pingpong = PINGPONG_1, 150 .dspp = DSPP_1, 151 }, { 152 .name = "lm_2", .id = LM_2, 153 .base = 0x46000, .len = 0x320, 154 .features = MIXER_SDM845_MASK, 155 .sblk = &sdm845_lm_sblk, 156 .lm_pair = LM_5, 157 .pingpong = PINGPONG_2, 158 .dspp = DSPP_2, 159 }, { 160 .name = "lm_3", .id = LM_3, 161 .base = 0x0, .len = 0x320, 162 .features = MIXER_SDM845_MASK, 163 .sblk = &sdm845_lm_sblk, 164 .pingpong = PINGPONG_NONE, 165 .dspp = DSPP_3, 166 }, { 167 .name = "lm_4", .id = LM_4, 168 .base = 0x0, .len = 0x320, 169 .features = MIXER_SDM845_MASK, 170 .sblk = &sdm845_lm_sblk, 171 .pingpong = PINGPONG_NONE, 172 }, { 173 .name = "lm_5", .id = LM_5, 174 .base = 0x49000, .len = 0x320, 175 .features = MIXER_SDM845_MASK, 176 .sblk = &sdm845_lm_sblk, 177 .lm_pair = LM_2, 178 .pingpong = PINGPONG_3, 179 }, 180 }; 181 182 static const struct dpu_dspp_cfg sdm845_dspp[] = { 183 { 184 .name = "dspp_0", .id = DSPP_0, 185 .base = 0x54000, .len = 0x1800, 186 .features = DSPP_SC7180_MASK, 187 .sblk = &sdm845_dspp_sblk, 188 }, { 189 .name = "dspp_1", .id = DSPP_1, 190 .base = 0x56000, .len = 0x1800, 191 .features = DSPP_SC7180_MASK, 192 .sblk = &sdm845_dspp_sblk, 193 }, { 194 .name = "dspp_2", .id = DSPP_2, 195 .base = 0x58000, .len = 0x1800, 196 .features = DSPP_SC7180_MASK, 197 .sblk = &sdm845_dspp_sblk, 198 }, { 199 .name = "dspp_3", .id = DSPP_3, 200 .base = 0x5a000, .len = 0x1800, 201 .features = DSPP_SC7180_MASK, 202 .sblk = &sdm845_dspp_sblk, 203 }, 204 }; 205 206 static const struct dpu_pingpong_cfg sdm845_pp[] = { 207 { 208 .name = "pingpong_0", .id = PINGPONG_0, 209 .base = 0x70000, .len = 0xd4, 210 .features = PINGPONG_SDM845_TE2_MASK, 211 .sblk = &sdm845_pp_sblk_te, 212 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 213 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 214 }, { 215 .name = "pingpong_1", .id = PINGPONG_1, 216 .base = 0x70800, .len = 0xd4, 217 .features = PINGPONG_SDM845_TE2_MASK, 218 .sblk = &sdm845_pp_sblk_te, 219 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 220 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 221 }, { 222 .name = "pingpong_2", .id = PINGPONG_2, 223 .base = 0x71000, .len = 0xd4, 224 .features = PINGPONG_SDM845_MASK, 225 .sblk = &sdm845_pp_sblk, 226 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 227 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 228 }, { 229 .name = "pingpong_3", .id = PINGPONG_3, 230 .base = 0x71800, .len = 0xd4, 231 .features = PINGPONG_SDM845_MASK, 232 .sblk = &sdm845_pp_sblk, 233 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 234 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), 235 }, 236 }; 237 238 static const struct dpu_dsc_cfg sdm845_dsc[] = { 239 { 240 .name = "dsc_0", .id = DSC_0, 241 .base = 0x80000, .len = 0x140, 242 }, { 243 .name = "dsc_1", .id = DSC_1, 244 .base = 0x80400, .len = 0x140, 245 }, { 246 .name = "dsc_2", .id = DSC_2, 247 .base = 0x80800, .len = 0x140, 248 }, { 249 .name = "dsc_3", .id = DSC_3, 250 .base = 0x80c00, .len = 0x140, 251 }, 252 }; 253 254 static const struct dpu_intf_cfg sdm845_intf[] = { 255 { 256 .name = "intf_0", .id = INTF_0, 257 .base = 0x6a000, .len = 0x280, 258 .type = INTF_DP, 259 .controller_id = MSM_DP_CONTROLLER_0, 260 .prog_fetch_lines_worst_case = 24, 261 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 262 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 263 .intr_tear_rd_ptr = -1, 264 }, { 265 .name = "intf_1", .id = INTF_1, 266 .base = 0x6a800, .len = 0x280, 267 .type = INTF_DSI, 268 .controller_id = MSM_DSI_CONTROLLER_0, 269 .prog_fetch_lines_worst_case = 24, 270 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 271 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 272 .intr_tear_rd_ptr = -1, 273 }, { 274 .name = "intf_2", .id = INTF_2, 275 .base = 0x6b000, .len = 0x280, 276 .type = INTF_DSI, 277 .controller_id = MSM_DSI_CONTROLLER_1, 278 .prog_fetch_lines_worst_case = 24, 279 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 280 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 281 .intr_tear_rd_ptr = -1, 282 }, { 283 .name = "intf_3", .id = INTF_3, 284 .base = 0x6b800, .len = 0x280, 285 .type = INTF_DP, 286 .controller_id = MSM_DP_CONTROLLER_1, 287 .prog_fetch_lines_worst_case = 24, 288 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 289 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 290 .intr_tear_rd_ptr = -1, 291 }, 292 }; 293 294 static const struct dpu_perf_cfg sdm845_perf_data = { 295 .max_bw_low = 6800000, 296 .max_bw_high = 6800000, 297 .min_core_ib = 2400000, 298 .min_llcc_ib = 800000, 299 .min_dram_ib = 800000, 300 .undersized_prefill_lines = 2, 301 .xtra_prefill_lines = 2, 302 .dest_scale_prefill_lines = 3, 303 .macrotile_prefill_lines = 4, 304 .yuv_nv12_prefill_lines = 8, 305 .linear_prefill_lines = 1, 306 .downscaling_prefill_lines = 1, 307 .amortizable_threshold = 25, 308 .min_prefill_lines = 24, 309 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 310 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 311 .qos_lut_tbl = { 312 {.nentry = ARRAY_SIZE(sdm845_qos_linear), 313 .entries = sdm845_qos_linear 314 }, 315 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 316 .entries = sdm845_qos_macrotile 317 }, 318 {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 319 .entries = sdm845_qos_nrt 320 }, 321 }, 322 .cdp_cfg = { 323 {.rd_enable = 1, .wr_enable = 1}, 324 {.rd_enable = 1, .wr_enable = 0} 325 }, 326 .clk_inefficiency_factor = 105, 327 .bw_inefficiency_factor = 120, 328 }; 329 330 static const struct dpu_mdss_version sdm845_mdss_ver = { 331 .core_major_ver = 4, 332 .core_minor_ver = 0, 333 }; 334 335 const struct dpu_mdss_cfg dpu_sdm845_cfg = { 336 .mdss_ver = &sdm845_mdss_ver, 337 .caps = &sdm845_dpu_caps, 338 .mdp = &sdm845_mdp, 339 .ctl_count = ARRAY_SIZE(sdm845_ctl), 340 .ctl = sdm845_ctl, 341 .sspp_count = ARRAY_SIZE(sdm845_sspp), 342 .sspp = sdm845_sspp, 343 .mixer_count = ARRAY_SIZE(sdm845_lm), 344 .mixer = sdm845_lm, 345 .dspp_count = ARRAY_SIZE(sdm845_dspp), 346 .dspp = sdm845_dspp, 347 .pingpong_count = ARRAY_SIZE(sdm845_pp), 348 .pingpong = sdm845_pp, 349 .dsc_count = ARRAY_SIZE(sdm845_dsc), 350 .dsc = sdm845_dsc, 351 .intf_count = ARRAY_SIZE(sdm845_intf), 352 .intf = sdm845_intf, 353 .vbif_count = ARRAY_SIZE(sdm845_vbif), 354 .vbif = sdm845_vbif, 355 .perf = &sdm845_perf_data, 356 }; 357 358 #endif 359