1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
4 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
5 */
6
7 #include <linux/pci.h>
8 #include <linux/module.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13
14 #include <linux/mmc/host.h>
15
16 #define DRV_NAME "via_sdmmc"
17
18 #define PCI_DEVICE_ID_VIA_9530 0x9530
19
20 #define VIA_CRDR_SDC_OFF 0x200
21 #define VIA_CRDR_DDMA_OFF 0x400
22 #define VIA_CRDR_PCICTRL_OFF 0x600
23
24 #define VIA_CRDR_MIN_CLOCK 375000
25 #define VIA_CRDR_MAX_CLOCK 48000000
26
27 /*
28 * PCI registers
29 */
30
31 #define VIA_CRDR_PCI_WORK_MODE 0x40
32 #define VIA_CRDR_PCI_DBG_MODE 0x41
33
34 /*
35 * SDC MMIO Registers
36 */
37
38 #define VIA_CRDR_SDCTRL 0x0
39 #define VIA_CRDR_SDCTRL_START 0x01
40 #define VIA_CRDR_SDCTRL_WRITE 0x04
41 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
42 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
43 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
44 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
45 #define VIA_CRDR_SDCTRL_STOP 0x70
46
47 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
48 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
49 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
50 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
51 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
52
53 #define VIA_CRDR_SDCARG 0x4
54
55 #define VIA_CRDR_SDBUSMODE 0x8
56 #define VIA_CRDR_SDMODE_4BIT 0x02
57 #define VIA_CRDR_SDMODE_CLK_ON 0x40
58
59 #define VIA_CRDR_SDBLKLEN 0xc
60 /*
61 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
62 * Bit 11 - Bit 13 : Reserved.
63 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
64 * INTEN : Enable SD host interrupt.
65 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
66 */
67 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
68 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
69 #define VIA_CRDR_MAX_BLOCK_COUNT 65536
70 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
71
72 #define VIA_CRDR_SDRESP0 0x10
73 #define VIA_CRDR_SDRESP1 0x14
74 #define VIA_CRDR_SDRESP2 0x18
75 #define VIA_CRDR_SDRESP3 0x1c
76
77 #define VIA_CRDR_SDCURBLKCNT 0x20
78
79 #define VIA_CRDR_SDINTMASK 0x24
80 /*
81 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
82 * BDDIE : Block Data transfer Done Interrupt Enable
83 * CIRIE : Card Insertion or Removal Interrupt Enable
84 * CRDIE : Command-Response transfer Done Interrupt Enable
85 * CRTOIE : Command-Response response TimeOut Interrupt Enable
86 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
87 * DTIE : Data access Timeout Interrupt Enable
88 * SCIE : reSponse CRC error Interrupt Enable
89 * RCIE : Read data CRC error Interrupt Enable
90 * WCIE : Write data CRC error Interrupt Enable
91 */
92 #define VIA_CRDR_SDINTMASK_MBDIE 0x10
93 #define VIA_CRDR_SDINTMASK_BDDIE 0x20
94 #define VIA_CRDR_SDINTMASK_CIRIE 0x80
95 #define VIA_CRDR_SDINTMASK_CRDIE 0x200
96 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
97 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
98 #define VIA_CRDR_SDINTMASK_DTIE 0x1000
99 #define VIA_CRDR_SDINTMASK_SCIE 0x2000
100 #define VIA_CRDR_SDINTMASK_RCIE 0x4000
101 #define VIA_CRDR_SDINTMASK_WCIE 0x8000
102
103 #define VIA_CRDR_SDACTIVE_INTMASK \
104 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
105 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
106 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
107 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
108
109 #define VIA_CRDR_SDSTATUS 0x28
110 /*
111 * CECC : Reserved
112 * WP : SD card Write Protect status
113 * SLOTD : Reserved
114 * SLOTG : SD SLOT status(Gpi pin status)
115 * MBD : Multiple Blocks transfer Done interrupt status
116 * BDD : Block Data transfer Done interrupt status
117 * CD : Reserved
118 * CIR : Card Insertion or Removal interrupt detected on GPI pin
119 * IO : Reserved
120 * CRD : Command-Response transfer Done interrupt status
121 * CRTO : Command-Response response TimeOut interrupt status
122 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
123 * DT : Data access Timeout interrupt status
124 * SC : reSponse CRC error interrupt status
125 * RC : Read data CRC error interrupt status
126 * WC : Write data CRC error interrupt status
127 */
128 #define VIA_CRDR_SDSTS_CECC 0x01
129 #define VIA_CRDR_SDSTS_WP 0x02
130 #define VIA_CRDR_SDSTS_SLOTD 0x04
131 #define VIA_CRDR_SDSTS_SLOTG 0x08
132 #define VIA_CRDR_SDSTS_MBD 0x10
133 #define VIA_CRDR_SDSTS_BDD 0x20
134 #define VIA_CRDR_SDSTS_CD 0x40
135 #define VIA_CRDR_SDSTS_CIR 0x80
136 #define VIA_CRDR_SDSTS_IO 0x100
137 #define VIA_CRDR_SDSTS_CRD 0x200
138 #define VIA_CRDR_SDSTS_CRTO 0x400
139 #define VIA_CRDR_SDSTS_ASCRDIE 0x800
140 #define VIA_CRDR_SDSTS_DT 0x1000
141 #define VIA_CRDR_SDSTS_SC 0x2000
142 #define VIA_CRDR_SDSTS_RC 0x4000
143 #define VIA_CRDR_SDSTS_WC 0x8000
144
145 #define VIA_CRDR_SDSTS_IGN_MASK\
146 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
147 #define VIA_CRDR_SDSTS_INT_MASK \
148 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
149 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
150 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
151 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
152 #define VIA_CRDR_SDSTS_W1C_MASK \
153 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
154 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
155 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
156 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
157 #define VIA_CRDR_SDSTS_CMD_MASK \
158 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
159 #define VIA_CRDR_SDSTS_DATA_MASK\
160 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
161 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
162
163 #define VIA_CRDR_SDSTATUS2 0x2a
164 /*
165 * CFE : Enable SD host automatic Clock FReezing
166 */
167 #define VIA_CRDR_SDSTS_CFE 0x80
168
169 #define VIA_CRDR_SDRSPTMO 0x2C
170
171 #define VIA_CRDR_SDCLKSEL 0x30
172
173 #define VIA_CRDR_SDEXTCTRL 0x34
174 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
175 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
176 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
177 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
178 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
179 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
180 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
181 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
182 /* 0x38-0xFF reserved */
183
184 /*
185 * Data DMA Control Registers
186 */
187
188 #define VIA_CRDR_DMABASEADD 0x0
189 #define VIA_CRDR_DMACOUNTER 0x4
190
191 #define VIA_CRDR_DMACTRL 0x8
192 /*
193 * DIR :Transaction Direction
194 * 0 : From card to memory
195 * 1 : From memory to card
196 */
197 #define VIA_CRDR_DMACTRL_DIR 0x100
198 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
199 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
200
201 #define VIA_CRDR_DMASTS 0xc
202
203 #define VIA_CRDR_DMASTART 0x10
204 /*0x14-0xFF reserved*/
205
206 /*
207 * PCI Control Registers
208 */
209
210 /*0x0 - 0x1 reserved*/
211 #define VIA_CRDR_PCICLKGATT 0x2
212 /*
213 * SFTRST :
214 * 0 : Soft reset all the controller and it will be de-asserted automatically
215 * 1 : Soft reset is de-asserted
216 */
217 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
218 /*
219 * 3V3 : Pad power select
220 * 0 : 1.8V
221 * 1 : 3.3V
222 * NOTE : No mater what the actual value should be, this bit always
223 * read as 0. This is a hardware bug.
224 */
225 #define VIA_CRDR_PCICLKGATT_3V3 0x10
226 /*
227 * PAD_PWRON : Pad Power on/off select
228 * 0 : Power off
229 * 1 : Power on
230 * NOTE : No mater what the actual value should be, this bit always
231 * read as 0. This is a hardware bug.
232 */
233 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
234
235 #define VIA_CRDR_PCISDCCLK 0x5
236
237 #define VIA_CRDR_PCIDMACLK 0x7
238 #define VIA_CRDR_PCIDMACLK_SDC 0x2
239
240 #define VIA_CRDR_PCIINTCTRL 0x8
241 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
242
243 #define VIA_CRDR_PCIINTSTATUS 0x9
244 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
245
246 #define VIA_CRDR_PCITMOCTRL 0xa
247 #define VIA_CRDR_PCITMOCTRL_NO 0x0
248 #define VIA_CRDR_PCITMOCTRL_32US 0x1
249 #define VIA_CRDR_PCITMOCTRL_256US 0x2
250 #define VIA_CRDR_PCITMOCTRL_1024US 0x3
251 #define VIA_CRDR_PCITMOCTRL_256MS 0x4
252 #define VIA_CRDR_PCITMOCTRL_512MS 0x5
253 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
254
255 /*0xB-0xFF reserved*/
256
257 enum PCI_HOST_CLK_CONTROL {
258 PCI_CLK_375K = 0x03,
259 PCI_CLK_8M = 0x04,
260 PCI_CLK_12M = 0x00,
261 PCI_CLK_16M = 0x05,
262 PCI_CLK_24M = 0x01,
263 PCI_CLK_33M = 0x06,
264 PCI_CLK_48M = 0x02
265 };
266
267 struct sdhcreg {
268 u32 sdcontrol_reg;
269 u32 sdcmdarg_reg;
270 u32 sdbusmode_reg;
271 u32 sdblklen_reg;
272 u32 sdresp_reg[4];
273 u32 sdcurblkcnt_reg;
274 u32 sdintmask_reg;
275 u32 sdstatus_reg;
276 u32 sdrsptmo_reg;
277 u32 sdclksel_reg;
278 u32 sdextctrl_reg;
279 };
280
281 struct pcictrlreg {
282 u8 reserve[2];
283 u8 pciclkgat_reg;
284 u8 pcinfcclk_reg;
285 u8 pcimscclk_reg;
286 u8 pcisdclk_reg;
287 u8 pcicaclk_reg;
288 u8 pcidmaclk_reg;
289 u8 pciintctrl_reg;
290 u8 pciintstatus_reg;
291 u8 pcitmoctrl_reg;
292 u8 Resv;
293 };
294
295 struct via_crdr_mmc_host {
296 struct mmc_host *mmc;
297 struct mmc_request *mrq;
298 struct mmc_command *cmd;
299 struct mmc_data *data;
300
301 void __iomem *mmiobase;
302 void __iomem *sdhc_mmiobase;
303 void __iomem *ddma_mmiobase;
304 void __iomem *pcictrl_mmiobase;
305
306 struct pcictrlreg pm_pcictrl_reg;
307 struct sdhcreg pm_sdhc_reg;
308
309 struct work_struct carddet_work;
310 struct tasklet_struct finish_tasklet;
311
312 struct timer_list timer;
313 spinlock_t lock;
314 u8 power;
315 int reject;
316 unsigned int quirks;
317 };
318
319 /* some devices need a very long delay for power to stabilize */
320 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
321
322 #define VIA_CMD_TIMEOUT_MS 1000
323
324 static const struct pci_device_id via_ids[] = {
325 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
327 {0,}
328 };
329
330 MODULE_DEVICE_TABLE(pci, via_ids);
331
via_print_sdchc(struct via_crdr_mmc_host * host)332 static void via_print_sdchc(struct via_crdr_mmc_host *host)
333 {
334 void __iomem *addrbase = host->sdhc_mmiobase;
335
336 pr_debug("SDC MMIO Registers:\n");
337 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
338 readl(addrbase + VIA_CRDR_SDCTRL),
339 readl(addrbase + VIA_CRDR_SDCARG),
340 readl(addrbase + VIA_CRDR_SDBUSMODE));
341 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
342 readl(addrbase + VIA_CRDR_SDBLKLEN),
343 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
344 readl(addrbase + VIA_CRDR_SDINTMASK));
345 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
346 readl(addrbase + VIA_CRDR_SDSTATUS),
347 readl(addrbase + VIA_CRDR_SDCLKSEL),
348 readl(addrbase + VIA_CRDR_SDEXTCTRL));
349 }
350
via_print_pcictrl(struct via_crdr_mmc_host * host)351 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
352 {
353 void __iomem *addrbase = host->pcictrl_mmiobase;
354
355 pr_debug("PCI Control Registers:\n");
356 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
357 readb(addrbase + VIA_CRDR_PCICLKGATT),
358 readb(addrbase + VIA_CRDR_PCISDCCLK),
359 readb(addrbase + VIA_CRDR_PCIDMACLK));
360 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
361 readb(addrbase + VIA_CRDR_PCIINTCTRL),
362 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
363 }
364
via_save_pcictrlreg(struct via_crdr_mmc_host * host)365 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
366 {
367 struct pcictrlreg *pm_pcictrl_reg;
368 void __iomem *addrbase;
369
370 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
371 addrbase = host->pcictrl_mmiobase;
372
373 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
374 pm_pcictrl_reg->pciclkgat_reg |=
375 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
376 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
377 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
378 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
379 pm_pcictrl_reg->pciintstatus_reg =
380 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
381 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
382 }
383
via_restore_pcictrlreg(struct via_crdr_mmc_host * host)384 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
385 {
386 struct pcictrlreg *pm_pcictrl_reg;
387 void __iomem *addrbase;
388
389 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
390 addrbase = host->pcictrl_mmiobase;
391
392 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
393 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
394 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
395 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
396 writeb(pm_pcictrl_reg->pciintstatus_reg,
397 addrbase + VIA_CRDR_PCIINTSTATUS);
398 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
399 }
400
via_save_sdcreg(struct via_crdr_mmc_host * host)401 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
402 {
403 struct sdhcreg *pm_sdhc_reg;
404 void __iomem *addrbase;
405
406 pm_sdhc_reg = &(host->pm_sdhc_reg);
407 addrbase = host->sdhc_mmiobase;
408
409 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
410 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
411 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
412 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
413 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
414 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
415 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
416 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
417 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
418 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
419 }
420
via_restore_sdcreg(struct via_crdr_mmc_host * host)421 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
422 {
423 struct sdhcreg *pm_sdhc_reg;
424 void __iomem *addrbase;
425
426 pm_sdhc_reg = &(host->pm_sdhc_reg);
427 addrbase = host->sdhc_mmiobase;
428
429 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
430 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
431 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
432 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
433 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
434 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
435 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
436 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
437 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
438 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
439 }
440
via_pwron_sleep(struct via_crdr_mmc_host * sdhost)441 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
442 {
443 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
444 msleep(300);
445 else
446 msleep(3);
447 }
448
via_set_ddma(struct via_crdr_mmc_host * host,dma_addr_t dmaaddr,u32 count,int dir,int enirq)449 static void via_set_ddma(struct via_crdr_mmc_host *host,
450 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
451 {
452 void __iomem *addrbase;
453 u32 ctrl_data = 0;
454
455 if (enirq)
456 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
457
458 if (dir)
459 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
460
461 addrbase = host->ddma_mmiobase;
462
463 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
464 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
465 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
466 writel(0x01, addrbase + VIA_CRDR_DMASTART);
467
468 /* It seems that our DMA can not work normally with 375kHz clock */
469 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
470 addrbase = host->pcictrl_mmiobase;
471 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
472 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
473 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
474 }
475 }
476
via_sdc_preparedata(struct via_crdr_mmc_host * host,struct mmc_data * data)477 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
478 struct mmc_data *data)
479 {
480 void __iomem *addrbase;
481 u32 blk_reg;
482 int count;
483
484 WARN_ON(host->data);
485
486 /* Sanity checks */
487 BUG_ON(data->blksz > host->mmc->max_blk_size);
488 BUG_ON(data->blocks > host->mmc->max_blk_count);
489
490 host->data = data;
491
492 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
493 ((data->flags & MMC_DATA_READ) ?
494 DMA_FROM_DEVICE : DMA_TO_DEVICE));
495 BUG_ON(count != 1);
496
497 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
498 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
499
500 addrbase = host->sdhc_mmiobase;
501
502 blk_reg = data->blksz - 1;
503 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
504 blk_reg |= (data->blocks) << 16;
505
506 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
507 }
508
via_sdc_get_response(struct via_crdr_mmc_host * host,struct mmc_command * cmd)509 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
510 struct mmc_command *cmd)
511 {
512 void __iomem *addrbase = host->sdhc_mmiobase;
513 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
514 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
515 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
516 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
517
518 if (cmd->flags & MMC_RSP_136) {
519 cmd->resp[0] = ((u8) (dwdata1)) |
520 (((u8) (dwdata0 >> 24)) << 8) |
521 (((u8) (dwdata0 >> 16)) << 16) |
522 (((u8) (dwdata0 >> 8)) << 24);
523
524 cmd->resp[1] = ((u8) (dwdata2)) |
525 (((u8) (dwdata1 >> 24)) << 8) |
526 (((u8) (dwdata1 >> 16)) << 16) |
527 (((u8) (dwdata1 >> 8)) << 24);
528
529 cmd->resp[2] = ((u8) (dwdata3)) |
530 (((u8) (dwdata2 >> 24)) << 8) |
531 (((u8) (dwdata2 >> 16)) << 16) |
532 (((u8) (dwdata2 >> 8)) << 24);
533
534 cmd->resp[3] = 0xff |
535 ((((u8) (dwdata3 >> 24))) << 8) |
536 (((u8) (dwdata3 >> 16)) << 16) |
537 (((u8) (dwdata3 >> 8)) << 24);
538 } else {
539 dwdata0 >>= 8;
540 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
541 (((dwdata0 >> 8) & 0xff) << 16) |
542 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
543
544 dwdata1 >>= 8;
545 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
546 (((dwdata1 >> 8) & 0xff) << 16) |
547 (((dwdata1 >> 16) & 0xff) << 8);
548 }
549 }
550
via_sdc_send_command(struct via_crdr_mmc_host * host,struct mmc_command * cmd)551 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
552 struct mmc_command *cmd)
553 {
554 void __iomem *addrbase;
555 struct mmc_data *data;
556 unsigned int timeout_ms;
557 u32 cmdctrl = 0;
558
559 WARN_ON(host->cmd);
560
561 data = cmd->data;
562 host->cmd = cmd;
563
564 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : VIA_CMD_TIMEOUT_MS;
565 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
566
567 /*Command index*/
568 cmdctrl = cmd->opcode << 8;
569
570 /*Response type*/
571 switch (mmc_resp_type(cmd)) {
572 case MMC_RSP_NONE:
573 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
574 break;
575 case MMC_RSP_R1:
576 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
577 break;
578 case MMC_RSP_R1B:
579 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
580 break;
581 case MMC_RSP_R2:
582 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
583 break;
584 case MMC_RSP_R3:
585 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
586 break;
587 default:
588 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
589 break;
590 }
591
592 if (!(cmd->data))
593 goto nodata;
594
595 via_sdc_preparedata(host, data);
596
597 /*Command control*/
598 if (data->blocks > 1) {
599 if (data->flags & MMC_DATA_WRITE) {
600 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
601 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
602 } else {
603 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
604 }
605 } else {
606 if (data->flags & MMC_DATA_WRITE) {
607 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
608 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
609 } else {
610 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
611 }
612 }
613
614 nodata:
615 if (cmd == host->mrq->stop)
616 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
617
618 cmdctrl |= VIA_CRDR_SDCTRL_START;
619
620 addrbase = host->sdhc_mmiobase;
621 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
622 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
623 }
624
via_sdc_finish_data(struct via_crdr_mmc_host * host)625 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
626 {
627 struct mmc_data *data;
628
629 BUG_ON(!host->data);
630
631 data = host->data;
632 host->data = NULL;
633
634 if (data->error)
635 data->bytes_xfered = 0;
636 else
637 data->bytes_xfered = data->blocks * data->blksz;
638
639 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
640 ((data->flags & MMC_DATA_READ) ?
641 DMA_FROM_DEVICE : DMA_TO_DEVICE));
642
643 if (data->stop)
644 via_sdc_send_command(host, data->stop);
645 else
646 tasklet_schedule(&host->finish_tasklet);
647 }
648
via_sdc_finish_command(struct via_crdr_mmc_host * host)649 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
650 {
651 via_sdc_get_response(host, host->cmd);
652
653 host->cmd->error = 0;
654
655 if (!host->cmd->data)
656 tasklet_schedule(&host->finish_tasklet);
657
658 host->cmd = NULL;
659 }
660
via_sdc_request(struct mmc_host * mmc,struct mmc_request * mrq)661 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
662 {
663 void __iomem *addrbase;
664 struct via_crdr_mmc_host *host;
665 unsigned long flags;
666 u16 status;
667
668 host = mmc_priv(mmc);
669
670 spin_lock_irqsave(&host->lock, flags);
671
672 addrbase = host->pcictrl_mmiobase;
673 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
674
675 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
676 status &= VIA_CRDR_SDSTS_W1C_MASK;
677 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
678
679 WARN_ON(host->mrq != NULL);
680 host->mrq = mrq;
681
682 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
683 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
684 host->mrq->cmd->error = -ENOMEDIUM;
685 tasklet_schedule(&host->finish_tasklet);
686 } else {
687 via_sdc_send_command(host, mrq->cmd);
688 }
689
690 spin_unlock_irqrestore(&host->lock, flags);
691 }
692
via_sdc_set_power(struct via_crdr_mmc_host * host,unsigned short power,unsigned int on)693 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
694 unsigned short power, unsigned int on)
695 {
696 unsigned long flags;
697 u8 gatt;
698
699 spin_lock_irqsave(&host->lock, flags);
700
701 host->power = (1 << power);
702
703 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
704 if (host->power == MMC_VDD_165_195)
705 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
706 else
707 gatt |= VIA_CRDR_PCICLKGATT_3V3;
708 if (on)
709 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
710 else
711 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
712 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
713
714 spin_unlock_irqrestore(&host->lock, flags);
715
716 via_pwron_sleep(host);
717 }
718
via_sdc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)719 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
720 {
721 struct via_crdr_mmc_host *host;
722 unsigned long flags;
723 void __iomem *addrbase;
724 u32 org_data, sdextctrl;
725 u8 clock;
726
727 host = mmc_priv(mmc);
728
729 spin_lock_irqsave(&host->lock, flags);
730
731 addrbase = host->sdhc_mmiobase;
732 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
733 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
734
735 if (ios->bus_width == MMC_BUS_WIDTH_1)
736 org_data &= ~VIA_CRDR_SDMODE_4BIT;
737 else
738 org_data |= VIA_CRDR_SDMODE_4BIT;
739
740 if (ios->power_mode == MMC_POWER_OFF)
741 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
742 else
743 org_data |= VIA_CRDR_SDMODE_CLK_ON;
744
745 if (ios->timing == MMC_TIMING_SD_HS)
746 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
747 else
748 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
749
750 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
751 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
752
753 if (ios->clock >= 48000000)
754 clock = PCI_CLK_48M;
755 else if (ios->clock >= 33000000)
756 clock = PCI_CLK_33M;
757 else if (ios->clock >= 24000000)
758 clock = PCI_CLK_24M;
759 else if (ios->clock >= 16000000)
760 clock = PCI_CLK_16M;
761 else if (ios->clock >= 12000000)
762 clock = PCI_CLK_12M;
763 else if (ios->clock >= 8000000)
764 clock = PCI_CLK_8M;
765 else
766 clock = PCI_CLK_375K;
767
768 addrbase = host->pcictrl_mmiobase;
769 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
770 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
771
772 spin_unlock_irqrestore(&host->lock, flags);
773
774 if (ios->power_mode != MMC_POWER_OFF)
775 via_sdc_set_power(host, ios->vdd, 1);
776 else
777 via_sdc_set_power(host, ios->vdd, 0);
778 }
779
via_sdc_get_ro(struct mmc_host * mmc)780 static int via_sdc_get_ro(struct mmc_host *mmc)
781 {
782 struct via_crdr_mmc_host *host;
783 unsigned long flags;
784 u16 status;
785
786 host = mmc_priv(mmc);
787
788 spin_lock_irqsave(&host->lock, flags);
789
790 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
791
792 spin_unlock_irqrestore(&host->lock, flags);
793
794 return !(status & VIA_CRDR_SDSTS_WP);
795 }
796
797 static const struct mmc_host_ops via_sdc_ops = {
798 .request = via_sdc_request,
799 .set_ios = via_sdc_set_ios,
800 .get_ro = via_sdc_get_ro,
801 };
802
via_reset_pcictrl(struct via_crdr_mmc_host * host)803 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
804 {
805 unsigned long flags;
806 u8 gatt;
807
808 spin_lock_irqsave(&host->lock, flags);
809
810 via_save_pcictrlreg(host);
811 via_save_sdcreg(host);
812
813 spin_unlock_irqrestore(&host->lock, flags);
814
815 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
816 if (host->power == MMC_VDD_165_195)
817 gatt &= VIA_CRDR_PCICLKGATT_3V3;
818 else
819 gatt |= VIA_CRDR_PCICLKGATT_3V3;
820 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
821 via_pwron_sleep(host);
822 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
823 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
824 msleep(3);
825
826 spin_lock_irqsave(&host->lock, flags);
827
828 via_restore_pcictrlreg(host);
829 via_restore_sdcreg(host);
830
831 spin_unlock_irqrestore(&host->lock, flags);
832 }
833
via_sdc_cmd_isr(struct via_crdr_mmc_host * host,u16 intmask)834 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
835 {
836 BUG_ON(intmask == 0);
837
838 if (!host->cmd) {
839 pr_err("%s: Got command interrupt 0x%x even "
840 "though no command operation was in progress.\n",
841 mmc_hostname(host->mmc), intmask);
842 return;
843 }
844
845 if (intmask & VIA_CRDR_SDSTS_CRTO)
846 host->cmd->error = -ETIMEDOUT;
847 else if (intmask & VIA_CRDR_SDSTS_SC)
848 host->cmd->error = -EILSEQ;
849
850 if (host->cmd->error)
851 tasklet_schedule(&host->finish_tasklet);
852 else if (intmask & VIA_CRDR_SDSTS_CRD)
853 via_sdc_finish_command(host);
854 }
855
via_sdc_data_isr(struct via_crdr_mmc_host * host,u16 intmask)856 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
857 {
858 BUG_ON(intmask == 0);
859
860 if (!host->data)
861 return;
862
863 if (intmask & VIA_CRDR_SDSTS_DT)
864 host->data->error = -ETIMEDOUT;
865 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
866 host->data->error = -EILSEQ;
867
868 via_sdc_finish_data(host);
869 }
870
via_sdc_isr(int irq,void * dev_id)871 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
872 {
873 struct via_crdr_mmc_host *sdhost = dev_id;
874 void __iomem *addrbase;
875 u8 pci_status;
876 u16 sd_status;
877 irqreturn_t result;
878
879 if (!sdhost)
880 return IRQ_NONE;
881
882 spin_lock(&sdhost->lock);
883
884 addrbase = sdhost->pcictrl_mmiobase;
885 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
886 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
887 result = IRQ_NONE;
888 goto out;
889 }
890
891 addrbase = sdhost->sdhc_mmiobase;
892 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
893 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
894 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
895 if (!sd_status) {
896 result = IRQ_NONE;
897 goto out;
898 }
899
900 if (sd_status & VIA_CRDR_SDSTS_CIR) {
901 writew(sd_status & VIA_CRDR_SDSTS_CIR,
902 addrbase + VIA_CRDR_SDSTATUS);
903
904 schedule_work(&sdhost->carddet_work);
905 }
906
907 sd_status &= ~VIA_CRDR_SDSTS_CIR;
908 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
909 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
910 addrbase + VIA_CRDR_SDSTATUS);
911 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
912 }
913 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
914 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
915 addrbase + VIA_CRDR_SDSTATUS);
916 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
917 }
918
919 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
920 if (sd_status) {
921 pr_err("%s: Unexpected interrupt 0x%x\n",
922 mmc_hostname(sdhost->mmc), sd_status);
923 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
924 }
925
926 result = IRQ_HANDLED;
927
928 out:
929 spin_unlock(&sdhost->lock);
930
931 return result;
932 }
933
via_sdc_timeout(struct timer_list * t)934 static void via_sdc_timeout(struct timer_list *t)
935 {
936 struct via_crdr_mmc_host *sdhost;
937 unsigned long flags;
938
939 sdhost = from_timer(sdhost, t, timer);
940
941 spin_lock_irqsave(&sdhost->lock, flags);
942
943 if (sdhost->mrq) {
944 pr_err("%s: Timeout waiting for hardware interrupt."
945 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
946 sdhost->mrq->cmd->opcode);
947
948 if (sdhost->data) {
949 writel(VIA_CRDR_DMACTRL_SFTRST,
950 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
951 sdhost->data->error = -ETIMEDOUT;
952 via_sdc_finish_data(sdhost);
953 } else {
954 if (sdhost->cmd)
955 sdhost->cmd->error = -ETIMEDOUT;
956 else
957 sdhost->mrq->cmd->error = -ETIMEDOUT;
958 tasklet_schedule(&sdhost->finish_tasklet);
959 }
960 }
961
962 spin_unlock_irqrestore(&sdhost->lock, flags);
963 }
964
via_sdc_tasklet_finish(struct tasklet_struct * t)965 static void via_sdc_tasklet_finish(struct tasklet_struct *t)
966 {
967 struct via_crdr_mmc_host *host = from_tasklet(host, t, finish_tasklet);
968 unsigned long flags;
969 struct mmc_request *mrq;
970
971 spin_lock_irqsave(&host->lock, flags);
972
973 del_timer(&host->timer);
974 mrq = host->mrq;
975 host->mrq = NULL;
976 host->cmd = NULL;
977 host->data = NULL;
978
979 spin_unlock_irqrestore(&host->lock, flags);
980
981 mmc_request_done(host->mmc, mrq);
982 }
983
via_sdc_card_detect(struct work_struct * work)984 static void via_sdc_card_detect(struct work_struct *work)
985 {
986 struct via_crdr_mmc_host *host;
987 void __iomem *addrbase;
988 unsigned long flags;
989 u16 status;
990
991 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
992
993 addrbase = host->ddma_mmiobase;
994 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
995
996 spin_lock_irqsave(&host->lock, flags);
997
998 addrbase = host->pcictrl_mmiobase;
999 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1000
1001 addrbase = host->sdhc_mmiobase;
1002 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1003 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1004 if (host->mrq) {
1005 pr_err("%s: Card removed during transfer!\n",
1006 mmc_hostname(host->mmc));
1007 host->mrq->cmd->error = -ENOMEDIUM;
1008 tasklet_schedule(&host->finish_tasklet);
1009 }
1010
1011 spin_unlock_irqrestore(&host->lock, flags);
1012
1013 via_reset_pcictrl(host);
1014
1015 spin_lock_irqsave(&host->lock, flags);
1016 }
1017
1018 spin_unlock_irqrestore(&host->lock, flags);
1019
1020 via_print_pcictrl(host);
1021 via_print_sdchc(host);
1022
1023 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1024 }
1025
via_init_mmc_host(struct via_crdr_mmc_host * host)1026 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1027 {
1028 struct mmc_host *mmc = host->mmc;
1029 void __iomem *addrbase;
1030 u32 lenreg;
1031 u32 status;
1032
1033 timer_setup(&host->timer, via_sdc_timeout, 0);
1034
1035 spin_lock_init(&host->lock);
1036
1037 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1038 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1039 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1040 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1041 mmc->ops = &via_sdc_ops;
1042
1043 /*Hardware cannot do scatter lists*/
1044 mmc->max_segs = 1;
1045
1046 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1047 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1048
1049 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1050 mmc->max_req_size = mmc->max_seg_size;
1051
1052 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1053
1054 tasklet_setup(&host->finish_tasklet, via_sdc_tasklet_finish);
1055
1056 addrbase = host->sdhc_mmiobase;
1057 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1058 msleep(1);
1059
1060 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1061 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1062
1063 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1064 status &= VIA_CRDR_SDSTS_W1C_MASK;
1065 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1066
1067 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1068 status |= VIA_CRDR_SDSTS_CFE;
1069 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1070
1071 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1072
1073 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1074 msleep(1);
1075 }
1076
via_sd_probe(struct pci_dev * pcidev,const struct pci_device_id * id)1077 static int via_sd_probe(struct pci_dev *pcidev,
1078 const struct pci_device_id *id)
1079 {
1080 struct mmc_host *mmc;
1081 struct via_crdr_mmc_host *sdhost;
1082 u32 base, len;
1083 u8 gatt;
1084 int ret;
1085
1086 pr_info(DRV_NAME
1087 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1088 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1089 (int)pcidev->revision);
1090
1091 ret = pci_enable_device(pcidev);
1092 if (ret)
1093 return ret;
1094
1095 ret = pci_request_regions(pcidev, DRV_NAME);
1096 if (ret)
1097 goto disable;
1098
1099 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1100 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1101
1102 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1103 if (!mmc) {
1104 ret = -ENOMEM;
1105 goto release;
1106 }
1107
1108 sdhost = mmc_priv(mmc);
1109 sdhost->mmc = mmc;
1110 dev_set_drvdata(&pcidev->dev, sdhost);
1111
1112 len = pci_resource_len(pcidev, 0);
1113 base = pci_resource_start(pcidev, 0);
1114 sdhost->mmiobase = ioremap(base, len);
1115 if (!sdhost->mmiobase) {
1116 ret = -ENOMEM;
1117 goto free_mmc_host;
1118 }
1119
1120 sdhost->sdhc_mmiobase =
1121 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1122 sdhost->ddma_mmiobase =
1123 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1124 sdhost->pcictrl_mmiobase =
1125 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1126
1127 sdhost->power = MMC_VDD_165_195;
1128
1129 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1130 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1131 via_pwron_sleep(sdhost);
1132 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1133 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1134 msleep(3);
1135
1136 via_init_mmc_host(sdhost);
1137
1138 ret =
1139 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1140 sdhost);
1141 if (ret)
1142 goto unmap;
1143
1144 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1145 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1146 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1147 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1148
1149 /* device-specific quirks */
1150 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1151 pcidev->subsystem_device == 0x3891)
1152 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1153
1154 ret = mmc_add_host(mmc);
1155 if (ret)
1156 goto unmap;
1157
1158 return 0;
1159
1160 unmap:
1161 iounmap(sdhost->mmiobase);
1162 free_mmc_host:
1163 mmc_free_host(mmc);
1164 release:
1165 pci_release_regions(pcidev);
1166 disable:
1167 pci_disable_device(pcidev);
1168
1169 return ret;
1170 }
1171
via_sd_remove(struct pci_dev * pcidev)1172 static void via_sd_remove(struct pci_dev *pcidev)
1173 {
1174 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1175 unsigned long flags;
1176 u8 gatt;
1177
1178 spin_lock_irqsave(&sdhost->lock, flags);
1179
1180 /* Ensure we don't accept more commands from mmc layer */
1181 sdhost->reject = 1;
1182
1183 /* Disable generating further interrupts */
1184 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1185
1186 if (sdhost->mrq) {
1187 pr_err("%s: Controller removed during "
1188 "transfer\n", mmc_hostname(sdhost->mmc));
1189
1190 /* make sure all DMA is stopped */
1191 writel(VIA_CRDR_DMACTRL_SFTRST,
1192 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1193 sdhost->mrq->cmd->error = -ENOMEDIUM;
1194 if (sdhost->mrq->stop)
1195 sdhost->mrq->stop->error = -ENOMEDIUM;
1196 tasklet_schedule(&sdhost->finish_tasklet);
1197 }
1198 spin_unlock_irqrestore(&sdhost->lock, flags);
1199
1200 mmc_remove_host(sdhost->mmc);
1201
1202 free_irq(pcidev->irq, sdhost);
1203
1204 del_timer_sync(&sdhost->timer);
1205
1206 tasklet_kill(&sdhost->finish_tasklet);
1207
1208 /* switch off power */
1209 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1210 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1211 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1212
1213 iounmap(sdhost->mmiobase);
1214 mmc_free_host(sdhost->mmc);
1215 pci_release_regions(pcidev);
1216 pci_disable_device(pcidev);
1217
1218 pr_info(DRV_NAME
1219 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1220 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1221 }
1222
via_init_sdc_pm(struct via_crdr_mmc_host * host)1223 static void __maybe_unused via_init_sdc_pm(struct via_crdr_mmc_host *host)
1224 {
1225 struct sdhcreg *pm_sdhcreg;
1226 void __iomem *addrbase;
1227 u32 lenreg;
1228 u16 status;
1229
1230 pm_sdhcreg = &(host->pm_sdhc_reg);
1231 addrbase = host->sdhc_mmiobase;
1232
1233 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1234
1235 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1236 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1237
1238 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1239 status &= VIA_CRDR_SDSTS_W1C_MASK;
1240 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1241
1242 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1243 status |= VIA_CRDR_SDSTS_CFE;
1244 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1245
1246 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1247 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1248 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1249 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1250 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1251 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1252
1253 via_print_pcictrl(host);
1254 via_print_sdchc(host);
1255 }
1256
via_sd_suspend(struct device * dev)1257 static int __maybe_unused via_sd_suspend(struct device *dev)
1258 {
1259 struct via_crdr_mmc_host *host;
1260 unsigned long flags;
1261
1262 host = dev_get_drvdata(dev);
1263
1264 spin_lock_irqsave(&host->lock, flags);
1265 via_save_pcictrlreg(host);
1266 via_save_sdcreg(host);
1267 spin_unlock_irqrestore(&host->lock, flags);
1268
1269 device_wakeup_enable(dev);
1270
1271 return 0;
1272 }
1273
via_sd_resume(struct device * dev)1274 static int __maybe_unused via_sd_resume(struct device *dev)
1275 {
1276 struct via_crdr_mmc_host *sdhost;
1277 u8 gatt;
1278
1279 sdhost = dev_get_drvdata(dev);
1280
1281 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1282 if (sdhost->power == MMC_VDD_165_195)
1283 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1284 else
1285 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1286 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1287 via_pwron_sleep(sdhost);
1288 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1289 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1290 msleep(3);
1291
1292 msleep(100);
1293
1294 via_restore_pcictrlreg(sdhost);
1295 via_init_sdc_pm(sdhost);
1296
1297 return 0;
1298 }
1299
1300 static SIMPLE_DEV_PM_OPS(via_sd_pm_ops, via_sd_suspend, via_sd_resume);
1301
1302 static struct pci_driver via_sd_driver = {
1303 .name = DRV_NAME,
1304 .id_table = via_ids,
1305 .probe = via_sd_probe,
1306 .remove = via_sd_remove,
1307 .driver.pm = &via_sd_pm_ops,
1308 };
1309
1310 module_pci_driver(via_sd_driver);
1311
1312 MODULE_LICENSE("GPL");
1313 MODULE_AUTHOR("VIA Technologies Inc.");
1314 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
1315