xref: /openbmc/u-boot/include/imx_lpi2c.h (revision fc82e768)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 Freescale Semiconductors, Inc.
4  *
5  * I2CLP driver for i.MX
6  *
7  */
8 #ifndef __IMX_LPI2C_H__
9 #define __IMX_LPI2C_H__
10 
11 #include <clk.h>
12 
13 struct imx_lpi2c_bus {
14 	int index;
15 	ulong base;
16 	ulong driver_data;
17 	int speed;
18 	struct i2c_pads_info *pads_info;
19 	struct udevice *bus;
20 	struct clk per_clk;
21 };
22 
23 struct imx_lpi2c_reg {
24 	u32 verid;
25 	u32 param;
26 	u8  reserved_0[8];
27 	u32 mcr;
28 	u32 msr;
29 	u32 mier;
30 	u32 mder;
31 	u32 mcfgr0;
32 	u32 mcfgr1;
33 	u32 mcfgr2;
34 	u32 mcfgr3;
35 	u8  reserved_1[16];
36 	u32 mdmr;
37 	u8  reserved_2[4];
38 	u32 mccr0;
39 	u8  reserved_3[4];
40 	u32 mccr1;
41 	u8  reserved_4[4];
42 	u32 mfcr;
43 	u32 mfsr;
44 	u32 mtdr;
45 	u8  reserved_5[12];
46 	u32 mrdr;
47 	u8  reserved_6[156];
48 	u32 scr;
49 	u32 ssr;
50 	u32 sier;
51 	u32 sder;
52 	u8  reserved_7[4];
53 	u32 scfgr1;
54 	u32 scfgr2;
55 	u8  reserved_8[20];
56 	u32 samr;
57 	u8  reserved_9[12];
58 	u32 sasr;
59 	u32 star;
60 	u8  reserved_10[8];
61 	u32 stdr;
62 	u8  reserved_11[12];
63 	u32 srdr;
64 };
65 
66 typedef enum lpi2c_status {
67 	LPI2C_SUCESS = 0,
68 	LPI2C_END_PACKET_ERR,
69 	LPI2C_STOP_ERR,
70 	LPI2C_NAK_ERR,
71 	LPI2C_ARB_LOST_ERR,
72 	LPI2C_FIFO_ERR,
73 	LPI2C_PIN_LOW_TIMEOUT_ERR,
74 	LPI2C_DATA_MATCH_ERR,
75 	LPI2C_BUSY,
76 	LPI2C_IDLE,
77 	LPI2C_BIT_ERR,
78 	LPI2C_NO_TRANS_PROG,
79 	LPI2C_DMA_REQ_FAIL,
80 } lpi2c_status_t;
81 
82 /* ----------------------------------------------------------------------------
83    -- LPI2C Register Masks
84    ---------------------------------------------------------------------------- */
85 
86 /*!
87  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
88  * @{
89  */
90 
91 /*! @name VERID - Version ID Register */
92 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
93 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
94 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
95 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
96 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
97 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
98 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
99 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
100 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
101 
102 /*! @name PARAM - Parameter Register */
103 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
104 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
105 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
106 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
107 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
108 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
109 
110 /*! @name MCR - Master Control Register */
111 #define LPI2C_MCR_MEN_MASK                       (0x1U)
112 #define LPI2C_MCR_MEN_SHIFT                      (0U)
113 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
114 #define LPI2C_MCR_RST_MASK                       (0x2U)
115 #define LPI2C_MCR_RST_SHIFT                      (1U)
116 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
117 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
118 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
119 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
120 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
121 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
122 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
123 #define LPI2C_MCR_RTF_MASK                       (0x100U)
124 #define LPI2C_MCR_RTF_SHIFT                      (8U)
125 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
126 #define LPI2C_MCR_RRF_MASK                       (0x200U)
127 #define LPI2C_MCR_RRF_SHIFT                      (9U)
128 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
129 
130 /*! @name MSR - Master Status Register */
131 #define LPI2C_MSR_TDF_MASK                       (0x1U)
132 #define LPI2C_MSR_TDF_SHIFT                      (0U)
133 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
134 #define LPI2C_MSR_RDF_MASK                       (0x2U)
135 #define LPI2C_MSR_RDF_SHIFT                      (1U)
136 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
137 #define LPI2C_MSR_EPF_MASK                       (0x100U)
138 #define LPI2C_MSR_EPF_SHIFT                      (8U)
139 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
140 #define LPI2C_MSR_SDF_MASK                       (0x200U)
141 #define LPI2C_MSR_SDF_SHIFT                      (9U)
142 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
143 #define LPI2C_MSR_NDF_MASK                       (0x400U)
144 #define LPI2C_MSR_NDF_SHIFT                      (10U)
145 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
146 #define LPI2C_MSR_ALF_MASK                       (0x800U)
147 #define LPI2C_MSR_ALF_SHIFT                      (11U)
148 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
149 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
150 #define LPI2C_MSR_FEF_SHIFT                      (12U)
151 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
152 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
153 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
154 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
155 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
156 #define LPI2C_MSR_DMF_SHIFT                      (14U)
157 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
158 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
159 #define LPI2C_MSR_MBF_SHIFT                      (24U)
160 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
161 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
162 #define LPI2C_MSR_BBF_SHIFT                      (25U)
163 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
164 
165 /*! @name MIER - Master Interrupt Enable Register */
166 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
167 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
168 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
169 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
170 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
171 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
172 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
173 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
174 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
175 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
176 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
177 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
178 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
179 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
180 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
181 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
182 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
183 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
184 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
185 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
186 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
187 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
188 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
189 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
190 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
191 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
192 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
193 
194 /*! @name MDER - Master DMA Enable Register */
195 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
196 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
197 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
198 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
199 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
200 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
201 
202 /*! @name MCFGR0 - Master Configuration Register 0 */
203 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
204 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
205 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
206 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
207 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
208 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
209 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
210 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
211 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
212 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
213 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
214 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
215 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
216 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
217 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
218 
219 /*! @name MCFGR1 - Master Configuration Register 1 */
220 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
221 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
222 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
223 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
224 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
225 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
226 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
227 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
228 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
229 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
230 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
231 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
232 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
233 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
234 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
235 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
236 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
237 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
238 
239 /*! @name MCFGR2 - Master Configuration Register 2 */
240 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
241 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
242 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
243 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
244 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
245 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
246 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
247 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
248 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
249 
250 /*! @name MCFGR3 - Master Configuration Register 3 */
251 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
252 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
253 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
254 
255 /*! @name MDMR - Master Data Match Register */
256 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
257 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
258 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
259 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
260 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
261 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
262 
263 /*! @name MCCR0 - Master Clock Configuration Register 0 */
264 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
265 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
266 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
267 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
268 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
269 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
270 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
271 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
272 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
273 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
274 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
275 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
276 
277 /*! @name MCCR1 - Master Clock Configuration Register 1 */
278 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
279 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
280 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
281 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
282 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
283 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
284 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
285 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
286 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
287 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
288 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
289 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
290 
291 /*! @name MFCR - Master FIFO Control Register */
292 #define LPI2C_MFCR_TXWATER_MASK                  (0xFFU)
293 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
294 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
295 #define LPI2C_MFCR_RXWATER_MASK                  (0xFF0000U)
296 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
297 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
298 
299 /*! @name MFSR - Master FIFO Status Register */
300 #define LPI2C_MFSR_TXCOUNT_MASK                  (0xFFU)
301 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
302 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
303 #define LPI2C_MFSR_RXCOUNT_MASK                  (0xFF0000U)
304 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
305 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
306 
307 /*! @name MTDR - Master Transmit Data Register */
308 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
309 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
310 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
311 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
312 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
313 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
314 
315 /*! @name MRDR - Master Receive Data Register */
316 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
317 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
318 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
319 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
320 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
321 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
322 
323 /*! @name SCR - Slave Control Register */
324 #define LPI2C_SCR_SEN_MASK                       (0x1U)
325 #define LPI2C_SCR_SEN_SHIFT                      (0U)
326 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
327 #define LPI2C_SCR_RST_MASK                       (0x2U)
328 #define LPI2C_SCR_RST_SHIFT                      (1U)
329 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
330 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
331 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
332 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
333 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
334 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
335 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
336 #define LPI2C_SCR_RTF_MASK                       (0x100U)
337 #define LPI2C_SCR_RTF_SHIFT                      (8U)
338 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
339 #define LPI2C_SCR_RRF_MASK                       (0x200U)
340 #define LPI2C_SCR_RRF_SHIFT                      (9U)
341 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
342 
343 /*! @name SSR - Slave Status Register */
344 #define LPI2C_SSR_TDF_MASK                       (0x1U)
345 #define LPI2C_SSR_TDF_SHIFT                      (0U)
346 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
347 #define LPI2C_SSR_RDF_MASK                       (0x2U)
348 #define LPI2C_SSR_RDF_SHIFT                      (1U)
349 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
350 #define LPI2C_SSR_AVF_MASK                       (0x4U)
351 #define LPI2C_SSR_AVF_SHIFT                      (2U)
352 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
353 #define LPI2C_SSR_TAF_MASK                       (0x8U)
354 #define LPI2C_SSR_TAF_SHIFT                      (3U)
355 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
356 #define LPI2C_SSR_RSF_MASK                       (0x100U)
357 #define LPI2C_SSR_RSF_SHIFT                      (8U)
358 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
359 #define LPI2C_SSR_SDF_MASK                       (0x200U)
360 #define LPI2C_SSR_SDF_SHIFT                      (9U)
361 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
362 #define LPI2C_SSR_BEF_MASK                       (0x400U)
363 #define LPI2C_SSR_BEF_SHIFT                      (10U)
364 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
365 #define LPI2C_SSR_FEF_MASK                       (0x800U)
366 #define LPI2C_SSR_FEF_SHIFT                      (11U)
367 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
368 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
369 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
370 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
371 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
372 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
373 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
374 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
375 #define LPI2C_SSR_GCF_SHIFT                      (14U)
376 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
377 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
378 #define LPI2C_SSR_SARF_SHIFT                     (15U)
379 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
380 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
381 #define LPI2C_SSR_SBF_SHIFT                      (24U)
382 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
383 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
384 #define LPI2C_SSR_BBF_SHIFT                      (25U)
385 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
386 
387 /*! @name SIER - Slave Interrupt Enable Register */
388 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
389 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
390 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
391 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
392 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
393 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
394 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
395 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
396 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
397 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
398 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
399 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
400 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
401 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
402 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
403 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
404 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
405 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
406 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
407 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
408 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
409 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
410 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
411 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
412 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
413 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
414 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
415 #define LPI2C_SIER_AM1F_MASK                     (0x2000U)
416 #define LPI2C_SIER_AM1F_SHIFT                    (13U)
417 #define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
418 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
419 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
420 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
421 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
422 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
423 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
424 
425 /*! @name SDER - Slave DMA Enable Register */
426 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
427 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
428 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
429 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
430 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
431 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
432 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
433 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
434 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
435 
436 /*! @name SCFGR1 - Slave Configuration Register 1 */
437 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
438 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
439 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
440 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
441 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
442 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
443 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
444 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
445 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
446 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
447 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
448 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
449 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
450 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
451 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
452 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
453 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
454 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
455 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
456 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
457 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
458 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
459 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
460 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
461 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
462 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
463 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
464 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
465 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
466 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
467 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
468 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
469 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
470 
471 /*! @name SCFGR2 - Slave Configuration Register 2 */
472 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
473 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
474 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
475 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
476 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
477 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
478 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
479 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
480 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
481 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
482 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
483 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
484 
485 /*! @name SAMR - Slave Address Match Register */
486 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
487 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
488 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
489 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
490 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
491 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
492 
493 /*! @name SASR - Slave Address Status Register */
494 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
495 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
496 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
497 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
498 #define LPI2C_SASR_ANV_SHIFT                     (14U)
499 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
500 
501 /*! @name STAR - Slave Transmit ACK Register */
502 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
503 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
504 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
505 
506 /*! @name STDR - Slave Transmit Data Register */
507 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
508 #define LPI2C_STDR_DATA_SHIFT                    (0U)
509 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
510 
511 /*! @name SRDR - Slave Receive Data Register */
512 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
513 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
514 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
515 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
516 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
517 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
518 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
519 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
520 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
521 
522 #endif /* __ASM_ARCH_IMX_I2C_H__ */
523