xref: /openbmc/linux/drivers/video/fbdev/s3fb.c (revision 0ba2fa8c)
1 /*
2  * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3  *
4  * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file COPYING in the main directory of this archive for
8  * more details.
9  *
10  * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11  * which is based on the code of neofb.
12  */
13 
14 #include <linux/aperture.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/delay.h>
22 #include <linux/fb.h>
23 #include <linux/svga.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
27 #include <video/vga.h>
28 
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 
32 struct s3fb_info {
33 	int chip, rev, mclk_freq;
34 	int wc_cookie;
35 	struct vgastate state;
36 	struct mutex open_lock;
37 	unsigned int ref_count;
38 	u32 pseudo_palette[16];
39 #ifdef CONFIG_FB_S3_DDC
40 	u8 __iomem *mmio;
41 	bool ddc_registered;
42 	struct i2c_adapter ddc_adapter;
43 	struct i2c_algo_bit_data ddc_algo;
44 #endif
45 };
46 
47 
48 /* ------------------------------------------------------------------------- */
49 
50 static const struct svga_fb_format s3fb_formats[] = {
51 	{ 0,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,
52 		FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4,	FB_VISUAL_PSEUDOCOLOR, 8, 16},
53 	{ 4,  {0, 4, 0},  {0, 4, 0},  {0, 4, 0}, {0, 0, 0}, 0,
54 		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_PSEUDOCOLOR, 8, 16},
55 	{ 4,  {0, 4, 0},  {0, 4, 0},  {0, 4, 0}, {0, 0, 0}, 1,
56 		FB_TYPE_INTERLEAVED_PLANES, 1,		FB_VISUAL_PSEUDOCOLOR, 8, 16},
57 	{ 8,  {0, 8, 0},  {0, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,
58 		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_PSEUDOCOLOR, 4, 8},
59 	{16,  {10, 5, 0}, {5, 5, 0},  {0, 5, 0}, {0, 0, 0}, 0,
60 		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 2, 4},
61 	{16,  {11, 5, 0}, {5, 6, 0},  {0, 5, 0}, {0, 0, 0}, 0,
62 		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 2, 4},
63 	{24,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,
64 		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 1, 2},
65 	{32,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,
66 		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 1, 2},
67 	SVGA_FORMAT_END
68 };
69 
70 
71 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
72 	35000, 240000, 14318};
73 static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
74 	230000, 460000, 14318};
75 
76 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
77 
78 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
79 			"S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
80 			"S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
81 			"S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
82 			"S3 Virge/GX2", "S3 Virge/GX2+", "",
83 			"S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
84 			"S3 Trio3D", "S3 Virge/MX"};
85 
86 #define CHIP_UNKNOWN		0x00
87 #define CHIP_732_TRIO32		0x01
88 #define CHIP_764_TRIO64		0x02
89 #define CHIP_765_TRIO64VP	0x03
90 #define CHIP_767_TRIO64UVP	0x04
91 #define CHIP_775_TRIO64V2_DX	0x05
92 #define CHIP_785_TRIO64V2_GX	0x06
93 #define CHIP_551_PLATO_PX	0x07
94 #define CHIP_M65_AURORA64VP	0x08
95 #define CHIP_325_VIRGE		0x09
96 #define CHIP_988_VIRGE_VX	0x0A
97 #define CHIP_375_VIRGE_DX	0x0B
98 #define CHIP_385_VIRGE_GX	0x0C
99 #define CHIP_357_VIRGE_GX2	0x0D
100 #define CHIP_359_VIRGE_GX2P	0x0E
101 #define CHIP_360_TRIO3D_1X	0x10
102 #define CHIP_362_TRIO3D_2X	0x11
103 #define CHIP_368_TRIO3D_2X	0x12
104 #define CHIP_365_TRIO3D		0x13
105 #define CHIP_260_VIRGE_MX	0x14
106 
107 #define CHIP_XXX_TRIO		0x80
108 #define CHIP_XXX_TRIO64V2_DXGX	0x81
109 #define CHIP_XXX_VIRGE_DXGX	0x82
110 #define CHIP_36X_TRIO3D_1X_2X	0x83
111 
112 #define CHIP_UNDECIDED_FLAG	0x80
113 #define CHIP_MASK		0xFF
114 
115 #define MMIO_OFFSET		0x1000000
116 #define MMIO_SIZE		0x10000
117 
118 /* CRT timing register sets */
119 
120 static const struct vga_regset s3_h_total_regs[]        = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
121 static const struct vga_regset s3_h_display_regs[]      = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
122 static const struct vga_regset s3_h_blank_start_regs[]  = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
123 static const struct vga_regset s3_h_blank_end_regs[]    = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
124 static const struct vga_regset s3_h_sync_start_regs[]   = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
125 static const struct vga_regset s3_h_sync_end_regs[]     = {{0x05, 0, 4}, VGA_REGSET_END};
126 
127 static const struct vga_regset s3_v_total_regs[]        = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
128 static const struct vga_regset s3_v_display_regs[]      = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
129 static const struct vga_regset s3_v_blank_start_regs[]  = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
130 static const struct vga_regset s3_v_blank_end_regs[]    = {{0x16, 0, 7}, VGA_REGSET_END};
131 static const struct vga_regset s3_v_sync_start_regs[]   = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
132 static const struct vga_regset s3_v_sync_end_regs[]     = {{0x11, 0, 3}, VGA_REGSET_END};
133 
134 static const struct vga_regset s3_line_compare_regs[]   = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
135 static const struct vga_regset s3_start_address_regs[]  = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
136 static const struct vga_regset s3_offset_regs[]         = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
137 
138 static const struct vga_regset s3_dtpc_regs[]		= {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
139 
140 static const struct svga_timing_regs s3_timing_regs     = {
141 	s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
142 	s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
143 	s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
144 	s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
145 };
146 
147 
148 /* ------------------------------------------------------------------------- */
149 
150 /* Module parameters */
151 
152 
153 static char *mode_option;
154 static int mtrr = 1;
155 static int fasttext = 1;
156 
157 
158 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
159 MODULE_LICENSE("GPL");
160 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
161 
162 module_param(mode_option, charp, 0444);
163 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
164 module_param_named(mode, mode_option, charp, 0444);
165 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
166 module_param(mtrr, int, 0444);
167 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
168 
169 module_param(fasttext, int, 0644);
170 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
171 
172 
173 /* ------------------------------------------------------------------------- */
174 
175 #ifdef CONFIG_FB_S3_DDC
176 
177 #define DDC_REG		0xaa		/* Trio 3D/1X/2X */
178 #define DDC_MMIO_REG	0xff20		/* all other chips */
179 #define DDC_SCL_OUT	(1 << 0)
180 #define DDC_SDA_OUT	(1 << 1)
181 #define DDC_SCL_IN	(1 << 2)
182 #define DDC_SDA_IN	(1 << 3)
183 #define DDC_DRIVE_EN	(1 << 4)
184 
s3fb_ddc_needs_mmio(int chip)185 static bool s3fb_ddc_needs_mmio(int chip)
186 {
187 	return !(chip == CHIP_360_TRIO3D_1X  ||
188 		 chip == CHIP_362_TRIO3D_2X  ||
189 		 chip == CHIP_368_TRIO3D_2X);
190 }
191 
s3fb_ddc_read(struct s3fb_info * par)192 static u8 s3fb_ddc_read(struct s3fb_info *par)
193 {
194 	if (s3fb_ddc_needs_mmio(par->chip))
195 		return readb(par->mmio + DDC_MMIO_REG);
196 	else
197 		return vga_rcrt(par->state.vgabase, DDC_REG);
198 }
199 
s3fb_ddc_write(struct s3fb_info * par,u8 val)200 static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
201 {
202 	if (s3fb_ddc_needs_mmio(par->chip))
203 		writeb(val, par->mmio + DDC_MMIO_REG);
204 	else
205 		vga_wcrt(par->state.vgabase, DDC_REG, val);
206 }
207 
s3fb_ddc_setscl(void * data,int val)208 static void s3fb_ddc_setscl(void *data, int val)
209 {
210 	struct s3fb_info *par = data;
211 	unsigned char reg;
212 
213 	reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
214 	if (val)
215 		reg |= DDC_SCL_OUT;
216 	else
217 		reg &= ~DDC_SCL_OUT;
218 	s3fb_ddc_write(par, reg);
219 }
220 
s3fb_ddc_setsda(void * data,int val)221 static void s3fb_ddc_setsda(void *data, int val)
222 {
223 	struct s3fb_info *par = data;
224 	unsigned char reg;
225 
226 	reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
227 	if (val)
228 		reg |= DDC_SDA_OUT;
229 	else
230 		reg &= ~DDC_SDA_OUT;
231 	s3fb_ddc_write(par, reg);
232 }
233 
s3fb_ddc_getscl(void * data)234 static int s3fb_ddc_getscl(void *data)
235 {
236 	struct s3fb_info *par = data;
237 
238 	return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
239 }
240 
s3fb_ddc_getsda(void * data)241 static int s3fb_ddc_getsda(void *data)
242 {
243 	struct s3fb_info *par = data;
244 
245 	return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
246 }
247 
s3fb_setup_ddc_bus(struct fb_info * info)248 static int s3fb_setup_ddc_bus(struct fb_info *info)
249 {
250 	struct s3fb_info *par = info->par;
251 
252 	strscpy(par->ddc_adapter.name, info->fix.id,
253 		sizeof(par->ddc_adapter.name));
254 	par->ddc_adapter.owner		= THIS_MODULE;
255 	par->ddc_adapter.class		= I2C_CLASS_DDC;
256 	par->ddc_adapter.algo_data	= &par->ddc_algo;
257 	par->ddc_adapter.dev.parent	= info->device;
258 	par->ddc_algo.setsda		= s3fb_ddc_setsda;
259 	par->ddc_algo.setscl		= s3fb_ddc_setscl;
260 	par->ddc_algo.getsda		= s3fb_ddc_getsda;
261 	par->ddc_algo.getscl		= s3fb_ddc_getscl;
262 	par->ddc_algo.udelay		= 10;
263 	par->ddc_algo.timeout		= 20;
264 	par->ddc_algo.data		= par;
265 
266 	i2c_set_adapdata(&par->ddc_adapter, par);
267 
268 	/*
269 	 * some Virge cards have external MUX to switch chip I2C bus between
270 	 * DDC and extension pins - switch it do DDC
271 	 */
272 /*	vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
273 	if (par->chip == CHIP_357_VIRGE_GX2 ||
274 	    par->chip == CHIP_359_VIRGE_GX2P ||
275 	    par->chip == CHIP_260_VIRGE_MX)
276 		svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
277 	else
278 		svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
279 	/* some Virge need this or the DDC is ignored */
280 	svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
281 
282 	return i2c_bit_add_bus(&par->ddc_adapter);
283 }
284 #endif /* CONFIG_FB_S3_DDC */
285 
286 
287 /* ------------------------------------------------------------------------- */
288 
289 /* Set font in S3 fast text mode */
290 
s3fb_settile_fast(struct fb_info * info,struct fb_tilemap * map)291 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
292 {
293 	const u8 *font = map->data;
294 	u8 __iomem *fb = (u8 __iomem *) info->screen_base;
295 	int i, c;
296 
297 	if ((map->width != 8) || (map->height != 16) ||
298 	    (map->depth != 1) || (map->length != 256)) {
299 		fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
300 		       map->width, map->height, map->depth, map->length);
301 		return;
302 	}
303 
304 	fb += 2;
305 	for (i = 0; i < map->height; i++) {
306 		for (c = 0; c < map->length; c++) {
307 			fb_writeb(font[c * map->height + i], fb + c * 4);
308 		}
309 		fb += 1024;
310 	}
311 }
312 
s3fb_tilecursor(struct fb_info * info,struct fb_tilecursor * cursor)313 static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
314 {
315 	struct s3fb_info *par = info->par;
316 
317 	svga_tilecursor(par->state.vgabase, info, cursor);
318 }
319 
320 static struct fb_tile_ops s3fb_tile_ops = {
321 	.fb_settile	= svga_settile,
322 	.fb_tilecopy	= svga_tilecopy,
323 	.fb_tilefill    = svga_tilefill,
324 	.fb_tileblit    = svga_tileblit,
325 	.fb_tilecursor  = s3fb_tilecursor,
326 	.fb_get_tilemax = svga_get_tilemax,
327 };
328 
329 static struct fb_tile_ops s3fb_fast_tile_ops = {
330 	.fb_settile	= s3fb_settile_fast,
331 	.fb_tilecopy	= svga_tilecopy,
332 	.fb_tilefill    = svga_tilefill,
333 	.fb_tileblit    = svga_tileblit,
334 	.fb_tilecursor  = s3fb_tilecursor,
335 	.fb_get_tilemax = svga_get_tilemax,
336 };
337 
338 
339 /* ------------------------------------------------------------------------- */
340 
341 /* image data is MSB-first, fb structure is MSB-first too */
expand_color(u32 c)342 static inline u32 expand_color(u32 c)
343 {
344 	return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
345 }
346 
347 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
s3fb_iplan_imageblit(struct fb_info * info,const struct fb_image * image)348 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
349 {
350 	u32 fg = expand_color(image->fg_color);
351 	u32 bg = expand_color(image->bg_color);
352 	const u8 *src1, *src;
353 	u8 __iomem *dst1;
354 	u32 __iomem *dst;
355 	u32 val;
356 	int x, y;
357 
358 	src1 = image->data;
359 	dst1 = info->screen_base + (image->dy * info->fix.line_length)
360 		 + ((image->dx / 8) * 4);
361 
362 	for (y = 0; y < image->height; y++) {
363 		src = src1;
364 		dst = (u32 __iomem *) dst1;
365 		for (x = 0; x < image->width; x += 8) {
366 			val = *(src++) * 0x01010101;
367 			val = (val & fg) | (~val & bg);
368 			fb_writel(val, dst++);
369 		}
370 		src1 += image->width / 8;
371 		dst1 += info->fix.line_length;
372 	}
373 
374 }
375 
376 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
s3fb_iplan_fillrect(struct fb_info * info,const struct fb_fillrect * rect)377 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
378 {
379 	u32 fg = expand_color(rect->color);
380 	u8 __iomem *dst1;
381 	u32 __iomem *dst;
382 	int x, y;
383 
384 	dst1 = info->screen_base + (rect->dy * info->fix.line_length)
385 		 + ((rect->dx / 8) * 4);
386 
387 	for (y = 0; y < rect->height; y++) {
388 		dst = (u32 __iomem *) dst1;
389 		for (x = 0; x < rect->width; x += 8) {
390 			fb_writel(fg, dst++);
391 		}
392 		dst1 += info->fix.line_length;
393 	}
394 }
395 
396 
397 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
expand_pixel(u32 c)398 static inline u32 expand_pixel(u32 c)
399 {
400 	return (((c &  1) << 24) | ((c &  2) << 27) | ((c &  4) << 14) | ((c &   8) << 17) |
401 		((c & 16) <<  4) | ((c & 32) <<  7) | ((c & 64) >>  6) | ((c & 128) >>  3)) * 0xF;
402 }
403 
404 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
s3fb_cfb4_imageblit(struct fb_info * info,const struct fb_image * image)405 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
406 {
407 	u32 fg = image->fg_color * 0x11111111;
408 	u32 bg = image->bg_color * 0x11111111;
409 	const u8 *src1, *src;
410 	u8 __iomem *dst1;
411 	u32 __iomem *dst;
412 	u32 val;
413 	int x, y;
414 
415 	src1 = image->data;
416 	dst1 = info->screen_base + (image->dy * info->fix.line_length)
417 		 + ((image->dx / 8) * 4);
418 
419 	for (y = 0; y < image->height; y++) {
420 		src = src1;
421 		dst = (u32 __iomem *) dst1;
422 		for (x = 0; x < image->width; x += 8) {
423 			val = expand_pixel(*(src++));
424 			val = (val & fg) | (~val & bg);
425 			fb_writel(val, dst++);
426 		}
427 		src1 += image->width / 8;
428 		dst1 += info->fix.line_length;
429 	}
430 }
431 
s3fb_imageblit(struct fb_info * info,const struct fb_image * image)432 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
433 {
434 	if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
435 	    && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
436 		if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
437 			s3fb_iplan_imageblit(info, image);
438 		else
439 			s3fb_cfb4_imageblit(info, image);
440 	} else
441 		cfb_imageblit(info, image);
442 }
443 
s3fb_fillrect(struct fb_info * info,const struct fb_fillrect * rect)444 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
445 {
446 	if ((info->var.bits_per_pixel == 4)
447 	    && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
448 	    && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
449 		s3fb_iplan_fillrect(info, rect);
450 	 else
451 		cfb_fillrect(info, rect);
452 }
453 
454 
455 
456 /* ------------------------------------------------------------------------- */
457 
458 
s3_set_pixclock(struct fb_info * info,u32 pixclock)459 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
460 {
461 	struct s3fb_info *par = info->par;
462 	u16 m, n, r;
463 	u8 regval;
464 	int rv;
465 
466 	rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
467 			      1000000000 / pixclock, &m, &n, &r, info->node);
468 	if (rv < 0) {
469 		fb_err(info, "cannot set requested pixclock, keeping old value\n");
470 		return;
471 	}
472 
473 	/* Set VGA misc register  */
474 	regval = vga_r(par->state.vgabase, VGA_MIS_R);
475 	vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
476 
477 	/* Set S3 clock registers */
478 	if (par->chip == CHIP_357_VIRGE_GX2 ||
479 	    par->chip == CHIP_359_VIRGE_GX2P ||
480 	    par->chip == CHIP_360_TRIO3D_1X ||
481 	    par->chip == CHIP_362_TRIO3D_2X ||
482 	    par->chip == CHIP_368_TRIO3D_2X ||
483 	    par->chip == CHIP_260_VIRGE_MX) {
484 		vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6));	/* n and two bits of r */
485 		vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
486 	} else
487 		vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
488 	vga_wseq(par->state.vgabase, 0x13, m - 2);
489 
490 	udelay(1000);
491 
492 	/* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
493 	regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
494 	vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
495 	vga_wseq(par->state.vgabase, 0x15, regval |  (1<<5));
496 	vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
497 }
498 
499 
500 /* Open framebuffer */
501 
s3fb_open(struct fb_info * info,int user)502 static int s3fb_open(struct fb_info *info, int user)
503 {
504 	struct s3fb_info *par = info->par;
505 
506 	mutex_lock(&(par->open_lock));
507 	if (par->ref_count == 0) {
508 		void __iomem *vgabase = par->state.vgabase;
509 
510 		memset(&(par->state), 0, sizeof(struct vgastate));
511 		par->state.vgabase = vgabase;
512 		par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
513 		par->state.num_crtc = 0x70;
514 		par->state.num_seq = 0x20;
515 		save_vga(&(par->state));
516 	}
517 
518 	par->ref_count++;
519 	mutex_unlock(&(par->open_lock));
520 
521 	return 0;
522 }
523 
524 /* Close framebuffer */
525 
s3fb_release(struct fb_info * info,int user)526 static int s3fb_release(struct fb_info *info, int user)
527 {
528 	struct s3fb_info *par = info->par;
529 
530 	mutex_lock(&(par->open_lock));
531 	if (par->ref_count == 0) {
532 		mutex_unlock(&(par->open_lock));
533 		return -EINVAL;
534 	}
535 
536 	if (par->ref_count == 1)
537 		restore_vga(&(par->state));
538 
539 	par->ref_count--;
540 	mutex_unlock(&(par->open_lock));
541 
542 	return 0;
543 }
544 
545 /* Validate passed in var */
546 
s3fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)547 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
548 {
549 	struct s3fb_info *par = info->par;
550 	int rv, mem, step;
551 	u16 m, n, r;
552 
553 	if (!var->pixclock)
554 		return -EINVAL;
555 
556 	/* Find appropriate format */
557 	rv = svga_match_format (s3fb_formats, var, NULL);
558 
559 	/* 32bpp mode is not supported on VIRGE VX,
560 	   24bpp is not supported on others */
561 	if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
562 		rv = -EINVAL;
563 
564 	if (rv < 0) {
565 		fb_err(info, "unsupported mode requested\n");
566 		return rv;
567 	}
568 
569 	/* Do not allow to have real resoulution larger than virtual */
570 	if (var->xres > var->xres_virtual)
571 		var->xres_virtual = var->xres;
572 
573 	if (var->yres > var->yres_virtual)
574 		var->yres_virtual = var->yres;
575 
576 	/* Round up xres_virtual to have proper alignment of lines */
577 	step = s3fb_formats[rv].xresstep - 1;
578 	var->xres_virtual = (var->xres_virtual+step) & ~step;
579 
580 	/* Check whether have enough memory */
581 	mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
582 	if (mem > info->screen_size) {
583 		fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n",
584 		       mem >> 10, (unsigned int) (info->screen_size >> 10));
585 		return -EINVAL;
586 	}
587 
588 	rv = svga_check_timings (&s3_timing_regs, var, info->node);
589 	if (rv < 0) {
590 		fb_err(info, "invalid timings requested\n");
591 		return rv;
592 	}
593 
594 	rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
595 				info->node);
596 	if (rv < 0) {
597 		fb_err(info, "invalid pixclock value requested\n");
598 		return rv;
599 	}
600 
601 	return 0;
602 }
603 
604 /* Set video mode from par */
605 
s3fb_set_par(struct fb_info * info)606 static int s3fb_set_par(struct fb_info *info)
607 {
608 	struct s3fb_info *par = info->par;
609 	u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
610 	u32 bpp = info->var.bits_per_pixel;
611 	u32 htotal, hsstart;
612 
613 	if (bpp != 0) {
614 		info->fix.ypanstep = 1;
615 		info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
616 
617 		info->flags &= ~FBINFO_MISC_TILEBLITTING;
618 		info->tileops = NULL;
619 
620 		/* in 4bpp supports 8p wide tiles only, any tiles otherwise */
621 		info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
622 		info->pixmap.blit_y = ~(u32)0;
623 
624 		offset_value = (info->var.xres_virtual * bpp) / 64;
625 		screen_size = info->var.yres_virtual * info->fix.line_length;
626 	} else {
627 		info->fix.ypanstep = 16;
628 		info->fix.line_length = 0;
629 
630 		info->flags |= FBINFO_MISC_TILEBLITTING;
631 		info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
632 
633 		/* supports 8x16 tiles only */
634 		info->pixmap.blit_x = 1 << (8 - 1);
635 		info->pixmap.blit_y = 1 << (16 - 1);
636 
637 		offset_value = info->var.xres_virtual / 16;
638 		screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
639 	}
640 
641 	info->var.xoffset = 0;
642 	info->var.yoffset = 0;
643 	info->var.activate = FB_ACTIVATE_NOW;
644 
645 	/* Unlock registers */
646 	vga_wcrt(par->state.vgabase, 0x38, 0x48);
647 	vga_wcrt(par->state.vgabase, 0x39, 0xA5);
648 	vga_wseq(par->state.vgabase, 0x08, 0x06);
649 	svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
650 
651 	/* Blank screen and turn off sync */
652 	svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
653 	svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
654 
655 	/* Set default values */
656 	svga_set_default_gfx_regs(par->state.vgabase);
657 	svga_set_default_atc_regs(par->state.vgabase);
658 	svga_set_default_seq_regs(par->state.vgabase);
659 	svga_set_default_crt_regs(par->state.vgabase);
660 	svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
661 	svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
662 
663 	/* S3 specific initialization */
664 	svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
665 	svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
666 
667 /*	svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ?	*/
668 /*	svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ?	*/
669 	svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ?	*/
670 	svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ?	*/
671 
672 	svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
673 
674 /*	svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
675 
676 /*	svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
677 /*	svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
678 
679 
680 	/* Set the offset register */
681 	fb_dbg(info, "offset register       : %d\n", offset_value);
682 	svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
683 
684 	if (par->chip != CHIP_357_VIRGE_GX2 &&
685 	    par->chip != CHIP_359_VIRGE_GX2P &&
686 	    par->chip != CHIP_360_TRIO3D_1X &&
687 	    par->chip != CHIP_362_TRIO3D_2X &&
688 	    par->chip != CHIP_368_TRIO3D_2X &&
689 	    par->chip != CHIP_260_VIRGE_MX) {
690 		vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
691 		vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
692 		vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
693 		vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
694 	}
695 
696 	vga_wcrt(par->state.vgabase, 0x3A, 0x35);
697 	svga_wattr(par->state.vgabase, 0x33, 0x00);
698 
699 	if (info->var.vmode & FB_VMODE_DOUBLE)
700 		svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
701 	else
702 		svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
703 
704 	if (info->var.vmode & FB_VMODE_INTERLACED)
705 		svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
706 	else
707 		svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
708 
709 	/* Disable hardware graphics cursor */
710 	svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
711 	/* Disable Streams engine */
712 	svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
713 
714 	mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
715 
716 	/* S3 virge DX hack */
717 	if (par->chip == CHIP_375_VIRGE_DX) {
718 		vga_wcrt(par->state.vgabase, 0x86, 0x80);
719 		vga_wcrt(par->state.vgabase, 0x90, 0x00);
720 	}
721 
722 	/* S3 virge VX hack */
723 	if (par->chip == CHIP_988_VIRGE_VX) {
724 		vga_wcrt(par->state.vgabase, 0x50, 0x00);
725 		vga_wcrt(par->state.vgabase, 0x67, 0x50);
726 		msleep(10); /* screen remains blank sometimes without this */
727 		vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
728 		vga_wcrt(par->state.vgabase, 0x66, 0x90);
729 	}
730 
731 	if (par->chip == CHIP_357_VIRGE_GX2 ||
732 	    par->chip == CHIP_359_VIRGE_GX2P ||
733 	    par->chip == CHIP_360_TRIO3D_1X ||
734 	    par->chip == CHIP_362_TRIO3D_2X ||
735 	    par->chip == CHIP_368_TRIO3D_2X ||
736 	    par->chip == CHIP_365_TRIO3D    ||
737 	    par->chip == CHIP_375_VIRGE_DX  ||
738 	    par->chip == CHIP_385_VIRGE_GX  ||
739 	    par->chip == CHIP_260_VIRGE_MX) {
740 		dbytes = info->var.xres * ((bpp+7)/8);
741 		vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
742 		vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
743 
744 		vga_wcrt(par->state.vgabase, 0x66, 0x81);
745 	}
746 
747 	if (par->chip == CHIP_357_VIRGE_GX2  ||
748 	    par->chip == CHIP_359_VIRGE_GX2P ||
749 	    par->chip == CHIP_360_TRIO3D_1X ||
750 	    par->chip == CHIP_362_TRIO3D_2X ||
751 	    par->chip == CHIP_368_TRIO3D_2X ||
752 	    par->chip == CHIP_260_VIRGE_MX)
753 		vga_wcrt(par->state.vgabase, 0x34, 0x00);
754 	else	/* enable Data Transfer Position Control (DTPC) */
755 		vga_wcrt(par->state.vgabase, 0x34, 0x10);
756 
757 	svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
758 	multiplex = 0;
759 	hmul = 1;
760 
761 	/* Set mode-specific register values */
762 	switch (mode) {
763 	case 0:
764 		fb_dbg(info, "text mode\n");
765 		svga_set_textmode_vga_regs(par->state.vgabase);
766 
767 		/* Set additional registers like in 8-bit mode */
768 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
769 		svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
770 
771 		/* Disable enhanced mode */
772 		svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
773 
774 		if (fasttext) {
775 			fb_dbg(info, "high speed text mode set\n");
776 			svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
777 		}
778 		break;
779 	case 1:
780 		fb_dbg(info, "4 bit pseudocolor\n");
781 		vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
782 
783 		/* Set additional registers like in 8-bit mode */
784 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
785 		svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
786 
787 		/* disable enhanced mode */
788 		svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
789 		break;
790 	case 2:
791 		fb_dbg(info, "4 bit pseudocolor, planar\n");
792 
793 		/* Set additional registers like in 8-bit mode */
794 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
795 		svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
796 
797 		/* disable enhanced mode */
798 		svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
799 		break;
800 	case 3:
801 		fb_dbg(info, "8 bit pseudocolor\n");
802 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
803 		if (info->var.pixclock > 20000 ||
804 		    par->chip == CHIP_357_VIRGE_GX2 ||
805 		    par->chip == CHIP_359_VIRGE_GX2P ||
806 		    par->chip == CHIP_360_TRIO3D_1X ||
807 		    par->chip == CHIP_362_TRIO3D_2X ||
808 		    par->chip == CHIP_368_TRIO3D_2X ||
809 		    par->chip == CHIP_260_VIRGE_MX)
810 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
811 		else {
812 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
813 			multiplex = 1;
814 		}
815 		break;
816 	case 4:
817 		fb_dbg(info, "5/5/5 truecolor\n");
818 		if (par->chip == CHIP_988_VIRGE_VX) {
819 			if (info->var.pixclock > 20000)
820 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
821 			else
822 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
823 		} else if (par->chip == CHIP_365_TRIO3D) {
824 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
825 			if (info->var.pixclock > 8695) {
826 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
827 				hmul = 2;
828 			} else {
829 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
830 				multiplex = 1;
831 			}
832 		} else {
833 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
834 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
835 			if (par->chip != CHIP_357_VIRGE_GX2 &&
836 			    par->chip != CHIP_359_VIRGE_GX2P &&
837 			    par->chip != CHIP_360_TRIO3D_1X &&
838 			    par->chip != CHIP_362_TRIO3D_2X &&
839 			    par->chip != CHIP_368_TRIO3D_2X &&
840 			    par->chip != CHIP_260_VIRGE_MX)
841 				hmul = 2;
842 		}
843 		break;
844 	case 5:
845 		fb_dbg(info, "5/6/5 truecolor\n");
846 		if (par->chip == CHIP_988_VIRGE_VX) {
847 			if (info->var.pixclock > 20000)
848 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
849 			else
850 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
851 		} else if (par->chip == CHIP_365_TRIO3D) {
852 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
853 			if (info->var.pixclock > 8695) {
854 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
855 				hmul = 2;
856 			} else {
857 				svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
858 				multiplex = 1;
859 			}
860 		} else {
861 			svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
862 			svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
863 			if (par->chip != CHIP_357_VIRGE_GX2 &&
864 			    par->chip != CHIP_359_VIRGE_GX2P &&
865 			    par->chip != CHIP_360_TRIO3D_1X &&
866 			    par->chip != CHIP_362_TRIO3D_2X &&
867 			    par->chip != CHIP_368_TRIO3D_2X &&
868 			    par->chip != CHIP_260_VIRGE_MX)
869 				hmul = 2;
870 		}
871 		break;
872 	case 6:
873 		/* VIRGE VX case */
874 		fb_dbg(info, "8/8/8 truecolor\n");
875 		svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
876 		break;
877 	case 7:
878 		fb_dbg(info, "8/8/8/8 truecolor\n");
879 		svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
880 		svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
881 		break;
882 	default:
883 		fb_err(info, "unsupported mode - bug\n");
884 		return -EINVAL;
885 	}
886 
887 	if (par->chip != CHIP_988_VIRGE_VX) {
888 		svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
889 		svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
890 	}
891 
892 	s3_set_pixclock(info, info->var.pixclock);
893 	svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
894 			 (info->var.vmode & FB_VMODE_DOUBLE)     ? 2 : 1,
895 			 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
896 			 hmul, info->node);
897 
898 	/* Set interlaced mode start/end register */
899 	htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
900 	htotal = ((htotal * hmul) / 8) - 5;
901 	vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
902 
903 	/* Set Data Transfer Position */
904 	hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
905 	/* + 2 is needed for Virge/VX, does no harm on other cards */
906 	value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1);
907 	svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
908 
909 	if (screen_size > info->screen_size)
910 		screen_size = info->screen_size;
911 	memset_io(info->screen_base, 0x00, screen_size);
912 	/* Device and screen back on */
913 	svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
914 	svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
915 
916 	return 0;
917 }
918 
919 /* Set a colour register */
920 
s3fb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * fb)921 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
922 				u_int transp, struct fb_info *fb)
923 {
924 	switch (fb->var.bits_per_pixel) {
925 	case 0:
926 	case 4:
927 		if (regno >= 16)
928 			return -EINVAL;
929 
930 		if ((fb->var.bits_per_pixel == 4) &&
931 		    (fb->var.nonstd == 0)) {
932 			outb(0xF0, VGA_PEL_MSK);
933 			outb(regno*16, VGA_PEL_IW);
934 		} else {
935 			outb(0x0F, VGA_PEL_MSK);
936 			outb(regno, VGA_PEL_IW);
937 		}
938 		outb(red >> 10, VGA_PEL_D);
939 		outb(green >> 10, VGA_PEL_D);
940 		outb(blue >> 10, VGA_PEL_D);
941 		break;
942 	case 8:
943 		if (regno >= 256)
944 			return -EINVAL;
945 
946 		outb(0xFF, VGA_PEL_MSK);
947 		outb(regno, VGA_PEL_IW);
948 		outb(red >> 10, VGA_PEL_D);
949 		outb(green >> 10, VGA_PEL_D);
950 		outb(blue >> 10, VGA_PEL_D);
951 		break;
952 	case 16:
953 		if (regno >= 16)
954 			return 0;
955 
956 		if (fb->var.green.length == 5)
957 			((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
958 				((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
959 		else if (fb->var.green.length == 6)
960 			((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
961 				((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
962 		else return -EINVAL;
963 		break;
964 	case 24:
965 	case 32:
966 		if (regno >= 16)
967 			return 0;
968 
969 		((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
970 			(green & 0xFF00) | ((blue & 0xFF00) >> 8);
971 		break;
972 	default:
973 		return -EINVAL;
974 	}
975 
976 	return 0;
977 }
978 
979 
980 /* Set the display blanking state */
981 
s3fb_blank(int blank_mode,struct fb_info * info)982 static int s3fb_blank(int blank_mode, struct fb_info *info)
983 {
984 	struct s3fb_info *par = info->par;
985 
986 	switch (blank_mode) {
987 	case FB_BLANK_UNBLANK:
988 		fb_dbg(info, "unblank\n");
989 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
990 		svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
991 		break;
992 	case FB_BLANK_NORMAL:
993 		fb_dbg(info, "blank\n");
994 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
995 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
996 		break;
997 	case FB_BLANK_HSYNC_SUSPEND:
998 		fb_dbg(info, "hsync\n");
999 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
1000 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1001 		break;
1002 	case FB_BLANK_VSYNC_SUSPEND:
1003 		fb_dbg(info, "vsync\n");
1004 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
1005 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1006 		break;
1007 	case FB_BLANK_POWERDOWN:
1008 		fb_dbg(info, "sync down\n");
1009 		svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
1010 		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1011 		break;
1012 	}
1013 
1014 	return 0;
1015 }
1016 
1017 
1018 /* Pan the display */
1019 
s3fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1020 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1021 {
1022 	struct s3fb_info *par = info->par;
1023 	unsigned int offset;
1024 
1025 	/* Calculate the offset */
1026 	if (info->var.bits_per_pixel == 0) {
1027 		offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
1028 		       + (var->xoffset / 2);
1029 		offset = offset >> 2;
1030 	} else {
1031 		offset = (var->yoffset * info->fix.line_length) +
1032 			 (var->xoffset * info->var.bits_per_pixel / 8);
1033 		offset = offset >> 2;
1034 	}
1035 
1036 	/* Set the offset */
1037 	svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
1038 
1039 	return 0;
1040 }
1041 
1042 /* ------------------------------------------------------------------------- */
1043 
1044 /* Frame buffer operations */
1045 
1046 static const struct fb_ops s3fb_ops = {
1047 	.owner		= THIS_MODULE,
1048 	.fb_open	= s3fb_open,
1049 	.fb_release	= s3fb_release,
1050 	.fb_check_var	= s3fb_check_var,
1051 	.fb_set_par	= s3fb_set_par,
1052 	.fb_setcolreg	= s3fb_setcolreg,
1053 	.fb_blank	= s3fb_blank,
1054 	.fb_pan_display	= s3fb_pan_display,
1055 	.fb_fillrect	= s3fb_fillrect,
1056 	.fb_copyarea	= cfb_copyarea,
1057 	.fb_imageblit	= s3fb_imageblit,
1058 	.fb_get_caps    = svga_get_caps,
1059 };
1060 
1061 /* ------------------------------------------------------------------------- */
1062 
s3_identification(struct s3fb_info * par)1063 static int s3_identification(struct s3fb_info *par)
1064 {
1065 	int chip = par->chip;
1066 
1067 	if (chip == CHIP_XXX_TRIO) {
1068 		u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
1069 		u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
1070 		u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
1071 
1072 		if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
1073 			if (cr2e == 0x10)
1074 				return CHIP_732_TRIO32;
1075 			if (cr2e == 0x11) {
1076 				if (! (cr2f & 0x40))
1077 					return CHIP_764_TRIO64;
1078 				else
1079 					return CHIP_765_TRIO64VP;
1080 			}
1081 		}
1082 	}
1083 
1084 	if (chip == CHIP_XXX_TRIO64V2_DXGX) {
1085 		u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1086 
1087 		if (! (cr6f & 0x01))
1088 			return CHIP_775_TRIO64V2_DX;
1089 		else
1090 			return CHIP_785_TRIO64V2_GX;
1091 	}
1092 
1093 	if (chip == CHIP_XXX_VIRGE_DXGX) {
1094 		u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1095 
1096 		if (! (cr6f & 0x01))
1097 			return CHIP_375_VIRGE_DX;
1098 		else
1099 			return CHIP_385_VIRGE_GX;
1100 	}
1101 
1102 	if (chip == CHIP_36X_TRIO3D_1X_2X) {
1103 		switch (vga_rcrt(par->state.vgabase, 0x2f)) {
1104 		case 0x00:
1105 			return CHIP_360_TRIO3D_1X;
1106 		case 0x01:
1107 			return CHIP_362_TRIO3D_2X;
1108 		case 0x02:
1109 			return CHIP_368_TRIO3D_2X;
1110 		}
1111 	}
1112 
1113 	return CHIP_UNKNOWN;
1114 }
1115 
1116 
1117 /* PCI probe */
1118 
s3_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)1119 static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1120 {
1121 	struct pci_bus_region bus_reg;
1122 	struct resource vga_res;
1123 	struct fb_info *info;
1124 	struct s3fb_info *par;
1125 	int rc;
1126 	u8 regval, cr38, cr39;
1127 	bool found = false;
1128 
1129 	/* Ignore secondary VGA device because there is no VGA arbitration */
1130 	if (! svga_primary_device(dev)) {
1131 		dev_info(&(dev->dev), "ignoring secondary device\n");
1132 		return -ENODEV;
1133 	}
1134 
1135 	rc = aperture_remove_conflicting_pci_devices(dev, "s3fb");
1136 	if (rc)
1137 		return rc;
1138 
1139 	/* Allocate and fill driver data structure */
1140 	info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
1141 	if (!info)
1142 		return -ENOMEM;
1143 
1144 	par = info->par;
1145 	mutex_init(&par->open_lock);
1146 
1147 	info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
1148 	info->fbops = &s3fb_ops;
1149 
1150 	/* Prepare PCI device */
1151 	rc = pci_enable_device(dev);
1152 	if (rc < 0) {
1153 		dev_err(info->device, "cannot enable PCI device\n");
1154 		goto err_enable_device;
1155 	}
1156 
1157 	rc = pci_request_regions(dev, "s3fb");
1158 	if (rc < 0) {
1159 		dev_err(info->device, "cannot reserve framebuffer region\n");
1160 		goto err_request_regions;
1161 	}
1162 
1163 
1164 	info->fix.smem_start = pci_resource_start(dev, 0);
1165 	info->fix.smem_len = pci_resource_len(dev, 0);
1166 
1167 	/* Map physical IO memory address into kernel space */
1168 	info->screen_base = pci_iomap_wc(dev, 0, 0);
1169 	if (! info->screen_base) {
1170 		rc = -ENOMEM;
1171 		dev_err(info->device, "iomap for framebuffer failed\n");
1172 		goto err_iomap;
1173 	}
1174 
1175 	bus_reg.start = 0;
1176 	bus_reg.end = 64 * 1024;
1177 
1178 	vga_res.flags = IORESOURCE_IO;
1179 
1180 	pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1181 
1182 	par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1183 
1184 	/* Unlock regs */
1185 	cr38 = vga_rcrt(par->state.vgabase, 0x38);
1186 	cr39 = vga_rcrt(par->state.vgabase, 0x39);
1187 	vga_wseq(par->state.vgabase, 0x08, 0x06);
1188 	vga_wcrt(par->state.vgabase, 0x38, 0x48);
1189 	vga_wcrt(par->state.vgabase, 0x39, 0xA5);
1190 
1191 	/* Identify chip type */
1192 	par->chip = id->driver_data & CHIP_MASK;
1193 	par->rev = vga_rcrt(par->state.vgabase, 0x2f);
1194 	if (par->chip & CHIP_UNDECIDED_FLAG)
1195 		par->chip = s3_identification(par);
1196 
1197 	/* Find how many physical memory there is on card */
1198 	/* 0x36 register is accessible even if other registers are locked */
1199 	regval = vga_rcrt(par->state.vgabase, 0x36);
1200 	if (par->chip == CHIP_360_TRIO3D_1X ||
1201 	    par->chip == CHIP_362_TRIO3D_2X ||
1202 	    par->chip == CHIP_368_TRIO3D_2X ||
1203 	    par->chip == CHIP_365_TRIO3D) {
1204 		switch ((regval & 0xE0) >> 5) {
1205 		case 0: /* 8MB -- only 4MB usable for display */
1206 		case 1: /* 4MB with 32-bit bus */
1207 		case 2:	/* 4MB */
1208 			info->screen_size = 4 << 20;
1209 			break;
1210 		case 4: /* 2MB on 365 Trio3D */
1211 		case 6: /* 2MB */
1212 			info->screen_size = 2 << 20;
1213 			break;
1214 		}
1215 	} else if (par->chip == CHIP_357_VIRGE_GX2 ||
1216 		   par->chip == CHIP_359_VIRGE_GX2P ||
1217 		   par->chip == CHIP_260_VIRGE_MX) {
1218 		switch ((regval & 0xC0) >> 6) {
1219 		case 1: /* 4MB */
1220 			info->screen_size = 4 << 20;
1221 			break;
1222 		case 3: /* 2MB */
1223 			info->screen_size = 2 << 20;
1224 			break;
1225 		}
1226 	} else if (par->chip == CHIP_988_VIRGE_VX) {
1227 		switch ((regval & 0x60) >> 5) {
1228 		case 0: /* 2MB */
1229 			info->screen_size = 2 << 20;
1230 			break;
1231 		case 1: /* 4MB */
1232 			info->screen_size = 4 << 20;
1233 			break;
1234 		case 2: /* 6MB */
1235 			info->screen_size = 6 << 20;
1236 			break;
1237 		case 3: /* 8MB */
1238 			info->screen_size = 8 << 20;
1239 			break;
1240 		}
1241 		/* off-screen memory */
1242 		regval = vga_rcrt(par->state.vgabase, 0x37);
1243 		switch ((regval & 0x60) >> 5) {
1244 		case 1: /* 4MB */
1245 			info->screen_size -= 4 << 20;
1246 			break;
1247 		case 2: /* 2MB */
1248 			info->screen_size -= 2 << 20;
1249 			break;
1250 		}
1251 	} else
1252 		info->screen_size = s3_memsizes[regval >> 5] << 10;
1253 	info->fix.smem_len = info->screen_size;
1254 
1255 	/* Find MCLK frequency */
1256 	regval = vga_rseq(par->state.vgabase, 0x10);
1257 	par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F)  + 2);
1258 	par->mclk_freq = par->mclk_freq >> (regval >> 5);
1259 
1260 	/* Restore locks */
1261 	vga_wcrt(par->state.vgabase, 0x38, cr38);
1262 	vga_wcrt(par->state.vgabase, 0x39, cr39);
1263 
1264 	strcpy(info->fix.id, s3_names [par->chip]);
1265 	info->fix.mmio_start = 0;
1266 	info->fix.mmio_len = 0;
1267 	info->fix.type = FB_TYPE_PACKED_PIXELS;
1268 	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1269 	info->fix.ypanstep = 0;
1270 	info->fix.accel = FB_ACCEL_NONE;
1271 	info->pseudo_palette = (void*) (par->pseudo_palette);
1272 	info->var.bits_per_pixel = 8;
1273 
1274 #ifdef CONFIG_FB_S3_DDC
1275 	/* Enable MMIO if needed */
1276 	if (s3fb_ddc_needs_mmio(par->chip)) {
1277 		par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
1278 		if (par->mmio)
1279 			svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08);	/* enable MMIO */
1280 		else
1281 			dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
1282 				info->fix.smem_start + MMIO_OFFSET);
1283 	}
1284 	if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
1285 		if (s3fb_setup_ddc_bus(info) == 0) {
1286 			u8 *edid = fb_ddc_read(&par->ddc_adapter);
1287 			par->ddc_registered = true;
1288 			if (edid) {
1289 				fb_edid_to_monspecs(edid, &info->monspecs);
1290 				kfree(edid);
1291 				if (!info->monspecs.modedb)
1292 					dev_err(info->device, "error getting mode database\n");
1293 				else {
1294 					const struct fb_videomode *m;
1295 
1296 					fb_videomode_to_modelist(info->monspecs.modedb,
1297 								 info->monspecs.modedb_len,
1298 								 &info->modelist);
1299 					m = fb_find_best_display(&info->monspecs, &info->modelist);
1300 					if (m) {
1301 						fb_videomode_to_var(&info->var, m);
1302 						/* fill all other info->var's fields */
1303 						if (s3fb_check_var(&info->var, info) == 0)
1304 							found = true;
1305 					}
1306 				}
1307 			}
1308 		}
1309 #endif
1310 	if (!mode_option && !found)
1311 		mode_option = "640x480-8@60";
1312 
1313 	/* Prepare startup mode */
1314 	if (mode_option) {
1315 		rc = fb_find_mode(&info->var, info, mode_option,
1316 				   info->monspecs.modedb, info->monspecs.modedb_len,
1317 				   NULL, info->var.bits_per_pixel);
1318 		if (!rc || rc == 4) {
1319 			rc = -EINVAL;
1320 			dev_err(info->device, "mode %s not found\n", mode_option);
1321 			fb_destroy_modedb(info->monspecs.modedb);
1322 			info->monspecs.modedb = NULL;
1323 			goto err_find_mode;
1324 		}
1325 	}
1326 
1327 	fb_destroy_modedb(info->monspecs.modedb);
1328 	info->monspecs.modedb = NULL;
1329 
1330 	/* maximize virtual vertical size for fast scrolling */
1331 	info->var.yres_virtual = info->fix.smem_len * 8 /
1332 			(info->var.bits_per_pixel * info->var.xres_virtual);
1333 	if (info->var.yres_virtual < info->var.yres) {
1334 		dev_err(info->device, "virtual vertical size smaller than real\n");
1335 		rc = -EINVAL;
1336 		goto err_find_mode;
1337 	}
1338 
1339 	rc = fb_alloc_cmap(&info->cmap, 256, 0);
1340 	if (rc < 0) {
1341 		dev_err(info->device, "cannot allocate colormap\n");
1342 		goto err_alloc_cmap;
1343 	}
1344 
1345 	rc = register_framebuffer(info);
1346 	if (rc < 0) {
1347 		dev_err(info->device, "cannot register framebuffer\n");
1348 		goto err_reg_fb;
1349 	}
1350 
1351 	fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n",
1352 		info->fix.id, pci_name(dev),
1353 		info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1354 
1355 	if (par->chip == CHIP_UNKNOWN)
1356 		fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
1357 			vga_rcrt(par->state.vgabase, 0x2d),
1358 			vga_rcrt(par->state.vgabase, 0x2e),
1359 			vga_rcrt(par->state.vgabase, 0x2f),
1360 			vga_rcrt(par->state.vgabase, 0x30));
1361 
1362 	/* Record a reference to the driver data */
1363 	pci_set_drvdata(dev, info);
1364 
1365 	if (mtrr)
1366 		par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1367 						  info->fix.smem_len);
1368 
1369 	return 0;
1370 
1371 	/* Error handling */
1372 err_reg_fb:
1373 	fb_dealloc_cmap(&info->cmap);
1374 err_alloc_cmap:
1375 err_find_mode:
1376 #ifdef CONFIG_FB_S3_DDC
1377 	if (par->ddc_registered)
1378 		i2c_del_adapter(&par->ddc_adapter);
1379 	if (par->mmio)
1380 		iounmap(par->mmio);
1381 #endif
1382 	pci_iounmap(dev, info->screen_base);
1383 err_iomap:
1384 	pci_release_regions(dev);
1385 err_request_regions:
1386 /*	pci_disable_device(dev); */
1387 err_enable_device:
1388 	framebuffer_release(info);
1389 	return rc;
1390 }
1391 
1392 
1393 /* PCI remove */
1394 
s3_pci_remove(struct pci_dev * dev)1395 static void s3_pci_remove(struct pci_dev *dev)
1396 {
1397 	struct fb_info *info = pci_get_drvdata(dev);
1398 	struct s3fb_info __maybe_unused *par;
1399 
1400 	if (info) {
1401 		par = info->par;
1402 		arch_phys_wc_del(par->wc_cookie);
1403 		unregister_framebuffer(info);
1404 		fb_dealloc_cmap(&info->cmap);
1405 
1406 #ifdef CONFIG_FB_S3_DDC
1407 		if (par->ddc_registered)
1408 			i2c_del_adapter(&par->ddc_adapter);
1409 		if (par->mmio)
1410 			iounmap(par->mmio);
1411 #endif
1412 
1413 		pci_iounmap(dev, info->screen_base);
1414 		pci_release_regions(dev);
1415 /*		pci_disable_device(dev); */
1416 
1417 		framebuffer_release(info);
1418 	}
1419 }
1420 
1421 /* PCI suspend */
1422 
s3_pci_suspend(struct device * dev)1423 static int __maybe_unused s3_pci_suspend(struct device *dev)
1424 {
1425 	struct fb_info *info = dev_get_drvdata(dev);
1426 	struct s3fb_info *par = info->par;
1427 
1428 	dev_info(info->device, "suspend\n");
1429 
1430 	console_lock();
1431 	mutex_lock(&(par->open_lock));
1432 
1433 	if (par->ref_count == 0) {
1434 		mutex_unlock(&(par->open_lock));
1435 		console_unlock();
1436 		return 0;
1437 	}
1438 
1439 	fb_set_suspend(info, 1);
1440 
1441 	mutex_unlock(&(par->open_lock));
1442 	console_unlock();
1443 
1444 	return 0;
1445 }
1446 
1447 
1448 /* PCI resume */
1449 
s3_pci_resume(struct device * dev)1450 static int __maybe_unused s3_pci_resume(struct device *dev)
1451 {
1452 	struct fb_info *info = dev_get_drvdata(dev);
1453 	struct s3fb_info *par = info->par;
1454 
1455 	dev_info(info->device, "resume\n");
1456 
1457 	console_lock();
1458 	mutex_lock(&(par->open_lock));
1459 
1460 	if (par->ref_count == 0) {
1461 		mutex_unlock(&(par->open_lock));
1462 		console_unlock();
1463 		return 0;
1464 	}
1465 
1466 	s3fb_set_par(info);
1467 	fb_set_suspend(info, 0);
1468 
1469 	mutex_unlock(&(par->open_lock));
1470 	console_unlock();
1471 
1472 	return 0;
1473 }
1474 
1475 static const struct dev_pm_ops s3_pci_pm_ops = {
1476 #ifdef CONFIG_PM_SLEEP
1477 	.suspend	= s3_pci_suspend,
1478 	.resume		= s3_pci_resume,
1479 	.freeze		= NULL,
1480 	.thaw		= s3_pci_resume,
1481 	.poweroff	= s3_pci_suspend,
1482 	.restore	= s3_pci_resume,
1483 #endif
1484 };
1485 
1486 /* List of boards that we are trying to support */
1487 
1488 static const struct pci_device_id s3_devices[] = {
1489 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1490 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1491 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1492 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1493 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1494 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1495 
1496 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1497 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1498 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1499 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
1500 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
1501 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1502 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
1503 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
1504 	{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
1505 
1506 	{0, 0, 0, 0, 0, 0, 0}
1507 };
1508 
1509 
1510 MODULE_DEVICE_TABLE(pci, s3_devices);
1511 
1512 static struct pci_driver s3fb_pci_driver = {
1513 	.name		= "s3fb",
1514 	.id_table	= s3_devices,
1515 	.probe		= s3_pci_probe,
1516 	.remove		= s3_pci_remove,
1517 	.driver.pm	= &s3_pci_pm_ops,
1518 };
1519 
1520 /* Parse user specified options */
1521 
1522 #ifndef MODULE
s3fb_setup(char * options)1523 static int  __init s3fb_setup(char *options)
1524 {
1525 	char *opt;
1526 
1527 	if (!options || !*options)
1528 		return 0;
1529 
1530 	while ((opt = strsep(&options, ",")) != NULL) {
1531 
1532 		if (!*opt)
1533 			continue;
1534 		else if (!strncmp(opt, "mtrr:", 5))
1535 			mtrr = simple_strtoul(opt + 5, NULL, 0);
1536 		else if (!strncmp(opt, "fasttext:", 9))
1537 			fasttext = simple_strtoul(opt + 9, NULL, 0);
1538 		else
1539 			mode_option = opt;
1540 	}
1541 
1542 	return 0;
1543 }
1544 #endif
1545 
1546 /* Cleanup */
1547 
s3fb_cleanup(void)1548 static void __exit s3fb_cleanup(void)
1549 {
1550 	pr_debug("s3fb: cleaning up\n");
1551 	pci_unregister_driver(&s3fb_pci_driver);
1552 }
1553 
1554 /* Driver Initialisation */
1555 
s3fb_init(void)1556 static int __init s3fb_init(void)
1557 {
1558 
1559 #ifndef MODULE
1560 	char *option = NULL;
1561 #endif
1562 
1563 	if (fb_modesetting_disabled("s3fb"))
1564 		return -ENODEV;
1565 
1566 #ifndef MODULE
1567 	if (fb_get_options("s3fb", &option))
1568 		return -ENODEV;
1569 	s3fb_setup(option);
1570 #endif
1571 
1572 	pr_debug("s3fb: initializing\n");
1573 	return pci_register_driver(&s3fb_pci_driver);
1574 }
1575 
1576 /* ------------------------------------------------------------------------- */
1577 
1578 /* Modularization */
1579 
1580 module_init(s3fb_init);
1581 module_exit(s3fb_cleanup);
1582