1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "wifi.h" 5 #include "core.h" 6 #include "pci.h" 7 #include "base.h" 8 #include "ps.h" 9 #include "efuse.h" 10 #include <linux/interrupt.h> 11 #include <linux/export.h> 12 #include <linux/module.h> 13 14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 17 MODULE_LICENSE("GPL"); 18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 19 20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 21 INTEL_VENDOR_ID, 22 ATI_VENDOR_ID, 23 AMD_VENDOR_ID, 24 SIS_VENDOR_ID 25 }; 26 27 static const u8 ac_to_hwq[] = { 28 VO_QUEUE, 29 VI_QUEUE, 30 BE_QUEUE, 31 BK_QUEUE 32 }; 33 _rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 35 { 36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 37 __le16 fc = rtl_get_fc(skb); 38 u8 queue_index = skb_get_queue_mapping(skb); 39 struct ieee80211_hdr *hdr; 40 41 if (unlikely(ieee80211_is_beacon(fc))) 42 return BEACON_QUEUE; 43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 44 return MGNT_QUEUE; 45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 46 if (ieee80211_is_nullfunc(fc)) 47 return HIGH_QUEUE; 48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 49 hdr = rtl_get_hdr(skb); 50 51 if (is_multicast_ether_addr(hdr->addr1) || 52 is_broadcast_ether_addr(hdr->addr1)) 53 return HIGH_QUEUE; 54 } 55 56 return ac_to_hwq[queue_index]; 57 } 58 59 /* Update PCI dependent default settings*/ _rtl_pci_update_default_setting(struct ieee80211_hw * hw)60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 61 { 62 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 67 u8 init_aspm; 68 69 ppsc->reg_rfps_level = 0; 70 ppsc->support_aspm = false; 71 72 /*Update PCI ASPM setting */ 73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 74 switch (rtlpci->const_pci_aspm) { 75 case 0: 76 /*No ASPM */ 77 break; 78 79 case 1: 80 /*ASPM dynamically enabled/disable. */ 81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 82 break; 83 84 case 2: 85 /*ASPM with Clock Req dynamically enabled/disable. */ 86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 87 RT_RF_OFF_LEVL_CLK_REQ); 88 break; 89 90 case 3: 91 /* Always enable ASPM and Clock Req 92 * from initialization to halt. 93 */ 94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 96 RT_RF_OFF_LEVL_CLK_REQ); 97 break; 98 99 case 4: 100 /* Always enable ASPM without Clock Req 101 * from initialization to halt. 102 */ 103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 104 RT_RF_OFF_LEVL_CLK_REQ); 105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 106 break; 107 } 108 109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 110 111 /*Update Radio OFF setting */ 112 switch (rtlpci->const_hwsw_rfoff_d3) { 113 case 1: 114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 116 break; 117 118 case 2: 119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 122 break; 123 124 case 3: 125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 126 break; 127 } 128 129 /*Set HW definition to determine if it supports ASPM. */ 130 switch (rtlpci->const_support_pciaspm) { 131 case 0: 132 /*Not support ASPM. */ 133 ppsc->support_aspm = false; 134 break; 135 case 1: 136 /*Support ASPM. */ 137 ppsc->support_aspm = true; 138 ppsc->support_backdoor = true; 139 break; 140 case 2: 141 /*ASPM value set by chipset. */ 142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 143 ppsc->support_aspm = true; 144 break; 145 default: 146 pr_err("switch case %#x not processed\n", 147 rtlpci->const_support_pciaspm); 148 break; 149 } 150 151 /* toshiba aspm issue, toshiba will set aspm selfly 152 * so we should not set aspm in driver 153 */ 154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 156 init_aspm == 0x43) 157 ppsc->support_aspm = false; 158 } 159 _rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)160 static bool _rtl_pci_platform_switch_device_pci_aspm( 161 struct ieee80211_hw *hw, 162 u8 value) 163 { 164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 166 167 value &= PCI_EXP_LNKCTL_ASPMC; 168 169 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 170 value |= PCI_EXP_LNKCTL_CCC; 171 172 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 173 PCI_EXP_LNKCTL_ASPMC | value, 174 value); 175 176 return false; 177 } 178 179 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */ _rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u16 value)180 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value) 181 { 182 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 183 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 184 185 value &= PCI_EXP_LNKCTL_CLKREQ_EN; 186 187 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 188 PCI_EXP_LNKCTL_CLKREQ_EN, 189 value); 190 191 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 192 udelay(100); 193 } 194 195 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ rtl_pci_disable_aspm(struct ieee80211_hw * hw)196 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 197 { 198 struct rtl_priv *rtlpriv = rtl_priv(hw); 199 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 200 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 202 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 203 /*Retrieve original configuration settings. */ 204 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 205 u16 aspmlevel = 0; 206 u8 tmp_u1b = 0; 207 208 if (!ppsc->support_aspm) 209 return; 210 211 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 212 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 213 "PCI(Bridge) UNKNOWN\n"); 214 215 return; 216 } 217 218 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 219 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 220 _rtl_pci_switch_clk_req(hw, 0x0); 221 } 222 223 /*for promising device will in L0 state after an I/O. */ 224 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 225 226 /*Set corresponding value. */ 227 aspmlevel |= BIT(0) | BIT(1); 228 linkctrl_reg &= ~aspmlevel; 229 230 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 231 } 232 233 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 234 *power saving We should follow the sequence to enable 235 *RTL8192SE first then enable Pci Bridge ASPM 236 *or the system will show bluescreen. 237 */ rtl_pci_enable_aspm(struct ieee80211_hw * hw)238 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 239 { 240 struct rtl_priv *rtlpriv = rtl_priv(hw); 241 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 242 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 244 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 245 u16 aspmlevel; 246 u8 u_device_aspmsetting; 247 248 if (!ppsc->support_aspm) 249 return; 250 251 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 252 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 253 "PCI(Bridge) UNKNOWN\n"); 254 return; 255 } 256 257 /*Get ASPM level (with/without Clock Req) */ 258 aspmlevel = rtlpci->const_devicepci_aspm_setting; 259 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 260 261 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 262 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 263 264 u_device_aspmsetting |= aspmlevel; 265 266 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 267 268 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 269 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 270 RT_RF_OFF_LEVL_CLK_REQ) ? 271 PCI_EXP_LNKCTL_CLKREQ_EN : 0); 272 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 273 } 274 udelay(100); 275 } 276 rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)277 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 278 { 279 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 280 281 bool status = false; 282 u8 offset_e0; 283 unsigned int offset_e4; 284 285 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 286 287 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 288 289 if (offset_e0 == 0xA0) { 290 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 291 if (offset_e4 & BIT(23)) 292 status = true; 293 } 294 295 return status; 296 } 297 rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)298 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 299 struct ieee80211_hw *hw) 300 { 301 struct rtl_priv *rtlpriv = rtl_priv(hw); 302 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 303 304 u8 tmp; 305 u16 linkctrl_reg; 306 307 /*Link Control Register */ 308 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 309 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 310 311 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 312 pcipriv->ndis_adapter.linkctrl_reg); 313 314 pci_read_config_byte(pdev, 0x98, &tmp); 315 tmp |= BIT(4); 316 pci_write_config_byte(pdev, 0x98, tmp); 317 318 tmp = 0x17; 319 pci_write_config_byte(pdev, 0x70f, tmp); 320 } 321 rtl_pci_init_aspm(struct ieee80211_hw * hw)322 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 323 { 324 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 325 326 _rtl_pci_update_default_setting(hw); 327 328 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 329 /*Always enable ASPM & Clock Req. */ 330 rtl_pci_enable_aspm(hw); 331 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 332 } 333 } 334 _rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)335 static void _rtl_pci_io_handler_init(struct device *dev, 336 struct ieee80211_hw *hw) 337 { 338 struct rtl_priv *rtlpriv = rtl_priv(hw); 339 340 rtlpriv->io.dev = dev; 341 342 rtlpriv->io.write8_async = pci_write8_async; 343 rtlpriv->io.write16_async = pci_write16_async; 344 rtlpriv->io.write32_async = pci_write32_async; 345 346 rtlpriv->io.read8_sync = pci_read8_sync; 347 rtlpriv->io.read16_sync = pci_read16_sync; 348 rtlpriv->io.read32_sync = pci_read32_sync; 349 } 350 _rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)351 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 352 struct sk_buff *skb, 353 struct rtl_tcb_desc *tcb_desc, u8 tid) 354 { 355 struct rtl_priv *rtlpriv = rtl_priv(hw); 356 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 357 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 358 struct sk_buff *next_skb; 359 u8 additionlen = FCS_LEN; 360 361 /* here open is 4, wep/tkip is 8, aes is 12*/ 362 if (info->control.hw_key) 363 additionlen += info->control.hw_key->icv_len; 364 365 /* The most skb num is 6 */ 366 tcb_desc->empkt_num = 0; 367 spin_lock_bh(&rtlpriv->locks.waitq_lock); 368 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 369 struct ieee80211_tx_info *next_info; 370 371 next_info = IEEE80211_SKB_CB(next_skb); 372 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 373 tcb_desc->empkt_len[tcb_desc->empkt_num] = 374 next_skb->len + additionlen; 375 tcb_desc->empkt_num++; 376 } else { 377 break; 378 } 379 380 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 381 next_skb)) 382 break; 383 384 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 385 break; 386 } 387 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 388 389 return true; 390 } 391 392 /* just for early mode now */ _rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)393 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 394 { 395 struct rtl_priv *rtlpriv = rtl_priv(hw); 396 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 397 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 398 struct sk_buff *skb = NULL; 399 struct ieee80211_tx_info *info = NULL; 400 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 401 int tid; 402 403 if (!rtlpriv->rtlhal.earlymode_enable) 404 return; 405 406 /* we just use em for BE/BK/VI/VO */ 407 for (tid = 7; tid >= 0; tid--) { 408 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 409 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 410 411 while (!mac->act_scanning && 412 rtlpriv->psc.rfpwr_state == ERFON) { 413 struct rtl_tcb_desc tcb_desc; 414 415 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 416 417 spin_lock(&rtlpriv->locks.waitq_lock); 418 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 419 (ring->entries - skb_queue_len(&ring->queue) > 420 rtlhal->max_earlymode_num)) { 421 skb = skb_dequeue(&mac->skb_waitq[tid]); 422 } else { 423 spin_unlock(&rtlpriv->locks.waitq_lock); 424 break; 425 } 426 spin_unlock(&rtlpriv->locks.waitq_lock); 427 428 /* Some macaddr can't do early mode. like 429 * multicast/broadcast/no_qos data 430 */ 431 info = IEEE80211_SKB_CB(skb); 432 if (info->flags & IEEE80211_TX_CTL_AMPDU) 433 _rtl_update_earlymode_info(hw, skb, 434 &tcb_desc, tid); 435 436 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 437 } 438 } 439 } 440 _rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)441 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 442 { 443 struct rtl_priv *rtlpriv = rtl_priv(hw); 444 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 445 446 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 447 448 while (skb_queue_len(&ring->queue)) { 449 struct sk_buff *skb; 450 struct ieee80211_tx_info *info; 451 __le16 fc; 452 u8 tid; 453 u8 *entry; 454 455 if (rtlpriv->use_new_trx_flow) 456 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 457 else 458 entry = (u8 *)(&ring->desc[ring->idx]); 459 460 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 461 return; 462 ring->idx = (ring->idx + 1) % ring->entries; 463 464 skb = __skb_dequeue(&ring->queue); 465 dma_unmap_single(&rtlpci->pdev->dev, 466 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 467 true, HW_DESC_TXBUFF_ADDR), 468 skb->len, DMA_TO_DEVICE); 469 470 /* remove early mode header */ 471 if (rtlpriv->rtlhal.earlymode_enable) 472 skb_pull(skb, EM_HDR_LEN); 473 474 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 475 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 476 ring->idx, 477 skb_queue_len(&ring->queue), 478 *(u16 *)(skb->data + 22)); 479 480 if (prio == TXCMD_QUEUE) { 481 dev_kfree_skb(skb); 482 goto tx_status_ok; 483 } 484 485 /* for sw LPS, just after NULL skb send out, we can 486 * sure AP knows we are sleeping, we should not let 487 * rf sleep 488 */ 489 fc = rtl_get_fc(skb); 490 if (ieee80211_is_nullfunc(fc)) { 491 if (ieee80211_has_pm(fc)) { 492 rtlpriv->mac80211.offchan_delay = true; 493 rtlpriv->psc.state_inap = true; 494 } else { 495 rtlpriv->psc.state_inap = false; 496 } 497 } 498 if (ieee80211_is_action(fc)) { 499 struct ieee80211_mgmt *action_frame = 500 (struct ieee80211_mgmt *)skb->data; 501 if (action_frame->u.action.u.ht_smps.action == 502 WLAN_HT_ACTION_SMPS) { 503 dev_kfree_skb(skb); 504 goto tx_status_ok; 505 } 506 } 507 508 /* update tid tx pkt num */ 509 tid = rtl_get_tid(skb); 510 if (tid <= 7) 511 rtlpriv->link_info.tidtx_inperiod[tid]++; 512 513 info = IEEE80211_SKB_CB(skb); 514 515 if (likely(!ieee80211_is_nullfunc(fc))) { 516 ieee80211_tx_info_clear_status(info); 517 info->flags |= IEEE80211_TX_STAT_ACK; 518 /*info->status.rates[0].count = 1; */ 519 ieee80211_tx_status_irqsafe(hw, skb); 520 } else { 521 rtl_tx_ackqueue(hw, skb); 522 } 523 524 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 525 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, 526 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 527 prio, ring->idx, 528 skb_queue_len(&ring->queue)); 529 530 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 531 } 532 tx_status_ok: 533 skb = NULL; 534 } 535 536 if (((rtlpriv->link_info.num_rx_inperiod + 537 rtlpriv->link_info.num_tx_inperiod) > 8) || 538 rtlpriv->link_info.num_rx_inperiod > 2) 539 rtl_lps_leave(hw, false); 540 } 541 _rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)542 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 543 struct sk_buff *new_skb, u8 *entry, 544 int rxring_idx, int desc_idx) 545 { 546 struct rtl_priv *rtlpriv = rtl_priv(hw); 547 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 548 u32 bufferaddress; 549 u8 tmp_one = 1; 550 struct sk_buff *skb; 551 552 if (likely(new_skb)) { 553 skb = new_skb; 554 goto remap; 555 } 556 skb = dev_alloc_skb(rtlpci->rxbuffersize); 557 if (!skb) 558 return 0; 559 560 remap: 561 /* just set skb->cb to mapping addr for pci_unmap_single use */ 562 *((dma_addr_t *)skb->cb) = 563 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb), 564 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 565 bufferaddress = *((dma_addr_t *)skb->cb); 566 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress)) 567 return 0; 568 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 569 if (rtlpriv->use_new_trx_flow) { 570 /* skb->cb may be 64 bit address */ 571 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 572 HW_DESC_RX_PREPARE, 573 (u8 *)(dma_addr_t *)skb->cb); 574 } else { 575 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 576 HW_DESC_RXBUFF_ADDR, 577 (u8 *)&bufferaddress); 578 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 579 HW_DESC_RXPKT_LEN, 580 (u8 *)&rtlpci->rxbuffersize); 581 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 582 HW_DESC_RXOWN, 583 (u8 *)&tmp_one); 584 } 585 return 1; 586 } 587 588 /* inorder to receive 8K AMSDU we have set skb to 589 * 9100bytes in init rx ring, but if this packet is 590 * not a AMSDU, this large packet will be sent to 591 * TCP/IP directly, this cause big packet ping fail 592 * like: "ping -s 65507", so here we will realloc skb 593 * based on the true size of packet, Mac80211 594 * Probably will do it better, but does not yet. 595 * 596 * Some platform will fail when alloc skb sometimes. 597 * in this condition, we will send the old skb to 598 * mac80211 directly, this will not cause any other 599 * issues, but only this packet will be lost by TCP/IP 600 */ _rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)601 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 602 struct sk_buff *skb, 603 struct ieee80211_rx_status rx_status) 604 { 605 if (unlikely(!rtl_action_proc(hw, skb, false))) { 606 dev_kfree_skb_any(skb); 607 } else { 608 struct sk_buff *uskb = NULL; 609 610 uskb = dev_alloc_skb(skb->len + 128); 611 if (likely(uskb)) { 612 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 613 sizeof(rx_status)); 614 skb_put_data(uskb, skb->data, skb->len); 615 dev_kfree_skb_any(skb); 616 ieee80211_rx_irqsafe(hw, uskb); 617 } else { 618 ieee80211_rx_irqsafe(hw, skb); 619 } 620 } 621 } 622 623 /*hsisr interrupt handler*/ _rtl_pci_hs_interrupt(struct ieee80211_hw * hw)624 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 625 { 626 struct rtl_priv *rtlpriv = rtl_priv(hw); 627 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 628 629 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 630 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 631 rtlpci->sys_irq_mask); 632 } 633 _rtl_pci_rx_interrupt(struct ieee80211_hw * hw)634 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 635 { 636 struct rtl_priv *rtlpriv = rtl_priv(hw); 637 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 638 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 639 struct ieee80211_rx_status rx_status = { 0 }; 640 unsigned int count = rtlpci->rxringcount; 641 u8 own; 642 u8 tmp_one; 643 bool unicast = false; 644 u8 hw_queue = 0; 645 unsigned int rx_remained_cnt = 0; 646 struct rtl_stats stats = { 647 .signal = 0, 648 .rate = 0, 649 }; 650 651 /*RX NORMAL PKT */ 652 while (count--) { 653 struct ieee80211_hdr *hdr; 654 __le16 fc; 655 u16 len; 656 /*rx buffer descriptor */ 657 struct rtl_rx_buffer_desc *buffer_desc = NULL; 658 /*if use new trx flow, it means wifi info */ 659 struct rtl_rx_desc *pdesc = NULL; 660 /*rx pkt */ 661 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 662 rtlpci->rx_ring[rxring_idx].idx]; 663 struct sk_buff *new_skb; 664 665 if (rtlpriv->use_new_trx_flow) { 666 if (rx_remained_cnt == 0) 667 rx_remained_cnt = 668 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 669 hw_queue); 670 if (rx_remained_cnt == 0) 671 return; 672 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 673 rtlpci->rx_ring[rxring_idx].idx]; 674 pdesc = (struct rtl_rx_desc *)skb->data; 675 } else { /* rx descriptor */ 676 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 677 rtlpci->rx_ring[rxring_idx].idx]; 678 679 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 680 false, 681 HW_DESC_OWN); 682 if (own) /* wait data to be filled by hardware */ 683 return; 684 } 685 686 /* Reaching this point means: data is filled already 687 * AAAAAAttention !!! 688 * We can NOT access 'skb' before 'pci_unmap_single' 689 */ 690 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 691 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 692 693 /* get a new skb - if fail, old one will be reused */ 694 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 695 if (unlikely(!new_skb)) 696 goto no_new; 697 memset(&rx_status, 0, sizeof(rx_status)); 698 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 699 &rx_status, (u8 *)pdesc, skb); 700 701 if (rtlpriv->use_new_trx_flow) 702 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 703 (u8 *)buffer_desc, 704 hw_queue); 705 706 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 707 HW_DESC_RXPKT_LEN); 708 709 if (skb->end - skb->tail > len) { 710 skb_put(skb, len); 711 if (rtlpriv->use_new_trx_flow) 712 skb_reserve(skb, stats.rx_drvinfo_size + 713 stats.rx_bufshift + 24); 714 else 715 skb_reserve(skb, stats.rx_drvinfo_size + 716 stats.rx_bufshift); 717 } else { 718 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 719 "skb->end - skb->tail = %d, len is %d\n", 720 skb->end - skb->tail, len); 721 dev_kfree_skb_any(skb); 722 goto new_trx_end; 723 } 724 /* handle command packet here */ 725 if (stats.packet_report_type == C2H_PACKET) { 726 rtl_c2hcmd_enqueue(hw, skb); 727 goto new_trx_end; 728 } 729 730 /* NOTICE This can not be use for mac80211, 731 * this is done in mac80211 code, 732 * if done here sec DHCP will fail 733 * skb_trim(skb, skb->len - 4); 734 */ 735 736 hdr = rtl_get_hdr(skb); 737 fc = rtl_get_fc(skb); 738 739 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) { 740 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 741 sizeof(rx_status)); 742 743 if (is_broadcast_ether_addr(hdr->addr1)) { 744 ;/*TODO*/ 745 } else if (is_multicast_ether_addr(hdr->addr1)) { 746 ;/*TODO*/ 747 } else { 748 unicast = true; 749 rtlpriv->stats.rxbytesunicast += skb->len; 750 } 751 rtl_is_special_data(hw, skb, false, true); 752 753 if (ieee80211_is_data(fc)) { 754 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 755 if (unicast) 756 rtlpriv->link_info.num_rx_inperiod++; 757 } 758 759 rtl_collect_scan_list(hw, skb); 760 761 /* static bcn for roaming */ 762 rtl_beacon_statistic(hw, skb); 763 rtl_p2p_info(hw, (void *)skb->data, skb->len); 764 /* for sw lps */ 765 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 766 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 767 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 768 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 769 (ieee80211_is_beacon(fc) || 770 ieee80211_is_probe_resp(fc))) { 771 dev_kfree_skb_any(skb); 772 } else { 773 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 774 } 775 } else { 776 /* drop packets with errors or those too short */ 777 dev_kfree_skb_any(skb); 778 } 779 new_trx_end: 780 if (rtlpriv->use_new_trx_flow) { 781 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 782 rtlpci->rx_ring[hw_queue].next_rx_rp %= 783 RTL_PCI_MAX_RX_COUNT; 784 785 rx_remained_cnt--; 786 rtl_write_word(rtlpriv, 0x3B4, 787 rtlpci->rx_ring[hw_queue].next_rx_rp); 788 } 789 if (((rtlpriv->link_info.num_rx_inperiod + 790 rtlpriv->link_info.num_tx_inperiod) > 8) || 791 rtlpriv->link_info.num_rx_inperiod > 2) 792 rtl_lps_leave(hw, false); 793 skb = new_skb; 794 no_new: 795 if (rtlpriv->use_new_trx_flow) { 796 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 797 rxring_idx, 798 rtlpci->rx_ring[rxring_idx].idx); 799 } else { 800 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 801 rxring_idx, 802 rtlpci->rx_ring[rxring_idx].idx); 803 if (rtlpci->rx_ring[rxring_idx].idx == 804 rtlpci->rxringcount - 1) 805 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 806 false, 807 HW_DESC_RXERO, 808 (u8 *)&tmp_one); 809 } 810 rtlpci->rx_ring[rxring_idx].idx = 811 (rtlpci->rx_ring[rxring_idx].idx + 1) % 812 rtlpci->rxringcount; 813 } 814 } 815 _rtl_pci_interrupt(int irq,void * dev_id)816 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 817 { 818 struct ieee80211_hw *hw = dev_id; 819 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 820 struct rtl_priv *rtlpriv = rtl_priv(hw); 821 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 822 unsigned long flags; 823 struct rtl_int intvec = {0}; 824 825 irqreturn_t ret = IRQ_HANDLED; 826 827 if (rtlpci->irq_enabled == 0) 828 return ret; 829 830 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 831 rtlpriv->cfg->ops->disable_interrupt(hw); 832 833 /*read ISR: 4/8bytes */ 834 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 835 836 /*Shared IRQ or HW disappeared */ 837 if (!intvec.inta || intvec.inta == 0xffff) 838 goto done; 839 840 /*<1> beacon related */ 841 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 842 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 843 "beacon ok interrupt!\n"); 844 845 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 846 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 847 "beacon err interrupt!\n"); 848 849 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 850 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 851 852 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 853 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 854 "prepare beacon for interrupt!\n"); 855 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 856 } 857 858 /*<2> Tx related */ 859 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 860 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 861 862 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 863 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 864 "Manage ok interrupt!\n"); 865 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 866 } 867 868 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 869 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 870 "HIGH_QUEUE ok interrupt!\n"); 871 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 872 } 873 874 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 875 rtlpriv->link_info.num_tx_inperiod++; 876 877 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 878 "BK Tx OK interrupt!\n"); 879 _rtl_pci_tx_isr(hw, BK_QUEUE); 880 } 881 882 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 883 rtlpriv->link_info.num_tx_inperiod++; 884 885 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 886 "BE TX OK interrupt!\n"); 887 _rtl_pci_tx_isr(hw, BE_QUEUE); 888 } 889 890 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 891 rtlpriv->link_info.num_tx_inperiod++; 892 893 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 894 "VI TX OK interrupt!\n"); 895 _rtl_pci_tx_isr(hw, VI_QUEUE); 896 } 897 898 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 899 rtlpriv->link_info.num_tx_inperiod++; 900 901 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 902 "Vo TX OK interrupt!\n"); 903 _rtl_pci_tx_isr(hw, VO_QUEUE); 904 } 905 906 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 907 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 908 rtlpriv->link_info.num_tx_inperiod++; 909 910 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 911 "H2C TX OK interrupt!\n"); 912 _rtl_pci_tx_isr(hw, H2C_QUEUE); 913 } 914 } 915 916 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 917 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 918 rtlpriv->link_info.num_tx_inperiod++; 919 920 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 921 "CMD TX OK interrupt!\n"); 922 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 923 } 924 } 925 926 /*<3> Rx related */ 927 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 928 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 929 _rtl_pci_rx_interrupt(hw); 930 } 931 932 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 933 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 934 "rx descriptor unavailable!\n"); 935 _rtl_pci_rx_interrupt(hw); 936 } 937 938 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 939 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 940 _rtl_pci_rx_interrupt(hw); 941 } 942 943 /*<4> fw related*/ 944 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 945 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 946 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 947 "firmware interrupt!\n"); 948 queue_delayed_work(rtlpriv->works.rtl_wq, 949 &rtlpriv->works.fwevt_wq, 0); 950 } 951 } 952 953 /*<5> hsisr related*/ 954 /* Only 8188EE & 8723BE Supported. 955 * If Other ICs Come in, System will corrupt, 956 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 957 * are not initialized 958 */ 959 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 960 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 961 if (unlikely(intvec.inta & 962 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 963 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 964 "hsisr interrupt!\n"); 965 _rtl_pci_hs_interrupt(hw); 966 } 967 } 968 969 if (rtlpriv->rtlhal.earlymode_enable) 970 tasklet_schedule(&rtlpriv->works.irq_tasklet); 971 972 done: 973 rtlpriv->cfg->ops->enable_interrupt(hw); 974 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 975 return ret; 976 } 977 _rtl_pci_irq_tasklet(struct tasklet_struct * t)978 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t) 979 { 980 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet); 981 struct ieee80211_hw *hw = rtlpriv->hw; 982 _rtl_pci_tx_chk_waitq(hw); 983 } 984 _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct * t)985 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t) 986 { 987 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, 988 works.irq_prepare_bcn_tasklet); 989 struct ieee80211_hw *hw = rtlpriv->hw; 990 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 991 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 992 struct rtl8192_tx_ring *ring = NULL; 993 struct ieee80211_hdr *hdr = NULL; 994 struct ieee80211_tx_info *info = NULL; 995 struct sk_buff *pskb = NULL; 996 struct rtl_tx_desc *pdesc = NULL; 997 struct rtl_tcb_desc tcb_desc; 998 /*This is for new trx flow*/ 999 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1000 u8 temp_one = 1; 1001 u8 *entry; 1002 1003 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1004 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1005 pskb = __skb_dequeue(&ring->queue); 1006 if (rtlpriv->use_new_trx_flow) 1007 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1008 else 1009 entry = (u8 *)(&ring->desc[ring->idx]); 1010 if (pskb) { 1011 dma_unmap_single(&rtlpci->pdev->dev, 1012 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1013 true, HW_DESC_TXBUFF_ADDR), 1014 pskb->len, DMA_TO_DEVICE); 1015 kfree_skb(pskb); 1016 } 1017 1018 /*NB: the beacon data buffer must be 32-bit aligned. */ 1019 pskb = ieee80211_beacon_get(hw, mac->vif, 0); 1020 if (!pskb) 1021 return; 1022 hdr = rtl_get_hdr(pskb); 1023 info = IEEE80211_SKB_CB(pskb); 1024 pdesc = &ring->desc[0]; 1025 if (rtlpriv->use_new_trx_flow) 1026 pbuffer_desc = &ring->buffer_desc[0]; 1027 1028 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1029 (u8 *)pbuffer_desc, info, NULL, pskb, 1030 BEACON_QUEUE, &tcb_desc); 1031 1032 __skb_queue_tail(&ring->queue, pskb); 1033 1034 if (rtlpriv->use_new_trx_flow) { 1035 temp_one = 4; 1036 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1037 HW_DESC_OWN, (u8 *)&temp_one); 1038 } else { 1039 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1040 &temp_one); 1041 } 1042 } 1043 _rtl_pci_init_trx_var(struct ieee80211_hw * hw)1044 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1045 { 1046 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1047 struct rtl_priv *rtlpriv = rtl_priv(hw); 1048 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1049 u8 i; 1050 u16 desc_num; 1051 1052 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1053 desc_num = TX_DESC_NUM_92E; 1054 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1055 desc_num = TX_DESC_NUM_8822B; 1056 else 1057 desc_num = RT_TXDESC_NUM; 1058 1059 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1060 rtlpci->txringcount[i] = desc_num; 1061 1062 /*we just alloc 2 desc for beacon queue, 1063 *because we just need first desc in hw beacon. 1064 */ 1065 rtlpci->txringcount[BEACON_QUEUE] = 2; 1066 1067 /*BE queue need more descriptor for performance 1068 *consideration or, No more tx desc will happen, 1069 *and may cause mac80211 mem leakage. 1070 */ 1071 if (!rtl_priv(hw)->use_new_trx_flow) 1072 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1073 1074 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1075 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1076 } 1077 _rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1078 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1079 struct pci_dev *pdev) 1080 { 1081 struct rtl_priv *rtlpriv = rtl_priv(hw); 1082 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1083 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1084 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1085 1086 rtlpci->up_first_time = true; 1087 rtlpci->being_init_adapter = false; 1088 1089 rtlhal->hw = hw; 1090 rtlpci->pdev = pdev; 1091 1092 /*Tx/Rx related var */ 1093 _rtl_pci_init_trx_var(hw); 1094 1095 /*IBSS*/ 1096 mac->beacon_interval = 100; 1097 1098 /*AMPDU*/ 1099 mac->min_space_cfg = 0; 1100 mac->max_mss_density = 0; 1101 /*set sane AMPDU defaults */ 1102 mac->current_ampdu_density = 7; 1103 mac->current_ampdu_factor = 3; 1104 1105 /*Retry Limit*/ 1106 mac->retry_short = 7; 1107 mac->retry_long = 7; 1108 1109 /*QOS*/ 1110 rtlpci->acm_method = EACMWAY2_SW; 1111 1112 /*task */ 1113 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet); 1114 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet, 1115 _rtl_pci_prepare_bcn_tasklet); 1116 INIT_WORK(&rtlpriv->works.lps_change_work, 1117 rtl_lps_change_work_callback); 1118 } 1119 _rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1120 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1121 unsigned int prio, unsigned int entries) 1122 { 1123 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1124 struct rtl_priv *rtlpriv = rtl_priv(hw); 1125 struct rtl_tx_buffer_desc *buffer_desc; 1126 struct rtl_tx_desc *desc; 1127 dma_addr_t buffer_desc_dma, desc_dma; 1128 u32 nextdescaddress; 1129 int i; 1130 1131 /* alloc tx buffer desc for new trx flow*/ 1132 if (rtlpriv->use_new_trx_flow) { 1133 buffer_desc = 1134 dma_alloc_coherent(&rtlpci->pdev->dev, 1135 sizeof(*buffer_desc) * entries, 1136 &buffer_desc_dma, GFP_KERNEL); 1137 1138 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1139 pr_err("Cannot allocate TX ring (prio = %d)\n", 1140 prio); 1141 return -ENOMEM; 1142 } 1143 1144 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1145 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1146 1147 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1148 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1149 } 1150 1151 /* alloc dma for this ring */ 1152 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries, 1153 &desc_dma, GFP_KERNEL); 1154 1155 if (!desc || (unsigned long)desc & 0xFF) { 1156 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1157 return -ENOMEM; 1158 } 1159 1160 rtlpci->tx_ring[prio].desc = desc; 1161 rtlpci->tx_ring[prio].dma = desc_dma; 1162 1163 rtlpci->tx_ring[prio].idx = 0; 1164 rtlpci->tx_ring[prio].entries = entries; 1165 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1166 1167 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1168 prio, desc); 1169 1170 /* init every desc in this ring */ 1171 if (!rtlpriv->use_new_trx_flow) { 1172 for (i = 0; i < entries; i++) { 1173 nextdescaddress = (u32)desc_dma + 1174 ((i + 1) % entries) * 1175 sizeof(*desc); 1176 1177 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1178 true, 1179 HW_DESC_TX_NEXTDESC_ADDR, 1180 (u8 *)&nextdescaddress); 1181 } 1182 } 1183 return 0; 1184 } 1185 _rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1186 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1187 { 1188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1189 struct rtl_priv *rtlpriv = rtl_priv(hw); 1190 int i; 1191 1192 if (rtlpriv->use_new_trx_flow) { 1193 struct rtl_rx_buffer_desc *entry = NULL; 1194 /* alloc dma for this ring */ 1195 rtlpci->rx_ring[rxring_idx].buffer_desc = 1196 dma_alloc_coherent(&rtlpci->pdev->dev, 1197 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1198 rtlpci->rxringcount, 1199 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1200 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1201 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1202 pr_err("Cannot allocate RX ring\n"); 1203 return -ENOMEM; 1204 } 1205 1206 /* init every desc in this ring */ 1207 rtlpci->rx_ring[rxring_idx].idx = 0; 1208 for (i = 0; i < rtlpci->rxringcount; i++) { 1209 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1210 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1211 rxring_idx, i)) 1212 return -ENOMEM; 1213 } 1214 } else { 1215 struct rtl_rx_desc *entry = NULL; 1216 u8 tmp_one = 1; 1217 /* alloc dma for this ring */ 1218 rtlpci->rx_ring[rxring_idx].desc = 1219 dma_alloc_coherent(&rtlpci->pdev->dev, 1220 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1221 rtlpci->rxringcount, 1222 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1223 if (!rtlpci->rx_ring[rxring_idx].desc || 1224 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1225 pr_err("Cannot allocate RX ring\n"); 1226 return -ENOMEM; 1227 } 1228 1229 /* init every desc in this ring */ 1230 rtlpci->rx_ring[rxring_idx].idx = 0; 1231 1232 for (i = 0; i < rtlpci->rxringcount; i++) { 1233 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1234 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1235 rxring_idx, i)) 1236 return -ENOMEM; 1237 } 1238 1239 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1240 HW_DESC_RXERO, &tmp_one); 1241 } 1242 return 0; 1243 } 1244 _rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1245 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1246 unsigned int prio) 1247 { 1248 struct rtl_priv *rtlpriv = rtl_priv(hw); 1249 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1250 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1251 1252 /* free every desc in this ring */ 1253 while (skb_queue_len(&ring->queue)) { 1254 u8 *entry; 1255 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1256 1257 if (rtlpriv->use_new_trx_flow) 1258 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1259 else 1260 entry = (u8 *)(&ring->desc[ring->idx]); 1261 1262 dma_unmap_single(&rtlpci->pdev->dev, 1263 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1264 true, HW_DESC_TXBUFF_ADDR), 1265 skb->len, DMA_TO_DEVICE); 1266 kfree_skb(skb); 1267 ring->idx = (ring->idx + 1) % ring->entries; 1268 } 1269 1270 /* free dma of this ring */ 1271 dma_free_coherent(&rtlpci->pdev->dev, 1272 sizeof(*ring->desc) * ring->entries, ring->desc, 1273 ring->dma); 1274 ring->desc = NULL; 1275 if (rtlpriv->use_new_trx_flow) { 1276 dma_free_coherent(&rtlpci->pdev->dev, 1277 sizeof(*ring->buffer_desc) * ring->entries, 1278 ring->buffer_desc, ring->buffer_desc_dma); 1279 ring->buffer_desc = NULL; 1280 } 1281 } 1282 _rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1283 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1284 { 1285 struct rtl_priv *rtlpriv = rtl_priv(hw); 1286 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1287 int i; 1288 1289 /* free every desc in this ring */ 1290 for (i = 0; i < rtlpci->rxringcount; i++) { 1291 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1292 1293 if (!skb) 1294 continue; 1295 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 1296 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 1297 kfree_skb(skb); 1298 } 1299 1300 /* free dma of this ring */ 1301 if (rtlpriv->use_new_trx_flow) { 1302 dma_free_coherent(&rtlpci->pdev->dev, 1303 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1304 rtlpci->rxringcount, 1305 rtlpci->rx_ring[rxring_idx].buffer_desc, 1306 rtlpci->rx_ring[rxring_idx].dma); 1307 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1308 } else { 1309 dma_free_coherent(&rtlpci->pdev->dev, 1310 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1311 rtlpci->rxringcount, 1312 rtlpci->rx_ring[rxring_idx].desc, 1313 rtlpci->rx_ring[rxring_idx].dma); 1314 rtlpci->rx_ring[rxring_idx].desc = NULL; 1315 } 1316 } 1317 _rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1318 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1319 { 1320 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1321 int ret; 1322 int i, rxring_idx; 1323 1324 /* rxring_idx 0:RX_MPDU_QUEUE 1325 * rxring_idx 1:RX_CMD_QUEUE 1326 */ 1327 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1328 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1329 if (ret) 1330 return ret; 1331 } 1332 1333 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1334 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1335 if (ret) 1336 goto err_free_rings; 1337 } 1338 1339 return 0; 1340 1341 err_free_rings: 1342 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1343 _rtl_pci_free_rx_ring(hw, rxring_idx); 1344 1345 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1346 if (rtlpci->tx_ring[i].desc || 1347 rtlpci->tx_ring[i].buffer_desc) 1348 _rtl_pci_free_tx_ring(hw, i); 1349 1350 return 1; 1351 } 1352 _rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1353 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1354 { 1355 u32 i, rxring_idx; 1356 1357 /*free rx rings */ 1358 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1359 _rtl_pci_free_rx_ring(hw, rxring_idx); 1360 1361 /*free tx rings */ 1362 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1363 _rtl_pci_free_tx_ring(hw, i); 1364 1365 return 0; 1366 } 1367 rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1368 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1369 { 1370 struct rtl_priv *rtlpriv = rtl_priv(hw); 1371 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1372 int i, rxring_idx; 1373 unsigned long flags; 1374 u8 tmp_one = 1; 1375 u32 bufferaddress; 1376 /* rxring_idx 0:RX_MPDU_QUEUE */ 1377 /* rxring_idx 1:RX_CMD_QUEUE */ 1378 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1379 /* force the rx_ring[RX_MPDU_QUEUE/ 1380 * RX_CMD_QUEUE].idx to the first one 1381 *new trx flow, do nothing 1382 */ 1383 if (!rtlpriv->use_new_trx_flow && 1384 rtlpci->rx_ring[rxring_idx].desc) { 1385 struct rtl_rx_desc *entry = NULL; 1386 1387 rtlpci->rx_ring[rxring_idx].idx = 0; 1388 for (i = 0; i < rtlpci->rxringcount; i++) { 1389 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1390 bufferaddress = 1391 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1392 false, HW_DESC_RXBUFF_ADDR); 1393 memset((u8 *)entry, 0, 1394 sizeof(*rtlpci->rx_ring 1395 [rxring_idx].desc));/*clear one entry*/ 1396 if (rtlpriv->use_new_trx_flow) { 1397 rtlpriv->cfg->ops->set_desc(hw, 1398 (u8 *)entry, false, 1399 HW_DESC_RX_PREPARE, 1400 (u8 *)&bufferaddress); 1401 } else { 1402 rtlpriv->cfg->ops->set_desc(hw, 1403 (u8 *)entry, false, 1404 HW_DESC_RXBUFF_ADDR, 1405 (u8 *)&bufferaddress); 1406 rtlpriv->cfg->ops->set_desc(hw, 1407 (u8 *)entry, false, 1408 HW_DESC_RXPKT_LEN, 1409 (u8 *)&rtlpci->rxbuffersize); 1410 rtlpriv->cfg->ops->set_desc(hw, 1411 (u8 *)entry, false, 1412 HW_DESC_RXOWN, 1413 (u8 *)&tmp_one); 1414 } 1415 } 1416 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1417 HW_DESC_RXERO, (u8 *)&tmp_one); 1418 } 1419 rtlpci->rx_ring[rxring_idx].idx = 0; 1420 } 1421 1422 /*after reset, release previous pending packet, 1423 *and force the tx idx to the first one 1424 */ 1425 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1426 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1427 if (rtlpci->tx_ring[i].desc || 1428 rtlpci->tx_ring[i].buffer_desc) { 1429 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1430 1431 while (skb_queue_len(&ring->queue)) { 1432 u8 *entry; 1433 struct sk_buff *skb = 1434 __skb_dequeue(&ring->queue); 1435 if (rtlpriv->use_new_trx_flow) 1436 entry = (u8 *)(&ring->buffer_desc 1437 [ring->idx]); 1438 else 1439 entry = (u8 *)(&ring->desc[ring->idx]); 1440 1441 dma_unmap_single(&rtlpci->pdev->dev, 1442 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1443 true, HW_DESC_TXBUFF_ADDR), 1444 skb->len, DMA_TO_DEVICE); 1445 dev_kfree_skb_irq(skb); 1446 ring->idx = (ring->idx + 1) % ring->entries; 1447 } 1448 1449 if (rtlpriv->use_new_trx_flow) { 1450 rtlpci->tx_ring[i].cur_tx_rp = 0; 1451 rtlpci->tx_ring[i].cur_tx_wp = 0; 1452 } 1453 1454 ring->idx = 0; 1455 ring->entries = rtlpci->txringcount[i]; 1456 } 1457 } 1458 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1459 1460 return 0; 1461 } 1462 rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1463 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1464 struct ieee80211_sta *sta, 1465 struct sk_buff *skb) 1466 { 1467 struct rtl_priv *rtlpriv = rtl_priv(hw); 1468 struct rtl_sta_info *sta_entry = NULL; 1469 u8 tid = rtl_get_tid(skb); 1470 __le16 fc = rtl_get_fc(skb); 1471 1472 if (!sta) 1473 return false; 1474 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1475 1476 if (!rtlpriv->rtlhal.earlymode_enable) 1477 return false; 1478 if (ieee80211_is_nullfunc(fc)) 1479 return false; 1480 if (ieee80211_is_qos_nullfunc(fc)) 1481 return false; 1482 if (ieee80211_is_pspoll(fc)) 1483 return false; 1484 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1485 return false; 1486 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1487 return false; 1488 if (tid > 7) 1489 return false; 1490 1491 /* maybe every tid should be checked */ 1492 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1493 return false; 1494 1495 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1496 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1497 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1498 1499 return true; 1500 } 1501 rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1502 static int rtl_pci_tx(struct ieee80211_hw *hw, 1503 struct ieee80211_sta *sta, 1504 struct sk_buff *skb, 1505 struct rtl_tcb_desc *ptcb_desc) 1506 { 1507 struct rtl_priv *rtlpriv = rtl_priv(hw); 1508 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1509 struct rtl8192_tx_ring *ring; 1510 struct rtl_tx_desc *pdesc; 1511 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1512 u16 idx; 1513 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1514 unsigned long flags; 1515 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1516 __le16 fc = rtl_get_fc(skb); 1517 u8 *pda_addr = hdr->addr1; 1518 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1519 u8 own; 1520 u8 temp_one = 1; 1521 1522 if (ieee80211_is_mgmt(fc)) 1523 rtl_tx_mgmt_proc(hw, skb); 1524 1525 if (rtlpriv->psc.sw_ps_enabled) { 1526 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1527 !ieee80211_has_pm(fc)) 1528 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1529 } 1530 1531 rtl_action_proc(hw, skb, true); 1532 1533 if (is_multicast_ether_addr(pda_addr)) 1534 rtlpriv->stats.txbytesmulticast += skb->len; 1535 else if (is_broadcast_ether_addr(pda_addr)) 1536 rtlpriv->stats.txbytesbroadcast += skb->len; 1537 else 1538 rtlpriv->stats.txbytesunicast += skb->len; 1539 1540 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1541 ring = &rtlpci->tx_ring[hw_queue]; 1542 if (hw_queue != BEACON_QUEUE) { 1543 if (rtlpriv->use_new_trx_flow) 1544 idx = ring->cur_tx_wp; 1545 else 1546 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1547 ring->entries; 1548 } else { 1549 idx = 0; 1550 } 1551 1552 pdesc = &ring->desc[idx]; 1553 if (rtlpriv->use_new_trx_flow) { 1554 ptx_bd_desc = &ring->buffer_desc[idx]; 1555 } else { 1556 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1557 true, HW_DESC_OWN); 1558 1559 if (own == 1 && hw_queue != BEACON_QUEUE) { 1560 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1561 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1562 hw_queue, ring->idx, idx, 1563 skb_queue_len(&ring->queue)); 1564 1565 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1566 flags); 1567 return skb->len; 1568 } 1569 } 1570 1571 if (rtlpriv->cfg->ops->get_available_desc && 1572 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1573 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1574 "get_available_desc fail\n"); 1575 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1576 return skb->len; 1577 } 1578 1579 if (ieee80211_is_data(fc)) 1580 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1581 1582 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1583 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1584 1585 __skb_queue_tail(&ring->queue, skb); 1586 1587 if (rtlpriv->use_new_trx_flow) { 1588 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1589 HW_DESC_OWN, &hw_queue); 1590 } else { 1591 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1592 HW_DESC_OWN, &temp_one); 1593 } 1594 1595 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1596 hw_queue != BEACON_QUEUE) { 1597 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1598 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1599 hw_queue, ring->idx, idx, 1600 skb_queue_len(&ring->queue)); 1601 1602 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1603 } 1604 1605 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1606 1607 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1608 1609 return 0; 1610 } 1611 rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1612 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1613 { 1614 struct rtl_priv *rtlpriv = rtl_priv(hw); 1615 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1616 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1617 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1618 u16 i = 0; 1619 int queue_id; 1620 struct rtl8192_tx_ring *ring; 1621 1622 if (mac->skip_scan) 1623 return; 1624 1625 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1626 u32 queue_len; 1627 1628 if (((queues >> queue_id) & 0x1) == 0) { 1629 queue_id--; 1630 continue; 1631 } 1632 ring = &pcipriv->dev.tx_ring[queue_id]; 1633 queue_len = skb_queue_len(&ring->queue); 1634 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1635 queue_id == TXCMD_QUEUE) { 1636 queue_id--; 1637 continue; 1638 } else { 1639 msleep(20); 1640 i++; 1641 } 1642 1643 /* we just wait 1s for all queues */ 1644 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1645 is_hal_stop(rtlhal) || i >= 200) 1646 return; 1647 } 1648 } 1649 rtl_pci_deinit(struct ieee80211_hw * hw)1650 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1651 { 1652 struct rtl_priv *rtlpriv = rtl_priv(hw); 1653 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1654 1655 _rtl_pci_deinit_trx_ring(hw); 1656 1657 synchronize_irq(rtlpci->pdev->irq); 1658 tasklet_kill(&rtlpriv->works.irq_tasklet); 1659 cancel_work_sync(&rtlpriv->works.lps_change_work); 1660 } 1661 rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1662 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1663 { 1664 int err; 1665 1666 _rtl_pci_init_struct(hw, pdev); 1667 1668 err = _rtl_pci_init_trx_ring(hw); 1669 if (err) { 1670 pr_err("tx ring initialization failed\n"); 1671 return err; 1672 } 1673 1674 return 0; 1675 } 1676 rtl_pci_start(struct ieee80211_hw * hw)1677 static int rtl_pci_start(struct ieee80211_hw *hw) 1678 { 1679 struct rtl_priv *rtlpriv = rtl_priv(hw); 1680 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1681 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1682 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1683 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1684 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1685 1686 int err; 1687 1688 rtl_pci_reset_trx_ring(hw); 1689 1690 rtlpci->driver_is_goingto_unload = false; 1691 if (rtlpriv->cfg->ops->get_btc_status && 1692 rtlpriv->cfg->ops->get_btc_status()) { 1693 rtlpriv->btcoexist.btc_info.ap_num = 36; 1694 btc_ops->btc_init_variables(rtlpriv); 1695 btc_ops->btc_init_hal_vars(rtlpriv); 1696 } else if (btc_ops) { 1697 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1698 } 1699 1700 err = rtlpriv->cfg->ops->hw_init(hw); 1701 if (err) { 1702 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1703 "Failed to config hardware!\n"); 1704 kfree(rtlpriv->btcoexist.btc_context); 1705 kfree(rtlpriv->btcoexist.wifi_only_context); 1706 return err; 1707 } 1708 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1709 &rtlmac->retry_long); 1710 1711 rtlpriv->cfg->ops->enable_interrupt(hw); 1712 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1713 1714 rtl_init_rx_config(hw); 1715 1716 /*should be after adapter start and interrupt enable. */ 1717 set_hal_start(rtlhal); 1718 1719 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1720 1721 rtlpci->up_first_time = false; 1722 1723 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1724 return 0; 1725 } 1726 rtl_pci_stop(struct ieee80211_hw * hw)1727 static void rtl_pci_stop(struct ieee80211_hw *hw) 1728 { 1729 struct rtl_priv *rtlpriv = rtl_priv(hw); 1730 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1731 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1732 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1733 unsigned long flags; 1734 u8 rf_timeout = 0; 1735 1736 if (rtlpriv->cfg->ops->get_btc_status()) 1737 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1738 1739 if (rtlpriv->btcoexist.btc_ops) 1740 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1741 1742 /*should be before disable interrupt&adapter 1743 *and will do it immediately. 1744 */ 1745 set_hal_stop(rtlhal); 1746 1747 rtlpci->driver_is_goingto_unload = true; 1748 rtlpriv->cfg->ops->disable_interrupt(hw); 1749 cancel_work_sync(&rtlpriv->works.lps_change_work); 1750 1751 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1752 while (ppsc->rfchange_inprogress) { 1753 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1754 if (rf_timeout > 100) { 1755 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1756 break; 1757 } 1758 mdelay(1); 1759 rf_timeout++; 1760 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1761 } 1762 ppsc->rfchange_inprogress = true; 1763 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1764 1765 rtlpriv->cfg->ops->hw_disable(hw); 1766 /* some things are not needed if firmware not available */ 1767 if (!rtlpriv->max_fw_size) 1768 return; 1769 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1770 1771 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1772 ppsc->rfchange_inprogress = false; 1773 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1774 1775 rtl_pci_enable_aspm(hw); 1776 } 1777 _rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1778 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1779 struct ieee80211_hw *hw) 1780 { 1781 struct rtl_priv *rtlpriv = rtl_priv(hw); 1782 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1783 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1784 struct pci_dev *bridge_pdev = pdev->bus->self; 1785 u16 venderid; 1786 u16 deviceid; 1787 u8 revisionid; 1788 u16 irqline; 1789 u8 tmp; 1790 1791 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1792 venderid = pdev->vendor; 1793 deviceid = pdev->device; 1794 pci_read_config_byte(pdev, 0x8, &revisionid); 1795 pci_read_config_word(pdev, 0x3C, &irqline); 1796 1797 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1798 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1799 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1800 * the correct driver is r8192e_pci, thus this routine should 1801 * return false. 1802 */ 1803 if (deviceid == RTL_PCI_8192SE_DID && 1804 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1805 return false; 1806 1807 if (deviceid == RTL_PCI_8192_DID || 1808 deviceid == RTL_PCI_0044_DID || 1809 deviceid == RTL_PCI_0047_DID || 1810 deviceid == RTL_PCI_8192SE_DID || 1811 deviceid == RTL_PCI_8174_DID || 1812 deviceid == RTL_PCI_8173_DID || 1813 deviceid == RTL_PCI_8172_DID || 1814 deviceid == RTL_PCI_8171_DID) { 1815 switch (revisionid) { 1816 case RTL_PCI_REVISION_ID_8192PCIE: 1817 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1818 "8192 PCI-E is found - vid/did=%x/%x\n", 1819 venderid, deviceid); 1820 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1821 return false; 1822 case RTL_PCI_REVISION_ID_8192SE: 1823 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1824 "8192SE is found - vid/did=%x/%x\n", 1825 venderid, deviceid); 1826 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1827 break; 1828 default: 1829 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1830 "Err: Unknown device - vid/did=%x/%x\n", 1831 venderid, deviceid); 1832 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1833 break; 1834 } 1835 } else if (deviceid == RTL_PCI_8723AE_DID) { 1836 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1837 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1838 "8723AE PCI-E is found - vid/did=%x/%x\n", 1839 venderid, deviceid); 1840 } else if (deviceid == RTL_PCI_8192CET_DID || 1841 deviceid == RTL_PCI_8192CE_DID || 1842 deviceid == RTL_PCI_8191CE_DID || 1843 deviceid == RTL_PCI_8188CE_DID) { 1844 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1845 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1846 "8192C PCI-E is found - vid/did=%x/%x\n", 1847 venderid, deviceid); 1848 } else if (deviceid == RTL_PCI_8192DE_DID || 1849 deviceid == RTL_PCI_8192DE_DID2) { 1850 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1851 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1852 "8192D PCI-E is found - vid/did=%x/%x\n", 1853 venderid, deviceid); 1854 } else if (deviceid == RTL_PCI_8188EE_DID) { 1855 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1856 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1857 "Find adapter, Hardware type is 8188EE\n"); 1858 } else if (deviceid == RTL_PCI_8723BE_DID) { 1859 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1860 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1861 "Find adapter, Hardware type is 8723BE\n"); 1862 } else if (deviceid == RTL_PCI_8192EE_DID) { 1863 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1864 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1865 "Find adapter, Hardware type is 8192EE\n"); 1866 } else if (deviceid == RTL_PCI_8821AE_DID) { 1867 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1868 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1869 "Find adapter, Hardware type is 8821AE\n"); 1870 } else if (deviceid == RTL_PCI_8812AE_DID) { 1871 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1872 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1873 "Find adapter, Hardware type is 8812AE\n"); 1874 } else if (deviceid == RTL_PCI_8822BE_DID) { 1875 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1876 rtlhal->bandset = BAND_ON_BOTH; 1877 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1878 "Find adapter, Hardware type is 8822BE\n"); 1879 } else { 1880 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1881 "Err: Unknown device - vid/did=%x/%x\n", 1882 venderid, deviceid); 1883 1884 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1885 } 1886 1887 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1888 if (revisionid == 0 || revisionid == 1) { 1889 if (revisionid == 0) { 1890 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1891 "Find 92DE MAC0\n"); 1892 rtlhal->interfaceindex = 0; 1893 } else if (revisionid == 1) { 1894 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1895 "Find 92DE MAC1\n"); 1896 rtlhal->interfaceindex = 1; 1897 } 1898 } else { 1899 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1900 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 1901 venderid, deviceid, revisionid); 1902 rtlhal->interfaceindex = 0; 1903 } 1904 } 1905 1906 switch (rtlhal->hw_type) { 1907 case HARDWARE_TYPE_RTL8192EE: 1908 case HARDWARE_TYPE_RTL8822BE: 1909 /* use new trx flow */ 1910 rtlpriv->use_new_trx_flow = true; 1911 break; 1912 1913 default: 1914 rtlpriv->use_new_trx_flow = false; 1915 break; 1916 } 1917 1918 /*find bus info */ 1919 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 1920 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 1921 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 1922 1923 /*find bridge info */ 1924 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1925 /* some ARM have no bridge_pdev and will crash here 1926 * so we should check if bridge_pdev is NULL 1927 */ 1928 if (bridge_pdev) { 1929 /*find bridge info if available */ 1930 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 1931 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 1932 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 1933 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 1934 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1935 "Pci Bridge Vendor is found index: %d\n", 1936 tmp); 1937 break; 1938 } 1939 } 1940 } 1941 1942 if (pcipriv->ndis_adapter.pcibridge_vendor != 1943 PCI_BRIDGE_VENDOR_UNKNOWN) { 1944 pcipriv->ndis_adapter.pcibridge_busnum = 1945 bridge_pdev->bus->number; 1946 pcipriv->ndis_adapter.pcibridge_devnum = 1947 PCI_SLOT(bridge_pdev->devfn); 1948 pcipriv->ndis_adapter.pcibridge_funcnum = 1949 PCI_FUNC(bridge_pdev->devfn); 1950 1951 if (pcipriv->ndis_adapter.pcibridge_vendor == 1952 PCI_BRIDGE_VENDOR_AMD) { 1953 pcipriv->ndis_adapter.amd_l1_patch = 1954 rtl_pci_get_amd_l1_patch(hw); 1955 } 1956 } 1957 1958 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1959 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 1960 pcipriv->ndis_adapter.busnumber, 1961 pcipriv->ndis_adapter.devnumber, 1962 pcipriv->ndis_adapter.funcnumber, 1963 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 1964 1965 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1966 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n", 1967 pcipriv->ndis_adapter.pcibridge_busnum, 1968 pcipriv->ndis_adapter.pcibridge_devnum, 1969 pcipriv->ndis_adapter.pcibridge_funcnum, 1970 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 1971 pcipriv->ndis_adapter.amd_l1_patch); 1972 1973 rtl_pci_parse_configuration(pdev, hw); 1974 1975 return true; 1976 } 1977 rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)1978 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 1979 { 1980 struct rtl_priv *rtlpriv = rtl_priv(hw); 1981 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1982 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 1983 int ret; 1984 1985 ret = pci_enable_msi(rtlpci->pdev); 1986 if (ret < 0) 1987 return ret; 1988 1989 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 1990 IRQF_SHARED, KBUILD_MODNAME, hw); 1991 if (ret < 0) { 1992 pci_disable_msi(rtlpci->pdev); 1993 return ret; 1994 } 1995 1996 rtlpci->using_msi = true; 1997 1998 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 1999 "MSI Interrupt Mode!\n"); 2000 return 0; 2001 } 2002 rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2003 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2004 { 2005 struct rtl_priv *rtlpriv = rtl_priv(hw); 2006 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2007 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2008 int ret; 2009 2010 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2011 IRQF_SHARED, KBUILD_MODNAME, hw); 2012 if (ret < 0) 2013 return ret; 2014 2015 rtlpci->using_msi = false; 2016 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2017 "Pin-based Interrupt Mode!\n"); 2018 return 0; 2019 } 2020 rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2021 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2022 { 2023 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2024 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2025 int ret; 2026 2027 if (rtlpci->msi_support) { 2028 ret = rtl_pci_intr_mode_msi(hw); 2029 if (ret < 0) 2030 ret = rtl_pci_intr_mode_legacy(hw); 2031 } else { 2032 ret = rtl_pci_intr_mode_legacy(hw); 2033 } 2034 return ret; 2035 } 2036 platform_enable_dma64(struct pci_dev * pdev,bool dma64)2037 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2038 { 2039 u8 value; 2040 2041 pci_read_config_byte(pdev, 0x719, &value); 2042 2043 /* 0x719 Bit5 is DMA64 bit fetch. */ 2044 if (dma64) 2045 value |= BIT(5); 2046 else 2047 value &= ~BIT(5); 2048 2049 pci_write_config_byte(pdev, 0x719, value); 2050 } 2051 rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2052 int rtl_pci_probe(struct pci_dev *pdev, 2053 const struct pci_device_id *id) 2054 { 2055 struct ieee80211_hw *hw = NULL; 2056 2057 struct rtl_priv *rtlpriv = NULL; 2058 struct rtl_pci_priv *pcipriv = NULL; 2059 struct rtl_pci *rtlpci; 2060 unsigned long pmem_start, pmem_len, pmem_flags; 2061 int err; 2062 2063 err = pci_enable_device(pdev); 2064 if (err) { 2065 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2066 pci_name(pdev)); 2067 return err; 2068 } 2069 2070 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2071 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2072 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2073 WARN_ONCE(true, 2074 "Unable to obtain 64bit DMA for consistent allocations\n"); 2075 err = -ENOMEM; 2076 goto fail1; 2077 } 2078 2079 platform_enable_dma64(pdev, true); 2080 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2081 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2082 WARN_ONCE(true, 2083 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2084 err = -ENOMEM; 2085 goto fail1; 2086 } 2087 2088 platform_enable_dma64(pdev, false); 2089 } 2090 2091 pci_set_master(pdev); 2092 2093 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2094 sizeof(struct rtl_priv), &rtl_ops); 2095 if (!hw) { 2096 WARN_ONCE(true, 2097 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2098 err = -ENOMEM; 2099 goto fail1; 2100 } 2101 2102 SET_IEEE80211_DEV(hw, &pdev->dev); 2103 pci_set_drvdata(pdev, hw); 2104 2105 rtlpriv = hw->priv; 2106 rtlpriv->hw = hw; 2107 pcipriv = (void *)rtlpriv->priv; 2108 pcipriv->dev.pdev = pdev; 2109 init_completion(&rtlpriv->firmware_loading_complete); 2110 /*proximity init here*/ 2111 rtlpriv->proximity.proxim_on = false; 2112 2113 pcipriv = (void *)rtlpriv->priv; 2114 pcipriv->dev.pdev = pdev; 2115 2116 /* init cfg & intf_ops */ 2117 rtlpriv->rtlhal.interface = INTF_PCI; 2118 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2119 rtlpriv->intf_ops = &rtl_pci_ops; 2120 rtl_efuse_ops_init(hw); 2121 2122 /* MEM map */ 2123 err = pci_request_regions(pdev, KBUILD_MODNAME); 2124 if (err) { 2125 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2126 goto fail1; 2127 } 2128 2129 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2130 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2131 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2132 2133 /*shared mem start */ 2134 rtlpriv->io.pci_mem_start = 2135 (unsigned long)pci_iomap(pdev, 2136 rtlpriv->cfg->bar_id, pmem_len); 2137 if (rtlpriv->io.pci_mem_start == 0) { 2138 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2139 err = -ENOMEM; 2140 goto fail2; 2141 } 2142 2143 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2144 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2145 pmem_start, pmem_len, pmem_flags, 2146 rtlpriv->io.pci_mem_start); 2147 2148 /* Disable Clk Request */ 2149 pci_write_config_byte(pdev, 0x81, 0); 2150 /* leave D3 mode */ 2151 pci_write_config_byte(pdev, 0x44, 0); 2152 pci_write_config_byte(pdev, 0x04, 0x06); 2153 pci_write_config_byte(pdev, 0x04, 0x07); 2154 2155 /* find adapter */ 2156 if (!_rtl_pci_find_adapter(pdev, hw)) { 2157 err = -ENODEV; 2158 goto fail2; 2159 } 2160 2161 /* Init IO handler */ 2162 _rtl_pci_io_handler_init(&pdev->dev, hw); 2163 2164 /*like read eeprom and so on */ 2165 rtlpriv->cfg->ops->read_eeprom_info(hw); 2166 2167 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2168 pr_err("Can't init_sw_vars\n"); 2169 err = -ENODEV; 2170 goto fail2; 2171 } 2172 rtl_init_sw_leds(hw); 2173 2174 /*aspm */ 2175 rtl_pci_init_aspm(hw); 2176 2177 /* Init mac80211 sw */ 2178 err = rtl_init_core(hw); 2179 if (err) { 2180 pr_err("Can't allocate sw for mac80211\n"); 2181 goto fail3; 2182 } 2183 2184 /* Init PCI sw */ 2185 err = rtl_pci_init(hw, pdev); 2186 if (err) { 2187 pr_err("Failed to init PCI\n"); 2188 goto fail4; 2189 } 2190 2191 err = ieee80211_register_hw(hw); 2192 if (err) { 2193 pr_err("Can't register mac80211 hw.\n"); 2194 err = -ENODEV; 2195 goto fail5; 2196 } 2197 rtlpriv->mac80211.mac80211_registered = 1; 2198 2199 /* add for debug */ 2200 rtl_debug_add_one(hw); 2201 2202 /*init rfkill */ 2203 rtl_init_rfkill(hw); /* Init PCI sw */ 2204 2205 rtlpci = rtl_pcidev(pcipriv); 2206 err = rtl_pci_intr_mode_decide(hw); 2207 if (err) { 2208 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2209 "%s: failed to register IRQ handler\n", 2210 wiphy_name(hw->wiphy)); 2211 goto fail3; 2212 } 2213 rtlpci->irq_alloc = 1; 2214 2215 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2216 return 0; 2217 2218 fail5: 2219 rtl_pci_deinit(hw); 2220 fail4: 2221 rtl_deinit_core(hw); 2222 fail3: 2223 wait_for_completion(&rtlpriv->firmware_loading_complete); 2224 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2225 2226 fail2: 2227 if (rtlpriv->io.pci_mem_start != 0) 2228 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2229 2230 pci_release_regions(pdev); 2231 2232 fail1: 2233 if (hw) 2234 ieee80211_free_hw(hw); 2235 pci_disable_device(pdev); 2236 2237 return err; 2238 } 2239 EXPORT_SYMBOL(rtl_pci_probe); 2240 rtl_pci_disconnect(struct pci_dev * pdev)2241 void rtl_pci_disconnect(struct pci_dev *pdev) 2242 { 2243 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2244 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2245 struct rtl_priv *rtlpriv = rtl_priv(hw); 2246 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2247 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2248 2249 /* just in case driver is removed before firmware callback */ 2250 wait_for_completion(&rtlpriv->firmware_loading_complete); 2251 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2252 2253 /* remove form debug */ 2254 rtl_debug_remove_one(hw); 2255 2256 /*ieee80211_unregister_hw will call ops_stop */ 2257 if (rtlmac->mac80211_registered == 1) { 2258 ieee80211_unregister_hw(hw); 2259 rtlmac->mac80211_registered = 0; 2260 } else { 2261 rtl_deinit_deferred_work(hw, false); 2262 rtlpriv->intf_ops->adapter_stop(hw); 2263 } 2264 rtlpriv->cfg->ops->disable_interrupt(hw); 2265 2266 /*deinit rfkill */ 2267 rtl_deinit_rfkill(hw); 2268 2269 rtl_pci_deinit(hw); 2270 rtl_deinit_core(hw); 2271 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2272 2273 if (rtlpci->irq_alloc) { 2274 free_irq(rtlpci->pdev->irq, hw); 2275 rtlpci->irq_alloc = 0; 2276 } 2277 2278 if (rtlpci->using_msi) 2279 pci_disable_msi(rtlpci->pdev); 2280 2281 if (rtlpriv->io.pci_mem_start != 0) { 2282 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2283 pci_release_regions(pdev); 2284 } 2285 2286 pci_disable_device(pdev); 2287 2288 rtl_pci_disable_aspm(hw); 2289 2290 pci_set_drvdata(pdev, NULL); 2291 2292 ieee80211_free_hw(hw); 2293 } 2294 EXPORT_SYMBOL(rtl_pci_disconnect); 2295 2296 #ifdef CONFIG_PM_SLEEP 2297 /*************************************** 2298 * kernel pci power state define: 2299 * PCI_D0 ((pci_power_t __force) 0) 2300 * PCI_D1 ((pci_power_t __force) 1) 2301 * PCI_D2 ((pci_power_t __force) 2) 2302 * PCI_D3hot ((pci_power_t __force) 3) 2303 * PCI_D3cold ((pci_power_t __force) 4) 2304 * PCI_UNKNOWN ((pci_power_t __force) 5) 2305 2306 * This function is called when system 2307 * goes into suspend state mac80211 will 2308 * call rtl_mac_stop() from the mac80211 2309 * suspend function first, So there is 2310 * no need to call hw_disable here. 2311 ****************************************/ rtl_pci_suspend(struct device * dev)2312 int rtl_pci_suspend(struct device *dev) 2313 { 2314 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2315 struct rtl_priv *rtlpriv = rtl_priv(hw); 2316 2317 rtlpriv->cfg->ops->hw_suspend(hw); 2318 rtl_deinit_rfkill(hw); 2319 2320 return 0; 2321 } 2322 EXPORT_SYMBOL(rtl_pci_suspend); 2323 rtl_pci_resume(struct device * dev)2324 int rtl_pci_resume(struct device *dev) 2325 { 2326 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2327 struct rtl_priv *rtlpriv = rtl_priv(hw); 2328 2329 rtlpriv->cfg->ops->hw_resume(hw); 2330 rtl_init_rfkill(hw); 2331 return 0; 2332 } 2333 EXPORT_SYMBOL(rtl_pci_resume); 2334 #endif /* CONFIG_PM_SLEEP */ 2335 2336 const struct rtl_intf_ops rtl_pci_ops = { 2337 .read_efuse_byte = read_efuse_byte, 2338 .adapter_start = rtl_pci_start, 2339 .adapter_stop = rtl_pci_stop, 2340 .adapter_tx = rtl_pci_tx, 2341 .flush = rtl_pci_flush, 2342 .reset_trx_ring = rtl_pci_reset_trx_ring, 2343 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2344 2345 .disable_aspm = rtl_pci_disable_aspm, 2346 .enable_aspm = rtl_pci_enable_aspm, 2347 }; 2348