xref: /openbmc/linux/drivers/net/phy/realtek.c (revision b45cbfa2)
1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
3  *
4  * Driver for Realtek PHYs
5  *
6  * Author: Johnson Leung <r58129@freescale.com>
7  *
8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
9  */
10 #include <linux/bitops.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16 
17 #define RTL821x_PHYSR				0x11
18 #define RTL821x_PHYSR_DUPLEX			BIT(13)
19 #define RTL821x_PHYSR_SPEED			GENMASK(15, 14)
20 
21 #define RTL821x_INER				0x12
22 #define RTL8211B_INER_INIT			0x6400
23 #define RTL8211E_INER_LINK_STATUS		BIT(10)
24 #define RTL8211F_INER_LINK_STATUS		BIT(4)
25 
26 #define RTL821x_INSR				0x13
27 
28 #define RTL821x_EXT_PAGE_SELECT			0x1e
29 #define RTL821x_PAGE_SELECT			0x1f
30 
31 #define RTL8211F_PHYCR1				0x18
32 #define RTL8211F_PHYCR2				0x19
33 #define RTL8211F_INSR				0x1d
34 
35 #define RTL8211F_TX_DELAY			BIT(8)
36 #define RTL8211F_RX_DELAY			BIT(3)
37 
38 #define RTL8211F_ALDPS_PLL_OFF			BIT(1)
39 #define RTL8211F_ALDPS_ENABLE			BIT(2)
40 #define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
41 
42 #define RTL8211E_CTRL_DELAY			BIT(13)
43 #define RTL8211E_TX_DELAY			BIT(12)
44 #define RTL8211E_RX_DELAY			BIT(11)
45 
46 #define RTL8211F_CLKOUT_EN			BIT(0)
47 
48 #define RTL8201F_ISR				0x1e
49 #define RTL8201F_ISR_ANERR			BIT(15)
50 #define RTL8201F_ISR_DUPLEX			BIT(13)
51 #define RTL8201F_ISR_LINK			BIT(11)
52 #define RTL8201F_ISR_MASK			(RTL8201F_ISR_ANERR | \
53 						 RTL8201F_ISR_DUPLEX | \
54 						 RTL8201F_ISR_LINK)
55 #define RTL8201F_IER				0x13
56 
57 #define RTL8366RB_POWER_SAVE			0x15
58 #define RTL8366RB_POWER_SAVE_ON			BIT(12)
59 
60 #define RTL_SUPPORTS_5000FULL			BIT(14)
61 #define RTL_SUPPORTS_2500FULL			BIT(13)
62 #define RTL_SUPPORTS_10000FULL			BIT(0)
63 #define RTL_ADV_2500FULL			BIT(7)
64 #define RTL_LPADV_10000FULL			BIT(11)
65 #define RTL_LPADV_5000FULL			BIT(6)
66 #define RTL_LPADV_2500FULL			BIT(5)
67 
68 #define RTL9000A_GINMR				0x14
69 #define RTL9000A_GINMR_LINK_STATUS		BIT(4)
70 
71 #define RTLGEN_SPEED_MASK			0x0630
72 
73 #define RTL_GENERIC_PHYID			0x001cc800
74 #define RTL_8211FVD_PHYID			0x001cc878
75 
76 MODULE_DESCRIPTION("Realtek PHY driver");
77 MODULE_AUTHOR("Johnson Leung");
78 MODULE_LICENSE("GPL");
79 
80 struct rtl821x_priv {
81 	u16 phycr1;
82 	u16 phycr2;
83 	bool has_phycr2;
84 	struct clk *clk;
85 };
86 
rtl821x_read_page(struct phy_device * phydev)87 static int rtl821x_read_page(struct phy_device *phydev)
88 {
89 	return __phy_read(phydev, RTL821x_PAGE_SELECT);
90 }
91 
rtl821x_write_page(struct phy_device * phydev,int page)92 static int rtl821x_write_page(struct phy_device *phydev, int page)
93 {
94 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
95 }
96 
rtl821x_probe(struct phy_device * phydev)97 static int rtl821x_probe(struct phy_device *phydev)
98 {
99 	struct device *dev = &phydev->mdio.dev;
100 	struct rtl821x_priv *priv;
101 	u32 phy_id = phydev->drv->phy_id;
102 	int ret;
103 
104 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
105 	if (!priv)
106 		return -ENOMEM;
107 
108 	priv->clk = devm_clk_get_optional_enabled(dev, NULL);
109 	if (IS_ERR(priv->clk))
110 		return dev_err_probe(dev, PTR_ERR(priv->clk),
111 				     "failed to get phy clock\n");
112 
113 	ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
114 	if (ret < 0)
115 		return ret;
116 
117 	priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
118 	if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
119 		priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
120 
121 	priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
122 	if (priv->has_phycr2) {
123 		ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
124 		if (ret < 0)
125 			return ret;
126 
127 		priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
128 		if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
129 			priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
130 	}
131 
132 	phydev->priv = priv;
133 
134 	return 0;
135 }
136 
rtl8201_ack_interrupt(struct phy_device * phydev)137 static int rtl8201_ack_interrupt(struct phy_device *phydev)
138 {
139 	int err;
140 
141 	err = phy_read(phydev, RTL8201F_ISR);
142 
143 	return (err < 0) ? err : 0;
144 }
145 
rtl821x_ack_interrupt(struct phy_device * phydev)146 static int rtl821x_ack_interrupt(struct phy_device *phydev)
147 {
148 	int err;
149 
150 	err = phy_read(phydev, RTL821x_INSR);
151 
152 	return (err < 0) ? err : 0;
153 }
154 
rtl8211f_ack_interrupt(struct phy_device * phydev)155 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
156 {
157 	int err;
158 
159 	err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
160 
161 	return (err < 0) ? err : 0;
162 }
163 
rtl8201_config_intr(struct phy_device * phydev)164 static int rtl8201_config_intr(struct phy_device *phydev)
165 {
166 	u16 val;
167 	int err;
168 
169 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
170 		err = rtl8201_ack_interrupt(phydev);
171 		if (err)
172 			return err;
173 
174 		val = BIT(13) | BIT(12) | BIT(11);
175 		err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
176 	} else {
177 		val = 0;
178 		err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
179 		if (err)
180 			return err;
181 
182 		err = rtl8201_ack_interrupt(phydev);
183 	}
184 
185 	return err;
186 }
187 
rtl8211b_config_intr(struct phy_device * phydev)188 static int rtl8211b_config_intr(struct phy_device *phydev)
189 {
190 	int err;
191 
192 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
193 		err = rtl821x_ack_interrupt(phydev);
194 		if (err)
195 			return err;
196 
197 		err = phy_write(phydev, RTL821x_INER,
198 				RTL8211B_INER_INIT);
199 	} else {
200 		err = phy_write(phydev, RTL821x_INER, 0);
201 		if (err)
202 			return err;
203 
204 		err = rtl821x_ack_interrupt(phydev);
205 	}
206 
207 	return err;
208 }
209 
rtl8211e_config_intr(struct phy_device * phydev)210 static int rtl8211e_config_intr(struct phy_device *phydev)
211 {
212 	int err;
213 
214 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
215 		err = rtl821x_ack_interrupt(phydev);
216 		if (err)
217 			return err;
218 
219 		err = phy_write(phydev, RTL821x_INER,
220 				RTL8211E_INER_LINK_STATUS);
221 	} else {
222 		err = phy_write(phydev, RTL821x_INER, 0);
223 		if (err)
224 			return err;
225 
226 		err = rtl821x_ack_interrupt(phydev);
227 	}
228 
229 	return err;
230 }
231 
rtl8211f_config_intr(struct phy_device * phydev)232 static int rtl8211f_config_intr(struct phy_device *phydev)
233 {
234 	u16 val;
235 	int err;
236 
237 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
238 		err = rtl8211f_ack_interrupt(phydev);
239 		if (err)
240 			return err;
241 
242 		val = RTL8211F_INER_LINK_STATUS;
243 		err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
244 	} else {
245 		val = 0;
246 		err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
247 		if (err)
248 			return err;
249 
250 		err = rtl8211f_ack_interrupt(phydev);
251 	}
252 
253 	return err;
254 }
255 
rtl8201_handle_interrupt(struct phy_device * phydev)256 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
257 {
258 	int irq_status;
259 
260 	irq_status = phy_read(phydev, RTL8201F_ISR);
261 	if (irq_status < 0) {
262 		phy_error(phydev);
263 		return IRQ_NONE;
264 	}
265 
266 	if (!(irq_status & RTL8201F_ISR_MASK))
267 		return IRQ_NONE;
268 
269 	phy_trigger_machine(phydev);
270 
271 	return IRQ_HANDLED;
272 }
273 
rtl821x_handle_interrupt(struct phy_device * phydev)274 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
275 {
276 	int irq_status, irq_enabled;
277 
278 	irq_status = phy_read(phydev, RTL821x_INSR);
279 	if (irq_status < 0) {
280 		phy_error(phydev);
281 		return IRQ_NONE;
282 	}
283 
284 	irq_enabled = phy_read(phydev, RTL821x_INER);
285 	if (irq_enabled < 0) {
286 		phy_error(phydev);
287 		return IRQ_NONE;
288 	}
289 
290 	if (!(irq_status & irq_enabled))
291 		return IRQ_NONE;
292 
293 	phy_trigger_machine(phydev);
294 
295 	return IRQ_HANDLED;
296 }
297 
rtl8211f_handle_interrupt(struct phy_device * phydev)298 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
299 {
300 	int irq_status;
301 
302 	irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
303 	if (irq_status < 0) {
304 		phy_error(phydev);
305 		return IRQ_NONE;
306 	}
307 
308 	if (!(irq_status & RTL8211F_INER_LINK_STATUS))
309 		return IRQ_NONE;
310 
311 	phy_trigger_machine(phydev);
312 
313 	return IRQ_HANDLED;
314 }
315 
rtl8211_config_aneg(struct phy_device * phydev)316 static int rtl8211_config_aneg(struct phy_device *phydev)
317 {
318 	int ret;
319 
320 	ret = genphy_config_aneg(phydev);
321 	if (ret < 0)
322 		return ret;
323 
324 	/* Quirk was copied from vendor driver. Unfortunately it includes no
325 	 * description of the magic numbers.
326 	 */
327 	if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
328 		phy_write(phydev, 0x17, 0x2138);
329 		phy_write(phydev, 0x0e, 0x0260);
330 	} else {
331 		phy_write(phydev, 0x17, 0x2108);
332 		phy_write(phydev, 0x0e, 0x0000);
333 	}
334 
335 	return 0;
336 }
337 
rtl8211c_config_init(struct phy_device * phydev)338 static int rtl8211c_config_init(struct phy_device *phydev)
339 {
340 	/* RTL8211C has an issue when operating in Gigabit slave mode */
341 	return phy_set_bits(phydev, MII_CTRL1000,
342 			    CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
343 }
344 
rtl8211f_config_init(struct phy_device * phydev)345 static int rtl8211f_config_init(struct phy_device *phydev)
346 {
347 	struct rtl821x_priv *priv = phydev->priv;
348 	struct device *dev = &phydev->mdio.dev;
349 	u16 val_txdly, val_rxdly;
350 	int ret;
351 
352 	ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
353 				       RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
354 				       priv->phycr1);
355 	if (ret < 0) {
356 		dev_err(dev, "aldps mode  configuration failed: %pe\n",
357 			ERR_PTR(ret));
358 		return ret;
359 	}
360 
361 	switch (phydev->interface) {
362 	case PHY_INTERFACE_MODE_RGMII:
363 		val_txdly = 0;
364 		val_rxdly = 0;
365 		break;
366 
367 	case PHY_INTERFACE_MODE_RGMII_RXID:
368 		val_txdly = 0;
369 		val_rxdly = RTL8211F_RX_DELAY;
370 		break;
371 
372 	case PHY_INTERFACE_MODE_RGMII_TXID:
373 		val_txdly = RTL8211F_TX_DELAY;
374 		val_rxdly = 0;
375 		break;
376 
377 	case PHY_INTERFACE_MODE_RGMII_ID:
378 		val_txdly = RTL8211F_TX_DELAY;
379 		val_rxdly = RTL8211F_RX_DELAY;
380 		break;
381 
382 	default: /* the rest of the modes imply leaving delay as is. */
383 		return 0;
384 	}
385 
386 	ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
387 				       val_txdly);
388 	if (ret < 0) {
389 		dev_err(dev, "Failed to update the TX delay register\n");
390 		return ret;
391 	} else if (ret) {
392 		dev_dbg(dev,
393 			"%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
394 			val_txdly ? "Enabling" : "Disabling");
395 	} else {
396 		dev_dbg(dev,
397 			"2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
398 			val_txdly ? "enabled" : "disabled");
399 	}
400 
401 	ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
402 				       val_rxdly);
403 	if (ret < 0) {
404 		dev_err(dev, "Failed to update the RX delay register\n");
405 		return ret;
406 	} else if (ret) {
407 		dev_dbg(dev,
408 			"%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
409 			val_rxdly ? "Enabling" : "Disabling");
410 	} else {
411 		dev_dbg(dev,
412 			"2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
413 			val_rxdly ? "enabled" : "disabled");
414 	}
415 
416 	if (priv->has_phycr2) {
417 		ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
418 				       RTL8211F_CLKOUT_EN, priv->phycr2);
419 		if (ret < 0) {
420 			dev_err(dev, "clkout configuration failed: %pe\n",
421 				ERR_PTR(ret));
422 			return ret;
423 		}
424 
425 		return genphy_soft_reset(phydev);
426 	}
427 
428 	return 0;
429 }
430 
rtl821x_suspend(struct phy_device * phydev)431 static int rtl821x_suspend(struct phy_device *phydev)
432 {
433 	struct rtl821x_priv *priv = phydev->priv;
434 	int ret = 0;
435 
436 	if (!phydev->wol_enabled) {
437 		ret = genphy_suspend(phydev);
438 
439 		if (ret)
440 			return ret;
441 
442 		clk_disable_unprepare(priv->clk);
443 	}
444 
445 	return ret;
446 }
447 
rtl821x_resume(struct phy_device * phydev)448 static int rtl821x_resume(struct phy_device *phydev)
449 {
450 	struct rtl821x_priv *priv = phydev->priv;
451 	int ret;
452 
453 	if (!phydev->wol_enabled)
454 		clk_prepare_enable(priv->clk);
455 
456 	ret = genphy_resume(phydev);
457 	if (ret < 0)
458 		return ret;
459 
460 	msleep(20);
461 
462 	return 0;
463 }
464 
rtl8211e_config_init(struct phy_device * phydev)465 static int rtl8211e_config_init(struct phy_device *phydev)
466 {
467 	int ret = 0, oldpage;
468 	u16 val;
469 
470 	/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
471 	switch (phydev->interface) {
472 	case PHY_INTERFACE_MODE_RGMII:
473 		val = RTL8211E_CTRL_DELAY | 0;
474 		break;
475 	case PHY_INTERFACE_MODE_RGMII_ID:
476 		val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
477 		break;
478 	case PHY_INTERFACE_MODE_RGMII_RXID:
479 		val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
480 		break;
481 	case PHY_INTERFACE_MODE_RGMII_TXID:
482 		val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
483 		break;
484 	default: /* the rest of the modes imply leaving delays as is. */
485 		return 0;
486 	}
487 
488 	/* According to a sample driver there is a 0x1c config register on the
489 	 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
490 	 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
491 	 * The configuration register definition:
492 	 * 14 = reserved
493 	 * 13 = Force Tx RX Delay controlled by bit12 bit11,
494 	 * 12 = RX Delay, 11 = TX Delay
495 	 * 10:0 = Test && debug settings reserved by realtek
496 	 */
497 	oldpage = phy_select_page(phydev, 0x7);
498 	if (oldpage < 0)
499 		goto err_restore_page;
500 
501 	ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
502 	if (ret)
503 		goto err_restore_page;
504 
505 	ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
506 			   | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
507 			   val);
508 
509 err_restore_page:
510 	return phy_restore_page(phydev, oldpage, ret);
511 }
512 
rtl8211b_suspend(struct phy_device * phydev)513 static int rtl8211b_suspend(struct phy_device *phydev)
514 {
515 	phy_write(phydev, MII_MMD_DATA, BIT(9));
516 
517 	return genphy_suspend(phydev);
518 }
519 
rtl8211b_resume(struct phy_device * phydev)520 static int rtl8211b_resume(struct phy_device *phydev)
521 {
522 	phy_write(phydev, MII_MMD_DATA, 0);
523 
524 	return genphy_resume(phydev);
525 }
526 
rtl8366rb_config_init(struct phy_device * phydev)527 static int rtl8366rb_config_init(struct phy_device *phydev)
528 {
529 	int ret;
530 
531 	ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
532 			   RTL8366RB_POWER_SAVE_ON);
533 	if (ret) {
534 		dev_err(&phydev->mdio.dev,
535 			"error enabling power management\n");
536 	}
537 
538 	return ret;
539 }
540 
541 /* get actual speed to cover the downshift case */
rtlgen_get_speed(struct phy_device * phydev)542 static int rtlgen_get_speed(struct phy_device *phydev)
543 {
544 	int val;
545 
546 	if (!phydev->link)
547 		return 0;
548 
549 	val = phy_read_paged(phydev, 0xa43, 0x12);
550 	if (val < 0)
551 		return val;
552 
553 	switch (val & RTLGEN_SPEED_MASK) {
554 	case 0x0000:
555 		phydev->speed = SPEED_10;
556 		break;
557 	case 0x0010:
558 		phydev->speed = SPEED_100;
559 		break;
560 	case 0x0020:
561 		phydev->speed = SPEED_1000;
562 		break;
563 	case 0x0200:
564 		phydev->speed = SPEED_10000;
565 		break;
566 	case 0x0210:
567 		phydev->speed = SPEED_2500;
568 		break;
569 	case 0x0220:
570 		phydev->speed = SPEED_5000;
571 		break;
572 	default:
573 		break;
574 	}
575 
576 	return 0;
577 }
578 
rtlgen_read_status(struct phy_device * phydev)579 static int rtlgen_read_status(struct phy_device *phydev)
580 {
581 	int ret;
582 
583 	ret = genphy_read_status(phydev);
584 	if (ret < 0)
585 		return ret;
586 
587 	return rtlgen_get_speed(phydev);
588 }
589 
rtlgen_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)590 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
591 {
592 	int ret;
593 
594 	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
595 		rtl821x_write_page(phydev, 0xa5c);
596 		ret = __phy_read(phydev, 0x12);
597 		rtl821x_write_page(phydev, 0);
598 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
599 		rtl821x_write_page(phydev, 0xa5d);
600 		ret = __phy_read(phydev, 0x10);
601 		rtl821x_write_page(phydev, 0);
602 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
603 		rtl821x_write_page(phydev, 0xa5d);
604 		ret = __phy_read(phydev, 0x11);
605 		rtl821x_write_page(phydev, 0);
606 	} else {
607 		ret = -EOPNOTSUPP;
608 	}
609 
610 	return ret;
611 }
612 
rtlgen_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)613 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
614 			    u16 val)
615 {
616 	int ret;
617 
618 	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
619 		rtl821x_write_page(phydev, 0xa5d);
620 		ret = __phy_write(phydev, 0x10, val);
621 		rtl821x_write_page(phydev, 0);
622 	} else {
623 		ret = -EOPNOTSUPP;
624 	}
625 
626 	return ret;
627 }
628 
rtl822x_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)629 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
630 {
631 	int ret = rtlgen_read_mmd(phydev, devnum, regnum);
632 
633 	if (ret != -EOPNOTSUPP)
634 		return ret;
635 
636 	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
637 		rtl821x_write_page(phydev, 0xa6e);
638 		ret = __phy_read(phydev, 0x16);
639 		rtl821x_write_page(phydev, 0);
640 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
641 		rtl821x_write_page(phydev, 0xa6d);
642 		ret = __phy_read(phydev, 0x12);
643 		rtl821x_write_page(phydev, 0);
644 	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
645 		rtl821x_write_page(phydev, 0xa6d);
646 		ret = __phy_read(phydev, 0x10);
647 		rtl821x_write_page(phydev, 0);
648 	}
649 
650 	return ret;
651 }
652 
rtl822x_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)653 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
654 			     u16 val)
655 {
656 	int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
657 
658 	if (ret != -EOPNOTSUPP)
659 		return ret;
660 
661 	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
662 		rtl821x_write_page(phydev, 0xa6d);
663 		ret = __phy_write(phydev, 0x12, val);
664 		rtl821x_write_page(phydev, 0);
665 	}
666 
667 	return ret;
668 }
669 
rtl822x_get_features(struct phy_device * phydev)670 static int rtl822x_get_features(struct phy_device *phydev)
671 {
672 	int val;
673 
674 	val = phy_read_paged(phydev, 0xa61, 0x13);
675 	if (val < 0)
676 		return val;
677 
678 	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
679 			 phydev->supported, val & RTL_SUPPORTS_2500FULL);
680 	linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
681 			 phydev->supported, val & RTL_SUPPORTS_5000FULL);
682 	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
683 			 phydev->supported, val & RTL_SUPPORTS_10000FULL);
684 
685 	return genphy_read_abilities(phydev);
686 }
687 
rtl822x_config_aneg(struct phy_device * phydev)688 static int rtl822x_config_aneg(struct phy_device *phydev)
689 {
690 	int ret = 0;
691 
692 	if (phydev->autoneg == AUTONEG_ENABLE) {
693 		u16 adv2500 = 0;
694 
695 		if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
696 				      phydev->advertising))
697 			adv2500 = RTL_ADV_2500FULL;
698 
699 		ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
700 					       RTL_ADV_2500FULL, adv2500);
701 		if (ret < 0)
702 			return ret;
703 	}
704 
705 	return __genphy_config_aneg(phydev, ret);
706 }
707 
rtl822x_read_status(struct phy_device * phydev)708 static int rtl822x_read_status(struct phy_device *phydev)
709 {
710 	int ret;
711 
712 	if (phydev->autoneg == AUTONEG_ENABLE) {
713 		int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
714 
715 		if (lpadv < 0)
716 			return lpadv;
717 
718 		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
719 			phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
720 		linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
721 			phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
722 		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
723 			phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
724 	}
725 
726 	ret = genphy_read_status(phydev);
727 	if (ret < 0)
728 		return ret;
729 
730 	return rtlgen_get_speed(phydev);
731 }
732 
rtlgen_supports_2_5gbps(struct phy_device * phydev)733 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
734 {
735 	int val;
736 
737 	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
738 	val = phy_read(phydev, 0x13);
739 	phy_write(phydev, RTL821x_PAGE_SELECT, 0);
740 
741 	return val >= 0 && val & RTL_SUPPORTS_2500FULL;
742 }
743 
rtlgen_match_phy_device(struct phy_device * phydev)744 static int rtlgen_match_phy_device(struct phy_device *phydev)
745 {
746 	return phydev->phy_id == RTL_GENERIC_PHYID &&
747 	       !rtlgen_supports_2_5gbps(phydev);
748 }
749 
rtl8226_match_phy_device(struct phy_device * phydev)750 static int rtl8226_match_phy_device(struct phy_device *phydev)
751 {
752 	return phydev->phy_id == RTL_GENERIC_PHYID &&
753 	       rtlgen_supports_2_5gbps(phydev);
754 }
755 
rtlgen_resume(struct phy_device * phydev)756 static int rtlgen_resume(struct phy_device *phydev)
757 {
758 	int ret = genphy_resume(phydev);
759 
760 	/* Internal PHY's from RTL8168h up may not be instantly ready */
761 	msleep(20);
762 
763 	return ret;
764 }
765 
rtl9000a_config_init(struct phy_device * phydev)766 static int rtl9000a_config_init(struct phy_device *phydev)
767 {
768 	phydev->autoneg = AUTONEG_DISABLE;
769 	phydev->speed = SPEED_100;
770 	phydev->duplex = DUPLEX_FULL;
771 
772 	return 0;
773 }
774 
rtl9000a_config_aneg(struct phy_device * phydev)775 static int rtl9000a_config_aneg(struct phy_device *phydev)
776 {
777 	int ret;
778 	u16 ctl = 0;
779 
780 	switch (phydev->master_slave_set) {
781 	case MASTER_SLAVE_CFG_MASTER_FORCE:
782 		ctl |= CTL1000_AS_MASTER;
783 		break;
784 	case MASTER_SLAVE_CFG_SLAVE_FORCE:
785 		break;
786 	case MASTER_SLAVE_CFG_UNKNOWN:
787 	case MASTER_SLAVE_CFG_UNSUPPORTED:
788 		return 0;
789 	default:
790 		phydev_warn(phydev, "Unsupported Master/Slave mode\n");
791 		return -EOPNOTSUPP;
792 	}
793 
794 	ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
795 	if (ret == 1)
796 		ret = genphy_soft_reset(phydev);
797 
798 	return ret;
799 }
800 
rtl9000a_read_status(struct phy_device * phydev)801 static int rtl9000a_read_status(struct phy_device *phydev)
802 {
803 	int ret;
804 
805 	phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
806 	phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
807 
808 	ret = genphy_update_link(phydev);
809 	if (ret)
810 		return ret;
811 
812 	ret = phy_read(phydev, MII_CTRL1000);
813 	if (ret < 0)
814 		return ret;
815 	if (ret & CTL1000_AS_MASTER)
816 		phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
817 	else
818 		phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
819 
820 	ret = phy_read(phydev, MII_STAT1000);
821 	if (ret < 0)
822 		return ret;
823 	if (ret & LPA_1000MSRES)
824 		phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
825 	else
826 		phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
827 
828 	return 0;
829 }
830 
rtl9000a_ack_interrupt(struct phy_device * phydev)831 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
832 {
833 	int err;
834 
835 	err = phy_read(phydev, RTL8211F_INSR);
836 
837 	return (err < 0) ? err : 0;
838 }
839 
rtl9000a_config_intr(struct phy_device * phydev)840 static int rtl9000a_config_intr(struct phy_device *phydev)
841 {
842 	u16 val;
843 	int err;
844 
845 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
846 		err = rtl9000a_ack_interrupt(phydev);
847 		if (err)
848 			return err;
849 
850 		val = (u16)~RTL9000A_GINMR_LINK_STATUS;
851 		err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
852 	} else {
853 		val = ~0;
854 		err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
855 		if (err)
856 			return err;
857 
858 		err = rtl9000a_ack_interrupt(phydev);
859 	}
860 
861 	return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
862 }
863 
rtl9000a_handle_interrupt(struct phy_device * phydev)864 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
865 {
866 	int irq_status;
867 
868 	irq_status = phy_read(phydev, RTL8211F_INSR);
869 	if (irq_status < 0) {
870 		phy_error(phydev);
871 		return IRQ_NONE;
872 	}
873 
874 	if (!(irq_status & RTL8211F_INER_LINK_STATUS))
875 		return IRQ_NONE;
876 
877 	phy_trigger_machine(phydev);
878 
879 	return IRQ_HANDLED;
880 }
881 
882 static struct phy_driver realtek_drvs[] = {
883 	{
884 		PHY_ID_MATCH_EXACT(0x00008201),
885 		.name           = "RTL8201CP Ethernet",
886 		.read_page	= rtl821x_read_page,
887 		.write_page	= rtl821x_write_page,
888 	}, {
889 		PHY_ID_MATCH_EXACT(0x001cc816),
890 		.name		= "RTL8201F Fast Ethernet",
891 		.config_intr	= &rtl8201_config_intr,
892 		.handle_interrupt = rtl8201_handle_interrupt,
893 		.suspend	= genphy_suspend,
894 		.resume		= genphy_resume,
895 		.read_page	= rtl821x_read_page,
896 		.write_page	= rtl821x_write_page,
897 	}, {
898 		PHY_ID_MATCH_MODEL(0x001cc880),
899 		.name		= "RTL8208 Fast Ethernet",
900 		.read_mmd	= genphy_read_mmd_unsupported,
901 		.write_mmd	= genphy_write_mmd_unsupported,
902 		.suspend	= genphy_suspend,
903 		.resume		= genphy_resume,
904 		.read_page	= rtl821x_read_page,
905 		.write_page	= rtl821x_write_page,
906 	}, {
907 		PHY_ID_MATCH_EXACT(0x001cc910),
908 		.name		= "RTL8211 Gigabit Ethernet",
909 		.config_aneg	= rtl8211_config_aneg,
910 		.read_mmd	= &genphy_read_mmd_unsupported,
911 		.write_mmd	= &genphy_write_mmd_unsupported,
912 		.read_page	= rtl821x_read_page,
913 		.write_page	= rtl821x_write_page,
914 	}, {
915 		PHY_ID_MATCH_EXACT(0x001cc912),
916 		.name		= "RTL8211B Gigabit Ethernet",
917 		.config_intr	= &rtl8211b_config_intr,
918 		.handle_interrupt = rtl821x_handle_interrupt,
919 		.read_mmd	= &genphy_read_mmd_unsupported,
920 		.write_mmd	= &genphy_write_mmd_unsupported,
921 		.suspend	= rtl8211b_suspend,
922 		.resume		= rtl8211b_resume,
923 		.read_page	= rtl821x_read_page,
924 		.write_page	= rtl821x_write_page,
925 	}, {
926 		PHY_ID_MATCH_EXACT(0x001cc913),
927 		.name		= "RTL8211C Gigabit Ethernet",
928 		.config_init	= rtl8211c_config_init,
929 		.read_mmd	= &genphy_read_mmd_unsupported,
930 		.write_mmd	= &genphy_write_mmd_unsupported,
931 		.read_page	= rtl821x_read_page,
932 		.write_page	= rtl821x_write_page,
933 	}, {
934 		PHY_ID_MATCH_EXACT(0x001cc914),
935 		.name		= "RTL8211DN Gigabit Ethernet",
936 		.config_intr	= rtl8211e_config_intr,
937 		.handle_interrupt = rtl821x_handle_interrupt,
938 		.suspend	= genphy_suspend,
939 		.resume		= genphy_resume,
940 		.read_page	= rtl821x_read_page,
941 		.write_page	= rtl821x_write_page,
942 	}, {
943 		PHY_ID_MATCH_EXACT(0x001cc915),
944 		.name		= "RTL8211E Gigabit Ethernet",
945 		.config_init	= &rtl8211e_config_init,
946 		.config_intr	= &rtl8211e_config_intr,
947 		.handle_interrupt = rtl821x_handle_interrupt,
948 		.suspend	= genphy_suspend,
949 		.resume		= genphy_resume,
950 		.read_page	= rtl821x_read_page,
951 		.write_page	= rtl821x_write_page,
952 	}, {
953 		PHY_ID_MATCH_EXACT(0x001cc916),
954 		.name		= "RTL8211F Gigabit Ethernet",
955 		.probe		= rtl821x_probe,
956 		.config_init	= &rtl8211f_config_init,
957 		.read_status	= rtlgen_read_status,
958 		.config_intr	= &rtl8211f_config_intr,
959 		.handle_interrupt = rtl8211f_handle_interrupt,
960 		.suspend	= rtl821x_suspend,
961 		.resume		= rtl821x_resume,
962 		.read_page	= rtl821x_read_page,
963 		.write_page	= rtl821x_write_page,
964 		.flags		= PHY_ALWAYS_CALL_SUSPEND,
965 	}, {
966 		PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
967 		.name		= "RTL8211F-VD Gigabit Ethernet",
968 		.probe		= rtl821x_probe,
969 		.config_init	= &rtl8211f_config_init,
970 		.read_status	= rtlgen_read_status,
971 		.config_intr	= &rtl8211f_config_intr,
972 		.handle_interrupt = rtl8211f_handle_interrupt,
973 		.suspend	= rtl821x_suspend,
974 		.resume		= rtl821x_resume,
975 		.read_page	= rtl821x_read_page,
976 		.write_page	= rtl821x_write_page,
977 		.flags		= PHY_ALWAYS_CALL_SUSPEND,
978 	}, {
979 		.name		= "Generic FE-GE Realtek PHY",
980 		.match_phy_device = rtlgen_match_phy_device,
981 		.read_status	= rtlgen_read_status,
982 		.suspend	= genphy_suspend,
983 		.resume		= rtlgen_resume,
984 		.read_page	= rtl821x_read_page,
985 		.write_page	= rtl821x_write_page,
986 		.read_mmd	= rtlgen_read_mmd,
987 		.write_mmd	= rtlgen_write_mmd,
988 	}, {
989 		.name		= "RTL8226 2.5Gbps PHY",
990 		.match_phy_device = rtl8226_match_phy_device,
991 		.get_features	= rtl822x_get_features,
992 		.config_aneg	= rtl822x_config_aneg,
993 		.read_status	= rtl822x_read_status,
994 		.suspend	= genphy_suspend,
995 		.resume		= rtlgen_resume,
996 		.read_page	= rtl821x_read_page,
997 		.write_page	= rtl821x_write_page,
998 		.read_mmd	= rtl822x_read_mmd,
999 		.write_mmd	= rtl822x_write_mmd,
1000 	}, {
1001 		PHY_ID_MATCH_EXACT(0x001cc840),
1002 		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
1003 		.get_features	= rtl822x_get_features,
1004 		.config_aneg	= rtl822x_config_aneg,
1005 		.read_status	= rtl822x_read_status,
1006 		.suspend	= genphy_suspend,
1007 		.resume		= rtlgen_resume,
1008 		.read_page	= rtl821x_read_page,
1009 		.write_page	= rtl821x_write_page,
1010 		.read_mmd	= rtl822x_read_mmd,
1011 		.write_mmd	= rtl822x_write_mmd,
1012 	}, {
1013 		PHY_ID_MATCH_EXACT(0x001cc838),
1014 		.name           = "RTL8226-CG 2.5Gbps PHY",
1015 		.get_features   = rtl822x_get_features,
1016 		.config_aneg    = rtl822x_config_aneg,
1017 		.read_status    = rtl822x_read_status,
1018 		.suspend        = genphy_suspend,
1019 		.resume         = rtlgen_resume,
1020 		.read_page      = rtl821x_read_page,
1021 		.write_page     = rtl821x_write_page,
1022 	}, {
1023 		PHY_ID_MATCH_EXACT(0x001cc848),
1024 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1025 		.get_features   = rtl822x_get_features,
1026 		.config_aneg    = rtl822x_config_aneg,
1027 		.read_status    = rtl822x_read_status,
1028 		.suspend        = genphy_suspend,
1029 		.resume         = rtlgen_resume,
1030 		.read_page      = rtl821x_read_page,
1031 		.write_page     = rtl821x_write_page,
1032 	}, {
1033 		PHY_ID_MATCH_EXACT(0x001cc849),
1034 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY",
1035 		.get_features   = rtl822x_get_features,
1036 		.config_aneg    = rtl822x_config_aneg,
1037 		.read_status    = rtl822x_read_status,
1038 		.suspend        = genphy_suspend,
1039 		.resume         = rtlgen_resume,
1040 		.read_page      = rtl821x_read_page,
1041 		.write_page     = rtl821x_write_page,
1042 	}, {
1043 		PHY_ID_MATCH_EXACT(0x001cc84a),
1044 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY",
1045 		.get_features   = rtl822x_get_features,
1046 		.config_aneg    = rtl822x_config_aneg,
1047 		.read_status    = rtl822x_read_status,
1048 		.suspend        = genphy_suspend,
1049 		.resume         = rtlgen_resume,
1050 		.read_page      = rtl821x_read_page,
1051 		.write_page     = rtl821x_write_page,
1052 	}, {
1053 		PHY_ID_MATCH_EXACT(0x001cc961),
1054 		.name		= "RTL8366RB Gigabit Ethernet",
1055 		.config_init	= &rtl8366rb_config_init,
1056 		/* These interrupts are handled by the irq controller
1057 		 * embedded inside the RTL8366RB, they get unmasked when the
1058 		 * irq is requested and ACKed by reading the status register,
1059 		 * which is done by the irqchip code.
1060 		 */
1061 		.config_intr	= genphy_no_config_intr,
1062 		.handle_interrupt = genphy_handle_interrupt_no_ack,
1063 		.suspend	= genphy_suspend,
1064 		.resume		= genphy_resume,
1065 	}, {
1066 		PHY_ID_MATCH_EXACT(0x001ccb00),
1067 		.name		= "RTL9000AA_RTL9000AN Ethernet",
1068 		.features       = PHY_BASIC_T1_FEATURES,
1069 		.config_init	= rtl9000a_config_init,
1070 		.config_aneg	= rtl9000a_config_aneg,
1071 		.read_status	= rtl9000a_read_status,
1072 		.config_intr	= rtl9000a_config_intr,
1073 		.handle_interrupt = rtl9000a_handle_interrupt,
1074 		.suspend	= genphy_suspend,
1075 		.resume		= genphy_resume,
1076 		.read_page	= rtl821x_read_page,
1077 		.write_page	= rtl821x_write_page,
1078 	}, {
1079 		PHY_ID_MATCH_EXACT(0x001cc942),
1080 		.name		= "RTL8365MB-VC Gigabit Ethernet",
1081 		/* Interrupt handling analogous to RTL8366RB */
1082 		.config_intr	= genphy_no_config_intr,
1083 		.handle_interrupt = genphy_handle_interrupt_no_ack,
1084 		.suspend	= genphy_suspend,
1085 		.resume		= genphy_resume,
1086 	}, {
1087 		PHY_ID_MATCH_EXACT(0x001cc960),
1088 		.name		= "RTL8366S Gigabit Ethernet",
1089 		.suspend	= genphy_suspend,
1090 		.resume		= genphy_resume,
1091 		.read_mmd	= genphy_read_mmd_unsupported,
1092 		.write_mmd	= genphy_write_mmd_unsupported,
1093 	},
1094 };
1095 
1096 module_phy_driver(realtek_drvs);
1097 
1098 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1099 	{ PHY_ID_MATCH_VENDOR(0x001cc800) },
1100 	{ }
1101 };
1102 
1103 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1104