1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Rockchip ISP1 Driver - V4l capture device
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 *
7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/pm_runtime.h>
13 #include <media/v4l2-common.h>
14 #include <media/v4l2-event.h>
15 #include <media/v4l2-fh.h>
16 #include <media/v4l2-ioctl.h>
17 #include <media/v4l2-mc.h>
18 #include <media/v4l2-subdev.h>
19 #include <media/videobuf2-dma-contig.h>
20
21 #include "rkisp1-common.h"
22
23 /*
24 * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath.
25 *
26 * differences between selfpath and mainpath
27 * available mp sink input: isp
28 * available sp sink input : isp, dma(TODO)
29 * available mp sink pad fmts: yuv422, raw
30 * available sp sink pad fmts: yuv422, yuv420......
31 * available mp source fmts: yuv, raw, jpeg(TODO)
32 * available sp source fmts: yuv, rgb
33 */
34
35 #define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath"
36 #define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath"
37
38 #define RKISP1_MIN_BUFFERS_NEEDED 3
39
40 enum rkisp1_plane {
41 RKISP1_PLANE_Y = 0,
42 RKISP1_PLANE_CB = 1,
43 RKISP1_PLANE_CR = 2
44 };
45
46 /*
47 * @fourcc: pixel format
48 * @fmt_type: helper filed for pixel format
49 * @uv_swap: if cb cr swapped, for yuv
50 * @write_format: defines how YCbCr self picture data is written to memory
51 * @output_format: defines sp output format
52 * @mbus: the mbus code on the src resizer pad that matches the pixel format
53 */
54 struct rkisp1_capture_fmt_cfg {
55 u32 fourcc;
56 u8 uv_swap;
57 u32 write_format;
58 u32 output_format;
59 u32 mbus;
60 };
61
62 struct rkisp1_capture_ops {
63 void (*config)(struct rkisp1_capture *cap);
64 void (*stop)(struct rkisp1_capture *cap);
65 void (*enable)(struct rkisp1_capture *cap);
66 void (*disable)(struct rkisp1_capture *cap);
67 void (*set_data_path)(struct rkisp1_capture *cap);
68 bool (*is_stopped)(struct rkisp1_capture *cap);
69 };
70
71 struct rkisp1_capture_config {
72 const struct rkisp1_capture_fmt_cfg *fmts;
73 int fmt_size;
74 struct {
75 u32 y_size_init;
76 u32 cb_size_init;
77 u32 cr_size_init;
78 u32 y_base_ad_init;
79 u32 cb_base_ad_init;
80 u32 cr_base_ad_init;
81 u32 y_offs_cnt_init;
82 u32 cb_offs_cnt_init;
83 u32 cr_offs_cnt_init;
84 } mi;
85 };
86
87 /*
88 * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus'
89 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes
90 */
91 static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
92 /* yuv422 */
93 {
94 .fourcc = V4L2_PIX_FMT_YUYV,
95 .uv_swap = 0,
96 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
97 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
98 }, {
99 .fourcc = V4L2_PIX_FMT_YUV422P,
100 .uv_swap = 0,
101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
102 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
103 }, {
104 .fourcc = V4L2_PIX_FMT_NV16,
105 .uv_swap = 0,
106 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
107 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
108 }, {
109 .fourcc = V4L2_PIX_FMT_NV61,
110 .uv_swap = 1,
111 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
112 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
113 }, {
114 .fourcc = V4L2_PIX_FMT_NV16M,
115 .uv_swap = 0,
116 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
117 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
118 }, {
119 .fourcc = V4L2_PIX_FMT_NV61M,
120 .uv_swap = 1,
121 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
122 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
123 }, {
124 .fourcc = V4L2_PIX_FMT_YVU422M,
125 .uv_swap = 1,
126 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
127 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
128 },
129 /* yuv400 */
130 {
131 .fourcc = V4L2_PIX_FMT_GREY,
132 .uv_swap = 0,
133 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
134 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
135 },
136 /* yuv420 */
137 {
138 .fourcc = V4L2_PIX_FMT_NV21,
139 .uv_swap = 1,
140 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
141 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
142 }, {
143 .fourcc = V4L2_PIX_FMT_NV12,
144 .uv_swap = 0,
145 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
146 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
147 }, {
148 .fourcc = V4L2_PIX_FMT_NV21M,
149 .uv_swap = 1,
150 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
151 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
152 }, {
153 .fourcc = V4L2_PIX_FMT_NV12M,
154 .uv_swap = 0,
155 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
156 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
157 }, {
158 .fourcc = V4L2_PIX_FMT_YUV420,
159 .uv_swap = 0,
160 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
161 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
162 }, {
163 .fourcc = V4L2_PIX_FMT_YVU420,
164 .uv_swap = 1,
165 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
166 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
167 },
168 /* raw */
169 {
170 .fourcc = V4L2_PIX_FMT_SRGGB8,
171 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
172 .mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
173 }, {
174 .fourcc = V4L2_PIX_FMT_SGRBG8,
175 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
176 .mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
177 }, {
178 .fourcc = V4L2_PIX_FMT_SGBRG8,
179 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
180 .mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
181 }, {
182 .fourcc = V4L2_PIX_FMT_SBGGR8,
183 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
184 .mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
185 }, {
186 .fourcc = V4L2_PIX_FMT_SRGGB10,
187 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
188 .mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
189 }, {
190 .fourcc = V4L2_PIX_FMT_SGRBG10,
191 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
192 .mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
193 }, {
194 .fourcc = V4L2_PIX_FMT_SGBRG10,
195 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
196 .mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
197 }, {
198 .fourcc = V4L2_PIX_FMT_SBGGR10,
199 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
200 .mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
201 }, {
202 .fourcc = V4L2_PIX_FMT_SRGGB12,
203 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
204 .mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
205 }, {
206 .fourcc = V4L2_PIX_FMT_SGRBG12,
207 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
208 .mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
209 }, {
210 .fourcc = V4L2_PIX_FMT_SGBRG12,
211 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
212 .mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
213 }, {
214 .fourcc = V4L2_PIX_FMT_SBGGR12,
215 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
216 .mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
217 },
218 };
219
220 /*
221 * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus'
222 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes
223 */
224 static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = {
225 /* yuv422 */
226 {
227 .fourcc = V4L2_PIX_FMT_YUYV,
228 .uv_swap = 0,
229 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
230 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
231 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
232 }, {
233 .fourcc = V4L2_PIX_FMT_YUV422P,
234 .uv_swap = 0,
235 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
236 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
237 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
238 }, {
239 .fourcc = V4L2_PIX_FMT_NV16,
240 .uv_swap = 0,
241 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
242 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
243 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
244 }, {
245 .fourcc = V4L2_PIX_FMT_NV61,
246 .uv_swap = 1,
247 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
248 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
249 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
250 }, {
251 .fourcc = V4L2_PIX_FMT_NV16M,
252 .uv_swap = 0,
253 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
254 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
255 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
256 }, {
257 .fourcc = V4L2_PIX_FMT_NV61M,
258 .uv_swap = 1,
259 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
260 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
261 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
262 }, {
263 .fourcc = V4L2_PIX_FMT_YVU422M,
264 .uv_swap = 1,
265 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
266 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
267 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
268 },
269 /* yuv400 */
270 {
271 .fourcc = V4L2_PIX_FMT_GREY,
272 .uv_swap = 0,
273 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
274 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
275 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
276 },
277 /* rgb */
278 {
279 .fourcc = V4L2_PIX_FMT_XBGR32,
280 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
281 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888,
282 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
283 }, {
284 .fourcc = V4L2_PIX_FMT_RGB565,
285 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
286 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565,
287 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
288 },
289 /* yuv420 */
290 {
291 .fourcc = V4L2_PIX_FMT_NV21,
292 .uv_swap = 1,
293 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
294 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
295 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
296 }, {
297 .fourcc = V4L2_PIX_FMT_NV12,
298 .uv_swap = 0,
299 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
300 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
301 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
302 }, {
303 .fourcc = V4L2_PIX_FMT_NV21M,
304 .uv_swap = 1,
305 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
306 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
307 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
308 }, {
309 .fourcc = V4L2_PIX_FMT_NV12M,
310 .uv_swap = 0,
311 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
312 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
313 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
314 }, {
315 .fourcc = V4L2_PIX_FMT_YUV420,
316 .uv_swap = 0,
317 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
318 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
319 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
320 }, {
321 .fourcc = V4L2_PIX_FMT_YVU420,
322 .uv_swap = 1,
323 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
324 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
325 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
326 },
327 };
328
329 static const struct rkisp1_capture_config rkisp1_capture_config_mp = {
330 .fmts = rkisp1_mp_fmts,
331 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts),
332 .mi = {
333 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT,
334 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT,
335 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT,
336 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT,
337 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT,
338 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT,
339 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT,
340 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT,
341 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT,
342 },
343 };
344
345 static const struct rkisp1_capture_config rkisp1_capture_config_sp = {
346 .fmts = rkisp1_sp_fmts,
347 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts),
348 .mi = {
349 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT,
350 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT,
351 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT,
352 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT,
353 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT,
354 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT,
355 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT,
356 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT,
357 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT,
358 },
359 };
360
361 static inline struct rkisp1_vdev_node *
rkisp1_vdev_to_node(struct video_device * vdev)362 rkisp1_vdev_to_node(struct video_device *vdev)
363 {
364 return container_of(vdev, struct rkisp1_vdev_node, vdev);
365 }
366
rkisp1_cap_enum_mbus_codes(struct rkisp1_capture * cap,struct v4l2_subdev_mbus_code_enum * code)367 int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap,
368 struct v4l2_subdev_mbus_code_enum *code)
369 {
370 const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts;
371 /*
372 * initialize curr_mbus to non existing mbus code 0 to ensure it is
373 * different from fmts[0].mbus
374 */
375 u32 curr_mbus = 0;
376 int i, n = 0;
377
378 for (i = 0; i < cap->config->fmt_size; i++) {
379 if (fmts[i].mbus == curr_mbus)
380 continue;
381
382 curr_mbus = fmts[i].mbus;
383 if (n++ == code->index) {
384 code->code = curr_mbus;
385 return 0;
386 }
387 }
388 return -EINVAL;
389 }
390
391 /* ----------------------------------------------------------------------------
392 * Stream operations for self-picture path (sp) and main-picture path (mp)
393 */
394
rkisp1_mi_config_ctrl(struct rkisp1_capture * cap)395 static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap)
396 {
397 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
398
399 mi_ctrl &= ~GENMASK(17, 16);
400 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64;
401
402 mi_ctrl &= ~GENMASK(19, 18);
403 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64;
404
405 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN |
406 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN;
407
408 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
409 }
410
rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane * pixm,unsigned int component)411 static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm,
412 unsigned int component)
413 {
414 /*
415 * If packed format, then plane_fmt[0].sizeimage is the sum of all
416 * components, so we need to calculate just the size of Y component.
417 * See rkisp1_fill_pixfmt().
418 */
419 if (!component && pixm->num_planes == 1)
420 return pixm->plane_fmt[0].bytesperline * pixm->height;
421 return pixm->plane_fmt[component].sizeimage;
422 }
423
rkisp1_irq_frame_end_enable(struct rkisp1_capture * cap)424 static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap)
425 {
426 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC);
427
428 mi_imsc |= RKISP1_CIF_MI_FRAME(cap);
429 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_IMSC, mi_imsc);
430 }
431
rkisp1_mp_config(struct rkisp1_capture * cap)432 static void rkisp1_mp_config(struct rkisp1_capture *cap)
433 {
434 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
435 struct rkisp1_device *rkisp1 = cap->rkisp1;
436 u32 reg;
437
438 rkisp1_write(rkisp1, cap->config->mi.y_size_init,
439 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y));
440 rkisp1_write(rkisp1, cap->config->mi.cb_size_init,
441 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB));
442 rkisp1_write(rkisp1, cap->config->mi.cr_size_init,
443 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
444
445 rkisp1_irq_frame_end_enable(cap);
446
447 /* set uv swapping for semiplanar formats */
448 if (cap->pix.info->comp_planes == 2) {
449 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
450 if (cap->pix.cfg->uv_swap)
451 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
452 else
453 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
454 rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg);
455 }
456
457 rkisp1_mi_config_ctrl(cap);
458
459 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
460 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK;
461 reg |= cap->pix.cfg->write_format;
462 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, reg);
463
464 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
465 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE;
466 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, reg);
467 }
468
rkisp1_sp_config(struct rkisp1_capture * cap)469 static void rkisp1_sp_config(struct rkisp1_capture *cap)
470 {
471 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
472 struct rkisp1_device *rkisp1 = cap->rkisp1;
473 u32 mi_ctrl, reg;
474
475 rkisp1_write(rkisp1, cap->config->mi.y_size_init,
476 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y));
477 rkisp1_write(rkisp1, cap->config->mi.cb_size_init,
478 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB));
479 rkisp1_write(rkisp1, cap->config->mi.cr_size_init,
480 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
481
482 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_WIDTH, pixm->width);
483 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT, pixm->height);
484 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_LLENGTH, cap->sp_y_stride);
485
486 rkisp1_irq_frame_end_enable(cap);
487
488 /* set uv swapping for semiplanar formats */
489 if (cap->pix.info->comp_planes == 2) {
490 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
491 if (cap->pix.cfg->uv_swap)
492 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
493 else
494 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
495 rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg);
496 }
497
498 rkisp1_mi_config_ctrl(cap);
499
500 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
501 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK;
502 mi_ctrl |= cap->pix.cfg->write_format |
503 RKISP1_MI_CTRL_SP_INPUT_YUV422 |
504 cap->pix.cfg->output_format |
505 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
506 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
507 }
508
rkisp1_mp_disable(struct rkisp1_capture * cap)509 static void rkisp1_mp_disable(struct rkisp1_capture *cap)
510 {
511 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
512
513 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE |
514 RKISP1_CIF_MI_CTRL_RAW_ENABLE);
515 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
516 }
517
rkisp1_sp_disable(struct rkisp1_capture * cap)518 static void rkisp1_sp_disable(struct rkisp1_capture *cap)
519 {
520 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
521
522 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE;
523 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
524 }
525
rkisp1_mp_enable(struct rkisp1_capture * cap)526 static void rkisp1_mp_enable(struct rkisp1_capture *cap)
527 {
528 u32 mi_ctrl;
529
530 rkisp1_mp_disable(cap);
531
532 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
533 if (v4l2_is_format_bayer(cap->pix.info))
534 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE;
535 /* YUV */
536 else
537 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE;
538
539 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
540 }
541
rkisp1_sp_enable(struct rkisp1_capture * cap)542 static void rkisp1_sp_enable(struct rkisp1_capture *cap)
543 {
544 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
545
546 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE;
547 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
548 }
549
rkisp1_mp_sp_stop(struct rkisp1_capture * cap)550 static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap)
551 {
552 if (!cap->is_streaming)
553 return;
554 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_ICR, RKISP1_CIF_MI_FRAME(cap));
555 cap->ops->disable(cap);
556 }
557
rkisp1_mp_is_stopped(struct rkisp1_capture * cap)558 static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap)
559 {
560 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED |
561 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
562
563 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en);
564 }
565
rkisp1_sp_is_stopped(struct rkisp1_capture * cap)566 static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap)
567 {
568 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) &
569 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED);
570 }
571
rkisp1_mp_set_data_path(struct rkisp1_capture * cap)572 static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap)
573 {
574 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
575
576 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP |
577 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI;
578 rkisp1_write(cap->rkisp1, RKISP1_CIF_VI_DPCL, dpcl);
579 }
580
rkisp1_sp_set_data_path(struct rkisp1_capture * cap)581 static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap)
582 {
583 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
584
585 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP;
586 rkisp1_write(cap->rkisp1, RKISP1_CIF_VI_DPCL, dpcl);
587 }
588
589 static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = {
590 .config = rkisp1_mp_config,
591 .enable = rkisp1_mp_enable,
592 .disable = rkisp1_mp_disable,
593 .stop = rkisp1_mp_sp_stop,
594 .set_data_path = rkisp1_mp_set_data_path,
595 .is_stopped = rkisp1_mp_is_stopped,
596 };
597
598 static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = {
599 .config = rkisp1_sp_config,
600 .enable = rkisp1_sp_enable,
601 .disable = rkisp1_sp_disable,
602 .stop = rkisp1_mp_sp_stop,
603 .set_data_path = rkisp1_sp_set_data_path,
604 .is_stopped = rkisp1_sp_is_stopped,
605 };
606
607 /* ----------------------------------------------------------------------------
608 * Frame buffer operations
609 */
610
rkisp1_dummy_buf_create(struct rkisp1_capture * cap)611 static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap)
612 {
613 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
614 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy;
615
616 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
617 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
618 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
619
620 /* The driver never access vaddr, no mapping is required */
621 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev,
622 dummy_buf->size,
623 &dummy_buf->dma_addr,
624 GFP_KERNEL,
625 DMA_ATTR_NO_KERNEL_MAPPING);
626 if (!dummy_buf->vaddr)
627 return -ENOMEM;
628
629 return 0;
630 }
631
rkisp1_dummy_buf_destroy(struct rkisp1_capture * cap)632 static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap)
633 {
634 dma_free_attrs(cap->rkisp1->dev,
635 cap->buf.dummy.size, cap->buf.dummy.vaddr,
636 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING);
637 }
638
rkisp1_set_next_buf(struct rkisp1_capture * cap)639 static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
640 {
641 cap->buf.curr = cap->buf.next;
642 cap->buf.next = NULL;
643
644 if (!list_empty(&cap->buf.queue)) {
645 u32 *buff_addr;
646
647 cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue);
648 list_del(&cap->buf.next->queue);
649
650 buff_addr = cap->buf.next->buff_addr;
651
652 rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init,
653 buff_addr[RKISP1_PLANE_Y]);
654 /*
655 * In order to support grey format we capture
656 * YUV422 planar format from the camera and
657 * set the U and V planes to the dummy buffer
658 */
659 if (cap->pix.cfg->fourcc == V4L2_PIX_FMT_GREY) {
660 rkisp1_write(cap->rkisp1,
661 cap->config->mi.cb_base_ad_init,
662 cap->buf.dummy.dma_addr);
663 rkisp1_write(cap->rkisp1,
664 cap->config->mi.cr_base_ad_init,
665 cap->buf.dummy.dma_addr);
666 } else {
667 rkisp1_write(cap->rkisp1,
668 cap->config->mi.cb_base_ad_init,
669 buff_addr[RKISP1_PLANE_CB]);
670 rkisp1_write(cap->rkisp1,
671 cap->config->mi.cr_base_ad_init,
672 buff_addr[RKISP1_PLANE_CR]);
673 }
674 } else {
675 /*
676 * Use the dummy space allocated by dma_alloc_coherent to
677 * throw data if there is no available buffer.
678 */
679 rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init,
680 cap->buf.dummy.dma_addr);
681 rkisp1_write(cap->rkisp1, cap->config->mi.cb_base_ad_init,
682 cap->buf.dummy.dma_addr);
683 rkisp1_write(cap->rkisp1, cap->config->mi.cr_base_ad_init,
684 cap->buf.dummy.dma_addr);
685 }
686
687 /* Set plane offsets */
688 rkisp1_write(cap->rkisp1, cap->config->mi.y_offs_cnt_init, 0);
689 rkisp1_write(cap->rkisp1, cap->config->mi.cb_offs_cnt_init, 0);
690 rkisp1_write(cap->rkisp1, cap->config->mi.cr_offs_cnt_init, 0);
691 }
692
693 /*
694 * This function is called when a frame end comes. The next frame
695 * is processing and we should set up buffer for next-next frame,
696 * otherwise it will overflow.
697 */
rkisp1_handle_buffer(struct rkisp1_capture * cap)698 static void rkisp1_handle_buffer(struct rkisp1_capture *cap)
699 {
700 struct rkisp1_isp *isp = &cap->rkisp1->isp;
701 struct rkisp1_buffer *curr_buf;
702
703 spin_lock(&cap->buf.lock);
704 curr_buf = cap->buf.curr;
705
706 if (curr_buf) {
707 curr_buf->vb.sequence = isp->frame_sequence;
708 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns();
709 curr_buf->vb.field = V4L2_FIELD_NONE;
710 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
711 } else {
712 cap->rkisp1->debug.frame_drop[cap->id]++;
713 }
714
715 rkisp1_set_next_buf(cap);
716 spin_unlock(&cap->buf.lock);
717 }
718
rkisp1_capture_isr(int irq,void * ctx)719 irqreturn_t rkisp1_capture_isr(int irq, void *ctx)
720 {
721 struct device *dev = ctx;
722 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
723 unsigned int i;
724 u32 status;
725
726 if (!rkisp1->irqs_enabled)
727 return IRQ_NONE;
728
729 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS);
730 if (!status)
731 return IRQ_NONE;
732
733 rkisp1_write(rkisp1, RKISP1_CIF_MI_ICR, status);
734
735 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
736 struct rkisp1_capture *cap = &rkisp1->capture_devs[i];
737
738 if (!(status & RKISP1_CIF_MI_FRAME(cap)))
739 continue;
740 if (!cap->is_stopping) {
741 rkisp1_handle_buffer(cap);
742 continue;
743 }
744 /*
745 * Make sure stream is actually stopped, whose state
746 * can be read from the shadow register, before
747 * wake_up() thread which would immediately free all
748 * frame buffers. stop() takes effect at the next
749 * frame end that sync the configurations to shadow
750 * regs.
751 */
752 if (!cap->ops->is_stopped(cap)) {
753 cap->ops->stop(cap);
754 continue;
755 }
756 cap->is_stopping = false;
757 cap->is_streaming = false;
758 wake_up(&cap->done);
759 }
760
761 return IRQ_HANDLED;
762 }
763
764 /* ----------------------------------------------------------------------------
765 * Vb2 operations
766 */
767
rkisp1_vb2_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])768 static int rkisp1_vb2_queue_setup(struct vb2_queue *queue,
769 unsigned int *num_buffers,
770 unsigned int *num_planes,
771 unsigned int sizes[],
772 struct device *alloc_devs[])
773 {
774 struct rkisp1_capture *cap = queue->drv_priv;
775 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
776 unsigned int i;
777
778 if (*num_planes) {
779 if (*num_planes != pixm->num_planes)
780 return -EINVAL;
781
782 for (i = 0; i < pixm->num_planes; i++)
783 if (sizes[i] < pixm->plane_fmt[i].sizeimage)
784 return -EINVAL;
785 } else {
786 *num_planes = pixm->num_planes;
787 for (i = 0; i < pixm->num_planes; i++)
788 sizes[i] = pixm->plane_fmt[i].sizeimage;
789 }
790
791 return 0;
792 }
793
rkisp1_vb2_buf_init(struct vb2_buffer * vb)794 static int rkisp1_vb2_buf_init(struct vb2_buffer *vb)
795 {
796 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
797 struct rkisp1_buffer *ispbuf =
798 container_of(vbuf, struct rkisp1_buffer, vb);
799 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
800 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
801 unsigned int i;
802
803 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
804 for (i = 0; i < pixm->num_planes; i++)
805 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
806
807 /* Convert to non-MPLANE */
808 if (pixm->num_planes == 1) {
809 ispbuf->buff_addr[RKISP1_PLANE_CB] =
810 ispbuf->buff_addr[RKISP1_PLANE_Y] +
811 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y);
812 ispbuf->buff_addr[RKISP1_PLANE_CR] =
813 ispbuf->buff_addr[RKISP1_PLANE_CB] +
814 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB);
815 }
816
817 /*
818 * uv swap can be supported for planar formats by switching
819 * the address of cb and cr
820 */
821 if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap)
822 swap(ispbuf->buff_addr[RKISP1_PLANE_CR],
823 ispbuf->buff_addr[RKISP1_PLANE_CB]);
824 return 0;
825 }
826
rkisp1_vb2_buf_queue(struct vb2_buffer * vb)827 static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb)
828 {
829 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
830 struct rkisp1_buffer *ispbuf =
831 container_of(vbuf, struct rkisp1_buffer, vb);
832 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
833
834 spin_lock_irq(&cap->buf.lock);
835 list_add_tail(&ispbuf->queue, &cap->buf.queue);
836 spin_unlock_irq(&cap->buf.lock);
837 }
838
rkisp1_vb2_buf_prepare(struct vb2_buffer * vb)839 static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb)
840 {
841 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
842 unsigned int i;
843
844 for (i = 0; i < cap->pix.fmt.num_planes; i++) {
845 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage;
846
847 if (vb2_plane_size(vb, i) < size) {
848 dev_err(cap->rkisp1->dev,
849 "User buffer too small (%ld < %ld)\n",
850 vb2_plane_size(vb, i), size);
851 return -EINVAL;
852 }
853 vb2_set_plane_payload(vb, i, size);
854 }
855
856 return 0;
857 }
858
rkisp1_return_all_buffers(struct rkisp1_capture * cap,enum vb2_buffer_state state)859 static void rkisp1_return_all_buffers(struct rkisp1_capture *cap,
860 enum vb2_buffer_state state)
861 {
862 struct rkisp1_buffer *buf;
863
864 spin_lock_irq(&cap->buf.lock);
865 if (cap->buf.curr) {
866 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state);
867 cap->buf.curr = NULL;
868 }
869 if (cap->buf.next) {
870 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state);
871 cap->buf.next = NULL;
872 }
873 while (!list_empty(&cap->buf.queue)) {
874 buf = list_first_entry(&cap->buf.queue,
875 struct rkisp1_buffer, queue);
876 list_del(&buf->queue);
877 vb2_buffer_done(&buf->vb.vb2_buf, state);
878 }
879 spin_unlock_irq(&cap->buf.lock);
880 }
881
882 /*
883 * Most registers inside the rockchip ISP1 have shadow register since
884 * they must not be changed while processing a frame.
885 * Usually, each sub-module updates its shadow register after
886 * processing the last pixel of a frame.
887 */
rkisp1_cap_stream_enable(struct rkisp1_capture * cap)888 static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
889 {
890 struct rkisp1_device *rkisp1 = cap->rkisp1;
891 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
892
893 cap->ops->set_data_path(cap);
894 cap->ops->config(cap);
895
896 /* Setup a buffer for the next frame */
897 spin_lock_irq(&cap->buf.lock);
898 rkisp1_set_next_buf(cap);
899 cap->ops->enable(cap);
900 /* It's safe to configure ACTIVE and SHADOW registers for the
901 * first stream. While when the second is starting, do NOT
902 * force update because it also updates the first one.
903 *
904 * The latter case would drop one more buffer(that is 2) since
905 * there's no buffer in a shadow register when the second FE received.
906 * This's also required because the second FE maybe corrupt
907 * especially when run at 120fps.
908 */
909 if (!other->is_streaming) {
910 /* force cfg update */
911 rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
912 RKISP1_CIF_MI_INIT_SOFT_UPD);
913 rkisp1_set_next_buf(cap);
914 }
915 spin_unlock_irq(&cap->buf.lock);
916 cap->is_streaming = true;
917 }
918
rkisp1_cap_stream_disable(struct rkisp1_capture * cap)919 static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap)
920 {
921 int ret;
922
923 /* Stream should stop in interrupt. If it doesn't, stop it by force. */
924 cap->is_stopping = true;
925 ret = wait_event_timeout(cap->done,
926 !cap->is_streaming,
927 msecs_to_jiffies(1000));
928 if (!ret) {
929 cap->rkisp1->debug.stop_timeout[cap->id]++;
930 cap->ops->stop(cap);
931 cap->is_stopping = false;
932 cap->is_streaming = false;
933 }
934 }
935
936 /*
937 * rkisp1_pipeline_stream_disable - disable nodes in the pipeline
938 *
939 * Call s_stream(false) in the reverse order from
940 * rkisp1_pipeline_stream_enable() and disable the DMA engine.
941 * Should be called before video_device_pipeline_stop()
942 */
rkisp1_pipeline_stream_disable(struct rkisp1_capture * cap)943 static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap)
944 __must_hold(&cap->rkisp1->stream_lock)
945 {
946 struct rkisp1_device *rkisp1 = cap->rkisp1;
947
948 rkisp1_cap_stream_disable(cap);
949
950 /*
951 * If the other capture is streaming, isp and sensor nodes shouldn't
952 * be disabled, skip them.
953 */
954 if (rkisp1->pipe.start_count < 2)
955 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false);
956
957 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream,
958 false);
959 }
960
961 /*
962 * rkisp1_pipeline_stream_enable - enable nodes in the pipeline
963 *
964 * Enable the DMA Engine and call s_stream(true) through the pipeline.
965 * Should be called after video_device_pipeline_start()
966 */
rkisp1_pipeline_stream_enable(struct rkisp1_capture * cap)967 static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap)
968 __must_hold(&cap->rkisp1->stream_lock)
969 {
970 struct rkisp1_device *rkisp1 = cap->rkisp1;
971 int ret;
972
973 rkisp1_cap_stream_enable(cap);
974
975 ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video,
976 s_stream, true);
977 if (ret)
978 goto err_disable_cap;
979
980 /*
981 * If the other capture is streaming, isp and sensor nodes are already
982 * enabled, skip them.
983 */
984 if (rkisp1->pipe.start_count > 1)
985 return 0;
986
987 ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true);
988 if (ret)
989 goto err_disable_rsz;
990
991 return 0;
992
993 err_disable_rsz:
994 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream,
995 false);
996 err_disable_cap:
997 rkisp1_cap_stream_disable(cap);
998
999 return ret;
1000 }
1001
rkisp1_vb2_stop_streaming(struct vb2_queue * queue)1002 static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue)
1003 {
1004 struct rkisp1_capture *cap = queue->drv_priv;
1005 struct rkisp1_vdev_node *node = &cap->vnode;
1006 struct rkisp1_device *rkisp1 = cap->rkisp1;
1007 int ret;
1008
1009 mutex_lock(&cap->rkisp1->stream_lock);
1010
1011 rkisp1_pipeline_stream_disable(cap);
1012
1013 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR);
1014
1015 v4l2_pipeline_pm_put(&node->vdev.entity);
1016 ret = pm_runtime_put(rkisp1->dev);
1017 if (ret < 0)
1018 dev_err(rkisp1->dev, "power down failed error:%d\n", ret);
1019
1020 rkisp1_dummy_buf_destroy(cap);
1021
1022 video_device_pipeline_stop(&node->vdev);
1023
1024 mutex_unlock(&cap->rkisp1->stream_lock);
1025 }
1026
1027 static int
rkisp1_vb2_start_streaming(struct vb2_queue * queue,unsigned int count)1028 rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
1029 {
1030 struct rkisp1_capture *cap = queue->drv_priv;
1031 struct media_entity *entity = &cap->vnode.vdev.entity;
1032 int ret;
1033
1034 mutex_lock(&cap->rkisp1->stream_lock);
1035
1036 ret = video_device_pipeline_start(&cap->vnode.vdev, &cap->rkisp1->pipe);
1037 if (ret) {
1038 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret);
1039 goto err_ret_buffers;
1040 }
1041
1042 ret = rkisp1_dummy_buf_create(cap);
1043 if (ret)
1044 goto err_pipeline_stop;
1045
1046 ret = pm_runtime_resume_and_get(cap->rkisp1->dev);
1047 if (ret < 0) {
1048 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret);
1049 goto err_destroy_dummy;
1050 }
1051 ret = v4l2_pipeline_pm_get(entity);
1052 if (ret) {
1053 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret);
1054 goto err_pipe_pm_put;
1055 }
1056
1057 ret = rkisp1_pipeline_stream_enable(cap);
1058 if (ret)
1059 goto err_v4l2_pm_put;
1060
1061 mutex_unlock(&cap->rkisp1->stream_lock);
1062
1063 return 0;
1064
1065 err_v4l2_pm_put:
1066 v4l2_pipeline_pm_put(entity);
1067 err_pipe_pm_put:
1068 pm_runtime_put(cap->rkisp1->dev);
1069 err_destroy_dummy:
1070 rkisp1_dummy_buf_destroy(cap);
1071 err_pipeline_stop:
1072 video_device_pipeline_stop(&cap->vnode.vdev);
1073 err_ret_buffers:
1074 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED);
1075 mutex_unlock(&cap->rkisp1->stream_lock);
1076
1077 return ret;
1078 }
1079
1080 static const struct vb2_ops rkisp1_vb2_ops = {
1081 .queue_setup = rkisp1_vb2_queue_setup,
1082 .buf_init = rkisp1_vb2_buf_init,
1083 .buf_queue = rkisp1_vb2_buf_queue,
1084 .buf_prepare = rkisp1_vb2_buf_prepare,
1085 .wait_prepare = vb2_ops_wait_prepare,
1086 .wait_finish = vb2_ops_wait_finish,
1087 .stop_streaming = rkisp1_vb2_stop_streaming,
1088 .start_streaming = rkisp1_vb2_start_streaming,
1089 };
1090
1091 /* ----------------------------------------------------------------------------
1092 * IOCTLs operations
1093 */
1094
1095 static const struct v4l2_format_info *
rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane * pixm,enum rkisp1_stream_id id)1096 rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm,
1097 enum rkisp1_stream_id id)
1098 {
1099 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0];
1100 const struct v4l2_format_info *info;
1101 unsigned int i;
1102 u32 stride;
1103
1104 memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt));
1105 info = v4l2_format_info(pixm->pixelformat);
1106 pixm->num_planes = info->mem_planes;
1107 stride = info->bpp[0] * pixm->width;
1108 /* Self path supports custom stride but Main path doesn't */
1109 if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride)
1110 plane_y->bytesperline = stride;
1111 plane_y->sizeimage = plane_y->bytesperline * pixm->height;
1112
1113 /* normalize stride to pixels per line */
1114 stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]);
1115
1116 for (i = 1; i < info->comp_planes; i++) {
1117 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i];
1118
1119 /* bytesperline for other components derive from Y component */
1120 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) *
1121 info->bpp[i];
1122 plane->sizeimage = plane->bytesperline *
1123 DIV_ROUND_UP(pixm->height, info->vdiv);
1124 }
1125
1126 /*
1127 * If pixfmt is packed, then plane_fmt[0] should contain the total size
1128 * considering all components. plane_fmt[i] for i > 0 should be ignored
1129 * by userspace as mem_planes == 1, but we are keeping information there
1130 * for convenience.
1131 */
1132 if (info->mem_planes == 1)
1133 for (i = 1; i < info->comp_planes; i++)
1134 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage;
1135
1136 return info;
1137 }
1138
1139 static const struct rkisp1_capture_fmt_cfg *
rkisp1_find_fmt_cfg(const struct rkisp1_capture * cap,const u32 pixelfmt)1140 rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt)
1141 {
1142 unsigned int i;
1143
1144 for (i = 0; i < cap->config->fmt_size; i++) {
1145 if (cap->config->fmts[i].fourcc == pixelfmt)
1146 return &cap->config->fmts[i];
1147 }
1148 return NULL;
1149 }
1150
rkisp1_try_fmt(const struct rkisp1_capture * cap,struct v4l2_pix_format_mplane * pixm,const struct rkisp1_capture_fmt_cfg ** fmt_cfg,const struct v4l2_format_info ** fmt_info)1151 static void rkisp1_try_fmt(const struct rkisp1_capture *cap,
1152 struct v4l2_pix_format_mplane *pixm,
1153 const struct rkisp1_capture_fmt_cfg **fmt_cfg,
1154 const struct v4l2_format_info **fmt_info)
1155 {
1156 const struct rkisp1_capture_config *config = cap->config;
1157 const struct rkisp1_capture_fmt_cfg *fmt;
1158 const struct v4l2_format_info *info;
1159 static const unsigned int max_widths[] = {
1160 RKISP1_RSZ_MP_SRC_MAX_WIDTH, RKISP1_RSZ_SP_SRC_MAX_WIDTH
1161 };
1162 static const unsigned int max_heights[] = {
1163 RKISP1_RSZ_MP_SRC_MAX_HEIGHT, RKISP1_RSZ_SP_SRC_MAX_HEIGHT
1164 };
1165
1166 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat);
1167 if (!fmt) {
1168 fmt = config->fmts;
1169 pixm->pixelformat = fmt->fourcc;
1170 }
1171
1172 pixm->width = clamp_t(u32, pixm->width,
1173 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]);
1174 pixm->height = clamp_t(u32, pixm->height,
1175 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]);
1176
1177 pixm->field = V4L2_FIELD_NONE;
1178 pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
1179 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1180 pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
1181
1182 info = rkisp1_fill_pixfmt(pixm, cap->id);
1183
1184 if (fmt_cfg)
1185 *fmt_cfg = fmt;
1186 if (fmt_info)
1187 *fmt_info = info;
1188 }
1189
rkisp1_set_fmt(struct rkisp1_capture * cap,struct v4l2_pix_format_mplane * pixm)1190 static void rkisp1_set_fmt(struct rkisp1_capture *cap,
1191 struct v4l2_pix_format_mplane *pixm)
1192 {
1193 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info);
1194 cap->pix.fmt = *pixm;
1195
1196 /* SP supports custom stride in number of pixels of the Y plane */
1197 if (cap->id == RKISP1_SELFPATH)
1198 cap->sp_y_stride = pixm->plane_fmt[0].bytesperline /
1199 cap->pix.info->bpp[0];
1200 }
1201
rkisp1_try_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1202 static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh,
1203 struct v4l2_format *f)
1204 {
1205 struct rkisp1_capture *cap = video_drvdata(file);
1206
1207 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL);
1208
1209 return 0;
1210 }
1211
rkisp1_enum_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)1212 static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
1213 struct v4l2_fmtdesc *f)
1214 {
1215 struct rkisp1_capture *cap = video_drvdata(file);
1216 const struct rkisp1_capture_fmt_cfg *fmt = NULL;
1217 unsigned int i, n = 0;
1218
1219 if (!f->mbus_code) {
1220 if (f->index >= cap->config->fmt_size)
1221 return -EINVAL;
1222
1223 fmt = &cap->config->fmts[f->index];
1224 f->pixelformat = fmt->fourcc;
1225 return 0;
1226 }
1227
1228 for (i = 0; i < cap->config->fmt_size; i++) {
1229 if (cap->config->fmts[i].mbus != f->mbus_code)
1230 continue;
1231
1232 if (n++ == f->index) {
1233 f->pixelformat = cap->config->fmts[i].fourcc;
1234 return 0;
1235 }
1236 }
1237 return -EINVAL;
1238 }
1239
rkisp1_enum_framesizes(struct file * file,void * fh,struct v4l2_frmsizeenum * fsize)1240 static int rkisp1_enum_framesizes(struct file *file, void *fh,
1241 struct v4l2_frmsizeenum *fsize)
1242 {
1243 static const unsigned int max_widths[] = {
1244 RKISP1_RSZ_MP_SRC_MAX_WIDTH,
1245 RKISP1_RSZ_SP_SRC_MAX_WIDTH,
1246 };
1247 static const unsigned int max_heights[] = {
1248 RKISP1_RSZ_MP_SRC_MAX_HEIGHT,
1249 RKISP1_RSZ_SP_SRC_MAX_HEIGHT,
1250 };
1251 struct rkisp1_capture *cap = video_drvdata(file);
1252
1253 if (fsize->index != 0)
1254 return -EINVAL;
1255
1256 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
1257
1258 fsize->stepwise.min_width = RKISP1_RSZ_SRC_MIN_WIDTH;
1259 fsize->stepwise.max_width = max_widths[cap->id];
1260 fsize->stepwise.step_width = 2;
1261
1262 fsize->stepwise.min_height = RKISP1_RSZ_SRC_MIN_HEIGHT;
1263 fsize->stepwise.max_height = max_heights[cap->id];
1264 fsize->stepwise.step_height = 2;
1265
1266 return 0;
1267 }
1268
rkisp1_s_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_format * f)1269 static int rkisp1_s_fmt_vid_cap_mplane(struct file *file,
1270 void *priv, struct v4l2_format *f)
1271 {
1272 struct rkisp1_capture *cap = video_drvdata(file);
1273 struct rkisp1_vdev_node *node =
1274 rkisp1_vdev_to_node(&cap->vnode.vdev);
1275
1276 if (vb2_is_busy(&node->buf_queue))
1277 return -EBUSY;
1278
1279 rkisp1_set_fmt(cap, &f->fmt.pix_mp);
1280
1281 return 0;
1282 }
1283
rkisp1_g_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1284 static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh,
1285 struct v4l2_format *f)
1286 {
1287 struct rkisp1_capture *cap = video_drvdata(file);
1288
1289 f->fmt.pix_mp = cap->pix.fmt;
1290
1291 return 0;
1292 }
1293
1294 static int
rkisp1_querycap(struct file * file,void * priv,struct v4l2_capability * cap)1295 rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
1296 {
1297 strscpy(cap->driver, RKISP1_DRIVER_NAME, sizeof(cap->driver));
1298 strscpy(cap->card, RKISP1_DRIVER_NAME, sizeof(cap->card));
1299 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info));
1300
1301 return 0;
1302 }
1303
1304 static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = {
1305 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1306 .vidioc_querybuf = vb2_ioctl_querybuf,
1307 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1308 .vidioc_qbuf = vb2_ioctl_qbuf,
1309 .vidioc_expbuf = vb2_ioctl_expbuf,
1310 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1311 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1312 .vidioc_streamon = vb2_ioctl_streamon,
1313 .vidioc_streamoff = vb2_ioctl_streamoff,
1314 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane,
1315 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane,
1316 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane,
1317 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane,
1318 .vidioc_enum_framesizes = rkisp1_enum_framesizes,
1319 .vidioc_querycap = rkisp1_querycap,
1320 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1321 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1322 };
1323
rkisp1_capture_link_validate(struct media_link * link)1324 static int rkisp1_capture_link_validate(struct media_link *link)
1325 {
1326 struct video_device *vdev =
1327 media_entity_to_video_device(link->sink->entity);
1328 struct v4l2_subdev *sd =
1329 media_entity_to_v4l2_subdev(link->source->entity);
1330 struct rkisp1_capture *cap = video_get_drvdata(vdev);
1331 const struct rkisp1_capture_fmt_cfg *fmt =
1332 rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat);
1333 struct v4l2_subdev_format sd_fmt = {
1334 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1335 .pad = link->source->index,
1336 };
1337 int ret;
1338
1339 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt);
1340 if (ret)
1341 return ret;
1342
1343 if (sd_fmt.format.height != cap->pix.fmt.height ||
1344 sd_fmt.format.width != cap->pix.fmt.width ||
1345 sd_fmt.format.code != fmt->mbus) {
1346 dev_dbg(cap->rkisp1->dev,
1347 "link '%s':%u -> '%s':%u not valid: 0x%04x/%ux%u != 0x%04x/%ux%u\n",
1348 link->source->entity->name, link->source->index,
1349 link->sink->entity->name, link->sink->index,
1350 sd_fmt.format.code, sd_fmt.format.width,
1351 sd_fmt.format.height, fmt->mbus, cap->pix.fmt.width,
1352 cap->pix.fmt.height);
1353 return -EPIPE;
1354 }
1355
1356 return 0;
1357 }
1358
1359 /* ----------------------------------------------------------------------------
1360 * core functions
1361 */
1362
1363 static const struct media_entity_operations rkisp1_media_ops = {
1364 .link_validate = rkisp1_capture_link_validate,
1365 };
1366
1367 static const struct v4l2_file_operations rkisp1_fops = {
1368 .open = v4l2_fh_open,
1369 .release = vb2_fop_release,
1370 .unlocked_ioctl = video_ioctl2,
1371 .poll = vb2_fop_poll,
1372 .mmap = vb2_fop_mmap,
1373 };
1374
rkisp1_unregister_capture(struct rkisp1_capture * cap)1375 static void rkisp1_unregister_capture(struct rkisp1_capture *cap)
1376 {
1377 if (!video_is_registered(&cap->vnode.vdev))
1378 return;
1379
1380 media_entity_cleanup(&cap->vnode.vdev.entity);
1381 vb2_video_unregister_device(&cap->vnode.vdev);
1382 mutex_destroy(&cap->vnode.vlock);
1383 }
1384
rkisp1_capture_devs_unregister(struct rkisp1_device * rkisp1)1385 void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1)
1386 {
1387 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH];
1388 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH];
1389
1390 rkisp1_unregister_capture(mp);
1391 rkisp1_unregister_capture(sp);
1392 }
1393
rkisp1_register_capture(struct rkisp1_capture * cap)1394 static int rkisp1_register_capture(struct rkisp1_capture *cap)
1395 {
1396 static const char * const dev_names[] = {
1397 RKISP1_MP_DEV_NAME, RKISP1_SP_DEV_NAME
1398 };
1399 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev;
1400 struct video_device *vdev = &cap->vnode.vdev;
1401 struct rkisp1_vdev_node *node;
1402 struct vb2_queue *q;
1403 int ret;
1404
1405 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name));
1406 node = rkisp1_vdev_to_node(vdev);
1407 mutex_init(&node->vlock);
1408
1409 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops;
1410 vdev->release = video_device_release_empty;
1411 vdev->fops = &rkisp1_fops;
1412 vdev->minor = -1;
1413 vdev->v4l2_dev = v4l2_dev;
1414 vdev->lock = &node->vlock;
1415 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1416 V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
1417 vdev->entity.ops = &rkisp1_media_ops;
1418 video_set_drvdata(vdev, cap);
1419 vdev->vfl_dir = VFL_DIR_RX;
1420 node->pad.flags = MEDIA_PAD_FL_SINK;
1421
1422 q = &node->buf_queue;
1423 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1424 q->io_modes = VB2_MMAP | VB2_DMABUF;
1425 q->drv_priv = cap;
1426 q->ops = &rkisp1_vb2_ops;
1427 q->mem_ops = &vb2_dma_contig_memops;
1428 q->buf_struct_size = sizeof(struct rkisp1_buffer);
1429 q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED;
1430 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1431 q->lock = &node->vlock;
1432 q->dev = cap->rkisp1->dev;
1433 ret = vb2_queue_init(q);
1434 if (ret) {
1435 dev_err(cap->rkisp1->dev,
1436 "vb2 queue init failed (err=%d)\n", ret);
1437 goto error;
1438 }
1439
1440 vdev->queue = q;
1441
1442 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
1443 if (ret)
1444 goto error;
1445
1446 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1447 if (ret) {
1448 dev_err(cap->rkisp1->dev,
1449 "failed to register %s, ret=%d\n", vdev->name, ret);
1450 goto error;
1451 }
1452
1453 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name,
1454 vdev->num);
1455
1456 return 0;
1457
1458 error:
1459 media_entity_cleanup(&vdev->entity);
1460 mutex_destroy(&node->vlock);
1461 return ret;
1462 }
1463
1464 static void
rkisp1_capture_init(struct rkisp1_device * rkisp1,enum rkisp1_stream_id id)1465 rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id)
1466 {
1467 struct rkisp1_capture *cap = &rkisp1->capture_devs[id];
1468 struct v4l2_pix_format_mplane pixm;
1469
1470 memset(cap, 0, sizeof(*cap));
1471 cap->id = id;
1472 cap->rkisp1 = rkisp1;
1473
1474 INIT_LIST_HEAD(&cap->buf.queue);
1475 init_waitqueue_head(&cap->done);
1476 spin_lock_init(&cap->buf.lock);
1477 if (cap->id == RKISP1_SELFPATH) {
1478 cap->ops = &rkisp1_capture_ops_sp;
1479 cap->config = &rkisp1_capture_config_sp;
1480 } else {
1481 cap->ops = &rkisp1_capture_ops_mp;
1482 cap->config = &rkisp1_capture_config_mp;
1483 }
1484
1485 cap->is_streaming = false;
1486
1487 memset(&pixm, 0, sizeof(pixm));
1488 pixm.pixelformat = V4L2_PIX_FMT_YUYV;
1489 pixm.width = RKISP1_DEFAULT_WIDTH;
1490 pixm.height = RKISP1_DEFAULT_HEIGHT;
1491 rkisp1_set_fmt(cap, &pixm);
1492 }
1493
rkisp1_capture_devs_register(struct rkisp1_device * rkisp1)1494 int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1)
1495 {
1496 unsigned int i;
1497 int ret;
1498
1499 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) {
1500 struct rkisp1_capture *cap = &rkisp1->capture_devs[i];
1501
1502 rkisp1_capture_init(rkisp1, i);
1503
1504 ret = rkisp1_register_capture(cap);
1505 if (ret) {
1506 rkisp1_capture_devs_unregister(rkisp1);
1507 return ret;
1508 }
1509 }
1510
1511 return 0;
1512
1513 }
1514