1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifndef __AMDGPU_RESET_H__
25 #define __AMDGPU_RESET_H__
26
27 #include "amdgpu.h"
28
29 enum AMDGPU_RESET_FLAGS {
30
31 AMDGPU_NEED_FULL_RESET = 0,
32 AMDGPU_SKIP_HW_RESET = 1,
33 AMDGPU_RESET_FOR_DEVICE_REMOVE = 2,
34 };
35
36 struct amdgpu_reset_context {
37 enum amd_reset_method method;
38 struct amdgpu_device *reset_req_dev;
39 struct amdgpu_job *job;
40 struct amdgpu_hive_info *hive;
41 struct list_head *reset_device_list;
42 unsigned long flags;
43 };
44
45 struct amdgpu_reset_handler {
46 enum amd_reset_method reset_method;
47 struct list_head handler_list;
48 int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
49 struct amdgpu_reset_context *context);
50 int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
51 struct amdgpu_reset_context *context);
52 int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
53 struct amdgpu_reset_context *context);
54 int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
55 struct amdgpu_reset_context *context);
56 int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
57 struct amdgpu_reset_context *context);
58
59 int (*do_reset)(struct amdgpu_device *adev);
60 };
61
62 struct amdgpu_reset_control {
63 void *handle;
64 struct work_struct reset_work;
65 struct mutex reset_lock;
66 struct list_head reset_handlers;
67 atomic_t in_reset;
68 enum amd_reset_method active_reset;
69 struct amdgpu_reset_handler *(*get_reset_handler)(
70 struct amdgpu_reset_control *reset_ctl,
71 struct amdgpu_reset_context *context);
72 void (*async_reset)(struct work_struct *work);
73 };
74
75
76 enum amdgpu_reset_domain_type {
77 SINGLE_DEVICE,
78 XGMI_HIVE
79 };
80
81 struct amdgpu_reset_domain {
82 struct kref refcount;
83 struct workqueue_struct *wq;
84 enum amdgpu_reset_domain_type type;
85 struct rw_semaphore sem;
86 atomic_t in_gpu_reset;
87 atomic_t reset_res;
88 };
89
90
91 int amdgpu_reset_init(struct amdgpu_device *adev);
92 int amdgpu_reset_fini(struct amdgpu_device *adev);
93
94 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
95 struct amdgpu_reset_context *reset_context);
96
97 int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
98 struct amdgpu_reset_context *reset_context);
99
100 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
101 struct amdgpu_reset_handler *handler);
102
103 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
104 char *wq_name);
105
106 void amdgpu_reset_destroy_reset_domain(struct kref *ref);
107
amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain * domain)108 static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
109 {
110 return kref_get_unless_zero(&domain->refcount) != 0;
111 }
112
amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain * domain)113 static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
114 {
115 if (domain)
116 kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
117 }
118
amdgpu_reset_domain_schedule(struct amdgpu_reset_domain * domain,struct work_struct * work)119 static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
120 struct work_struct *work)
121 {
122 return queue_work(domain->wq, work);
123 }
124
125 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
126
127 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
128
129 #endif
130