1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Atmel USBA high speed USB device controller
4 *
5 * Copyright (C) 2005-2007 Atmel Corporation
6 */
7 #include <linux/clk.h>
8 #include <linux/clk/at91_pmc.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/slab.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/list.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/ctype.h>
21 #include <linux/usb.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
24 #include <linux/delay.h>
25 #include <linux/of.h>
26 #include <linux/irq.h>
27 #include <linux/gpio/consumer.h>
28
29 #include "atmel_usba_udc.h"
30 #define USBA_VBUS_IRQFLAGS (IRQF_ONESHOT \
31 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)
32
33 #ifdef CONFIG_USB_GADGET_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/uaccess.h>
36
queue_dbg_open(struct inode * inode,struct file * file)37 static int queue_dbg_open(struct inode *inode, struct file *file)
38 {
39 struct usba_ep *ep = inode->i_private;
40 struct usba_request *req, *req_copy;
41 struct list_head *queue_data;
42
43 queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
44 if (!queue_data)
45 return -ENOMEM;
46 INIT_LIST_HEAD(queue_data);
47
48 spin_lock_irq(&ep->udc->lock);
49 list_for_each_entry(req, &ep->queue, queue) {
50 req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
51 if (!req_copy)
52 goto fail;
53 list_add_tail(&req_copy->queue, queue_data);
54 }
55 spin_unlock_irq(&ep->udc->lock);
56
57 file->private_data = queue_data;
58 return 0;
59
60 fail:
61 spin_unlock_irq(&ep->udc->lock);
62 list_for_each_entry_safe(req, req_copy, queue_data, queue) {
63 list_del(&req->queue);
64 kfree(req);
65 }
66 kfree(queue_data);
67 return -ENOMEM;
68 }
69
70 /*
71 * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
72 *
73 * b: buffer address
74 * l: buffer length
75 * I/i: interrupt/no interrupt
76 * Z/z: zero/no zero
77 * S/s: short ok/short not ok
78 * s: status
79 * n: nr_packets
80 * F/f: submitted/not submitted to FIFO
81 * D/d: using/not using DMA
82 * L/l: last transaction/not last transaction
83 */
queue_dbg_read(struct file * file,char __user * buf,size_t nbytes,loff_t * ppos)84 static ssize_t queue_dbg_read(struct file *file, char __user *buf,
85 size_t nbytes, loff_t *ppos)
86 {
87 struct list_head *queue = file->private_data;
88 struct usba_request *req, *tmp_req;
89 size_t len, remaining, actual = 0;
90 char tmpbuf[38];
91
92 if (!access_ok(buf, nbytes))
93 return -EFAULT;
94
95 inode_lock(file_inode(file));
96 list_for_each_entry_safe(req, tmp_req, queue, queue) {
97 len = snprintf(tmpbuf, sizeof(tmpbuf),
98 "%8p %08x %c%c%c %5d %c%c%c\n",
99 req->req.buf, req->req.length,
100 req->req.no_interrupt ? 'i' : 'I',
101 req->req.zero ? 'Z' : 'z',
102 req->req.short_not_ok ? 's' : 'S',
103 req->req.status,
104 req->submitted ? 'F' : 'f',
105 req->using_dma ? 'D' : 'd',
106 req->last_transaction ? 'L' : 'l');
107 len = min(len, sizeof(tmpbuf));
108 if (len > nbytes)
109 break;
110
111 list_del(&req->queue);
112 kfree(req);
113
114 remaining = __copy_to_user(buf, tmpbuf, len);
115 actual += len - remaining;
116 if (remaining)
117 break;
118
119 nbytes -= len;
120 buf += len;
121 }
122 inode_unlock(file_inode(file));
123
124 return actual;
125 }
126
queue_dbg_release(struct inode * inode,struct file * file)127 static int queue_dbg_release(struct inode *inode, struct file *file)
128 {
129 struct list_head *queue_data = file->private_data;
130 struct usba_request *req, *tmp_req;
131
132 list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
133 list_del(&req->queue);
134 kfree(req);
135 }
136 kfree(queue_data);
137 return 0;
138 }
139
regs_dbg_open(struct inode * inode,struct file * file)140 static int regs_dbg_open(struct inode *inode, struct file *file)
141 {
142 struct usba_udc *udc;
143 unsigned int i;
144 u32 *data;
145 int ret = -ENOMEM;
146
147 inode_lock(inode);
148 udc = inode->i_private;
149 data = kmalloc(inode->i_size, GFP_KERNEL);
150 if (!data)
151 goto out;
152
153 spin_lock_irq(&udc->lock);
154 for (i = 0; i < inode->i_size / 4; i++)
155 data[i] = readl_relaxed(udc->regs + i * 4);
156 spin_unlock_irq(&udc->lock);
157
158 file->private_data = data;
159 ret = 0;
160
161 out:
162 inode_unlock(inode);
163
164 return ret;
165 }
166
regs_dbg_read(struct file * file,char __user * buf,size_t nbytes,loff_t * ppos)167 static ssize_t regs_dbg_read(struct file *file, char __user *buf,
168 size_t nbytes, loff_t *ppos)
169 {
170 struct inode *inode = file_inode(file);
171 int ret;
172
173 inode_lock(inode);
174 ret = simple_read_from_buffer(buf, nbytes, ppos,
175 file->private_data,
176 file_inode(file)->i_size);
177 inode_unlock(inode);
178
179 return ret;
180 }
181
regs_dbg_release(struct inode * inode,struct file * file)182 static int regs_dbg_release(struct inode *inode, struct file *file)
183 {
184 kfree(file->private_data);
185 return 0;
186 }
187
188 static const struct file_operations queue_dbg_fops = {
189 .owner = THIS_MODULE,
190 .open = queue_dbg_open,
191 .llseek = no_llseek,
192 .read = queue_dbg_read,
193 .release = queue_dbg_release,
194 };
195
196 static const struct file_operations regs_dbg_fops = {
197 .owner = THIS_MODULE,
198 .open = regs_dbg_open,
199 .llseek = generic_file_llseek,
200 .read = regs_dbg_read,
201 .release = regs_dbg_release,
202 };
203
usba_ep_init_debugfs(struct usba_udc * udc,struct usba_ep * ep)204 static void usba_ep_init_debugfs(struct usba_udc *udc,
205 struct usba_ep *ep)
206 {
207 struct dentry *ep_root;
208
209 ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
210 ep->debugfs_dir = ep_root;
211
212 debugfs_create_file("queue", 0400, ep_root, ep, &queue_dbg_fops);
213 if (ep->can_dma)
214 debugfs_create_u32("dma_status", 0400, ep_root,
215 &ep->last_dma_status);
216 if (ep_is_control(ep))
217 debugfs_create_u32("state", 0400, ep_root, &ep->state);
218 }
219
usba_ep_cleanup_debugfs(struct usba_ep * ep)220 static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
221 {
222 debugfs_remove_recursive(ep->debugfs_dir);
223 }
224
usba_init_debugfs(struct usba_udc * udc)225 static void usba_init_debugfs(struct usba_udc *udc)
226 {
227 struct dentry *root;
228 struct resource *regs_resource;
229
230 root = debugfs_create_dir(udc->gadget.name, usb_debug_root);
231 udc->debugfs_root = root;
232
233 regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
234 CTRL_IOMEM_ID);
235
236 if (regs_resource) {
237 debugfs_create_file_size("regs", 0400, root, udc,
238 ®s_dbg_fops,
239 resource_size(regs_resource));
240 }
241
242 usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
243 }
244
usba_cleanup_debugfs(struct usba_udc * udc)245 static void usba_cleanup_debugfs(struct usba_udc *udc)
246 {
247 usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
248 debugfs_remove_recursive(udc->debugfs_root);
249 }
250 #else
usba_ep_init_debugfs(struct usba_udc * udc,struct usba_ep * ep)251 static inline void usba_ep_init_debugfs(struct usba_udc *udc,
252 struct usba_ep *ep)
253 {
254
255 }
256
usba_ep_cleanup_debugfs(struct usba_ep * ep)257 static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
258 {
259
260 }
261
usba_init_debugfs(struct usba_udc * udc)262 static inline void usba_init_debugfs(struct usba_udc *udc)
263 {
264
265 }
266
usba_cleanup_debugfs(struct usba_udc * udc)267 static inline void usba_cleanup_debugfs(struct usba_udc *udc)
268 {
269
270 }
271 #endif
272
273 static ushort fifo_mode;
274
275 module_param(fifo_mode, ushort, 0x0);
276 MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode");
277
278 /* mode 0 - uses autoconfig */
279
280 /* mode 1 - fits in 8KB, generic max fifo configuration */
281 static struct usba_fifo_cfg mode_1_cfg[] = {
282 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
283 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
284 { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 1, },
285 { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 1, },
286 { .hw_ep_num = 4, .fifo_size = 1024, .nr_banks = 1, },
287 { .hw_ep_num = 5, .fifo_size = 1024, .nr_banks = 1, },
288 { .hw_ep_num = 6, .fifo_size = 1024, .nr_banks = 1, },
289 };
290
291 /* mode 2 - fits in 8KB, performance max fifo configuration */
292 static struct usba_fifo_cfg mode_2_cfg[] = {
293 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
294 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 3, },
295 { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 2, },
296 { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 2, },
297 };
298
299 /* mode 3 - fits in 8KB, mixed fifo configuration */
300 static struct usba_fifo_cfg mode_3_cfg[] = {
301 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
302 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
303 { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
304 { .hw_ep_num = 3, .fifo_size = 512, .nr_banks = 2, },
305 { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
306 { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
307 { .hw_ep_num = 6, .fifo_size = 512, .nr_banks = 2, },
308 };
309
310 /* mode 4 - fits in 8KB, custom fifo configuration */
311 static struct usba_fifo_cfg mode_4_cfg[] = {
312 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
313 { .hw_ep_num = 1, .fifo_size = 512, .nr_banks = 2, },
314 { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
315 { .hw_ep_num = 3, .fifo_size = 8, .nr_banks = 2, },
316 { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
317 { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
318 { .hw_ep_num = 6, .fifo_size = 16, .nr_banks = 2, },
319 { .hw_ep_num = 7, .fifo_size = 8, .nr_banks = 2, },
320 { .hw_ep_num = 8, .fifo_size = 8, .nr_banks = 2, },
321 };
322 /* Add additional configurations here */
323
usba_config_fifo_table(struct usba_udc * udc)324 static int usba_config_fifo_table(struct usba_udc *udc)
325 {
326 int n;
327
328 switch (fifo_mode) {
329 default:
330 fifo_mode = 0;
331 fallthrough;
332 case 0:
333 udc->fifo_cfg = NULL;
334 n = 0;
335 break;
336 case 1:
337 udc->fifo_cfg = mode_1_cfg;
338 n = ARRAY_SIZE(mode_1_cfg);
339 break;
340 case 2:
341 udc->fifo_cfg = mode_2_cfg;
342 n = ARRAY_SIZE(mode_2_cfg);
343 break;
344 case 3:
345 udc->fifo_cfg = mode_3_cfg;
346 n = ARRAY_SIZE(mode_3_cfg);
347 break;
348 case 4:
349 udc->fifo_cfg = mode_4_cfg;
350 n = ARRAY_SIZE(mode_4_cfg);
351 break;
352 }
353 DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode);
354
355 return n;
356 }
357
usba_int_enb_get(struct usba_udc * udc)358 static inline u32 usba_int_enb_get(struct usba_udc *udc)
359 {
360 return udc->int_enb_cache;
361 }
362
usba_int_enb_set(struct usba_udc * udc,u32 mask)363 static inline void usba_int_enb_set(struct usba_udc *udc, u32 mask)
364 {
365 u32 val;
366
367 val = udc->int_enb_cache | mask;
368 usba_writel(udc, INT_ENB, val);
369 udc->int_enb_cache = val;
370 }
371
usba_int_enb_clear(struct usba_udc * udc,u32 mask)372 static inline void usba_int_enb_clear(struct usba_udc *udc, u32 mask)
373 {
374 u32 val;
375
376 val = udc->int_enb_cache & ~mask;
377 usba_writel(udc, INT_ENB, val);
378 udc->int_enb_cache = val;
379 }
380
vbus_is_present(struct usba_udc * udc)381 static int vbus_is_present(struct usba_udc *udc)
382 {
383 if (udc->vbus_pin)
384 return gpiod_get_value(udc->vbus_pin);
385
386 /* No Vbus detection: Assume always present */
387 return 1;
388 }
389
toggle_bias(struct usba_udc * udc,int is_on)390 static void toggle_bias(struct usba_udc *udc, int is_on)
391 {
392 if (udc->errata && udc->errata->toggle_bias)
393 udc->errata->toggle_bias(udc, is_on);
394 }
395
generate_bias_pulse(struct usba_udc * udc)396 static void generate_bias_pulse(struct usba_udc *udc)
397 {
398 if (!udc->bias_pulse_needed)
399 return;
400
401 if (udc->errata && udc->errata->pulse_bias)
402 udc->errata->pulse_bias(udc);
403
404 udc->bias_pulse_needed = false;
405 }
406
next_fifo_transaction(struct usba_ep * ep,struct usba_request * req)407 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
408 {
409 unsigned int transaction_len;
410
411 transaction_len = req->req.length - req->req.actual;
412 req->last_transaction = 1;
413 if (transaction_len > ep->ep.maxpacket) {
414 transaction_len = ep->ep.maxpacket;
415 req->last_transaction = 0;
416 } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
417 req->last_transaction = 0;
418
419 DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
420 ep->ep.name, req, transaction_len,
421 req->last_transaction ? ", done" : "");
422
423 memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
424 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
425 req->req.actual += transaction_len;
426 }
427
submit_request(struct usba_ep * ep,struct usba_request * req)428 static void submit_request(struct usba_ep *ep, struct usba_request *req)
429 {
430 DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
431 ep->ep.name, req, req->req.length);
432
433 req->req.actual = 0;
434 req->submitted = 1;
435
436 if (req->using_dma) {
437 if (req->req.length == 0) {
438 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
439 return;
440 }
441
442 if (req->req.zero)
443 usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
444 else
445 usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
446
447 usba_dma_writel(ep, ADDRESS, req->req.dma);
448 usba_dma_writel(ep, CONTROL, req->ctrl);
449 } else {
450 next_fifo_transaction(ep, req);
451 if (req->last_transaction) {
452 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
453 if (ep_is_control(ep))
454 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
455 } else {
456 if (ep_is_control(ep))
457 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
458 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
459 }
460 }
461 }
462
submit_next_request(struct usba_ep * ep)463 static void submit_next_request(struct usba_ep *ep)
464 {
465 struct usba_request *req;
466
467 if (list_empty(&ep->queue)) {
468 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
469 return;
470 }
471
472 req = list_entry(ep->queue.next, struct usba_request, queue);
473 if (!req->submitted)
474 submit_request(ep, req);
475 }
476
send_status(struct usba_udc * udc,struct usba_ep * ep)477 static void send_status(struct usba_udc *udc, struct usba_ep *ep)
478 {
479 ep->state = STATUS_STAGE_IN;
480 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
481 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
482 }
483
receive_data(struct usba_ep * ep)484 static void receive_data(struct usba_ep *ep)
485 {
486 struct usba_udc *udc = ep->udc;
487 struct usba_request *req;
488 unsigned long status;
489 unsigned int bytecount, nr_busy;
490 int is_complete = 0;
491
492 status = usba_ep_readl(ep, STA);
493 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
494
495 DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
496
497 while (nr_busy > 0) {
498 if (list_empty(&ep->queue)) {
499 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
500 break;
501 }
502 req = list_entry(ep->queue.next,
503 struct usba_request, queue);
504
505 bytecount = USBA_BFEXT(BYTE_COUNT, status);
506
507 if (status & (1 << 31))
508 is_complete = 1;
509 if (req->req.actual + bytecount >= req->req.length) {
510 is_complete = 1;
511 bytecount = req->req.length - req->req.actual;
512 }
513
514 memcpy_fromio(req->req.buf + req->req.actual,
515 ep->fifo, bytecount);
516 req->req.actual += bytecount;
517
518 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
519
520 if (is_complete) {
521 DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
522 req->req.status = 0;
523 list_del_init(&req->queue);
524 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
525 spin_unlock(&udc->lock);
526 usb_gadget_giveback_request(&ep->ep, &req->req);
527 spin_lock(&udc->lock);
528 }
529
530 status = usba_ep_readl(ep, STA);
531 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
532
533 if (is_complete && ep_is_control(ep)) {
534 send_status(udc, ep);
535 break;
536 }
537 }
538 }
539
540 static void
request_complete(struct usba_ep * ep,struct usba_request * req,int status)541 request_complete(struct usba_ep *ep, struct usba_request *req, int status)
542 {
543 struct usba_udc *udc = ep->udc;
544
545 WARN_ON(!list_empty(&req->queue));
546
547 if (req->req.status == -EINPROGRESS)
548 req->req.status = status;
549
550 if (req->using_dma)
551 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
552
553 DBG(DBG_GADGET | DBG_REQ,
554 "%s: req %p complete: status %d, actual %u\n",
555 ep->ep.name, req, req->req.status, req->req.actual);
556
557 spin_unlock(&udc->lock);
558 usb_gadget_giveback_request(&ep->ep, &req->req);
559 spin_lock(&udc->lock);
560 }
561
562 static void
request_complete_list(struct usba_ep * ep,struct list_head * list,int status)563 request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
564 {
565 struct usba_request *req, *tmp_req;
566
567 list_for_each_entry_safe(req, tmp_req, list, queue) {
568 list_del_init(&req->queue);
569 request_complete(ep, req, status);
570 }
571 }
572
573 static int
usba_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)574 usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
575 {
576 struct usba_ep *ep = to_usba_ep(_ep);
577 struct usba_udc *udc = ep->udc;
578 unsigned long flags, maxpacket;
579 unsigned int nr_trans;
580
581 DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
582
583 maxpacket = usb_endpoint_maxp(desc);
584
585 if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
586 || ep->index == 0
587 || desc->bDescriptorType != USB_DT_ENDPOINT
588 || maxpacket == 0
589 || maxpacket > ep->fifo_size) {
590 DBG(DBG_ERR, "ep_enable: Invalid argument");
591 return -EINVAL;
592 }
593
594 ep->is_isoc = 0;
595 ep->is_in = 0;
596
597 DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n",
598 ep->ep.name, ep->ept_cfg, maxpacket);
599
600 if (usb_endpoint_dir_in(desc)) {
601 ep->is_in = 1;
602 ep->ept_cfg |= USBA_EPT_DIR_IN;
603 }
604
605 switch (usb_endpoint_type(desc)) {
606 case USB_ENDPOINT_XFER_CONTROL:
607 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
608 break;
609 case USB_ENDPOINT_XFER_ISOC:
610 if (!ep->can_isoc) {
611 DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
612 ep->ep.name);
613 return -EINVAL;
614 }
615
616 /*
617 * Bits 11:12 specify number of _additional_
618 * transactions per microframe.
619 */
620 nr_trans = usb_endpoint_maxp_mult(desc);
621 if (nr_trans > 3)
622 return -EINVAL;
623
624 ep->is_isoc = 1;
625 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
626 ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
627
628 break;
629 case USB_ENDPOINT_XFER_BULK:
630 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
631 break;
632 case USB_ENDPOINT_XFER_INT:
633 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
634 break;
635 }
636
637 spin_lock_irqsave(&ep->udc->lock, flags);
638
639 ep->ep.desc = desc;
640 ep->ep.maxpacket = maxpacket;
641
642 usba_ep_writel(ep, CFG, ep->ept_cfg);
643 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
644
645 if (ep->can_dma) {
646 u32 ctrl;
647
648 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index) |
649 USBA_BF(DMA_INT, 1 << ep->index));
650 ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
651 usba_ep_writel(ep, CTL_ENB, ctrl);
652 } else {
653 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index));
654 }
655
656 spin_unlock_irqrestore(&udc->lock, flags);
657
658 DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
659 (unsigned long)usba_ep_readl(ep, CFG));
660 DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
661 (unsigned long)usba_int_enb_get(udc));
662
663 return 0;
664 }
665
usba_ep_disable(struct usb_ep * _ep)666 static int usba_ep_disable(struct usb_ep *_ep)
667 {
668 struct usba_ep *ep = to_usba_ep(_ep);
669 struct usba_udc *udc = ep->udc;
670 LIST_HEAD(req_list);
671 unsigned long flags;
672
673 DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
674
675 spin_lock_irqsave(&udc->lock, flags);
676
677 if (!ep->ep.desc) {
678 spin_unlock_irqrestore(&udc->lock, flags);
679 DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
680 return -EINVAL;
681 }
682 ep->ep.desc = NULL;
683
684 list_splice_init(&ep->queue, &req_list);
685 if (ep->can_dma) {
686 usba_dma_writel(ep, CONTROL, 0);
687 usba_dma_writel(ep, ADDRESS, 0);
688 usba_dma_readl(ep, STATUS);
689 }
690 usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
691 usba_int_enb_clear(udc, USBA_BF(EPT_INT, 1 << ep->index));
692
693 request_complete_list(ep, &req_list, -ESHUTDOWN);
694
695 spin_unlock_irqrestore(&udc->lock, flags);
696
697 return 0;
698 }
699
700 static struct usb_request *
usba_ep_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)701 usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
702 {
703 struct usba_request *req;
704
705 DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
706
707 req = kzalloc(sizeof(*req), gfp_flags);
708 if (!req)
709 return NULL;
710
711 INIT_LIST_HEAD(&req->queue);
712
713 return &req->req;
714 }
715
716 static void
usba_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)717 usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
718 {
719 struct usba_request *req = to_usba_req(_req);
720
721 DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
722
723 kfree(req);
724 }
725
queue_dma(struct usba_udc * udc,struct usba_ep * ep,struct usba_request * req,gfp_t gfp_flags)726 static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
727 struct usba_request *req, gfp_t gfp_flags)
728 {
729 unsigned long flags;
730 int ret;
731
732 DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n",
733 ep->ep.name, req->req.length, &req->req.dma,
734 req->req.zero ? 'Z' : 'z',
735 req->req.short_not_ok ? 'S' : 's',
736 req->req.no_interrupt ? 'I' : 'i');
737
738 if (req->req.length > 0x10000) {
739 /* Lengths from 0 to 65536 (inclusive) are supported */
740 DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
741 return -EINVAL;
742 }
743
744 ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
745 if (ret)
746 return ret;
747
748 req->using_dma = 1;
749 req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
750 | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
751 | USBA_DMA_END_BUF_EN;
752
753 if (!ep->is_in)
754 req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
755
756 /*
757 * Add this request to the queue and submit for DMA if
758 * possible. Check if we're still alive first -- we may have
759 * received a reset since last time we checked.
760 */
761 ret = -ESHUTDOWN;
762 spin_lock_irqsave(&udc->lock, flags);
763 if (ep->ep.desc) {
764 if (list_empty(&ep->queue))
765 submit_request(ep, req);
766
767 list_add_tail(&req->queue, &ep->queue);
768 ret = 0;
769 }
770 spin_unlock_irqrestore(&udc->lock, flags);
771
772 return ret;
773 }
774
775 static int
usba_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)776 usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
777 {
778 struct usba_request *req = to_usba_req(_req);
779 struct usba_ep *ep = to_usba_ep(_ep);
780 struct usba_udc *udc = ep->udc;
781 unsigned long flags;
782 int ret;
783
784 DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
785 ep->ep.name, req, _req->length);
786
787 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
788 !ep->ep.desc)
789 return -ESHUTDOWN;
790
791 req->submitted = 0;
792 req->using_dma = 0;
793 req->last_transaction = 0;
794
795 _req->status = -EINPROGRESS;
796 _req->actual = 0;
797
798 if (ep->can_dma)
799 return queue_dma(udc, ep, req, gfp_flags);
800
801 /* May have received a reset since last time we checked */
802 ret = -ESHUTDOWN;
803 spin_lock_irqsave(&udc->lock, flags);
804 if (ep->ep.desc) {
805 list_add_tail(&req->queue, &ep->queue);
806
807 if ((!ep_is_control(ep) && ep->is_in) ||
808 (ep_is_control(ep)
809 && (ep->state == DATA_STAGE_IN
810 || ep->state == STATUS_STAGE_IN)))
811 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
812 else
813 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
814 ret = 0;
815 }
816 spin_unlock_irqrestore(&udc->lock, flags);
817
818 return ret;
819 }
820
821 static void
usba_update_req(struct usba_ep * ep,struct usba_request * req,u32 status)822 usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
823 {
824 req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
825 }
826
stop_dma(struct usba_ep * ep,u32 * pstatus)827 static int stop_dma(struct usba_ep *ep, u32 *pstatus)
828 {
829 unsigned int timeout;
830 u32 status;
831
832 /*
833 * Stop the DMA controller. When writing both CH_EN
834 * and LINK to 0, the other bits are not affected.
835 */
836 usba_dma_writel(ep, CONTROL, 0);
837
838 /* Wait for the FIFO to empty */
839 for (timeout = 40; timeout; --timeout) {
840 status = usba_dma_readl(ep, STATUS);
841 if (!(status & USBA_DMA_CH_EN))
842 break;
843 udelay(1);
844 }
845
846 if (pstatus)
847 *pstatus = status;
848
849 if (timeout == 0) {
850 dev_err(&ep->udc->pdev->dev,
851 "%s: timed out waiting for DMA FIFO to empty\n",
852 ep->ep.name);
853 return -ETIMEDOUT;
854 }
855
856 return 0;
857 }
858
usba_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)859 static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
860 {
861 struct usba_ep *ep = to_usba_ep(_ep);
862 struct usba_udc *udc = ep->udc;
863 struct usba_request *req = NULL;
864 struct usba_request *iter;
865 unsigned long flags;
866 u32 status;
867
868 DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
869 ep->ep.name, _req);
870
871 spin_lock_irqsave(&udc->lock, flags);
872
873 list_for_each_entry(iter, &ep->queue, queue) {
874 if (&iter->req != _req)
875 continue;
876 req = iter;
877 break;
878 }
879
880 if (!req) {
881 spin_unlock_irqrestore(&udc->lock, flags);
882 return -EINVAL;
883 }
884
885 if (req->using_dma) {
886 /*
887 * If this request is currently being transferred,
888 * stop the DMA controller and reset the FIFO.
889 */
890 if (ep->queue.next == &req->queue) {
891 status = usba_dma_readl(ep, STATUS);
892 if (status & USBA_DMA_CH_EN)
893 stop_dma(ep, &status);
894
895 #ifdef CONFIG_USB_GADGET_DEBUG_FS
896 ep->last_dma_status = status;
897 #endif
898
899 usba_writel(udc, EPT_RST, 1 << ep->index);
900
901 usba_update_req(ep, req, status);
902 }
903 }
904
905 /*
906 * Errors should stop the queue from advancing until the
907 * completion function returns.
908 */
909 list_del_init(&req->queue);
910
911 request_complete(ep, req, -ECONNRESET);
912
913 /* Process the next request if any */
914 submit_next_request(ep);
915 spin_unlock_irqrestore(&udc->lock, flags);
916
917 return 0;
918 }
919
usba_ep_set_halt(struct usb_ep * _ep,int value)920 static int usba_ep_set_halt(struct usb_ep *_ep, int value)
921 {
922 struct usba_ep *ep = to_usba_ep(_ep);
923 struct usba_udc *udc = ep->udc;
924 unsigned long flags;
925 int ret = 0;
926
927 DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
928 value ? "set" : "clear");
929
930 if (!ep->ep.desc) {
931 DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
932 ep->ep.name);
933 return -ENODEV;
934 }
935 if (ep->is_isoc) {
936 DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
937 ep->ep.name);
938 return -ENOTTY;
939 }
940
941 spin_lock_irqsave(&udc->lock, flags);
942
943 /*
944 * We can't halt IN endpoints while there are still data to be
945 * transferred
946 */
947 if (!list_empty(&ep->queue)
948 || ((value && ep->is_in && (usba_ep_readl(ep, STA)
949 & USBA_BF(BUSY_BANKS, -1L))))) {
950 ret = -EAGAIN;
951 } else {
952 if (value)
953 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
954 else
955 usba_ep_writel(ep, CLR_STA,
956 USBA_FORCE_STALL | USBA_TOGGLE_CLR);
957 usba_ep_readl(ep, STA);
958 }
959
960 spin_unlock_irqrestore(&udc->lock, flags);
961
962 return ret;
963 }
964
usba_ep_fifo_status(struct usb_ep * _ep)965 static int usba_ep_fifo_status(struct usb_ep *_ep)
966 {
967 struct usba_ep *ep = to_usba_ep(_ep);
968
969 return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
970 }
971
usba_ep_fifo_flush(struct usb_ep * _ep)972 static void usba_ep_fifo_flush(struct usb_ep *_ep)
973 {
974 struct usba_ep *ep = to_usba_ep(_ep);
975 struct usba_udc *udc = ep->udc;
976
977 usba_writel(udc, EPT_RST, 1 << ep->index);
978 }
979
980 static const struct usb_ep_ops usba_ep_ops = {
981 .enable = usba_ep_enable,
982 .disable = usba_ep_disable,
983 .alloc_request = usba_ep_alloc_request,
984 .free_request = usba_ep_free_request,
985 .queue = usba_ep_queue,
986 .dequeue = usba_ep_dequeue,
987 .set_halt = usba_ep_set_halt,
988 .fifo_status = usba_ep_fifo_status,
989 .fifo_flush = usba_ep_fifo_flush,
990 };
991
usba_udc_get_frame(struct usb_gadget * gadget)992 static int usba_udc_get_frame(struct usb_gadget *gadget)
993 {
994 struct usba_udc *udc = to_usba_udc(gadget);
995
996 return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
997 }
998
usba_udc_wakeup(struct usb_gadget * gadget)999 static int usba_udc_wakeup(struct usb_gadget *gadget)
1000 {
1001 struct usba_udc *udc = to_usba_udc(gadget);
1002 unsigned long flags;
1003 u32 ctrl;
1004 int ret = -EINVAL;
1005
1006 spin_lock_irqsave(&udc->lock, flags);
1007 if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
1008 ctrl = usba_readl(udc, CTRL);
1009 usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
1010 ret = 0;
1011 }
1012 spin_unlock_irqrestore(&udc->lock, flags);
1013
1014 return ret;
1015 }
1016
1017 static int
usba_udc_set_selfpowered(struct usb_gadget * gadget,int is_selfpowered)1018 usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1019 {
1020 struct usba_udc *udc = to_usba_udc(gadget);
1021 unsigned long flags;
1022
1023 gadget->is_selfpowered = (is_selfpowered != 0);
1024 spin_lock_irqsave(&udc->lock, flags);
1025 if (is_selfpowered)
1026 udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
1027 else
1028 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
1029 spin_unlock_irqrestore(&udc->lock, flags);
1030
1031 return 0;
1032 }
1033
1034 static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on);
1035 static int atmel_usba_start(struct usb_gadget *gadget,
1036 struct usb_gadget_driver *driver);
1037 static int atmel_usba_stop(struct usb_gadget *gadget);
1038
atmel_usba_match_ep(struct usb_gadget * gadget,struct usb_endpoint_descriptor * desc,struct usb_ss_ep_comp_descriptor * ep_comp)1039 static struct usb_ep *atmel_usba_match_ep(struct usb_gadget *gadget,
1040 struct usb_endpoint_descriptor *desc,
1041 struct usb_ss_ep_comp_descriptor *ep_comp)
1042 {
1043 struct usb_ep *_ep;
1044 struct usba_ep *ep;
1045
1046 /* Look at endpoints until an unclaimed one looks usable */
1047 list_for_each_entry(_ep, &gadget->ep_list, ep_list) {
1048 if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp))
1049 goto found_ep;
1050 }
1051 /* Fail */
1052 return NULL;
1053
1054 found_ep:
1055
1056 if (fifo_mode == 0) {
1057 /* Optimize hw fifo size based on ep type and other info */
1058 ep = to_usba_ep(_ep);
1059
1060 switch (usb_endpoint_type(desc)) {
1061 case USB_ENDPOINT_XFER_CONTROL:
1062 ep->nr_banks = 1;
1063 break;
1064
1065 case USB_ENDPOINT_XFER_ISOC:
1066 ep->fifo_size = 1024;
1067 if (ep->udc->ep_prealloc)
1068 ep->nr_banks = 2;
1069 break;
1070
1071 case USB_ENDPOINT_XFER_BULK:
1072 ep->fifo_size = 512;
1073 if (ep->udc->ep_prealloc)
1074 ep->nr_banks = 1;
1075 break;
1076
1077 case USB_ENDPOINT_XFER_INT:
1078 if (desc->wMaxPacketSize == 0)
1079 ep->fifo_size =
1080 roundup_pow_of_two(_ep->maxpacket_limit);
1081 else
1082 ep->fifo_size =
1083 roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize));
1084 if (ep->udc->ep_prealloc)
1085 ep->nr_banks = 1;
1086 break;
1087 }
1088
1089 /* It might be a little bit late to set this */
1090 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
1091
1092 /* Generate ept_cfg basd on FIFO size and number of banks */
1093 if (ep->fifo_size <= 8)
1094 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
1095 else
1096 /* LSB is bit 1, not 0 */
1097 ep->ept_cfg =
1098 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
1099
1100 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
1101 }
1102
1103 return _ep;
1104 }
1105
1106 static const struct usb_gadget_ops usba_udc_ops = {
1107 .get_frame = usba_udc_get_frame,
1108 .wakeup = usba_udc_wakeup,
1109 .set_selfpowered = usba_udc_set_selfpowered,
1110 .pullup = atmel_usba_pullup,
1111 .udc_start = atmel_usba_start,
1112 .udc_stop = atmel_usba_stop,
1113 .match_ep = atmel_usba_match_ep,
1114 };
1115
1116 static struct usb_endpoint_descriptor usba_ep0_desc = {
1117 .bLength = USB_DT_ENDPOINT_SIZE,
1118 .bDescriptorType = USB_DT_ENDPOINT,
1119 .bEndpointAddress = 0,
1120 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1121 .wMaxPacketSize = cpu_to_le16(64),
1122 /* FIXME: I have no idea what to put here */
1123 .bInterval = 1,
1124 };
1125
1126 static const struct usb_gadget usba_gadget_template = {
1127 .ops = &usba_udc_ops,
1128 .max_speed = USB_SPEED_HIGH,
1129 .name = "atmel_usba_udc",
1130 };
1131
1132 /*
1133 * Called with interrupts disabled and udc->lock held.
1134 */
reset_all_endpoints(struct usba_udc * udc)1135 static void reset_all_endpoints(struct usba_udc *udc)
1136 {
1137 struct usba_ep *ep;
1138 struct usba_request *req, *tmp_req;
1139
1140 usba_writel(udc, EPT_RST, ~0UL);
1141
1142 ep = to_usba_ep(udc->gadget.ep0);
1143 list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
1144 list_del_init(&req->queue);
1145 request_complete(ep, req, -ECONNRESET);
1146 }
1147 }
1148
get_ep_by_addr(struct usba_udc * udc,u16 wIndex)1149 static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
1150 {
1151 struct usba_ep *ep;
1152
1153 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
1154 return to_usba_ep(udc->gadget.ep0);
1155
1156 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
1157 u8 bEndpointAddress;
1158
1159 if (!ep->ep.desc)
1160 continue;
1161 bEndpointAddress = ep->ep.desc->bEndpointAddress;
1162 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
1163 continue;
1164 if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
1165 == (wIndex & USB_ENDPOINT_NUMBER_MASK))
1166 return ep;
1167 }
1168
1169 return NULL;
1170 }
1171
1172 /* Called with interrupts disabled and udc->lock held */
set_protocol_stall(struct usba_udc * udc,struct usba_ep * ep)1173 static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
1174 {
1175 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
1176 ep->state = WAIT_FOR_SETUP;
1177 }
1178
is_stalled(struct usba_udc * udc,struct usba_ep * ep)1179 static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
1180 {
1181 if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
1182 return 1;
1183 return 0;
1184 }
1185
set_address(struct usba_udc * udc,unsigned int addr)1186 static inline void set_address(struct usba_udc *udc, unsigned int addr)
1187 {
1188 u32 regval;
1189
1190 DBG(DBG_BUS, "setting address %u...\n", addr);
1191 regval = usba_readl(udc, CTRL);
1192 regval = USBA_BFINS(DEV_ADDR, addr, regval);
1193 usba_writel(udc, CTRL, regval);
1194 }
1195
do_test_mode(struct usba_udc * udc)1196 static int do_test_mode(struct usba_udc *udc)
1197 {
1198 static const char test_packet_buffer[] = {
1199 /* JKJKJKJK * 9 */
1200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1201 /* JJKKJJKK * 8 */
1202 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1203 /* JJKKJJKK * 8 */
1204 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1205 /* JJJJJJJKKKKKKK * 8 */
1206 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1207 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1208 /* JJJJJJJK * 8 */
1209 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
1210 /* {JKKKKKKK * 10}, JK */
1211 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
1212 };
1213 struct usba_ep *ep;
1214 struct device *dev = &udc->pdev->dev;
1215 int test_mode;
1216
1217 test_mode = udc->test_mode;
1218
1219 /* Start from a clean slate */
1220 reset_all_endpoints(udc);
1221
1222 switch (test_mode) {
1223 case 0x0100:
1224 /* Test_J */
1225 usba_writel(udc, TST, USBA_TST_J_MODE);
1226 dev_info(dev, "Entering Test_J mode...\n");
1227 break;
1228 case 0x0200:
1229 /* Test_K */
1230 usba_writel(udc, TST, USBA_TST_K_MODE);
1231 dev_info(dev, "Entering Test_K mode...\n");
1232 break;
1233 case 0x0300:
1234 /*
1235 * Test_SE0_NAK: Force high-speed mode and set up ep0
1236 * for Bulk IN transfers
1237 */
1238 ep = &udc->usba_ep[0];
1239 usba_writel(udc, TST,
1240 USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
1241 usba_ep_writel(ep, CFG,
1242 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1243 | USBA_EPT_DIR_IN
1244 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1245 | USBA_BF(BK_NUMBER, 1));
1246 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1247 set_protocol_stall(udc, ep);
1248 dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
1249 } else {
1250 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1251 dev_info(dev, "Entering Test_SE0_NAK mode...\n");
1252 }
1253 break;
1254 case 0x0400:
1255 /* Test_Packet */
1256 ep = &udc->usba_ep[0];
1257 usba_ep_writel(ep, CFG,
1258 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1259 | USBA_EPT_DIR_IN
1260 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1261 | USBA_BF(BK_NUMBER, 1));
1262 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1263 set_protocol_stall(udc, ep);
1264 dev_err(dev, "Test_Packet: ep0 not mapped\n");
1265 } else {
1266 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1267 usba_writel(udc, TST, USBA_TST_PKT_MODE);
1268 memcpy_toio(ep->fifo, test_packet_buffer,
1269 sizeof(test_packet_buffer));
1270 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1271 dev_info(dev, "Entering Test_Packet mode...\n");
1272 }
1273 break;
1274 default:
1275 dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
1276 return -EINVAL;
1277 }
1278
1279 return 0;
1280 }
1281
1282 /* Avoid overly long expressions */
feature_is_dev_remote_wakeup(struct usb_ctrlrequest * crq)1283 static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
1284 {
1285 if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
1286 return true;
1287 return false;
1288 }
1289
feature_is_dev_test_mode(struct usb_ctrlrequest * crq)1290 static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
1291 {
1292 if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
1293 return true;
1294 return false;
1295 }
1296
feature_is_ep_halt(struct usb_ctrlrequest * crq)1297 static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
1298 {
1299 if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
1300 return true;
1301 return false;
1302 }
1303
handle_ep0_setup(struct usba_udc * udc,struct usba_ep * ep,struct usb_ctrlrequest * crq)1304 static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
1305 struct usb_ctrlrequest *crq)
1306 {
1307 int retval = 0;
1308
1309 switch (crq->bRequest) {
1310 case USB_REQ_GET_STATUS: {
1311 u16 status;
1312
1313 if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
1314 status = cpu_to_le16(udc->devstatus);
1315 } else if (crq->bRequestType
1316 == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
1317 status = cpu_to_le16(0);
1318 } else if (crq->bRequestType
1319 == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
1320 struct usba_ep *target;
1321
1322 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1323 if (!target)
1324 goto stall;
1325
1326 status = 0;
1327 if (is_stalled(udc, target))
1328 status |= cpu_to_le16(1);
1329 } else
1330 goto delegate;
1331
1332 /* Write directly to the FIFO. No queueing is done. */
1333 if (crq->wLength != cpu_to_le16(sizeof(status)))
1334 goto stall;
1335 ep->state = DATA_STAGE_IN;
1336 writew_relaxed(status, ep->fifo);
1337 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1338 break;
1339 }
1340
1341 case USB_REQ_CLEAR_FEATURE: {
1342 if (crq->bRequestType == USB_RECIP_DEVICE) {
1343 if (feature_is_dev_remote_wakeup(crq))
1344 udc->devstatus
1345 &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
1346 else
1347 /* Can't CLEAR_FEATURE TEST_MODE */
1348 goto stall;
1349 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1350 struct usba_ep *target;
1351
1352 if (crq->wLength != cpu_to_le16(0)
1353 || !feature_is_ep_halt(crq))
1354 goto stall;
1355 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1356 if (!target)
1357 goto stall;
1358
1359 usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
1360 if (target->index != 0)
1361 usba_ep_writel(target, CLR_STA,
1362 USBA_TOGGLE_CLR);
1363 } else {
1364 goto delegate;
1365 }
1366
1367 send_status(udc, ep);
1368 break;
1369 }
1370
1371 case USB_REQ_SET_FEATURE: {
1372 if (crq->bRequestType == USB_RECIP_DEVICE) {
1373 if (feature_is_dev_test_mode(crq)) {
1374 send_status(udc, ep);
1375 ep->state = STATUS_STAGE_TEST;
1376 udc->test_mode = le16_to_cpu(crq->wIndex);
1377 return 0;
1378 } else if (feature_is_dev_remote_wakeup(crq)) {
1379 udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
1380 } else {
1381 goto stall;
1382 }
1383 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1384 struct usba_ep *target;
1385
1386 if (crq->wLength != cpu_to_le16(0)
1387 || !feature_is_ep_halt(crq))
1388 goto stall;
1389
1390 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1391 if (!target)
1392 goto stall;
1393
1394 usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
1395 } else
1396 goto delegate;
1397
1398 send_status(udc, ep);
1399 break;
1400 }
1401
1402 case USB_REQ_SET_ADDRESS:
1403 if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
1404 goto delegate;
1405
1406 set_address(udc, le16_to_cpu(crq->wValue));
1407 send_status(udc, ep);
1408 ep->state = STATUS_STAGE_ADDR;
1409 break;
1410
1411 default:
1412 delegate:
1413 spin_unlock(&udc->lock);
1414 retval = udc->driver->setup(&udc->gadget, crq);
1415 spin_lock(&udc->lock);
1416 }
1417
1418 return retval;
1419
1420 stall:
1421 pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
1422 "halting endpoint...\n",
1423 ep->ep.name, crq->bRequestType, crq->bRequest,
1424 le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
1425 le16_to_cpu(crq->wLength));
1426 set_protocol_stall(udc, ep);
1427 return -1;
1428 }
1429
usba_control_irq(struct usba_udc * udc,struct usba_ep * ep)1430 static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
1431 {
1432 struct usba_request *req;
1433 u32 epstatus;
1434 u32 epctrl;
1435
1436 restart:
1437 epstatus = usba_ep_readl(ep, STA);
1438 epctrl = usba_ep_readl(ep, CTL);
1439
1440 DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
1441 ep->ep.name, ep->state, epstatus, epctrl);
1442
1443 req = NULL;
1444 if (!list_empty(&ep->queue))
1445 req = list_entry(ep->queue.next,
1446 struct usba_request, queue);
1447
1448 if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1449 if (req->submitted)
1450 next_fifo_transaction(ep, req);
1451 else
1452 submit_request(ep, req);
1453
1454 if (req->last_transaction) {
1455 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1456 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
1457 }
1458 goto restart;
1459 }
1460 if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
1461 usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
1462
1463 switch (ep->state) {
1464 case DATA_STAGE_IN:
1465 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
1466 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1467 ep->state = STATUS_STAGE_OUT;
1468 break;
1469 case STATUS_STAGE_ADDR:
1470 /* Activate our new address */
1471 usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
1472 | USBA_FADDR_EN));
1473 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1474 ep->state = WAIT_FOR_SETUP;
1475 break;
1476 case STATUS_STAGE_IN:
1477 if (req) {
1478 list_del_init(&req->queue);
1479 request_complete(ep, req, 0);
1480 submit_next_request(ep);
1481 }
1482 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1483 ep->state = WAIT_FOR_SETUP;
1484 break;
1485 case STATUS_STAGE_TEST:
1486 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1487 ep->state = WAIT_FOR_SETUP;
1488 if (do_test_mode(udc))
1489 set_protocol_stall(udc, ep);
1490 break;
1491 default:
1492 pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
1493 "halting endpoint...\n",
1494 ep->ep.name, ep->state);
1495 set_protocol_stall(udc, ep);
1496 break;
1497 }
1498
1499 goto restart;
1500 }
1501 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1502 switch (ep->state) {
1503 case STATUS_STAGE_OUT:
1504 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1505 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1506
1507 if (req) {
1508 list_del_init(&req->queue);
1509 request_complete(ep, req, 0);
1510 }
1511 ep->state = WAIT_FOR_SETUP;
1512 break;
1513
1514 case DATA_STAGE_OUT:
1515 receive_data(ep);
1516 break;
1517
1518 default:
1519 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1520 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1521 pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
1522 "halting endpoint...\n",
1523 ep->ep.name, ep->state);
1524 set_protocol_stall(udc, ep);
1525 break;
1526 }
1527
1528 goto restart;
1529 }
1530 if (epstatus & USBA_RX_SETUP) {
1531 union {
1532 struct usb_ctrlrequest crq;
1533 unsigned long data[2];
1534 } crq;
1535 unsigned int pkt_len;
1536 int ret;
1537
1538 if (ep->state != WAIT_FOR_SETUP) {
1539 /*
1540 * Didn't expect a SETUP packet at this
1541 * point. Clean up any pending requests (which
1542 * may be successful).
1543 */
1544 int status = -EPROTO;
1545
1546 /*
1547 * RXRDY and TXCOMP are dropped when SETUP
1548 * packets arrive. Just pretend we received
1549 * the status packet.
1550 */
1551 if (ep->state == STATUS_STAGE_OUT
1552 || ep->state == STATUS_STAGE_IN) {
1553 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1554 status = 0;
1555 }
1556
1557 if (req) {
1558 list_del_init(&req->queue);
1559 request_complete(ep, req, status);
1560 }
1561 }
1562
1563 pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
1564 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
1565 if (pkt_len != sizeof(crq)) {
1566 pr_warn("udc: Invalid packet length %u (expected %zu)\n",
1567 pkt_len, sizeof(crq));
1568 set_protocol_stall(udc, ep);
1569 return;
1570 }
1571
1572 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
1573 memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
1574
1575 /* Free up one bank in the FIFO so that we can
1576 * generate or receive a reply right away. */
1577 usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
1578
1579 /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
1580 ep->state, crq.crq.bRequestType,
1581 crq.crq.bRequest); */
1582
1583 if (crq.crq.bRequestType & USB_DIR_IN) {
1584 /*
1585 * The USB 2.0 spec states that "if wLength is
1586 * zero, there is no data transfer phase."
1587 * However, testusb #14 seems to actually
1588 * expect a data phase even if wLength = 0...
1589 */
1590 ep->state = DATA_STAGE_IN;
1591 } else {
1592 if (crq.crq.wLength != cpu_to_le16(0))
1593 ep->state = DATA_STAGE_OUT;
1594 else
1595 ep->state = STATUS_STAGE_IN;
1596 }
1597
1598 ret = -1;
1599 if (ep->index == 0)
1600 ret = handle_ep0_setup(udc, ep, &crq.crq);
1601 else {
1602 spin_unlock(&udc->lock);
1603 ret = udc->driver->setup(&udc->gadget, &crq.crq);
1604 spin_lock(&udc->lock);
1605 }
1606
1607 DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
1608 crq.crq.bRequestType, crq.crq.bRequest,
1609 le16_to_cpu(crq.crq.wLength), ep->state, ret);
1610
1611 if (ret < 0) {
1612 /* Let the host know that we failed */
1613 set_protocol_stall(udc, ep);
1614 }
1615 }
1616 }
1617
usba_ep_irq(struct usba_udc * udc,struct usba_ep * ep)1618 static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
1619 {
1620 struct usba_request *req;
1621 u32 epstatus;
1622 u32 epctrl;
1623
1624 epstatus = usba_ep_readl(ep, STA);
1625 epctrl = usba_ep_readl(ep, CTL);
1626
1627 DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
1628
1629 while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1630 DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
1631
1632 if (list_empty(&ep->queue)) {
1633 dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
1634 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1635 return;
1636 }
1637
1638 req = list_entry(ep->queue.next, struct usba_request, queue);
1639
1640 if (req->using_dma) {
1641 /* Send a zero-length packet */
1642 usba_ep_writel(ep, SET_STA,
1643 USBA_TX_PK_RDY);
1644 usba_ep_writel(ep, CTL_DIS,
1645 USBA_TX_PK_RDY);
1646 list_del_init(&req->queue);
1647 submit_next_request(ep);
1648 request_complete(ep, req, 0);
1649 } else {
1650 if (req->submitted)
1651 next_fifo_transaction(ep, req);
1652 else
1653 submit_request(ep, req);
1654
1655 if (req->last_transaction) {
1656 list_del_init(&req->queue);
1657 submit_next_request(ep);
1658 request_complete(ep, req, 0);
1659 }
1660 }
1661
1662 epstatus = usba_ep_readl(ep, STA);
1663 epctrl = usba_ep_readl(ep, CTL);
1664 }
1665 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1666 DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
1667 receive_data(ep);
1668 }
1669 }
1670
usba_dma_irq(struct usba_udc * udc,struct usba_ep * ep)1671 static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
1672 {
1673 struct usba_request *req;
1674 u32 status, control, pending;
1675
1676 status = usba_dma_readl(ep, STATUS);
1677 control = usba_dma_readl(ep, CONTROL);
1678 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1679 ep->last_dma_status = status;
1680 #endif
1681 pending = status & control;
1682 DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
1683
1684 if (status & USBA_DMA_CH_EN) {
1685 dev_err(&udc->pdev->dev,
1686 "DMA_CH_EN is set after transfer is finished!\n");
1687 dev_err(&udc->pdev->dev,
1688 "status=%#08x, pending=%#08x, control=%#08x\n",
1689 status, pending, control);
1690
1691 /*
1692 * try to pretend nothing happened. We might have to
1693 * do something here...
1694 */
1695 }
1696
1697 if (list_empty(&ep->queue))
1698 /* Might happen if a reset comes along at the right moment */
1699 return;
1700
1701 if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
1702 req = list_entry(ep->queue.next, struct usba_request, queue);
1703 usba_update_req(ep, req, status);
1704
1705 list_del_init(&req->queue);
1706 submit_next_request(ep);
1707 request_complete(ep, req, 0);
1708 }
1709 }
1710
1711 static int start_clock(struct usba_udc *udc);
1712 static void stop_clock(struct usba_udc *udc);
1713
usba_udc_irq(int irq,void * devid)1714 static irqreturn_t usba_udc_irq(int irq, void *devid)
1715 {
1716 struct usba_udc *udc = devid;
1717 u32 status, int_enb;
1718 u32 dma_status;
1719 u32 ep_status;
1720
1721 spin_lock(&udc->lock);
1722
1723 int_enb = usba_int_enb_get(udc);
1724 status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED);
1725 DBG(DBG_INT, "irq, status=%#08x\n", status);
1726
1727 if (status & USBA_DET_SUSPEND) {
1728 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND|USBA_WAKE_UP);
1729 usba_int_enb_set(udc, USBA_WAKE_UP);
1730 usba_int_enb_clear(udc, USBA_DET_SUSPEND);
1731 udc->suspended = true;
1732 toggle_bias(udc, 0);
1733 udc->bias_pulse_needed = true;
1734 stop_clock(udc);
1735 DBG(DBG_BUS, "Suspend detected\n");
1736 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1737 && udc->driver && udc->driver->suspend) {
1738 spin_unlock(&udc->lock);
1739 udc->driver->suspend(&udc->gadget);
1740 spin_lock(&udc->lock);
1741 }
1742 }
1743
1744 if (status & USBA_WAKE_UP) {
1745 start_clock(udc);
1746 toggle_bias(udc, 1);
1747 usba_writel(udc, INT_CLR, USBA_WAKE_UP);
1748 DBG(DBG_BUS, "Wake Up CPU detected\n");
1749 }
1750
1751 if (status & USBA_END_OF_RESUME) {
1752 udc->suspended = false;
1753 usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
1754 usba_int_enb_clear(udc, USBA_WAKE_UP);
1755 usba_int_enb_set(udc, USBA_DET_SUSPEND);
1756 generate_bias_pulse(udc);
1757 DBG(DBG_BUS, "Resume detected\n");
1758 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1759 && udc->driver && udc->driver->resume) {
1760 spin_unlock(&udc->lock);
1761 udc->driver->resume(&udc->gadget);
1762 spin_lock(&udc->lock);
1763 }
1764 }
1765
1766 dma_status = USBA_BFEXT(DMA_INT, status);
1767 if (dma_status) {
1768 int i;
1769
1770 usba_int_enb_set(udc, USBA_DET_SUSPEND);
1771
1772 for (i = 1; i <= USBA_NR_DMAS; i++)
1773 if (dma_status & (1 << i))
1774 usba_dma_irq(udc, &udc->usba_ep[i]);
1775 }
1776
1777 ep_status = USBA_BFEXT(EPT_INT, status);
1778 if (ep_status) {
1779 int i;
1780
1781 usba_int_enb_set(udc, USBA_DET_SUSPEND);
1782
1783 for (i = 0; i < udc->num_ep; i++)
1784 if (ep_status & (1 << i)) {
1785 if (ep_is_control(&udc->usba_ep[i]))
1786 usba_control_irq(udc, &udc->usba_ep[i]);
1787 else
1788 usba_ep_irq(udc, &udc->usba_ep[i]);
1789 }
1790 }
1791
1792 if (status & USBA_END_OF_RESET) {
1793 struct usba_ep *ep0, *ep;
1794 int i;
1795
1796 usba_writel(udc, INT_CLR,
1797 USBA_END_OF_RESET|USBA_END_OF_RESUME
1798 |USBA_DET_SUSPEND|USBA_WAKE_UP);
1799 generate_bias_pulse(udc);
1800 reset_all_endpoints(udc);
1801
1802 if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) {
1803 udc->gadget.speed = USB_SPEED_UNKNOWN;
1804 spin_unlock(&udc->lock);
1805 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1806 spin_lock(&udc->lock);
1807 }
1808
1809 if (status & USBA_HIGH_SPEED)
1810 udc->gadget.speed = USB_SPEED_HIGH;
1811 else
1812 udc->gadget.speed = USB_SPEED_FULL;
1813 DBG(DBG_BUS, "%s bus reset detected\n",
1814 usb_speed_string(udc->gadget.speed));
1815
1816 ep0 = &udc->usba_ep[0];
1817 ep0->ep.desc = &usba_ep0_desc;
1818 ep0->state = WAIT_FOR_SETUP;
1819 usba_ep_writel(ep0, CFG,
1820 (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
1821 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
1822 | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
1823 usba_ep_writel(ep0, CTL_ENB,
1824 USBA_EPT_ENABLE | USBA_RX_SETUP);
1825
1826 /* If we get reset while suspended... */
1827 udc->suspended = false;
1828 usba_int_enb_clear(udc, USBA_WAKE_UP);
1829
1830 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1) |
1831 USBA_DET_SUSPEND | USBA_END_OF_RESUME);
1832
1833 /*
1834 * Unclear why we hit this irregularly, e.g. in usbtest,
1835 * but it's clearly harmless...
1836 */
1837 if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
1838 dev_err(&udc->pdev->dev,
1839 "ODD: EP0 configuration is invalid!\n");
1840
1841 /* Preallocate other endpoints */
1842 for (i = 1; i < udc->num_ep; i++) {
1843 ep = &udc->usba_ep[i];
1844 if (ep->ep.claimed) {
1845 usba_ep_writel(ep, CFG, ep->ept_cfg);
1846 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED))
1847 dev_err(&udc->pdev->dev,
1848 "ODD: EP%d configuration is invalid!\n", i);
1849 }
1850 }
1851 }
1852
1853 spin_unlock(&udc->lock);
1854
1855 return IRQ_HANDLED;
1856 }
1857
start_clock(struct usba_udc * udc)1858 static int start_clock(struct usba_udc *udc)
1859 {
1860 int ret;
1861
1862 if (udc->clocked)
1863 return 0;
1864
1865 pm_stay_awake(&udc->pdev->dev);
1866
1867 ret = clk_prepare_enable(udc->pclk);
1868 if (ret)
1869 return ret;
1870 ret = clk_prepare_enable(udc->hclk);
1871 if (ret) {
1872 clk_disable_unprepare(udc->pclk);
1873 return ret;
1874 }
1875
1876 udc->clocked = true;
1877 return 0;
1878 }
1879
stop_clock(struct usba_udc * udc)1880 static void stop_clock(struct usba_udc *udc)
1881 {
1882 if (!udc->clocked)
1883 return;
1884
1885 clk_disable_unprepare(udc->hclk);
1886 clk_disable_unprepare(udc->pclk);
1887
1888 udc->clocked = false;
1889
1890 pm_relax(&udc->pdev->dev);
1891 }
1892
usba_start(struct usba_udc * udc)1893 static int usba_start(struct usba_udc *udc)
1894 {
1895 unsigned long flags;
1896 int ret;
1897
1898 ret = start_clock(udc);
1899 if (ret)
1900 return ret;
1901
1902 if (udc->suspended)
1903 return 0;
1904
1905 spin_lock_irqsave(&udc->lock, flags);
1906 toggle_bias(udc, 1);
1907 usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1908 /* Clear all requested and pending interrupts... */
1909 usba_writel(udc, INT_ENB, 0);
1910 udc->int_enb_cache = 0;
1911 usba_writel(udc, INT_CLR,
1912 USBA_END_OF_RESET|USBA_END_OF_RESUME
1913 |USBA_DET_SUSPEND|USBA_WAKE_UP);
1914 /* ...and enable just 'reset' IRQ to get us started */
1915 usba_int_enb_set(udc, USBA_END_OF_RESET);
1916 spin_unlock_irqrestore(&udc->lock, flags);
1917
1918 return 0;
1919 }
1920
usba_stop(struct usba_udc * udc)1921 static void usba_stop(struct usba_udc *udc)
1922 {
1923 unsigned long flags;
1924
1925 if (udc->suspended)
1926 return;
1927
1928 spin_lock_irqsave(&udc->lock, flags);
1929 udc->gadget.speed = USB_SPEED_UNKNOWN;
1930 reset_all_endpoints(udc);
1931
1932 /* This will also disable the DP pullup */
1933 toggle_bias(udc, 0);
1934 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1935 spin_unlock_irqrestore(&udc->lock, flags);
1936
1937 stop_clock(udc);
1938 }
1939
usba_vbus_irq_thread(int irq,void * devid)1940 static irqreturn_t usba_vbus_irq_thread(int irq, void *devid)
1941 {
1942 struct usba_udc *udc = devid;
1943 int vbus;
1944
1945 /* debounce */
1946 udelay(10);
1947
1948 mutex_lock(&udc->vbus_mutex);
1949
1950 vbus = vbus_is_present(udc);
1951 if (vbus != udc->vbus_prev) {
1952 if (vbus) {
1953 usba_start(udc);
1954 } else {
1955 udc->suspended = false;
1956 if (udc->driver->disconnect)
1957 udc->driver->disconnect(&udc->gadget);
1958
1959 usba_stop(udc);
1960 }
1961 udc->vbus_prev = vbus;
1962 }
1963
1964 mutex_unlock(&udc->vbus_mutex);
1965 return IRQ_HANDLED;
1966 }
1967
atmel_usba_pullup(struct usb_gadget * gadget,int is_on)1968 static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on)
1969 {
1970 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
1971 unsigned long flags;
1972 u32 ctrl;
1973
1974 spin_lock_irqsave(&udc->lock, flags);
1975 ctrl = usba_readl(udc, CTRL);
1976 if (is_on)
1977 ctrl &= ~USBA_DETACH;
1978 else
1979 ctrl |= USBA_DETACH;
1980 usba_writel(udc, CTRL, ctrl);
1981 spin_unlock_irqrestore(&udc->lock, flags);
1982
1983 return 0;
1984 }
1985
atmel_usba_start(struct usb_gadget * gadget,struct usb_gadget_driver * driver)1986 static int atmel_usba_start(struct usb_gadget *gadget,
1987 struct usb_gadget_driver *driver)
1988 {
1989 int ret;
1990 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
1991 unsigned long flags;
1992
1993 spin_lock_irqsave(&udc->lock, flags);
1994 udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
1995 udc->driver = driver;
1996 spin_unlock_irqrestore(&udc->lock, flags);
1997
1998 mutex_lock(&udc->vbus_mutex);
1999
2000 if (udc->vbus_pin)
2001 enable_irq(gpiod_to_irq(udc->vbus_pin));
2002
2003 /* If Vbus is present, enable the controller and wait for reset */
2004 udc->vbus_prev = vbus_is_present(udc);
2005 if (udc->vbus_prev) {
2006 ret = usba_start(udc);
2007 if (ret)
2008 goto err;
2009 }
2010
2011 mutex_unlock(&udc->vbus_mutex);
2012 return 0;
2013
2014 err:
2015 if (udc->vbus_pin)
2016 disable_irq(gpiod_to_irq(udc->vbus_pin));
2017
2018 mutex_unlock(&udc->vbus_mutex);
2019
2020 spin_lock_irqsave(&udc->lock, flags);
2021 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
2022 udc->driver = NULL;
2023 spin_unlock_irqrestore(&udc->lock, flags);
2024 return ret;
2025 }
2026
atmel_usba_stop(struct usb_gadget * gadget)2027 static int atmel_usba_stop(struct usb_gadget *gadget)
2028 {
2029 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
2030
2031 if (udc->vbus_pin)
2032 disable_irq(gpiod_to_irq(udc->vbus_pin));
2033
2034 udc->suspended = false;
2035 usba_stop(udc);
2036
2037 udc->driver = NULL;
2038
2039 return 0;
2040 }
2041
at91sam9rl_toggle_bias(struct usba_udc * udc,int is_on)2042 static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on)
2043 {
2044 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2045 is_on ? AT91_PMC_BIASEN : 0);
2046 }
2047
at91sam9g45_pulse_bias(struct usba_udc * udc)2048 static void at91sam9g45_pulse_bias(struct usba_udc *udc)
2049 {
2050 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0);
2051 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2052 AT91_PMC_BIASEN);
2053 }
2054
2055 static const struct usba_udc_errata at91sam9rl_errata = {
2056 .toggle_bias = at91sam9rl_toggle_bias,
2057 };
2058
2059 static const struct usba_udc_errata at91sam9g45_errata = {
2060 .pulse_bias = at91sam9g45_pulse_bias,
2061 };
2062
2063 static const struct usba_ep_config ep_config_sam9[] = {
2064 { .nr_banks = 1 }, /* ep 0 */
2065 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */
2066 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */
2067 { .nr_banks = 3, .can_dma = 1 }, /* ep 3 */
2068 { .nr_banks = 3, .can_dma = 1 }, /* ep 4 */
2069 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */
2070 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */
2071 };
2072
2073 static const struct usba_ep_config ep_config_sama5[] = {
2074 { .nr_banks = 1 }, /* ep 0 */
2075 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */
2076 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */
2077 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 3 */
2078 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 4 */
2079 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */
2080 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */
2081 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 7 */
2082 { .nr_banks = 2, .can_isoc = 1 }, /* ep 8 */
2083 { .nr_banks = 2, .can_isoc = 1 }, /* ep 9 */
2084 { .nr_banks = 2, .can_isoc = 1 }, /* ep 10 */
2085 { .nr_banks = 2, .can_isoc = 1 }, /* ep 11 */
2086 { .nr_banks = 2, .can_isoc = 1 }, /* ep 12 */
2087 { .nr_banks = 2, .can_isoc = 1 }, /* ep 13 */
2088 { .nr_banks = 2, .can_isoc = 1 }, /* ep 14 */
2089 { .nr_banks = 2, .can_isoc = 1 }, /* ep 15 */
2090 };
2091
2092 static const struct usba_udc_config udc_at91sam9rl_cfg = {
2093 .errata = &at91sam9rl_errata,
2094 .config = ep_config_sam9,
2095 .num_ep = ARRAY_SIZE(ep_config_sam9),
2096 .ep_prealloc = true,
2097 };
2098
2099 static const struct usba_udc_config udc_at91sam9g45_cfg = {
2100 .errata = &at91sam9g45_errata,
2101 .config = ep_config_sam9,
2102 .num_ep = ARRAY_SIZE(ep_config_sam9),
2103 .ep_prealloc = true,
2104 };
2105
2106 static const struct usba_udc_config udc_sama5d3_cfg = {
2107 .config = ep_config_sama5,
2108 .num_ep = ARRAY_SIZE(ep_config_sama5),
2109 .ep_prealloc = true,
2110 };
2111
2112 static const struct usba_udc_config udc_sam9x60_cfg = {
2113 .num_ep = ARRAY_SIZE(ep_config_sam9),
2114 .config = ep_config_sam9,
2115 .ep_prealloc = false,
2116 };
2117
2118 static const struct of_device_id atmel_udc_dt_ids[] = {
2119 { .compatible = "atmel,at91sam9rl-udc", .data = &udc_at91sam9rl_cfg },
2120 { .compatible = "atmel,at91sam9g45-udc", .data = &udc_at91sam9g45_cfg },
2121 { .compatible = "atmel,sama5d3-udc", .data = &udc_sama5d3_cfg },
2122 { .compatible = "microchip,sam9x60-udc", .data = &udc_sam9x60_cfg },
2123 { /* sentinel */ }
2124 };
2125
2126 MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
2127
2128 static const struct of_device_id atmel_pmc_dt_ids[] = {
2129 { .compatible = "atmel,at91sam9g45-pmc" },
2130 { .compatible = "atmel,at91sam9rl-pmc" },
2131 { .compatible = "atmel,at91sam9x5-pmc" },
2132 { /* sentinel */ }
2133 };
2134
atmel_udc_of_init(struct platform_device * pdev,struct usba_udc * udc)2135 static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
2136 struct usba_udc *udc)
2137 {
2138 struct device_node *np = pdev->dev.of_node;
2139 const struct of_device_id *match;
2140 struct device_node *pp;
2141 int i, ret;
2142 struct usba_ep *eps, *ep;
2143 const struct usba_udc_config *udc_config;
2144
2145 match = of_match_node(atmel_udc_dt_ids, np);
2146 if (!match)
2147 return ERR_PTR(-EINVAL);
2148
2149 udc_config = match->data;
2150 udc->ep_prealloc = udc_config->ep_prealloc;
2151 udc->errata = udc_config->errata;
2152 if (udc->errata) {
2153 pp = of_find_matching_node_and_match(NULL, atmel_pmc_dt_ids,
2154 NULL);
2155 if (!pp)
2156 return ERR_PTR(-ENODEV);
2157
2158 udc->pmc = syscon_node_to_regmap(pp);
2159 of_node_put(pp);
2160 if (IS_ERR(udc->pmc))
2161 return ERR_CAST(udc->pmc);
2162 }
2163
2164 udc->num_ep = 0;
2165
2166 udc->vbus_pin = devm_gpiod_get_optional(&pdev->dev, "atmel,vbus",
2167 GPIOD_IN);
2168 if (IS_ERR(udc->vbus_pin))
2169 return ERR_CAST(udc->vbus_pin);
2170
2171 if (fifo_mode == 0) {
2172 udc->num_ep = udc_config->num_ep;
2173 } else {
2174 udc->num_ep = usba_config_fifo_table(udc);
2175 }
2176
2177 eps = devm_kcalloc(&pdev->dev, udc->num_ep, sizeof(struct usba_ep),
2178 GFP_KERNEL);
2179 if (!eps)
2180 return ERR_PTR(-ENOMEM);
2181
2182 udc->gadget.ep0 = &eps[0].ep;
2183
2184 INIT_LIST_HEAD(&eps[0].ep.ep_list);
2185
2186 i = 0;
2187 while (i < udc->num_ep) {
2188 const struct usba_ep_config *ep_cfg = &udc_config->config[i];
2189
2190 ep = &eps[i];
2191
2192 ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : i;
2193
2194 /* Only the first EP is 64 bytes */
2195 if (ep->index == 0)
2196 ep->fifo_size = 64;
2197 else
2198 ep->fifo_size = 1024;
2199
2200 if (fifo_mode) {
2201 if (ep->fifo_size < udc->fifo_cfg[i].fifo_size)
2202 dev_warn(&pdev->dev,
2203 "Using default max fifo-size value\n");
2204 else
2205 ep->fifo_size = udc->fifo_cfg[i].fifo_size;
2206 }
2207
2208 ep->nr_banks = ep_cfg->nr_banks;
2209 if (fifo_mode) {
2210 if (ep->nr_banks < udc->fifo_cfg[i].nr_banks)
2211 dev_warn(&pdev->dev,
2212 "Using default max nb-banks value\n");
2213 else
2214 ep->nr_banks = udc->fifo_cfg[i].nr_banks;
2215 }
2216
2217 ep->can_dma = ep_cfg->can_dma;
2218 ep->can_isoc = ep_cfg->can_isoc;
2219
2220 sprintf(ep->name, "ep%d", ep->index);
2221 ep->ep.name = ep->name;
2222
2223 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
2224 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
2225 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
2226 ep->ep.ops = &usba_ep_ops;
2227 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
2228 ep->udc = udc;
2229 INIT_LIST_HEAD(&ep->queue);
2230
2231 if (ep->index == 0) {
2232 ep->ep.caps.type_control = true;
2233 } else {
2234 ep->ep.caps.type_iso = ep->can_isoc;
2235 ep->ep.caps.type_bulk = true;
2236 ep->ep.caps.type_int = true;
2237 }
2238
2239 ep->ep.caps.dir_in = true;
2240 ep->ep.caps.dir_out = true;
2241
2242 if (fifo_mode != 0) {
2243 /*
2244 * Generate ept_cfg based on FIFO size and
2245 * banks number
2246 */
2247 if (ep->fifo_size <= 8)
2248 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
2249 else
2250 /* LSB is bit 1, not 0 */
2251 ep->ept_cfg =
2252 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
2253
2254 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
2255 }
2256
2257 if (i)
2258 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2259
2260 i++;
2261 }
2262
2263 if (i == 0) {
2264 dev_err(&pdev->dev, "of_probe: no endpoint specified\n");
2265 ret = -EINVAL;
2266 goto err;
2267 }
2268
2269 return eps;
2270 err:
2271 return ERR_PTR(ret);
2272 }
2273
usba_udc_probe(struct platform_device * pdev)2274 static int usba_udc_probe(struct platform_device *pdev)
2275 {
2276 struct resource *res;
2277 struct clk *pclk, *hclk;
2278 struct usba_udc *udc;
2279 int irq, ret, i;
2280
2281 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2282 if (!udc)
2283 return -ENOMEM;
2284
2285 udc->gadget = usba_gadget_template;
2286 INIT_LIST_HEAD(&udc->gadget.ep_list);
2287
2288 udc->regs = devm_platform_get_and_ioremap_resource(pdev, CTRL_IOMEM_ID, &res);
2289 if (IS_ERR(udc->regs))
2290 return PTR_ERR(udc->regs);
2291 dev_info(&pdev->dev, "MMIO registers at %pR mapped at %p\n",
2292 res, udc->regs);
2293
2294 udc->fifo = devm_platform_get_and_ioremap_resource(pdev, FIFO_IOMEM_ID, &res);
2295 if (IS_ERR(udc->fifo))
2296 return PTR_ERR(udc->fifo);
2297 dev_info(&pdev->dev, "FIFO at %pR mapped at %p\n", res, udc->fifo);
2298
2299 irq = platform_get_irq(pdev, 0);
2300 if (irq < 0)
2301 return irq;
2302
2303 pclk = devm_clk_get(&pdev->dev, "pclk");
2304 if (IS_ERR(pclk))
2305 return PTR_ERR(pclk);
2306 hclk = devm_clk_get(&pdev->dev, "hclk");
2307 if (IS_ERR(hclk))
2308 return PTR_ERR(hclk);
2309
2310 spin_lock_init(&udc->lock);
2311 mutex_init(&udc->vbus_mutex);
2312 udc->pdev = pdev;
2313 udc->pclk = pclk;
2314 udc->hclk = hclk;
2315
2316 platform_set_drvdata(pdev, udc);
2317
2318 /* Make sure we start from a clean slate */
2319 ret = clk_prepare_enable(pclk);
2320 if (ret) {
2321 dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n");
2322 return ret;
2323 }
2324
2325 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
2326 clk_disable_unprepare(pclk);
2327
2328 udc->usba_ep = atmel_udc_of_init(pdev, udc);
2329
2330 toggle_bias(udc, 0);
2331
2332 if (IS_ERR(udc->usba_ep))
2333 return PTR_ERR(udc->usba_ep);
2334
2335 ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0,
2336 "atmel_usba_udc", udc);
2337 if (ret) {
2338 dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
2339 irq, ret);
2340 return ret;
2341 }
2342 udc->irq = irq;
2343
2344 if (udc->vbus_pin) {
2345 irq_set_status_flags(gpiod_to_irq(udc->vbus_pin), IRQ_NOAUTOEN);
2346 ret = devm_request_threaded_irq(&pdev->dev,
2347 gpiod_to_irq(udc->vbus_pin), NULL,
2348 usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS,
2349 "atmel_usba_udc", udc);
2350 if (ret) {
2351 udc->vbus_pin = NULL;
2352 dev_warn(&udc->pdev->dev,
2353 "failed to request vbus irq; "
2354 "assuming always on\n");
2355 }
2356 }
2357
2358 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2359 if (ret)
2360 return ret;
2361 device_init_wakeup(&pdev->dev, 1);
2362
2363 usba_init_debugfs(udc);
2364 for (i = 1; i < udc->num_ep; i++)
2365 usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
2366
2367 return 0;
2368 }
2369
usba_udc_remove(struct platform_device * pdev)2370 static void usba_udc_remove(struct platform_device *pdev)
2371 {
2372 struct usba_udc *udc;
2373 int i;
2374
2375 udc = platform_get_drvdata(pdev);
2376
2377 device_init_wakeup(&pdev->dev, 0);
2378 usb_del_gadget_udc(&udc->gadget);
2379
2380 for (i = 1; i < udc->num_ep; i++)
2381 usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
2382 usba_cleanup_debugfs(udc);
2383 }
2384
2385 #ifdef CONFIG_PM_SLEEP
usba_udc_suspend(struct device * dev)2386 static int usba_udc_suspend(struct device *dev)
2387 {
2388 struct usba_udc *udc = dev_get_drvdata(dev);
2389
2390 /* Not started */
2391 if (!udc->driver)
2392 return 0;
2393
2394 mutex_lock(&udc->vbus_mutex);
2395
2396 if (!device_may_wakeup(dev)) {
2397 udc->suspended = false;
2398 usba_stop(udc);
2399 goto out;
2400 }
2401
2402 /*
2403 * Device may wake up. We stay clocked if we failed
2404 * to request vbus irq, assuming always on.
2405 */
2406 if (udc->vbus_pin) {
2407 /* FIXME: right to stop here...??? */
2408 usba_stop(udc);
2409 enable_irq_wake(gpiod_to_irq(udc->vbus_pin));
2410 }
2411
2412 enable_irq_wake(udc->irq);
2413
2414 out:
2415 mutex_unlock(&udc->vbus_mutex);
2416 return 0;
2417 }
2418
usba_udc_resume(struct device * dev)2419 static int usba_udc_resume(struct device *dev)
2420 {
2421 struct usba_udc *udc = dev_get_drvdata(dev);
2422
2423 /* Not started */
2424 if (!udc->driver)
2425 return 0;
2426
2427 if (device_may_wakeup(dev)) {
2428 if (udc->vbus_pin)
2429 disable_irq_wake(gpiod_to_irq(udc->vbus_pin));
2430
2431 disable_irq_wake(udc->irq);
2432 }
2433
2434 /* If Vbus is present, enable the controller and wait for reset */
2435 mutex_lock(&udc->vbus_mutex);
2436 udc->vbus_prev = vbus_is_present(udc);
2437 if (udc->vbus_prev)
2438 usba_start(udc);
2439 mutex_unlock(&udc->vbus_mutex);
2440
2441 return 0;
2442 }
2443 #endif
2444
2445 static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume);
2446
2447 static struct platform_driver udc_driver = {
2448 .probe = usba_udc_probe,
2449 .remove_new = usba_udc_remove,
2450 .driver = {
2451 .name = "atmel_usba_udc",
2452 .pm = &usba_udc_pm_ops,
2453 .of_match_table = atmel_udc_dt_ids,
2454 },
2455 };
2456 module_platform_driver(udc_driver);
2457
2458 MODULE_DESCRIPTION("Atmel USBA UDC driver");
2459 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2460 MODULE_LICENSE("GPL");
2461 MODULE_ALIAS("platform:atmel_usba_udc");
2462