| /openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
58 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
61 #define REG_SET(reg_name, initial_val, field, val) \ argument
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
88 #define REG_UPDATE(reg_name, field, val) \ argument
112 #define REG_GET(reg_name, field, val) \ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_factory_dcn21.c | 57 #define REG(reg_name)\ argument
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 #define REGI(reg_name, block, id)\ argument
67 #define SF(reg_name, field_name, post_fix)\ argument
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
139 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| H A D | hw_factory_dcn30.c | 66 #define REG(reg_name)\ argument
69 #define SF_HPD(reg_name, field_name, post_fix)\ argument
72 #define REGI(reg_name, block, id)\ argument
76 #define SF(reg_name, field_name, post_fix)\ argument
109 #define SF_DDC(reg_name, field_name, post_fix)\ argument
165 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_factory_dcn20.c | 59 #define REG(reg_name)\ argument
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REGI(reg_name, block, id)\ argument
69 #define SF(reg_name, field_name, post_fix)\ argument
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
158 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| H A D | hw_factory_dcn32.c | 59 #define REG(reg_name)\ argument
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REGI(reg_name, block, id)\ argument
69 #define SF(reg_name, field_name, post_fix)\ argument
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
169 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| H A D | hw_factory_dcn315.c | 63 #define REG(reg_name)\ argument
66 #define SF_HPD(reg_name, field_name, post_fix)\ argument
69 #define REGI(reg_name, block, id)\ argument
73 #define SF(reg_name, field_name, post_fix)\ argument
105 #define SF_DDC(reg_name, field_name, post_fix)\ argument
157 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_factory_dce120.c | 46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
60 #define REG(reg_name)\ argument
63 #define REGI(reg_name, block, id)\ argument
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_factory_dcn10.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
57 #define REG(reg_name)\ argument
60 #define REGI(reg_name, block, id)\ argument
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| H A D | hw_factory_dce110.c | 42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
45 #define REG(reg_name)\ argument
48 #define REGI(reg_name, block, id)\ argument
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn321/ |
| H A D | dcn321_resource.c | 115 #define SR(reg_name)\ argument
118 #define SR_ARR(reg_name, id)\ argument
124 #define SRI(reg_name, block, id)\ argument
128 #define SRI_ARR(reg_name, block, id)\ argument
132 #define SR_ARR_I2C(reg_name, id) \ argument
143 #define SRI2(reg_name, block, id)\ argument
146 #define SRI2_ARR(reg_name, block, id)\ argument
154 #define SRII(reg_name, block, id)\ argument
187 #define NBIO_SR(reg_name)\ argument
190 #define NBIO_SR_ARR(reg_name, id)\ argument
[all …]
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| H A D | dcn321_dio_link_encoder.c | 51 #define FN(reg_name, field_name) \ argument
57 #define AUX_REG_READ(reg_name) \ argument
60 #define AUX_REG_WRITE(reg_name, val) \ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_services.h | 96 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
112 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
157 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
161 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
165 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ argument
171 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ argument
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| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | reg_mut.c | 26 #define WRITE_REG_NOCLOBBER(output, reg_name, input) \ argument
33 #define WRITE_REG_ENCODED(output, reg_name, input, encoding) \ argument
41 #define WRITE_REG_PAIR_ENCODED(output, reg_name, input, encoding) \ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_resource.c | 114 #define SR(reg_name)\ argument
118 #define SRI(reg_name, block, id)\ argument
122 #define SRI2(reg_name, block, id)\ argument
130 #define SRII(reg_name, block, id)\ argument
139 #define SRII_MPC_RMU(reg_name, block, id)\ argument
150 #define DCCG_SRII(reg_name, block, id)\ argument
154 #define VUPDATE_SRII(reg_name, block, id)\ argument
165 #define NBIO_SR(reg_name)\ argument
176 #define MMHUB_SR(reg_name)\ argument
187 #define CLK_SRI(reg_name, block, inst)\ argument
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource.c | 112 #define SR(reg_name)\ argument
115 #define SR_ARR(reg_name, id) \ argument
121 #define SRI(reg_name, block, id)\ argument
125 #define SRI_ARR(reg_name, block, id)\ argument
129 #define SR_ARR_I2C(reg_name, id) \ argument
140 #define SRI2(reg_name, block, id)\ argument
143 #define SRI2_ARR(reg_name, block, id)\ argument
151 #define SRII(reg_name, block, id)\ argument
184 #define NBIO_SR(reg_name)\ argument
187 #define NBIO_SR_ARR(reg_name, id)\ argument
[all …]
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| H A D | dcn32_dio_link_encoder.c | 52 #define FN(reg_name, field_name) \ argument
58 #define AUX_REG_READ(reg_name) \ argument
61 #define AUX_REG_WRITE(reg_name, val) \ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dio_link_encoder.c | 46 #define FN(reg_name, field_name) \ argument
213 #define AUX_REG_READ(reg_name) \ argument
216 #define AUX_REG_WRITE(reg_name, val) \ argument
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| /openbmc/linux/drivers/media/i2c/ccs/ |
| H A D | ccs-reg-access.h | 36 #define ccs_read(sensor, reg_name, val) \ argument
39 #define ccs_write(sensor, reg_name, val) \ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr_clk.c | 43 #define CLK_REG(reg_name, block, inst)\ argument
47 #define REG(reg_name) \ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_resource.c | 142 #define NBIO_SR(reg_name)\ argument
151 #define SR(reg_name)\ argument
154 #define SF(reg_name, field_name, post_fix)\ argument
157 #define SRI(reg_name, block, id)\ argument
160 #define SRI2(reg_name, block, id)\ argument
163 #define SRII(reg_name, block, id)\ argument
167 #define DCCG_SRII(reg_name, block, id)\ argument
171 #define VUPDATE_SRII(reg_name, block, id)\ argument
175 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
179 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| H A D | dcn302_resource.c | 164 #define NBIO_SR(reg_name)\ argument
173 #define SR(reg_name)\ argument
176 #define SF(reg_name, field_name, post_fix)\ argument
179 #define SRI(reg_name, block, id)\ argument
182 #define SRI2(reg_name, block, id)\ argument
185 #define SRII(reg_name, block, id)\ argument
189 #define DCCG_SRII(reg_name, block, id)\ argument
193 #define VUPDATE_SRII(reg_name, block, id)\ argument
197 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
201 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_panel_cntl.h | 32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_resource.c | 251 #define SR(reg_name)\ argument
255 #define SRI(reg_name, block, id)\ argument
259 #define SRIR(var_name, reg_name, block, id)\ argument
263 #define SRII(reg_name, block, id)\ argument
267 #define SRI_IX(reg_name, block, id)\ argument
270 #define DCCG_SRII(reg_name, block, id)\ argument
274 #define VUPDATE_SRII(reg_name, block, id)\ argument
285 #define NBIO_SR(reg_name)\ argument
296 #define MMHUB_SR(reg_name)\ argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_resource.c | 143 #define SR(reg_name)\ argument
147 #define SRI(reg_name, block, id)\ argument
151 #define SRI2(reg_name, block, id)\ argument
155 #define SRIR(var_name, reg_name, block, id)\ argument
159 #define SRII(reg_name, block, id)\ argument
163 #define SRII_MPC_RMU(reg_name, block, id)\ argument
174 #define DCCG_SRII(reg_name, block, id)\ argument
178 #define VUPDATE_SRII(reg_name, block, id)\ argument
189 #define NBIO_SR(reg_name)\ argument
200 #define MMHUB_SR(reg_name)\ argument
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_resource.c | 127 #define SR(reg_name)\ argument
131 #define SRI(reg_name, block, id)\ argument
135 #define SRI2(reg_name, block, id)\ argument
139 #define SRIR(var_name, reg_name, block, id)\ argument
143 #define SRII(reg_name, block, id)\ argument
147 #define SRII_MPC_RMU(reg_name, block, id)\ argument
158 #define DCCG_SRII(reg_name, block, id)\ argument
162 #define VUPDATE_SRII(reg_name, block, id)\ argument
173 #define NBIO_SR(reg_name)\ argument
184 #define MMHUB_SR(reg_name)\ argument
[all …]
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