1 /*
2 * ARM Aspeed I2C controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "migration/vmstate.h"
24 #include "qemu/cutils.h"
25 #include "qemu/log.h"
26 #include "qemu/module.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "hw/i2c/aspeed_i2c.h"
30 #include "hw/irq.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/registerfields.h"
33 #include "trace.h"
34
35 /* Enable SLAVE_ADDR_RX_MATCH always */
36 #define R_I2CD_INTR_STS_ALWAYS_ENABLE R_I2CD_INTR_STS_SLAVE_ADDR_RX_MATCH_MASK
37
aspeed_i2c_bus_raise_interrupt(AspeedI2CBus * bus)38 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
39 {
40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
41 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
42 uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus);
43 uint32_t intr_ctrl_mask = bus->regs[intr_ctrl_reg] |
44 R_I2CD_INTR_STS_ALWAYS_ENABLE;
45 bool raise_irq;
46
47 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT)) {
48 g_autofree char *buf = g_strdup_printf("%s%s%s%s%s%s%s",
49 aspeed_i2c_bus_pkt_mode_en(bus) &&
50 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ?
51 "pktdone|" : "",
52 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ?
53 "nak|" : "",
54 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ?
55 "ack|" : "",
56 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ?
57 "done|" : "",
58 ARRAY_FIELD_EX32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH) ?
59 "slave-match|" : "",
60 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, NORMAL_STOP) ?
61 "stop|" : "",
62 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, ABNORMAL) ?
63 "abnormal" : "");
64
65 trace_aspeed_i2c_bus_raise_interrupt(bus->regs[reg_intr_sts], buf);
66 }
67
68 raise_irq = bus->regs[reg_intr_sts] & intr_ctrl_mask ;
69
70 /* In packet mode we don't mask off INTR_STS */
71 if (!aspeed_i2c_bus_pkt_mode_en(bus)) {
72 bus->regs[reg_intr_sts] &= intr_ctrl_mask;
73 }
74
75 if (raise_irq) {
76 bus->controller->intr_status |= 1 << bus->id;
77 qemu_irq_raise(aic->bus_get_irq(bus));
78 }
79 }
80
aspeed_i2c_bus_raise_slave_interrupt(AspeedI2CBus * bus)81 static inline void aspeed_i2c_bus_raise_slave_interrupt(AspeedI2CBus *bus)
82 {
83 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
84
85 if (!bus->regs[R_I2CS_INTR_STS]) {
86 return;
87 }
88
89 bus->controller->intr_status |= 1 << bus->id;
90 qemu_irq_raise(aic->bus_get_irq(bus));
91 }
92
aspeed_i2c_bus_old_read(AspeedI2CBus * bus,hwaddr offset,unsigned size)93 static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset,
94 unsigned size)
95 {
96 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
97 uint64_t value = bus->regs[offset / sizeof(*bus->regs)];
98
99 switch (offset) {
100 case A_I2CD_FUN_CTRL:
101 case A_I2CD_AC_TIMING1:
102 case A_I2CD_AC_TIMING2:
103 case A_I2CD_INTR_CTRL:
104 case A_I2CD_INTR_STS:
105 case A_I2CD_DEV_ADDR:
106 case A_I2CD_POOL_CTRL:
107 case A_I2CD_BYTE_BUF:
108 /* Value is already set, don't do anything. */
109 break;
110 case A_I2CD_CMD:
111 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus));
112 break;
113 case A_I2CD_DMA_ADDR:
114 if (!aic->has_dma) {
115 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
116 value = -1;
117 break;
118 }
119 break;
120 case A_I2CD_DMA_LEN:
121 if (!aic->has_dma) {
122 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
123 value = -1;
124 }
125 break;
126
127 default:
128 qemu_log_mask(LOG_GUEST_ERROR,
129 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
130 value = -1;
131 break;
132 }
133
134 trace_aspeed_i2c_bus_read(bus->id, offset, size, value);
135 return value;
136 }
137
aspeed_i2c_bus_new_read(AspeedI2CBus * bus,hwaddr offset,unsigned size)138 static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset,
139 unsigned size)
140 {
141 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
142 uint64_t value = bus->regs[offset / sizeof(*bus->regs)];
143
144 switch (offset) {
145 case A_I2CC_FUN_CTRL:
146 case A_I2CC_AC_TIMING:
147 case A_I2CC_POOL_CTRL:
148 case A_I2CM_INTR_CTRL:
149 case A_I2CM_INTR_STS:
150 case A_I2CC_MS_TXRX_BYTE_BUF:
151 case A_I2CM_DMA_LEN:
152 case A_I2CM_DMA_TX_ADDR:
153 case A_I2CM_DMA_RX_ADDR:
154 case A_I2CM_DMA_LEN_STS:
155 case A_I2CC_DMA_LEN:
156 case A_I2CS_DEV_ADDR:
157 case A_I2CS_DMA_RX_ADDR:
158 case A_I2CS_DMA_LEN:
159 case A_I2CS_CMD:
160 case A_I2CS_INTR_CTRL:
161 case A_I2CS_DMA_LEN_STS:
162 /* Value is already set, don't do anything. */
163 break;
164 case A_I2CC_DMA_ADDR:
165 value = extract64(bus->dma_dram_offset, 0, 32);
166 break;
167 case A_I2CS_INTR_STS:
168 break;
169 case A_I2CM_CMD:
170 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus));
171 break;
172 case A_I2CM_DMA_TX_ADDR_HI:
173 case A_I2CM_DMA_RX_ADDR_HI:
174 case A_I2CS_DMA_TX_ADDR_HI:
175 case A_I2CS_DMA_RX_ADDR_HI:
176 if (!aic->has_dma64) {
177 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n",
178 __func__);
179 value = -1;
180 }
181 break;
182 default:
183 qemu_log_mask(LOG_GUEST_ERROR,
184 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
185 value = -1;
186 break;
187 }
188
189 trace_aspeed_i2c_bus_read(bus->id, offset, size, value);
190 return value;
191 }
192
aspeed_i2c_bus_read(void * opaque,hwaddr offset,unsigned size)193 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
194 unsigned size)
195 {
196 AspeedI2CBus *bus = opaque;
197 if (aspeed_i2c_is_new_mode(bus->controller)) {
198 return aspeed_i2c_bus_new_read(bus, offset, size);
199 }
200 return aspeed_i2c_bus_old_read(bus, offset, size);
201 }
202
aspeed_i2c_set_state(AspeedI2CBus * bus,uint8_t state)203 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
204 {
205 if (aspeed_i2c_is_new_mode(bus->controller)) {
206 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_STATE,
207 state);
208 } else {
209 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_CMD, TX_STATE, state);
210 }
211 }
212
aspeed_i2c_get_state(AspeedI2CBus * bus)213 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
214 {
215 if (aspeed_i2c_is_new_mode(bus->controller)) {
216 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF,
217 TX_STATE);
218 }
219 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE);
220 }
221
222 /*
223 * The AST2700 support the maximum DRAM size is 8 GB.
224 * The DRAM offset range is from 0x0_0000_0000 to
225 * 0x1_FFFF_FFFF and it is enough to use bits [33:0]
226 * saving the dram offset.
227 * Therefore, save the high part physical address bit[1:0]
228 * of Tx/Rx buffer address as dma_dram_offset bit[33:32].
229 */
aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus * bus)230 static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus *bus)
231 {
232 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
233 uint32_t value;
234
235 assert(aic->has_dma);
236
237 if (aspeed_i2c_is_new_mode(bus->controller)) {
238 value = bus->regs[R_I2CM_DMA_TX_ADDR];
239 bus->dma_dram_offset =
240 deposit64(bus->dma_dram_offset, 0, 32,
241 FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR));
242 if (!aic->has_dma64) {
243 value = bus->regs[R_I2CM_DMA_TX_ADDR_HI];
244 bus->dma_dram_offset =
245 deposit64(bus->dma_dram_offset, 32, 32,
246 extract32(value, 0, 2));
247 }
248 } else {
249 value = bus->regs[R_I2CD_DMA_ADDR];
250 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
251 value & 0x3ffffffc);
252 }
253 }
254
aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus * bus)255 static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus *bus)
256 {
257 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
258 uint32_t value;
259
260 assert(aic->has_dma);
261
262 if (aspeed_i2c_is_new_mode(bus->controller)) {
263 value = bus->regs[R_I2CM_DMA_RX_ADDR];
264 bus->dma_dram_offset =
265 deposit64(bus->dma_dram_offset, 0, 32,
266 FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR));
267 if (!aic->has_dma64) {
268 value = bus->regs[R_I2CM_DMA_RX_ADDR_HI];
269 bus->dma_dram_offset =
270 deposit64(bus->dma_dram_offset, 32, 32,
271 extract32(value, 0, 2));
272 }
273 } else {
274 value = bus->regs[R_I2CD_DMA_ADDR];
275 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32,
276 value & 0x3ffffffc);
277 }
278 }
279
aspeed_i2c_dma_read(AspeedI2CBus * bus,uint8_t * data)280 static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data)
281 {
282 MemTxResult result;
283 AspeedI2CState *s = bus->controller;
284 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
285
286 result = address_space_read(&s->dram_as, bus->dma_dram_offset,
287 MEMTXATTRS_UNSPECIFIED, data, 1);
288 if (result != MEMTX_OK) {
289 qemu_log_mask(LOG_GUEST_ERROR,
290 "%s: DRAM read failed @%" PRIx64 "\n",
291 __func__, bus->dma_dram_offset);
292 return -1;
293 }
294
295 bus->dma_dram_offset++;
296 bus->regs[reg_dma_len]--;
297 return 0;
298 }
299
aspeed_i2c_bus_send(AspeedI2CBus * bus)300 static int aspeed_i2c_bus_send(AspeedI2CBus *bus)
301 {
302 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
303 int ret = -1;
304 int i;
305 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus);
306 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus);
307 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
308 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
309 int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl,
310 TX_COUNT) + 1;
311
312 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) {
313 for (i = 0; i < pool_tx_count; i++) {
314 uint8_t *pool_base = aic->bus_pool_base(bus);
315
316 trace_aspeed_i2c_bus_send("BUF", i + 1, pool_tx_count,
317 pool_base[i]);
318 ret = i2c_send(bus->bus, pool_base[i]);
319 if (ret) {
320 break;
321 }
322 }
323 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0);
324 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) {
325 /* In new mode, clear how many bytes we TXed */
326 if (aspeed_i2c_is_new_mode(bus->controller)) {
327 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0);
328 }
329 aspeed_i2c_set_tx_dma_dram_offset(bus);
330 while (bus->regs[reg_dma_len]) {
331 uint8_t data;
332 ret = aspeed_i2c_dma_read(bus, &data);
333 /* Check that we were able to read the DMA */
334 if (ret) {
335 break;
336 }
337 trace_aspeed_i2c_bus_send("DMA", bus->regs[reg_dma_len],
338 bus->regs[reg_dma_len], data);
339 ret = i2c_send(bus->bus, data);
340 if (ret) {
341 break;
342 }
343 /* In new mode, keep track of how many bytes we TXed */
344 if (aspeed_i2c_is_new_mode(bus->controller)) {
345 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN,
346 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS,
347 TX_LEN) + 1);
348 }
349 }
350 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0);
351 } else {
352 trace_aspeed_i2c_bus_send("BYTE", 0, 1,
353 bus->regs[reg_byte_buf]);
354 ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]);
355 }
356
357 return ret;
358 }
359
aspeed_i2c_bus_recv(AspeedI2CBus * bus)360 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
361 {
362 AspeedI2CState *s = bus->controller;
363 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
364 uint8_t data;
365 int i;
366 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus);
367 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus);
368 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
369 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
370 int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl,
371 RX_SIZE) + 1;
372
373 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) {
374 uint8_t *pool_base = aic->bus_pool_base(bus);
375 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl,
376 BUF_ORGANIZATION)) {
377 pool_base += 16;
378 }
379
380 for (i = 0; i < pool_rx_count; i++) {
381 pool_base[i] = i2c_recv(bus->bus);
382 trace_aspeed_i2c_bus_recv("BUF", i + 1, pool_rx_count,
383 pool_base[i]);
384 }
385
386 /* Update RX count */
387 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff);
388 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0);
389 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) {
390 /* In new mode, clear how many bytes we RXed */
391 if (aspeed_i2c_is_new_mode(bus->controller)) {
392 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0);
393 }
394
395 aspeed_i2c_set_rx_dma_dram_offset(bus);
396 while (bus->regs[reg_dma_len]) {
397 MemTxResult result;
398
399 data = i2c_recv(bus->bus);
400 trace_aspeed_i2c_bus_recv("DMA", bus->regs[reg_dma_len],
401 bus->regs[reg_dma_len], data);
402
403 result = address_space_write(&s->dram_as, bus->dma_dram_offset,
404 MEMTXATTRS_UNSPECIFIED, &data, 1);
405 if (result != MEMTX_OK) {
406 qemu_log_mask(LOG_GUEST_ERROR,
407 "%s: DRAM write failed @%" PRIx64 "\n",
408 __func__, bus->dma_dram_offset);
409 return;
410 }
411
412 bus->dma_dram_offset++;
413 bus->regs[reg_dma_len]--;
414 /* In new mode, keep track of how many bytes we RXed */
415 if (aspeed_i2c_is_new_mode(bus->controller)) {
416 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN,
417 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS,
418 RX_LEN) + 1);
419 }
420 }
421 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0);
422 } else {
423 data = i2c_recv(bus->bus);
424 trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->regs[reg_byte_buf]);
425 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data);
426 }
427 }
428
aspeed_i2c_handle_rx_cmd(AspeedI2CBus * bus)429 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus)
430 {
431 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus);
432 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
433
434 aspeed_i2c_set_state(bus, I2CD_MRXD);
435 aspeed_i2c_bus_recv(bus);
436 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
437 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) {
438 i2c_nack(bus->bus);
439 }
440 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0);
441 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0);
442 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
443 }
444
aspeed_i2c_get_addr(AspeedI2CBus * bus)445 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus)
446 {
447 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
448 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
449 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus);
450
451 if (aspeed_i2c_bus_pkt_mode_en(bus)) {
452 return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) |
453 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD);
454 }
455 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) {
456 uint8_t *pool_base = aic->bus_pool_base(bus);
457
458 return pool_base[0];
459 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) {
460 uint8_t data;
461
462 aspeed_i2c_set_tx_dma_dram_offset(bus);
463 aspeed_i2c_dma_read(bus, &data);
464 return data;
465 } else {
466 return bus->regs[reg_byte_buf];
467 }
468 }
469
aspeed_i2c_check_sram(AspeedI2CBus * bus)470 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus)
471 {
472 AspeedI2CState *s = bus->controller;
473 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
474 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus);
475 bool dma_en = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ||
476 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ||
477 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ||
478 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN);
479 if (!aic->check_sram) {
480 return true;
481 }
482
483 /*
484 * AST2500: SRAM must be enabled before using the Buffer Pool or
485 * DMA mode.
486 */
487 if (!FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, SRAM_EN) && dma_en) {
488 qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__);
489 return false;
490 }
491
492 return true;
493 }
494
aspeed_i2c_bus_cmd_dump(AspeedI2CBus * bus)495 static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus)
496 {
497 g_autofree char *cmd_flags = NULL;
498 uint32_t count;
499 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus);
500 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus);
501 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
502 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
503 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) {
504 count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) + 1;
505 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) {
506 count = bus->regs[reg_dma_len];
507 } else { /* BYTE mode */
508 count = 1;
509 }
510
511 cmd_flags = g_strdup_printf("%s%s%s%s%s%s%s%s%s",
512 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD) ? "start|" : "",
513 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ? "rxdma|" : "",
514 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ? "txdma|" : "",
515 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ? "rxbuf|" : "",
516 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN) ? "txbuf|" : "",
517 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD) ? "tx|" : "",
518 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ? "rx|" : "",
519 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST) ? "last|" : "",
520 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD) ? "stop|" : "");
521
522 trace_aspeed_i2c_bus_cmd(bus->regs[reg_cmd], cmd_flags, count,
523 bus->regs[reg_intr_sts]);
524 }
525
526 /*
527 * The state machine needs some refinement. It is only used to track
528 * invalid STOP commands for the moment.
529 */
aspeed_i2c_bus_handle_cmd(AspeedI2CBus * bus,uint64_t value)530 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
531 {
532 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
533 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus);
534 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
535
536 if (!aspeed_i2c_check_sram(bus)) {
537 return;
538 }
539
540 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) {
541 aspeed_i2c_bus_cmd_dump(bus);
542 }
543
544 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD)) {
545 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
546 I2CD_MSTARTR : I2CD_MSTART;
547 uint8_t addr;
548
549 aspeed_i2c_set_state(bus, state);
550
551 addr = aspeed_i2c_get_addr(bus);
552 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7),
553 extract32(addr, 0, 1))) {
554 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1);
555 if (aspeed_i2c_bus_pkt_mode_en(bus)) {
556 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1);
557 }
558 } else {
559 /* START doesn't set TX_ACK in packet mode */
560 if (!aspeed_i2c_bus_pkt_mode_en(bus)) {
561 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1);
562 }
563 }
564
565 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0);
566
567 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) {
568 if (bus->regs[reg_dma_len] == 0) {
569 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0);
570 }
571 } else if (!SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) {
572 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0);
573 }
574
575 /* No slave found */
576 if (!i2c_bus_busy(bus->bus)) {
577 if (aspeed_i2c_bus_pkt_mode_en(bus)) {
578 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1);
579 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1);
580 }
581 return;
582 }
583 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
584 }
585
586 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) {
587 aspeed_i2c_set_state(bus, I2CD_MTXD);
588 if (aspeed_i2c_bus_send(bus)) {
589 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1);
590 i2c_end_transfer(bus->bus);
591 } else {
592 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1);
593 }
594 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0);
595 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
596 }
597
598 if ((SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ||
599 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) &&
600 !SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE)) {
601 aspeed_i2c_handle_rx_cmd(bus);
602 }
603
604 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD)) {
605 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
606 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
607 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, ABNORMAL, 1);
608 if (aspeed_i2c_bus_pkt_mode_en(bus)) {
609 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1);
610 }
611 } else {
612 aspeed_i2c_set_state(bus, I2CD_MSTOP);
613 i2c_end_transfer(bus->bus);
614 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1);
615 }
616 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0);
617 aspeed_i2c_set_state(bus, I2CD_IDLE);
618
619 i2c_schedule_pending_master(bus->bus);
620 }
621
622 if (aspeed_i2c_bus_pkt_mode_en(bus)) {
623 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1);
624 }
625 }
626
aspeed_i2c_bus_new_write(AspeedI2CBus * bus,hwaddr offset,uint64_t value,unsigned size)627 static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
628 uint64_t value, unsigned size)
629 {
630 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
631 bool handle_rx;
632 bool w1t;
633
634 trace_aspeed_i2c_bus_write(bus->id, offset, size, value);
635
636 switch (offset) {
637 case A_I2CC_FUN_CTRL:
638 bus->regs[R_I2CC_FUN_CTRL] = value;
639 break;
640 case A_I2CC_AC_TIMING:
641 bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff;
642 break;
643 case A_I2CC_MS_TXRX_BYTE_BUF:
644 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_BUF,
645 value);
646 break;
647 case A_I2CC_POOL_CTRL:
648 bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff;
649 bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff);
650 break;
651 case A_I2CM_INTR_CTRL:
652 bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f;
653 break;
654 case A_I2CM_INTR_STS:
655 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_INTR_STS, RX_DONE)
656 && SHARED_FIELD_EX32(value, RX_DONE);
657
658 /* In packet mode, clearing PKT_CMD_DONE clears other interrupts. */
659 if (aspeed_i2c_bus_pkt_mode_en(bus) &&
660 FIELD_EX32(value, I2CM_INTR_STS, PKT_CMD_DONE)) {
661 bus->regs[R_I2CM_INTR_STS] &= 0xf0001000;
662 if (!bus->regs[R_I2CM_INTR_STS]) {
663 bus->controller->intr_status &= ~(1 << bus->id);
664 qemu_irq_lower(aic->bus_get_irq(bus));
665 }
666 aspeed_i2c_bus_raise_slave_interrupt(bus);
667 break;
668 }
669 bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f);
670 if (!bus->regs[R_I2CM_INTR_STS]) {
671 bus->controller->intr_status &= ~(1 << bus->id);
672 qemu_irq_lower(aic->bus_get_irq(bus));
673 }
674 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD,
675 M_RX_CMD) ||
676 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD,
677 M_S_RX_CMD_LAST))) {
678 aspeed_i2c_handle_rx_cmd(bus);
679 aspeed_i2c_bus_raise_interrupt(bus);
680 }
681 break;
682 case A_I2CM_CMD:
683 if (!aspeed_i2c_bus_is_enabled(bus)) {
684 break;
685 }
686
687 if (!aspeed_i2c_bus_is_master(bus)) {
688 qemu_log_mask(LOG_GUEST_ERROR, "%s: Master mode is not enabled\n",
689 __func__);
690 break;
691 }
692
693 if (!aic->has_dma &&
694 (SHARED_FIELD_EX32(value, RX_DMA_EN) ||
695 SHARED_FIELD_EX32(value, TX_DMA_EN))) {
696 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
697 break;
698 }
699
700 if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) {
701 qemu_log_mask(LOG_UNIMP, "%s: Packet mode is not implemented\n",
702 __func__);
703 break;
704 }
705
706 value &= 0xff0ffbfb;
707 if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) {
708 bus->regs[R_I2CM_CMD] |= value;
709 } else {
710 bus->regs[R_I2CM_CMD] = value;
711 }
712
713 aspeed_i2c_bus_handle_cmd(bus, value);
714 aspeed_i2c_bus_raise_interrupt(bus);
715 break;
716 case A_I2CM_DMA_TX_ADDR:
717 bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR,
718 ADDR);
719 break;
720 case A_I2CM_DMA_RX_ADDR:
721 bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR,
722 ADDR);
723 break;
724 case A_I2CM_DMA_LEN:
725 w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
726 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
727 /* If none of the w1t bits are set, just write to the reg as normal. */
728 if (!w1t) {
729 bus->regs[R_I2CM_DMA_LEN] = value;
730 break;
731 }
732 if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
733 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN,
734 FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN));
735 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs,
736 I2CM_DMA_LEN,
737 RX_BUF_LEN) + 1;
738 }
739 if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
740 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN,
741 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN));
742 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs,
743 I2CM_DMA_LEN,
744 TX_BUF_LEN) + 1;
745 }
746 break;
747 case A_I2CM_DMA_LEN_STS:
748 /* Writes clear to 0 */
749 bus->regs[R_I2CM_DMA_LEN_STS] = 0;
750 break;
751 case A_I2CC_DMA_ADDR:
752 case A_I2CC_DMA_LEN:
753 /* RO */
754 break;
755 case A_I2CS_DEV_ADDR:
756 bus->regs[R_I2CS_DEV_ADDR] = value;
757 break;
758 case A_I2CS_DMA_RX_ADDR:
759 bus->regs[R_I2CS_DMA_RX_ADDR] = value;
760 break;
761 case A_I2CS_DMA_LEN:
762 assert(FIELD_EX32(value, I2CS_DMA_LEN, TX_BUF_LEN) == 0);
763 if (FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN_W1T)) {
764 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN,
765 FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN));
766 } else {
767 bus->regs[R_I2CS_DMA_LEN] = value;
768 }
769 break;
770 case A_I2CS_CMD:
771 if (FIELD_EX32(value, I2CS_CMD, W1_CTRL)) {
772 bus->regs[R_I2CS_CMD] |= value;
773 } else {
774 bus->regs[R_I2CS_CMD] = value;
775 }
776 i2c_slave_set_address(bus->slave, bus->regs[R_I2CS_DEV_ADDR]);
777 break;
778 case A_I2CS_INTR_CTRL:
779 bus->regs[R_I2CS_INTR_CTRL] = value;
780 break;
781
782 case A_I2CS_INTR_STS:
783 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_CTRL, PKT_CMD_DONE)) {
784 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE) &&
785 FIELD_EX32(value, I2CS_INTR_STS, PKT_CMD_DONE)) {
786 bus->regs[R_I2CS_INTR_STS] &= 0xfffc0000;
787 }
788 } else {
789 bus->regs[R_I2CS_INTR_STS] &= ~value;
790 }
791 if (!bus->regs[R_I2CS_INTR_STS]) {
792 bus->controller->intr_status &= ~(1 << bus->id);
793 qemu_irq_lower(aic->bus_get_irq(bus));
794 }
795 aspeed_i2c_bus_raise_interrupt(bus);
796 break;
797 case A_I2CS_DMA_LEN_STS:
798 bus->regs[R_I2CS_DMA_LEN_STS] = 0;
799 break;
800 case A_I2CS_DMA_TX_ADDR:
801 qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n",
802 __func__);
803 break;
804 case A_I2CM_DMA_TX_ADDR_HI:
805 if (!aic->has_dma64) {
806 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n",
807 __func__);
808 break;
809 }
810 bus->regs[R_I2CM_DMA_TX_ADDR_HI] = FIELD_EX32(value,
811 I2CM_DMA_TX_ADDR_HI,
812 ADDR_HI);
813 break;
814 case A_I2CM_DMA_RX_ADDR_HI:
815 if (!aic->has_dma64) {
816 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n",
817 __func__);
818 break;
819 }
820 bus->regs[R_I2CM_DMA_RX_ADDR_HI] = FIELD_EX32(value,
821 I2CM_DMA_RX_ADDR_HI,
822 ADDR_HI);
823 break;
824 case A_I2CS_DMA_TX_ADDR_HI:
825 qemu_log_mask(LOG_UNIMP,
826 "%s: Slave mode DMA TX Addr high is not implemented\n",
827 __func__);
828 break;
829 case A_I2CS_DMA_RX_ADDR_HI:
830 if (!aic->has_dma64) {
831 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n",
832 __func__);
833 break;
834 }
835 bus->regs[R_I2CS_DMA_RX_ADDR_HI] = FIELD_EX32(value,
836 I2CS_DMA_RX_ADDR_HI,
837 ADDR_HI);
838 break;
839 default:
840 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
841 __func__, offset);
842 }
843 }
844
aspeed_i2c_bus_old_write(AspeedI2CBus * bus,hwaddr offset,uint64_t value,unsigned size)845 static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset,
846 uint64_t value, unsigned size)
847 {
848 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
849 bool handle_rx;
850
851 trace_aspeed_i2c_bus_write(bus->id, offset, size, value);
852
853 switch (offset) {
854 case A_I2CD_FUN_CTRL:
855 if (SHARED_FIELD_EX32(value, SLAVE_EN)) {
856 i2c_slave_set_address(bus->slave, bus->regs[R_I2CD_DEV_ADDR]);
857 }
858 bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF;
859 break;
860 case A_I2CD_AC_TIMING1:
861 bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F;
862 break;
863 case A_I2CD_AC_TIMING2:
864 bus->regs[R_I2CD_AC_TIMING2] = value & 0x7;
865 break;
866 case A_I2CD_INTR_CTRL:
867 bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF;
868 break;
869 case A_I2CD_INTR_STS:
870 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_INTR_STS, RX_DONE)
871 && SHARED_FIELD_EX32(value, RX_DONE);
872 bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF);
873 if (!bus->regs[R_I2CD_INTR_STS]) {
874 bus->controller->intr_status &= ~(1 << bus->id);
875 qemu_irq_lower(aic->bus_get_irq(bus));
876 }
877 if (handle_rx) {
878 if (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, M_RX_CMD) ||
879 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD,
880 M_S_RX_CMD_LAST)) {
881 aspeed_i2c_handle_rx_cmd(bus);
882 aspeed_i2c_bus_raise_interrupt(bus);
883 } else if (aspeed_i2c_get_state(bus) == I2CD_STXD) {
884 i2c_ack(bus->bus);
885 }
886 }
887 break;
888 case A_I2CD_DEV_ADDR:
889 bus->regs[R_I2CD_DEV_ADDR] = value;
890 break;
891 case A_I2CD_POOL_CTRL:
892 bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff;
893 bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff);
894 break;
895
896 case A_I2CD_BYTE_BUF:
897 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_BYTE_BUF, TX_BUF, value);
898 break;
899 case A_I2CD_CMD:
900 if (!aspeed_i2c_bus_is_enabled(bus)) {
901 break;
902 }
903
904 if (!aspeed_i2c_bus_is_master(bus)) {
905 qemu_log_mask(LOG_GUEST_ERROR, "%s: Master mode is not enabled\n",
906 __func__);
907 break;
908 }
909
910 if (!aic->has_dma &&
911 (SHARED_FIELD_EX32(value, RX_DMA_EN) ||
912 SHARED_FIELD_EX32(value, TX_DMA_EN))) {
913 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
914 break;
915 }
916
917 bus->regs[R_I2CD_CMD] &= ~0xFFFF;
918 bus->regs[R_I2CD_CMD] |= value & 0xFFFF;
919
920 aspeed_i2c_bus_handle_cmd(bus, value);
921 aspeed_i2c_bus_raise_interrupt(bus);
922 break;
923 case A_I2CD_DMA_ADDR:
924 if (!aic->has_dma) {
925 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
926 break;
927 }
928 break;
929
930 case A_I2CD_DMA_LEN:
931 if (!aic->has_dma) {
932 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__);
933 break;
934 }
935
936 bus->regs[R_I2CD_DMA_LEN] = value & 0xfff;
937 if (!bus->regs[R_I2CD_DMA_LEN]) {
938 qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__);
939 }
940 break;
941
942 default:
943 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
944 __func__, offset);
945 }
946 }
947
aspeed_i2c_bus_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)948 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
949 uint64_t value, unsigned size)
950 {
951 AspeedI2CBus *bus = opaque;
952 if (aspeed_i2c_is_new_mode(bus->controller)) {
953 aspeed_i2c_bus_new_write(bus, offset, value, size);
954 } else {
955 aspeed_i2c_bus_old_write(bus, offset, value, size);
956 }
957 }
958
aspeed_i2c_ctrl_read(void * opaque,hwaddr offset,unsigned size)959 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
960 unsigned size)
961 {
962 AspeedI2CState *s = opaque;
963
964 switch (offset) {
965 case A_I2C_CTRL_STATUS:
966 return s->intr_status;
967 case A_I2C_CTRL_GLOBAL:
968 return s->ctrl_global;
969 case A_I2C_CTRL_NEW_CLK_DIVIDER:
970 if (aspeed_i2c_is_new_mode(s)) {
971 return s->new_clk_divider;
972 }
973 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
974 __func__, offset);
975 break;
976 default:
977 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
978 __func__, offset);
979 break;
980 }
981
982 return -1;
983 }
984
aspeed_i2c_ctrl_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)985 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
986 uint64_t value, unsigned size)
987 {
988 AspeedI2CState *s = opaque;
989
990 switch (offset) {
991 case A_I2C_CTRL_GLOBAL:
992 s->ctrl_global = value;
993 break;
994 case A_I2C_CTRL_NEW_CLK_DIVIDER:
995 if (aspeed_i2c_is_new_mode(s)) {
996 s->new_clk_divider = value;
997 } else {
998 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx
999 "\n", __func__, offset);
1000 }
1001 break;
1002 case A_I2C_CTRL_STATUS:
1003 default:
1004 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1005 __func__, offset);
1006 break;
1007 }
1008 }
1009
1010 static const MemoryRegionOps aspeed_i2c_bus_ops = {
1011 .read = aspeed_i2c_bus_read,
1012 .write = aspeed_i2c_bus_write,
1013 .endianness = DEVICE_LITTLE_ENDIAN,
1014 };
1015
1016 static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
1017 .read = aspeed_i2c_ctrl_read,
1018 .write = aspeed_i2c_ctrl_write,
1019 .endianness = DEVICE_LITTLE_ENDIAN,
1020 };
1021
aspeed_i2c_share_pool_read(void * opaque,hwaddr offset,unsigned size)1022 static uint64_t aspeed_i2c_share_pool_read(void *opaque, hwaddr offset,
1023 unsigned size)
1024 {
1025 AspeedI2CState *s = opaque;
1026 uint64_t ret = 0;
1027 int i;
1028
1029 for (i = 0; i < size; i++) {
1030 ret |= (uint64_t) s->share_pool[offset + i] << (8 * i);
1031 }
1032
1033 return ret;
1034 }
1035
aspeed_i2c_share_pool_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)1036 static void aspeed_i2c_share_pool_write(void *opaque, hwaddr offset,
1037 uint64_t value, unsigned size)
1038 {
1039 AspeedI2CState *s = opaque;
1040 int i;
1041
1042 for (i = 0; i < size; i++) {
1043 s->share_pool[offset + i] = (value >> (8 * i)) & 0xFF;
1044 }
1045 }
1046
1047 static const MemoryRegionOps aspeed_i2c_share_pool_ops = {
1048 .read = aspeed_i2c_share_pool_read,
1049 .write = aspeed_i2c_share_pool_write,
1050 .endianness = DEVICE_LITTLE_ENDIAN,
1051 .valid = {
1052 .min_access_size = 1,
1053 .max_access_size = 4,
1054 },
1055 };
1056
aspeed_i2c_bus_pool_read(void * opaque,hwaddr offset,unsigned size)1057 static uint64_t aspeed_i2c_bus_pool_read(void *opaque, hwaddr offset,
1058 unsigned size)
1059 {
1060 AspeedI2CBus *s = opaque;
1061 uint64_t ret = 0;
1062 int i;
1063
1064 for (i = 0; i < size; i++) {
1065 ret |= (uint64_t) s->pool[offset + i] << (8 * i);
1066 }
1067
1068 return ret;
1069 }
1070
aspeed_i2c_bus_pool_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)1071 static void aspeed_i2c_bus_pool_write(void *opaque, hwaddr offset,
1072 uint64_t value, unsigned size)
1073 {
1074 AspeedI2CBus *s = opaque;
1075 int i;
1076
1077 for (i = 0; i < size; i++) {
1078 s->pool[offset + i] = (value >> (8 * i)) & 0xFF;
1079 }
1080 }
1081
1082 static const MemoryRegionOps aspeed_i2c_bus_pool_ops = {
1083 .read = aspeed_i2c_bus_pool_read,
1084 .write = aspeed_i2c_bus_pool_write,
1085 .endianness = DEVICE_LITTLE_ENDIAN,
1086 .valid = {
1087 .min_access_size = 1,
1088 .max_access_size = 4,
1089 },
1090 };
1091
1092 static const VMStateDescription aspeed_i2c_bus_vmstate = {
1093 .name = TYPE_ASPEED_I2C,
1094 .version_id = 6,
1095 .minimum_version_id = 6,
1096 .fields = (const VMStateField[]) {
1097 VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG),
1098 VMSTATE_UINT8_ARRAY(pool, AspeedI2CBus, ASPEED_I2C_BUS_POOL_SIZE),
1099 VMSTATE_UINT64(dma_dram_offset, AspeedI2CBus),
1100 VMSTATE_END_OF_LIST()
1101 }
1102 };
1103
1104 static const VMStateDescription aspeed_i2c_vmstate = {
1105 .name = TYPE_ASPEED_I2C,
1106 .version_id = 3,
1107 .minimum_version_id = 3,
1108 .fields = (const VMStateField[]) {
1109 VMSTATE_UINT32(intr_status, AspeedI2CState),
1110 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
1111 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
1112 AspeedI2CBus),
1113 VMSTATE_UINT8_ARRAY(share_pool, AspeedI2CState,
1114 ASPEED_I2C_SHARE_POOL_SIZE),
1115 VMSTATE_END_OF_LIST()
1116 }
1117 };
1118
aspeed_i2c_reset(DeviceState * dev)1119 static void aspeed_i2c_reset(DeviceState *dev)
1120 {
1121 AspeedI2CState *s = ASPEED_I2C(dev);
1122
1123 s->intr_status = 0;
1124 }
1125
aspeed_i2c_instance_init(Object * obj)1126 static void aspeed_i2c_instance_init(Object *obj)
1127 {
1128 AspeedI2CState *s = ASPEED_I2C(obj);
1129 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
1130 int i;
1131
1132 for (i = 0; i < aic->num_busses; i++) {
1133 object_initialize_child(obj, "bus[*]", &s->busses[i],
1134 TYPE_ASPEED_I2C_BUS);
1135 }
1136 }
1137
1138 /*
1139 * Address Definitions (AST2400 and AST2500)
1140 *
1141 * 0x000 ... 0x03F: Global Register
1142 * 0x040 ... 0x07F: Device 1
1143 * 0x080 ... 0x0BF: Device 2
1144 * 0x0C0 ... 0x0FF: Device 3
1145 * 0x100 ... 0x13F: Device 4
1146 * 0x140 ... 0x17F: Device 5
1147 * 0x180 ... 0x1BF: Device 6
1148 * 0x1C0 ... 0x1FF: Device 7
1149 * 0x200 ... 0x20F: Device 1 buffer (AST2500 unused in linux driver)
1150 * 0x210 ... 0x21F: Device 2 buffer
1151 * 0x220 ... 0x22F: Device 3 buffer
1152 * 0x230 ... 0x23F: Device 4 buffer
1153 * 0x240 ... 0x24F: Device 5 buffer
1154 * 0x250 ... 0x25F: Device 6 buffer
1155 * 0x260 ... 0x26F: Device 7 buffer
1156 * 0x270 ... 0x27F: Device 8 buffer
1157 * 0x280 ... 0x28F: Device 9 buffer
1158 * 0x290 ... 0x29F: Device 10 buffer
1159 * 0x2A0 ... 0x2AF: Device 11 buffer
1160 * 0x2B0 ... 0x2BF: Device 12 buffer
1161 * 0x2C0 ... 0x2CF: Device 13 buffer
1162 * 0x2D0 ... 0x2DF: Device 14 buffer
1163 * 0x2E0 ... 0x2FF: Reserved
1164 * 0x300 ... 0x33F: Device 8
1165 * 0x340 ... 0x37F: Device 9
1166 * 0x380 ... 0x3BF: Device 10
1167 * 0x3C0 ... 0x3FF: Device 11
1168 * 0x400 ... 0x43F: Device 12
1169 * 0x440 ... 0x47F: Device 13
1170 * 0x480 ... 0x4BF: Device 14
1171 * 0x800 ... 0xFFF: Buffer Pool (AST2400 unused in linux driver)
1172 *
1173 * Address Definitions (AST2600 and AST1030)
1174 * 0x000 ... 0x07F: Global Register
1175 * 0x080 ... 0x0FF: Device 1
1176 * 0x100 ... 0x17F: Device 2
1177 * 0x180 ... 0x1FF: Device 3
1178 * 0x200 ... 0x27F: Device 4
1179 * 0x280 ... 0x2FF: Device 5
1180 * 0x300 ... 0x37F: Device 6
1181 * 0x380 ... 0x3FF: Device 7
1182 * 0x400 ... 0x47F: Device 8
1183 * 0x480 ... 0x4FF: Device 9
1184 * 0x500 ... 0x57F: Device 10
1185 * 0x580 ... 0x5FF: Device 11
1186 * 0x600 ... 0x67F: Device 12
1187 * 0x680 ... 0x6FF: Device 13
1188 * 0x700 ... 0x77F: Device 14
1189 * 0x780 ... 0x7FF: Device 15 (15 and 16 unused in AST1030)
1190 * 0x800 ... 0x87F: Device 16
1191 * 0xC00 ... 0xC1F: Device 1 buffer
1192 * 0xC20 ... 0xC3F: Device 2 buffer
1193 * 0xC40 ... 0xC5F: Device 3 buffer
1194 * 0xC60 ... 0xC7F: Device 4 buffer
1195 * 0xC80 ... 0xC9F: Device 5 buffer
1196 * 0xCA0 ... 0xCBF: Device 6 buffer
1197 * 0xCC0 ... 0xCDF: Device 7 buffer
1198 * 0xCE0 ... 0xCFF: Device 8 buffer
1199 * 0xD00 ... 0xD1F: Device 9 buffer
1200 * 0xD20 ... 0xD3F: Device 10 buffer
1201 * 0xD40 ... 0xD5F: Device 11 buffer
1202 * 0xD60 ... 0xD7F: Device 12 buffer
1203 * 0xD80 ... 0xD9F: Device 13 buffer
1204 * 0xDA0 ... 0xDBF: Device 14 buffer
1205 * 0xDC0 ... 0xDDF: Device 15 buffer (15 and 16 unused in AST1030)
1206 * 0xDE0 ... 0xDFF: Device 16 buffer
1207 *
1208 * Address Definitions (AST2700)
1209 * 0x000 ... 0x0FF: Global Register
1210 * 0x100 ... 0x17F: Device 0
1211 * 0x1A0 ... 0x1BF: Device 0 buffer
1212 * 0x200 ... 0x27F: Device 1
1213 * 0x2A0 ... 0x2BF: Device 1 buffer
1214 * 0x300 ... 0x37F: Device 2
1215 * 0x3A0 ... 0x3BF: Device 2 buffer
1216 * 0x400 ... 0x47F: Device 3
1217 * 0x4A0 ... 0x4BF: Device 3 buffer
1218 * 0x500 ... 0x57F: Device 4
1219 * 0x5A0 ... 0x5BF: Device 4 buffer
1220 * 0x600 ... 0x67F: Device 5
1221 * 0x6A0 ... 0x6BF: Device 5 buffer
1222 * 0x700 ... 0x77F: Device 6
1223 * 0x7A0 ... 0x7BF: Device 6 buffer
1224 * 0x800 ... 0x87F: Device 7
1225 * 0x8A0 ... 0x8BF: Device 7 buffer
1226 * 0x900 ... 0x97F: Device 8
1227 * 0x9A0 ... 0x9BF: Device 8 buffer
1228 * 0xA00 ... 0xA7F: Device 9
1229 * 0xAA0 ... 0xABF: Device 9 buffer
1230 * 0xB00 ... 0xB7F: Device 10
1231 * 0xBA0 ... 0xBBF: Device 10 buffer
1232 * 0xC00 ... 0xC7F: Device 11
1233 * 0xCA0 ... 0xCBF: Device 11 buffer
1234 * 0xD00 ... 0xD7F: Device 12
1235 * 0xDA0 ... 0xDBF: Device 12 buffer
1236 * 0xE00 ... 0xE7F: Device 13
1237 * 0xEA0 ... 0xEBF: Device 13 buffer
1238 * 0xF00 ... 0xF7F: Device 14
1239 * 0xFA0 ... 0xFBF: Device 14 buffer
1240 * 0x1000 ... 0x107F: Device 15
1241 * 0x10A0 ... 0x10BF: Device 15 buffer
1242 */
aspeed_i2c_realize(DeviceState * dev,Error ** errp)1243 static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
1244 {
1245 int i;
1246 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1247 AspeedI2CState *s = ASPEED_I2C(dev);
1248 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
1249 uint32_t reg_offset = aic->reg_size + aic->reg_gap_size;
1250 uint32_t pool_offset = aic->pool_size + aic->pool_gap_size;
1251
1252 sysbus_init_irq(sbd, &s->irq);
1253 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
1254 "aspeed.i2c", aic->mem_size);
1255 sysbus_init_mmio(sbd, &s->iomem);
1256
1257 for (i = 0; i < aic->num_busses; i++) {
1258 Object *bus = OBJECT(&s->busses[i]);
1259 int offset = i < aic->gap ? 1 : 5;
1260
1261 if (!object_property_set_link(bus, "controller", OBJECT(s), errp)) {
1262 return;
1263 }
1264
1265 if (!object_property_set_uint(bus, "bus-id", i, errp)) {
1266 return;
1267 }
1268
1269 if (!sysbus_realize(SYS_BUS_DEVICE(bus), errp)) {
1270 return;
1271 }
1272
1273 memory_region_add_subregion(&s->iomem, reg_offset * (i + offset),
1274 &s->busses[i].mr);
1275 }
1276
1277 if (aic->has_share_pool) {
1278 memory_region_init_io(&s->pool_iomem, OBJECT(s),
1279 &aspeed_i2c_share_pool_ops, s,
1280 "aspeed.i2c-share-pool", aic->pool_size);
1281 memory_region_add_subregion(&s->iomem, aic->pool_base,
1282 &s->pool_iomem);
1283 } else {
1284 for (i = 0; i < aic->num_busses; i++) {
1285 memory_region_add_subregion(&s->iomem,
1286 aic->pool_base + (pool_offset * i),
1287 &s->busses[i].mr_pool);
1288 }
1289 }
1290
1291 if (aic->has_dma) {
1292 if (!s->dram_mr) {
1293 error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set");
1294 return;
1295 }
1296
1297 address_space_init(&s->dram_as, s->dram_mr,
1298 TYPE_ASPEED_I2C "-dma-dram");
1299 }
1300 }
1301
1302 static const Property aspeed_i2c_properties[] = {
1303 DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr,
1304 TYPE_MEMORY_REGION, MemoryRegion *),
1305 DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label),
1306 };
1307
aspeed_i2c_class_init(ObjectClass * klass,const void * data)1308 static void aspeed_i2c_class_init(ObjectClass *klass, const void *data)
1309 {
1310 DeviceClass *dc = DEVICE_CLASS(klass);
1311
1312 dc->vmsd = &aspeed_i2c_vmstate;
1313 device_class_set_legacy_reset(dc, aspeed_i2c_reset);
1314 device_class_set_props(dc, aspeed_i2c_properties);
1315 dc->realize = aspeed_i2c_realize;
1316 dc->desc = "Aspeed I2C Controller";
1317 }
1318
1319 static const TypeInfo aspeed_i2c_info = {
1320 .name = TYPE_ASPEED_I2C,
1321 .parent = TYPE_SYS_BUS_DEVICE,
1322 .instance_init = aspeed_i2c_instance_init,
1323 .instance_size = sizeof(AspeedI2CState),
1324 .class_init = aspeed_i2c_class_init,
1325 .class_size = sizeof(AspeedI2CClass),
1326 .abstract = true,
1327 };
1328
aspeed_i2c_bus_new_slave_event(AspeedI2CBus * bus,enum i2c_event event)1329 static int aspeed_i2c_bus_new_slave_event(AspeedI2CBus *bus,
1330 enum i2c_event event)
1331 {
1332 switch (event) {
1333 case I2C_START_SEND_ASYNC:
1334 if (!SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CS_CMD, RX_DMA_EN)) {
1335 qemu_log_mask(LOG_GUEST_ERROR,
1336 "%s: Slave mode RX DMA is not enabled\n", __func__);
1337 return -1;
1338 }
1339 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0);
1340 bus->dma_dram_offset =
1341 deposit64(bus->dma_dram_offset, 0, 32,
1342 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_RX_ADDR, ADDR));
1343 bus->regs[R_I2CC_DMA_LEN] =
1344 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN) + 1;
1345 i2c_ack(bus->bus);
1346 break;
1347 case I2C_FINISH:
1348 ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE, 1);
1349 ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
1350 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, NORMAL_STOP, 1);
1351 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, RX_DONE, 1);
1352 aspeed_i2c_bus_raise_slave_interrupt(bus);
1353 break;
1354 default:
1355 qemu_log_mask(LOG_UNIMP, "%s: i2c event %d unimplemented\n",
1356 __func__, event);
1357 return -1;
1358 }
1359
1360 return 0;
1361 }
1362
aspeed_i2c_bus_slave_event(I2CSlave * slave,enum i2c_event event)1363 static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
1364 {
1365 BusState *qbus = qdev_get_parent_bus(DEVICE(slave));
1366 AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent);
1367 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
1368 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
1369 uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus);
1370 uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr,
1371 SLAVE_DEV_ADDR1);
1372
1373 if (aspeed_i2c_is_new_mode(bus->controller)) {
1374 return aspeed_i2c_bus_new_slave_event(bus, event);
1375 }
1376
1377 switch (event) {
1378 case I2C_START_SEND_ASYNC:
1379 /* Bit[0] == 0 indicates "send". */
1380 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1);
1381
1382 ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
1383 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
1384
1385 aspeed_i2c_set_state(bus, I2CD_STXD);
1386
1387 break;
1388
1389 case I2C_FINISH:
1390 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1);
1391
1392 aspeed_i2c_set_state(bus, I2CD_IDLE);
1393
1394 break;
1395
1396 default:
1397 return -1;
1398 }
1399
1400 aspeed_i2c_bus_raise_interrupt(bus);
1401
1402 return 0;
1403 }
1404
aspeed_i2c_bus_new_slave_send_async(AspeedI2CBus * bus,uint8_t data)1405 static void aspeed_i2c_bus_new_slave_send_async(AspeedI2CBus *bus, uint8_t data)
1406 {
1407 assert(address_space_write(&bus->controller->dram_as,
1408 bus->dma_dram_offset,
1409 MEMTXATTRS_UNSPECIFIED, &data, 1) == MEMTX_OK);
1410
1411 bus->dma_dram_offset++;
1412 bus->regs[R_I2CC_DMA_LEN]--;
1413 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN,
1414 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN) + 1);
1415 i2c_ack(bus->bus);
1416 }
1417
aspeed_i2c_bus_slave_send_async(I2CSlave * slave,uint8_t data)1418 static void aspeed_i2c_bus_slave_send_async(I2CSlave *slave, uint8_t data)
1419 {
1420 BusState *qbus = qdev_get_parent_bus(DEVICE(slave));
1421 AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent);
1422 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
1423 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
1424
1425 if (aspeed_i2c_is_new_mode(bus->controller)) {
1426 return aspeed_i2c_bus_new_slave_send_async(bus, data);
1427 }
1428
1429 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data);
1430 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
1431
1432 aspeed_i2c_bus_raise_interrupt(bus);
1433 }
1434
aspeed_i2c_bus_slave_class_init(ObjectClass * klass,const void * data)1435 static void aspeed_i2c_bus_slave_class_init(ObjectClass *klass,
1436 const void *data)
1437 {
1438 DeviceClass *dc = DEVICE_CLASS(klass);
1439 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
1440
1441 dc->desc = "Aspeed I2C Bus Slave";
1442
1443 sc->event = aspeed_i2c_bus_slave_event;
1444 sc->send_async = aspeed_i2c_bus_slave_send_async;
1445 }
1446
1447 static const TypeInfo aspeed_i2c_bus_slave_info = {
1448 .name = TYPE_ASPEED_I2C_BUS_SLAVE,
1449 .parent = TYPE_I2C_SLAVE,
1450 .instance_size = sizeof(AspeedI2CBusSlave),
1451 .class_init = aspeed_i2c_bus_slave_class_init,
1452 };
1453
aspeed_i2c_bus_reset(DeviceState * dev)1454 static void aspeed_i2c_bus_reset(DeviceState *dev)
1455 {
1456 AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
1457
1458 memset(s->regs, 0, sizeof(s->regs));
1459 i2c_end_transfer(s->bus);
1460 }
1461
aspeed_i2c_bus_realize(DeviceState * dev,Error ** errp)1462 static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
1463 {
1464 AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
1465 AspeedI2CClass *aic;
1466 g_autofree char *name = NULL;
1467 g_autofree char *pool_name = NULL;
1468
1469 if (!s->controller) {
1470 error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set");
1471 return;
1472 }
1473
1474 /*
1475 * I2C bus naming:
1476 * - Empty bus_label -> BMC internal controller, use default name.
1477 * - Non-empty bus_label -> external/addon controller, prefix with label
1478 * to avoid conflicts and show bus origin.
1479 */
1480 if (!s->controller->bus_label || (strlen(s->controller->bus_label) == 0)) {
1481 name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
1482 } else {
1483 name = g_strdup_printf("aspeed.%s.i2c.bus.%d",
1484 s->controller->bus_label, s->id);
1485 }
1486 pool_name = g_strdup_printf("%s.pool", name);
1487
1488 aic = ASPEED_I2C_GET_CLASS(s->controller);
1489
1490 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
1491
1492 s->bus = i2c_init_bus(dev, name);
1493 s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE,
1494 0xff);
1495
1496 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops,
1497 s, name, aic->reg_size);
1498 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr);
1499
1500 memory_region_init_io(&s->mr_pool, OBJECT(s), &aspeed_i2c_bus_pool_ops,
1501 s, pool_name, aic->pool_size);
1502 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr_pool);
1503 }
1504
1505 static const Property aspeed_i2c_bus_properties[] = {
1506 DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0),
1507 DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C,
1508 AspeedI2CState *),
1509 };
1510
aspeed_i2c_bus_class_init(ObjectClass * klass,const void * data)1511 static void aspeed_i2c_bus_class_init(ObjectClass *klass, const void *data)
1512 {
1513 DeviceClass *dc = DEVICE_CLASS(klass);
1514
1515 dc->desc = "Aspeed I2C Bus";
1516 dc->realize = aspeed_i2c_bus_realize;
1517 device_class_set_legacy_reset(dc, aspeed_i2c_bus_reset);
1518 device_class_set_props(dc, aspeed_i2c_bus_properties);
1519 }
1520
1521 static const TypeInfo aspeed_i2c_bus_info = {
1522 .name = TYPE_ASPEED_I2C_BUS,
1523 .parent = TYPE_SYS_BUS_DEVICE,
1524 .instance_size = sizeof(AspeedI2CBus),
1525 .class_init = aspeed_i2c_bus_class_init,
1526 };
1527
aspeed_2400_i2c_bus_get_irq(AspeedI2CBus * bus)1528 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus)
1529 {
1530 return bus->controller->irq;
1531 }
1532
aspeed_2400_i2c_bus_pool_base(AspeedI2CBus * bus)1533 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus)
1534 {
1535 uint8_t *pool_page =
1536 &bus->controller->share_pool[ARRAY_FIELD_EX32(bus->regs,
1537 I2CD_FUN_CTRL,
1538 POOL_PAGE_SEL) * 0x100];
1539
1540 return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)];
1541 }
1542
aspeed_2400_i2c_class_init(ObjectClass * klass,const void * data)1543 static void aspeed_2400_i2c_class_init(ObjectClass *klass, const void *data)
1544 {
1545 DeviceClass *dc = DEVICE_CLASS(klass);
1546 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
1547
1548 dc->desc = "ASPEED 2400 I2C Controller";
1549
1550 aic->num_busses = 14;
1551 aic->reg_size = 0x40;
1552 aic->gap = 7;
1553 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq;
1554 aic->has_share_pool = true;
1555 aic->pool_size = 0x800;
1556 aic->pool_base = 0x800;
1557 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base;
1558 aic->mem_size = 0x1000;
1559 }
1560
1561 static const TypeInfo aspeed_2400_i2c_info = {
1562 .name = TYPE_ASPEED_2400_I2C,
1563 .parent = TYPE_ASPEED_I2C,
1564 .class_init = aspeed_2400_i2c_class_init,
1565 };
1566
aspeed_2500_i2c_bus_get_irq(AspeedI2CBus * bus)1567 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus)
1568 {
1569 return bus->controller->irq;
1570 }
1571
aspeed_2500_i2c_bus_pool_base(AspeedI2CBus * bus)1572 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus)
1573 {
1574 return bus->pool;
1575 }
1576
aspeed_2500_i2c_class_init(ObjectClass * klass,const void * data)1577 static void aspeed_2500_i2c_class_init(ObjectClass *klass, const void *data)
1578 {
1579 DeviceClass *dc = DEVICE_CLASS(klass);
1580 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
1581
1582 dc->desc = "ASPEED 2500 I2C Controller";
1583
1584 aic->num_busses = 14;
1585 aic->reg_size = 0x40;
1586 aic->gap = 7;
1587 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq;
1588 aic->pool_size = 0x10;
1589 aic->pool_base = 0x200;
1590 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
1591 aic->check_sram = true;
1592 aic->has_dma = true;
1593 aic->mem_size = 0x1000;
1594 }
1595
1596 static const TypeInfo aspeed_2500_i2c_info = {
1597 .name = TYPE_ASPEED_2500_I2C,
1598 .parent = TYPE_ASPEED_I2C,
1599 .class_init = aspeed_2500_i2c_class_init,
1600 };
1601
aspeed_2600_i2c_bus_get_irq(AspeedI2CBus * bus)1602 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus)
1603 {
1604 return bus->irq;
1605 }
1606
aspeed_2600_i2c_class_init(ObjectClass * klass,const void * data)1607 static void aspeed_2600_i2c_class_init(ObjectClass *klass, const void *data)
1608 {
1609 DeviceClass *dc = DEVICE_CLASS(klass);
1610 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
1611
1612 dc->desc = "ASPEED 2600 I2C Controller";
1613
1614 aic->num_busses = 16;
1615 aic->reg_size = 0x80;
1616 aic->gap = -1; /* no gap */
1617 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
1618 aic->pool_size = 0x20;
1619 aic->pool_base = 0xC00;
1620 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
1621 aic->has_dma = true;
1622 aic->mem_size = 0x1000;
1623 }
1624
1625 static const TypeInfo aspeed_2600_i2c_info = {
1626 .name = TYPE_ASPEED_2600_I2C,
1627 .parent = TYPE_ASPEED_I2C,
1628 .class_init = aspeed_2600_i2c_class_init,
1629 };
1630
aspeed_1030_i2c_class_init(ObjectClass * klass,const void * data)1631 static void aspeed_1030_i2c_class_init(ObjectClass *klass, const void *data)
1632 {
1633 DeviceClass *dc = DEVICE_CLASS(klass);
1634 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
1635
1636 dc->desc = "ASPEED 1030 I2C Controller";
1637
1638 aic->num_busses = 14;
1639 aic->reg_size = 0x80;
1640 aic->gap = -1; /* no gap */
1641 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
1642 aic->pool_size = 0x20;
1643 aic->pool_base = 0xC00;
1644 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
1645 aic->has_dma = true;
1646 aic->mem_size = 0x10000;
1647 }
1648
1649 static const TypeInfo aspeed_1030_i2c_info = {
1650 .name = TYPE_ASPEED_1030_I2C,
1651 .parent = TYPE_ASPEED_I2C,
1652 .class_init = aspeed_1030_i2c_class_init,
1653 };
1654
aspeed_2700_i2c_class_init(ObjectClass * klass,const void * data)1655 static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data)
1656 {
1657 DeviceClass *dc = DEVICE_CLASS(klass);
1658 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
1659
1660 dc->desc = "ASPEED 2700 I2C Controller";
1661
1662 aic->num_busses = 16;
1663 aic->reg_size = 0x80;
1664 aic->reg_gap_size = 0x80;
1665 aic->gap = -1; /* no gap */
1666 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
1667 aic->pool_size = 0x20;
1668 aic->pool_gap_size = 0xe0;
1669 aic->pool_base = 0x1a0;
1670 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
1671 aic->has_dma = true;
1672 aic->mem_size = 0x2000;
1673 aic->has_dma64 = true;
1674 }
1675
1676 static const TypeInfo aspeed_2700_i2c_info = {
1677 .name = TYPE_ASPEED_2700_I2C,
1678 .parent = TYPE_ASPEED_I2C,
1679 .class_init = aspeed_2700_i2c_class_init,
1680 };
1681
aspeed_i2c_register_types(void)1682 static void aspeed_i2c_register_types(void)
1683 {
1684 type_register_static(&aspeed_i2c_bus_info);
1685 type_register_static(&aspeed_i2c_bus_slave_info);
1686 type_register_static(&aspeed_i2c_info);
1687 type_register_static(&aspeed_2400_i2c_info);
1688 type_register_static(&aspeed_2500_i2c_info);
1689 type_register_static(&aspeed_2600_i2c_info);
1690 type_register_static(&aspeed_1030_i2c_info);
1691 type_register_static(&aspeed_2700_i2c_info);
1692 }
1693
type_init(aspeed_i2c_register_types)1694 type_init(aspeed_i2c_register_types)
1695
1696
1697 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr)
1698 {
1699 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
1700 I2CBus *bus = NULL;
1701
1702 if (busnr >= 0 && busnr < aic->num_busses) {
1703 bus = s->busses[busnr].bus;
1704 }
1705
1706 return bus;
1707 }
1708