1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
4 * processor hardware monitoring
5 *
6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
8 *
9 * Implementation notes:
10 * - CCD register address information as well as the calculation to
11 * convert raw register values is from https://github.com/ocerman/zenpower.
12 * The information is not confirmed from chip datasheets, but experiments
13 * suggest that it provides reasonable temperature values.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/hwmon.h>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
23 #include <asm/amd_nb.h>
24 #include <asm/processor.h>
25
26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
28 MODULE_LICENSE("GPL");
29
30 static bool force;
31 module_param(force, bool, 0444);
32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
33
34 /* Provide lock for writing to NB_SMU_IND_ADDR */
35 static DEFINE_MUTEX(nb_smu_ind_mutex);
36
37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
39 #endif
40
41 /* CPUID function 0x80000001, ebx */
42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28)
43 #define CPUID_PKGTYPE_F 0x00000000
44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
45
46 /* DRAM controller (PCI function 2) */
47 #define REG_DCT0_CONFIG_HIGH 0x094
48 #define DDR3_MODE BIT(8)
49
50 /* miscellaneous (PCI function 3) */
51 #define REG_HARDWARE_THERMAL_CONTROL 0x64
52 #define HTC_ENABLE BIT(0)
53
54 #define REG_REPORTED_TEMPERATURE 0xa4
55
56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
57 #define NB_CAP_HTC BIT(10)
58
59 /*
60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
61 * and REG_REPORTED_TEMPERATURE have been moved to
62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
64 */
65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
67
68 /* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */
69 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800
70
71 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \
72 (offset) + ((x) * 4))
73 #define ZEN_CCD_TEMP_VALID BIT(11)
74 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
75
76 #define ZEN_CUR_TEMP_SHIFT 21
77 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
78 #define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)
79
80 /*
81 * AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius.
82 * Use the model name to identify 3255 CPUs and set a flag to display negative temperature.
83 * Do not round off to zero for negative Tctl or Tdie values if the flag is set
84 */
85 #define AMD_I3255_STR "3255"
86
87 struct k10temp_data {
88 struct pci_dev *pdev;
89 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
90 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
91 int temp_offset;
92 u32 temp_adjust_mask;
93 u32 show_temp;
94 bool is_zen;
95 u32 ccd_offset;
96 bool disp_negative;
97 };
98
99 #define TCTL_BIT 0
100 #define TDIE_BIT 1
101 #define TCCD_BIT(x) ((x) + 2)
102
103 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
104 #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
105
106 struct tctl_offset {
107 u8 model;
108 char const *id;
109 int offset;
110 };
111
112 static const struct tctl_offset tctl_offset_table[] = {
113 { 0x17, "AMD Ryzen 5 1600X", 20000 },
114 { 0x17, "AMD Ryzen 7 1700X", 20000 },
115 { 0x17, "AMD Ryzen 7 1800X", 20000 },
116 { 0x17, "AMD Ryzen 7 2700X", 10000 },
117 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
118 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
119 };
120
read_htcreg_pci(struct pci_dev * pdev,u32 * regval)121 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
122 {
123 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
124 }
125
read_tempreg_pci(struct pci_dev * pdev,u32 * regval)126 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
127 {
128 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
129 }
130
amd_nb_index_read(struct pci_dev * pdev,unsigned int devfn,unsigned int base,int offset,u32 * val)131 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
132 unsigned int base, int offset, u32 *val)
133 {
134 mutex_lock(&nb_smu_ind_mutex);
135 pci_bus_write_config_dword(pdev->bus, devfn,
136 base, offset);
137 pci_bus_read_config_dword(pdev->bus, devfn,
138 base + 4, val);
139 mutex_unlock(&nb_smu_ind_mutex);
140 }
141
read_htcreg_nb_f15(struct pci_dev * pdev,u32 * regval)142 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
143 {
144 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
145 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
146 }
147
read_tempreg_nb_f15(struct pci_dev * pdev,u32 * regval)148 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
149 {
150 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
151 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
152 }
153
read_tempreg_nb_zen(struct pci_dev * pdev,u32 * regval)154 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
155 {
156 if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
157 ZEN_REPORTED_TEMP_CTRL_BASE, regval))
158 *regval = 0;
159 }
160
get_raw_temp(struct k10temp_data * data)161 static long get_raw_temp(struct k10temp_data *data)
162 {
163 u32 regval;
164 long temp;
165
166 data->read_tempreg(data->pdev, ®val);
167 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
168 if ((regval & data->temp_adjust_mask) ||
169 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)
170 temp -= 49000;
171 return temp;
172 }
173
174 static const char *k10temp_temp_label[] = {
175 "Tctl",
176 "Tdie",
177 "Tccd1",
178 "Tccd2",
179 "Tccd3",
180 "Tccd4",
181 "Tccd5",
182 "Tccd6",
183 "Tccd7",
184 "Tccd8",
185 "Tccd9",
186 "Tccd10",
187 "Tccd11",
188 "Tccd12",
189 };
190
k10temp_read_labels(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)191 static int k10temp_read_labels(struct device *dev,
192 enum hwmon_sensor_types type,
193 u32 attr, int channel, const char **str)
194 {
195 switch (type) {
196 case hwmon_temp:
197 *str = k10temp_temp_label[channel];
198 break;
199 default:
200 return -EOPNOTSUPP;
201 }
202 return 0;
203 }
204
k10temp_read_temp(struct device * dev,u32 attr,int channel,long * val)205 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
206 long *val)
207 {
208 struct k10temp_data *data = dev_get_drvdata(dev);
209 int ret = -EOPNOTSUPP;
210 u32 regval;
211
212 switch (attr) {
213 case hwmon_temp_input:
214 switch (channel) {
215 case 0: /* Tctl */
216 *val = get_raw_temp(data);
217 if (*val < 0 && !data->disp_negative)
218 *val = 0;
219 break;
220 case 1: /* Tdie */
221 *val = get_raw_temp(data) - data->temp_offset;
222 if (*val < 0 && !data->disp_negative)
223 *val = 0;
224 break;
225 case 2 ... 13: /* Tccd{1-12} */
226 ret = amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
227 ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
228 ®val);
229
230 if (ret)
231 return ret;
232
233 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
234 break;
235 default:
236 return ret;
237 }
238 break;
239 case hwmon_temp_max:
240 *val = 70 * 1000;
241 break;
242 case hwmon_temp_crit:
243 data->read_htcreg(data->pdev, ®val);
244 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
245 break;
246 case hwmon_temp_crit_hyst:
247 data->read_htcreg(data->pdev, ®val);
248 *val = (((regval >> 16) & 0x7f)
249 - ((regval >> 24) & 0xf)) * 500 + 52000;
250 break;
251 default:
252 return ret;
253 }
254 return 0;
255 }
256
k10temp_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)257 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
258 u32 attr, int channel, long *val)
259 {
260 switch (type) {
261 case hwmon_temp:
262 return k10temp_read_temp(dev, attr, channel, val);
263 default:
264 return -EOPNOTSUPP;
265 }
266 }
267
k10temp_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)268 static umode_t k10temp_is_visible(const void *_data,
269 enum hwmon_sensor_types type,
270 u32 attr, int channel)
271 {
272 const struct k10temp_data *data = _data;
273 struct pci_dev *pdev = data->pdev;
274 u32 reg;
275
276 switch (type) {
277 case hwmon_temp:
278 switch (attr) {
279 case hwmon_temp_input:
280 if (!HAVE_TEMP(data, channel))
281 return 0;
282 break;
283 case hwmon_temp_max:
284 if (channel || data->is_zen)
285 return 0;
286 break;
287 case hwmon_temp_crit:
288 case hwmon_temp_crit_hyst:
289 if (channel || !data->read_htcreg)
290 return 0;
291
292 pci_read_config_dword(pdev,
293 REG_NORTHBRIDGE_CAPABILITIES,
294 ®);
295 if (!(reg & NB_CAP_HTC))
296 return 0;
297
298 data->read_htcreg(data->pdev, ®);
299 if (!(reg & HTC_ENABLE))
300 return 0;
301 break;
302 case hwmon_temp_label:
303 /* Show temperature labels only on Zen CPUs */
304 if (!data->is_zen || !HAVE_TEMP(data, channel))
305 return 0;
306 break;
307 default:
308 return 0;
309 }
310 break;
311 default:
312 return 0;
313 }
314 return 0444;
315 }
316
has_erratum_319(struct pci_dev * pdev)317 static bool has_erratum_319(struct pci_dev *pdev)
318 {
319 u32 pkg_type, reg_dram_cfg;
320
321 if (boot_cpu_data.x86 != 0x10)
322 return false;
323
324 /*
325 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
326 * may be unreliable.
327 */
328 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
329 if (pkg_type == CPUID_PKGTYPE_F)
330 return true;
331 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
332 return false;
333
334 /* DDR3 memory implies socket AM3, which is good */
335 pci_bus_read_config_dword(pdev->bus,
336 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
337 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
338 if (reg_dram_cfg & DDR3_MODE)
339 return false;
340
341 /*
342 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
343 * memory. We blacklist all the cores which do exist in socket AM2+
344 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
345 * and AM3 formats, but that's the best we can do.
346 */
347 return boot_cpu_data.x86_model < 4 ||
348 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
349 }
350
351 static const struct hwmon_channel_info * const k10temp_info[] = {
352 HWMON_CHANNEL_INFO(temp,
353 HWMON_T_INPUT | HWMON_T_MAX |
354 HWMON_T_CRIT | HWMON_T_CRIT_HYST |
355 HWMON_T_LABEL,
356 HWMON_T_INPUT | HWMON_T_LABEL,
357 HWMON_T_INPUT | HWMON_T_LABEL,
358 HWMON_T_INPUT | HWMON_T_LABEL,
359 HWMON_T_INPUT | HWMON_T_LABEL,
360 HWMON_T_INPUT | HWMON_T_LABEL,
361 HWMON_T_INPUT | HWMON_T_LABEL,
362 HWMON_T_INPUT | HWMON_T_LABEL,
363 HWMON_T_INPUT | HWMON_T_LABEL,
364 HWMON_T_INPUT | HWMON_T_LABEL,
365 HWMON_T_INPUT | HWMON_T_LABEL,
366 HWMON_T_INPUT | HWMON_T_LABEL,
367 HWMON_T_INPUT | HWMON_T_LABEL,
368 HWMON_T_INPUT | HWMON_T_LABEL),
369 NULL
370 };
371
372 static const struct hwmon_ops k10temp_hwmon_ops = {
373 .is_visible = k10temp_is_visible,
374 .read = k10temp_read,
375 .read_string = k10temp_read_labels,
376 };
377
378 static const struct hwmon_chip_info k10temp_chip_info = {
379 .ops = &k10temp_hwmon_ops,
380 .info = k10temp_info,
381 };
382
k10temp_get_ccd_support(struct pci_dev * pdev,struct k10temp_data * data,int limit)383 static void k10temp_get_ccd_support(struct pci_dev *pdev,
384 struct k10temp_data *data, int limit)
385 {
386 u32 regval;
387 int i;
388
389 for (i = 0; i < limit; i++) {
390 /*
391 * Ignore inaccessible CCDs.
392 *
393 * Some systems will return a register value of 0, and the TEMP_VALID
394 * bit check below will naturally fail.
395 *
396 * Other systems will return a PCI_ERROR_RESPONSE (0xFFFFFFFF) for
397 * the register value. And this will incorrectly pass the TEMP_VALID
398 * bit check.
399 */
400 if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
401 ZEN_CCD_TEMP(data->ccd_offset, i), ®val))
402 continue;
403
404 if (regval & ZEN_CCD_TEMP_VALID)
405 data->show_temp |= BIT(TCCD_BIT(i));
406 }
407 }
408
k10temp_probe(struct pci_dev * pdev,const struct pci_device_id * id)409 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
410 {
411 int unreliable = has_erratum_319(pdev);
412 struct device *dev = &pdev->dev;
413 struct k10temp_data *data;
414 struct device *hwmon_dev;
415 int i;
416
417 if (unreliable) {
418 if (!force) {
419 dev_err(dev,
420 "unreliable CPU thermal sensor; monitoring disabled\n");
421 return -ENODEV;
422 }
423 dev_warn(dev,
424 "unreliable CPU thermal sensor; check erratum 319\n");
425 }
426
427 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
428 if (!data)
429 return -ENOMEM;
430
431 data->pdev = pdev;
432 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
433
434 if (boot_cpu_data.x86 == 0x17 &&
435 strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) {
436 data->disp_negative = true;
437 }
438
439 if (boot_cpu_data.x86 == 0x15 &&
440 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
441 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
442 data->read_htcreg = read_htcreg_nb_f15;
443 data->read_tempreg = read_tempreg_nb_f15;
444 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
445 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
446 data->read_tempreg = read_tempreg_nb_zen;
447 data->is_zen = true;
448
449 switch (boot_cpu_data.x86_model) {
450 case 0x1: /* Zen */
451 case 0x8: /* Zen+ */
452 case 0x11: /* Zen APU */
453 case 0x18: /* Zen+ APU */
454 data->ccd_offset = 0x154;
455 k10temp_get_ccd_support(pdev, data, 4);
456 break;
457 case 0x31: /* Zen2 Threadripper */
458 case 0x60: /* Renoir */
459 case 0x68: /* Lucienne */
460 case 0x71: /* Zen2 */
461 data->ccd_offset = 0x154;
462 k10temp_get_ccd_support(pdev, data, 8);
463 break;
464 case 0xa0 ... 0xaf:
465 data->ccd_offset = 0x300;
466 k10temp_get_ccd_support(pdev, data, 8);
467 break;
468 }
469 } else if (boot_cpu_data.x86 == 0x19) {
470 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
471 data->read_tempreg = read_tempreg_nb_zen;
472 data->is_zen = true;
473
474 switch (boot_cpu_data.x86_model) {
475 case 0x0 ... 0x1: /* Zen3 SP3/TR */
476 case 0x21: /* Zen3 Ryzen Desktop */
477 case 0x50 ... 0x5f: /* Green Sardine */
478 data->ccd_offset = 0x154;
479 k10temp_get_ccd_support(pdev, data, 8);
480 break;
481 case 0x40 ... 0x4f: /* Yellow Carp */
482 data->ccd_offset = 0x300;
483 k10temp_get_ccd_support(pdev, data, 8);
484 break;
485 case 0x60 ... 0x6f:
486 case 0x70 ... 0x7f:
487 data->ccd_offset = 0x308;
488 k10temp_get_ccd_support(pdev, data, 8);
489 break;
490 case 0x10 ... 0x1f:
491 case 0xa0 ... 0xaf:
492 data->ccd_offset = 0x300;
493 k10temp_get_ccd_support(pdev, data, 12);
494 break;
495 }
496 } else if (boot_cpu_data.x86 == 0x1a) {
497 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
498 data->read_tempreg = read_tempreg_nb_zen;
499 data->is_zen = true;
500 } else {
501 data->read_htcreg = read_htcreg_pci;
502 data->read_tempreg = read_tempreg_pci;
503 }
504
505 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
506 const struct tctl_offset *entry = &tctl_offset_table[i];
507
508 if (boot_cpu_data.x86 == entry->model &&
509 strstr(boot_cpu_data.x86_model_id, entry->id)) {
510 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
511 data->temp_offset = entry->offset;
512 break;
513 }
514 }
515
516 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
517 &k10temp_chip_info,
518 NULL);
519 return PTR_ERR_OR_ZERO(hwmon_dev);
520 }
521
522 static const struct pci_device_id k10temp_id_table[] = {
523 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
524 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
525 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
526 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
527 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
528 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
529 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
530 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
531 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
532 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
533 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
534 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
535 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
536 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
537 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
538 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
539 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
540 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
541 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
542 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
543 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
544 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
545 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
546 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
547 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
548 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
549 {}
550 };
551 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
552
553 static struct pci_driver k10temp_driver = {
554 .name = "k10temp",
555 .id_table = k10temp_id_table,
556 .probe = k10temp_probe,
557 };
558
559 module_pci_driver(k10temp_driver);
560